High-voltage high-transconductance amplifier for comparator input stage

Abstract

To provide a high-voltage high-transconductance amplifier for a comparator input stage.SOLUTION: A gain stage circuit can include first and second follower circuits arranged as a differential pair and configured to receive respective input signals. The gain stage circuit can include or use a pass stage circuit including an adjustable-impedance signal path that couples the first and second follower circuits. The gain stage circuit can further include or use a control circuit to receive the input signals and, in response, provide a control signal to the pass stage circuit to control an impedance of the signal path that couples the first and second follower circuits.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] High voltage, high transconductance amplifier for comparator input stage. [Background technology]

[0002] A test system for testing electronic devices may include a pin driver circuit that provides voltage test pulses to a device under test (DUT). In response, the test system may be configured to measure a response from the DUT, such as to determine whether the DUT meets one or more specified operating parameters. The test system may optionally include multiple driver circuits, such as a class AB driver circuit and a class A driver circuit, to provide circuit test signals with different amplitude or timing characteristics. In one example, the test system is configured to measure the response from the DUT using a comparator circuit to sense transitions at the DUT pins.

[0003] A system for testing digital integrated circuits (ICs) may include a driver circuit configured to provide multiple voltage levels (e.g., Vhigh, Vlow, and Vterm) to a DUT. The DUT may exhibit bidirectional (I / O) capabilities in that the DUT can both source and receive stimulus. The Vhigh and Vlow levels of the driver circuit serve to stimulate the DUT during the driver circuit's "input" state, while the Vterm acts as a termination for the DUT during the driver circuit's "output" state. The process of switching between Vhigh, Vlow, and Vterm may be conceptualized as a set of three switches, each with one terminal connected to either Vhigh, Vlow, or Vterm, and the other terminal connected to a 50Ω resistor that is connected to a DUT node. Transitions between the three levels may be achieved by opening and closing the appropriate switches, such as closing only one switch at any given time.

[0004] In one example, the test system includes an amplifier or comparator that includes a transconductance circuit (also referred to as a "transconductor" or "voltage-to-current converter"). A transconductance circuit is a circuit that generates an output current that corresponds to or is proportional to an input voltage. Therefore, such a circuit may be referred to as a voltage-to-current converter.

[0005] Various comparator circuit structures have been proposed. Some offer improved latch accuracy or improved bandwidth capabilities for operations such as high-speed sampling in applications involving analog-to-digital converters or automatic test equipment (ATE). In one example, a comparator circuit includes an AC input node, a DC input node, and an output node. In an example involving a comparator in a circuit configured to perform automatic testing of a DUT, the AC input node may be coupled to a DUT interface node, and the DC input node may be coupled to a reference node to receive a reference voltage signal. Signal changes at the output node of the comparator circuit can provide information regarding the relationship between the DUT output and the reference voltage signal. Summary of the Invention [Problem to be solved by the invention]

[0006] The inventors have recognized that the problem to be solved includes providing a gain stage having high gain, large differential voltage compliance, and high bandwidth characteristics, which may optionally be used in a comparator or other automatic test equipment. [Means for solving the problem]

[0007] In one example, the solution may include or use a system including a transconductance circuit having a negative feedback transistor. In some examples, the transconductance circuit having a negative feedback transistor may be used as a transconductance input stage of an amplifier stage, the transconductance input stage configured to convert an input voltage signal to an output current signal. In some examples, the amplifier stage may further include a load stage configured to convert the output current of the input stage back to an output voltage. One or more of such amplifier stages may be included in a device such as an amplifier or a comparator.

[0008] In one example, the transconductance stage can include a first follower circuit coupled to a first input node, a second follower circuit coupled to a second input node, and a pass stage circuit providing a tunable impedance signal path coupling the first follower circuit and the second follower circuit. The transconductance stage can further include or use a control circuit configured to receive a first input signal from the first input node and a second input signal from the second input node, and in response, provide a control signal to the pass stage circuit to control the impedance of the signal path coupling the first follower circuit and the second follower circuit.

[0009] This summary is not intended to provide an exclusive or exhaustive description of the invention. The detailed description is included to provide further information regarding this patent application.

[0010] To easily identify the discussion of any particular element or act, one or more of the most significant digits of a reference number will refer to the figure number in which that element is first introduced. [Brief explanation of the drawings]

[0011] [Figure 1] 1 generally illustrates an example of a first test system including a pin driver. [Figure 2] 1 generally illustrates an example of a multi-stage comparator circuit. [Figure 3] 1 generally illustrates an example of a first transconductance circuit. [Figure 4] 1 generally illustrates an example of a second transconductance circuit. [Figure 5] 1 generally illustrates an example of a third transconductance circuit. [Figure 6] 1 generally shows an example of a gate drive circuit. [Figure 7] Generally, an example method for controlling the gain and bandwidth characteristics of a gain stage circuit is presented. DETAILED DESCRIPTION OF THE INVENTION

[0012] The test system's automatic test equipment (ATE) pin electronics integrated circuit can use pin drivers to provide voltage pulse stimuli to a device under test (DUT) at specified times, and can optionally use comparators to measure response signals from the DUT. The test system can be configured to provide high-fidelity output signal pulses over a relatively large range of output signal magnitudes to accommodate various tests and various types of devices under test.

[0013] In one example, the test system can include a pin driver architecture that can provide high-fidelity stimulus signals with minimal overshoot or spikes in high-frequency signals and can improve pulse edge placement accuracy and signal bandwidth at high or low power supply operating levels. In one example, the test system can include one or more driver stages, such as a Class A driver stage or a Class AB driver stage, that can be configured to provide a variety of pulse signals. The system can include control circuitry for precisely adjusting the switching voltage and current signals and for controlling the operating modes and monitoring or measurement activities of the comparators.

[0014] In one example, multiple drivers or driver stages can be used to provide a test system that is configurable to test a variety of semiconductor devices with different voltage and speed requirements. Additionally, multiple drivers can be used to enhance or enable multiple signal level testing or signal level "multiplexing" for physical layer testing. During physical layer testing, multiple drivers can be switched simultaneously to provide different stimulus or drive signals to the DUT.

[0015] In one example, a pin driver stage of a test system comprises part of the interface between the tester and the DUT. The pin driver stage can be responsible for establishing the timing accuracy of the test system. That is, the pin driver stage can be configured to accurately deliver DUT stimulus signal edges substantially independent of environmental or other factors. In some examples, the pin driver stage is configured to support higher frequency, lower voltage current stimulus signals and lower frequency, higher voltage stimulus signals. In one example, the pin driver stage maintains a particular characteristic impedance (e.g., 50 Ω) that is optimized for bandwidth and timing accuracy. The characteristic impedance can be matched, for example, to the impedance of a transmission line coupling the test system to the DUT.

[0016] The test system may include a comparator circuit or stage configured to receive a high-speed, high-voltage response signal from the DUT. A comparator is generally a decision-making element that provides information regarding the relationship between at least two input signals. For example, a comparator may provide a digital output (e.g., a logic high signal or a logic low signal) that indicates the relationship between the signal from the DUT and a reference signal, such as a reference voltage signal. The comparator may include one or more gain stages, which may be coupled in series to provide a high-gain response.

[0017] The present inventors have recognized that a problem to be solved includes providing a gain stage with high gain, large differential voltage compliance, and high bandwidth characteristics. This problem includes providing a differential gain stage with high tolerance to large common-mode (CM) and differential-mode (DM) input voltages. The present inventors have recognized that a problem with standard differential pair gain stages, such as those that can use DMOS devices (e.g., double-diffused MOSFET devices), is that while the differential pair can handle a large CM range, the gain stage can be limited by a relatively low (e.g., 5 V) Vgs (gate-source voltage) limit beyond which device damage can occur. This limit means that while DMOS devices can withstand high Vdg (drain-gate voltage), they have low Vgs tolerance, resulting in a circuit that can handle high CM voltages but has very little DM voltage tolerance. Furthermore, the present inventors have recognized that using a high-voltage diode at the tail node (e.g., provided in series with the source of the DMOS device comprising the differential pair) to improve CM tolerance is not always possible because not all processes provide high-voltage diodes. Other solutions that use transistors at the tail node (e.g., in series with the differential pair device sources; see FIG. 4 ) to achieve high CM and DM voltage tolerance can result in low gain and low bandwidth. Specifically, with transistor-based approaches, achieving high gain requires the use of physically large transistors, which capacitively load the positive and negative inputs and reduce the bandwidth of the gain stage, while achieving high bandwidth requires physically small transistors, which reduce gain. The inventors have recognized that solutions to these problems and limitations can include or use gate drive circuits to control transistors at the tail node. By controlling the operation of these transistors, the CM and DM voltage tolerance can be improved and high gain and high bandwidth can be achieved.

[0018] FIG. 1 illustrates a first exemplary test system 100 generally illustrating a test system topology including multiple driver stages, loads, and comparator stages. The first exemplary test system 100 includes a driver system including a first driver AB 102, which may include a Class AB driver circuit, and a first driver A 104, which may include a Class A driver circuit. The first exemplary test system 100 may further include an output element, such as a first resistor 106, that may be configured to provide a specified output or load impedance. In one example, the first exemplary test system 100 includes a first load circuit 108, which may include a comparator circuit 122 or an active load or other load device. In one example, the test system is configured to provide a first output current 120, i_OUT, at a DUT interface or DUT node 132. The DUT node 132 may be coupled to a DUT 124 using a loaded signal path 134. In some examples, the first resistor 106 and the loaded signal path 134 have matching impedance characteristics.

[0019] In one example, the first driver AB102 can be configured to generate a voltage stimulus signal by selecting between parallel-connected diode bridges, with each bridge driven by a unique, dedicated DC voltage level. In the first exemplary test system 100 of FIG. 1, DC voltages Vih 110 and Vil 112 drive the diode bridges in the first driver AB102. The switching stage can be followed by a voltage buffering stage that can provide power gain, such as can be used to generate large currents to serve a 50Ω DUT environment.

[0020] In contrast to first driver AB102, first driver A104 may be configured to generate transitions at DUT node 132 using a relatively large current switching stage, which may be directly coupled to DUT node 132. The current switching stage of first driver A104 may alternately switch current to and from DUT node 132 in response to a control signal Swing 118, which may be a voltage control signal. First driver A104 may provide high-speed operation because, for example, a class AB voltage buffering stage, with its associated bandwidth and other performance limitations, may not burden first driver A104.

[0021] In one example, the first driver A104 may be configured to provide a relatively low amplitude signal at the DUT node 132. For example, the first driver A104 may provide a signal having a swing of approximately 2 volts. The first driver AB102 may be configured to provide a relatively high amplitude signal at the DUT node 132, for example, between −1.5 and +7 volts. The first driver A104 generally operates at a higher switching speed or bandwidth than the first driver AB102. In one example, the first driver AB102 may be configured to absorb switching current from the first driver A104. That is, the first driver AB102 may act as a buffer through which the first driver A104 can source current, such as through the first resistor 106.

[0022] One or both of the first driver AB102 and the first driver A104 can be selected to meet disparate DUT test requirements that may not be met by a single driver. For example, while both driver circuits can provide DUT waveforms, the first driver AB102 can be configured to provide a larger amplitude, lower bandwidth stimulus signal, and the first driver A104 can be configured to provide a lower amplitude, higher bandwidth stimulus signal. In other examples, a single driver (e.g., the first driver AB102) can be used.

[0023] In one example, first driver AB102 and first driver A104 do not share an enable pin. Instead, each driver circuit includes independent enable control through pins EnAB114 and EnA116. The independent enable control facilitates first driver AB102 acting as a slow, high-voltage stimulus source and as a static, non-transitional buffer to absorb switching current from first driver A104.

[0024] 1 includes a comparator circuit 122. The comparator circuit 122 may include a single-stage or multi-stage comparator configured to receive a signal from a DUT 124, such as via a DUT node 132 and a load signal path 134. The comparator circuit 122 may compare the received signal to a comparator reference signal 128 (e.g., Vth) and, in response, provide a differential comparator output signal 130 (e.g., OP). For example, the comparator circuit 122 may receive a voltage response signal from the DUT 124 and compare the amplitude of the voltage response signal to the amplitude of the comparator reference signal 128. The comparator circuit 122 may use the differential comparator output signal 130 to provide information regarding an amplitude relationship, such as may include a digital or logic output signal.

[0025] 2 generally illustrates an example comparator 200 that may include a comparator circuit 122. The comparator circuit 122 may include a comparator input node 210, a reference signal input node 212, a first output node 214, and a second output node 216. The comparator circuit 122 may include multiple different circuit stages provided in series. For example, the comparator circuit 122 may include a comparison stage 206, one or more gain stages, such as a first gain stage 202 through an nth gain stage 208, and an output stage 204.

[0026] In one example, the comparison stage 206 may be configured to receive information from the DUT 124 from the DUT node 132, such as via the load signal path 134, using a comparator input node 210. The comparison stage 206 may receive a comparator reference signal 128Vth using a reference signal input node 212. Generally, the comparison stage 206 is configured to perform a signal comparison operation to determine which of the signals at the comparator input node 210 and the reference signal input node 212 has a larger or smaller signal amplitude characteristic, such as at a particular or specified time. A comparison result or output of the comparison stage 206 may be provided to the first gain stage 202. In one example, the comparison result includes a differential signal or a logic signal, i.e., a signal having two signal components.

[0027] In one example, comparison stage 206 includes a differential amplifier that amplifies the differential voltage received at comparator input node 210 and reference signal input node 212 and suppresses common-mode signal components. Various other comparison stage 206 circuits can be used, such as including one or more of the comparators described by McQuilkin in U.S. Patent No. 9,813,050, entitled "Comparator Circuit with Input Attenuator." The decision circuit of comparison stage 206 can include, among other things, a differential pair that reports when the DUT signal crosses a reference signal voltage, Vth, but can also serve as a level shifter that allows subsequent gain stages to operate below ground, such as to conserve power.

[0028] The first gain stage 202 can include various gain or amplifier circuits. That is, the first gain stage 202 can include an amplifier circuit, such as an operational amplifier, or other arrangement or configuration of transistors or other circuitry for performing signal amplification or signal buffering. Multiple gain stage entities can be provided in series, with each gain stage further amplifying or buffering the output of the preceding gain stage. In the example of FIG. 2 , the first gain stage 202 provides a first gain stage output signal to one or more intermediate gain stages, which in turn provide a gain stage output using the final or nth gain stage 208. The nth gain stage 208 can be configured to provide an output signal to a relatively high input impedance receiver in the output stage 204. In response, the output stage 204 can provide the output signal to a low-impedance environment. The various gain stages, such as the first gain stage 202, the nth gain stage 208, and any one or more intermediate gain stages, can be configured identically or differently.

[0029] In one example, output stage 204 provides differential comparator output signal 130 including first signal component Q and second signal component Qb at first output node 214 and second output node 216, respectively. That is, the comparator stage output signal components may be used to provide a digital output signal indicative of the magnitude relationship between the input signals received at comparator input node 210 and reference signal input node 212.

[0030] FIG. 3 generally illustrates an example of a first amplifier stage 302. The first amplifier stage 302 can include a first transconductance circuit 304 having multiple follower circuits. In the example of FIG. 3, the first transconductance circuit 304 includes a pair of source follower circuits arranged as a differential pair. In one example, the first amplifier stage 302 includes a comparator or amplifier, such as the comparison stage 206 of the example comparator 200 of FIG. 2. The first amplifier stage 302 can be a first preamplifier stage and can be followed by one or more other gain stages. In the example of FIG. 3, the first amplifier stage 302 can include a load circuit 306, which can provide an output to a subsequent gain stage or output stage.

[0031] The example of Figure 3 shows a first input transistor MP that includes a portion of a first follower circuit and a second input transistor MM that includes a portion of a second follower circuit. In one example, the input transistors MP and MM comprise a differential pair circuit. Each of the input transistors MP and MM can include a respective high-voltage transistor (e.g., an LDMOS transistor). The common-mode voltage range of the differential pair can be equal to the LDMOS drain-source (DS) breakdown voltage (BV), or BVDS (e.g., 24V or greater). However, the differential input voltage range can be approximately equal to the gate-source breakdown voltage plus the gate-source voltage, or VGS (e.g., 6V).

[0032] In the first transconductance circuit 304, one terminal of the first input transistor MP (e.g., the gate terminal of transistor MP) is coupled to the first input 308, where the first input transistor MP receives a first input voltage VIP. One terminal of the second input transistor MM (e.g., the gate terminal of transistor MM) is coupled to the second input 310, where the second input transistor MM receives a second input voltage VIM. A second terminal of the first input transistor MP (e.g., the drain terminal of transistor MP) is coupled to the first output 312 for providing a first output current IOP, and a second terminal of the second input transistor MM (e.g., the drain terminal of transistor MM) is coupled to the second output 314 for providing a second output current IOM. A third terminal of the first input transistor MP (e.g., the source terminal of transistor MP) is coupled to the third terminal of the second input transistor MM (e.g., the source terminal of transistor MM), for example, via an intermediate node NCM. For each of transistors MP and MM, the source terminal of the transistor may be coupled to the back gate terminal of the transistor.

[0033] In one example, the first transconductance circuit 304 may include a first current source 316 and a second current source 318. The first current source 316 may be coupled to a source terminal of the first input transistor MP, and the second current source 318 may be coupled to a source terminal of the second input transistor MM. The first current source 316 and the second current source 318 jointly provide a total tail current IT to the differential pair of input transistors MP and MM of the first transconductance circuit 304. In one example, the first current source 316 and the second current source 318 each provide a tail current IT / 2.

[0034] In some examples, the first transconductance circuit 304 includes a portion of a comparator circuit such as may be included in the example comparator 200. In this case, VIP and VIM may be inputs to the comparator. The inputs may be provided or driven by an external source, such as a DUT. Thus, the first transconductance circuit 304 may be configured to evaluate the difference between the voltage levels of the inputs VIP and VIM and generate an output current representing whether the difference is positive or negative (e.g., to generate a logic 1 or logic 0 output indicating whether the difference between the voltage levels of the inputs VIP and VIM is positive or negative). For example, if the difference IOP−IOM is positive, then the difference VIP−VIM is positive, and if the difference IOP−IOM is negative, then the difference VIP−VIM is negative. The magnitude of the difference between IOP and IOM may be a function of the difference in magnitude between VIP and VIM.

[0035] In one example, the first transconductance circuit 304 includes an amplifier such as may be used in a feedback circuit. Such an example of the first transconductance circuit 304 may be configured to substantially equalize the inputs VIP and VIM by modifying the outputs IOP and IOM, which may then be coupled to the amplifier inputs through a feedback path.

[0036] A problem with the first transconductance circuit 304 can arise because the voltage at the NCM node is set by the one of the input transistors MP and MM that has the highest input voltage at its gate. When the differential pair of input transistors MP and MM fully switches the tail current IT to a particular one of the first output 312 and the second output 314, the turned-off input transistor (i.e., the one of the input transistors MP and MM that has the lowest input signal at its gate terminal) may experience gate breakdown at its source terminal boundary. For example, when the first transconductance circuit 304 is used in a comparator (e.g., a high-voltage comparator), the minimum and maximum levels of the difference between VIP and VIM may exceed the gate oxide reliability voltage ratings of the input transistors MP and MM. When the first transconductance circuit 304 is used in an amplifier, and the amplifier input signal range is greater than the breakdown ratings of the input transistors MP and MM, the amplifier may have the same reliability issues as a high-voltage comparator. During steady state, such as when the amplifier settles to its final output level or waveform, the two inputs VIP and VIM will be substantially equal and will not have reliability issues, but the inputs VIP and VIM may differ significantly at the beginning of settling, which may cause reliability issues for the amplifier. Therefore, the differential pair-based first transconductance circuit 304 may be insufficient or unreliable for high-voltage applications.

[0037] 4 generally illustrates an example of a second transconductance circuit 404 that includes a differential pair in a second amplification stage 402. In one example, the second amplification stage 402 includes a comparator or amplifier, such as may include the comparison stage 206 of the example comparator 200. The second amplification stage 402 may be a first preamplifier stage and may be followed by one or more other gain stages.

[0038] 4 shows a differential pair of input transistors MP and MM including respective follower circuits, where each of the input transistors can include a high-voltage transistor (e.g., an LDMOS transistor). The common-mode voltage range of the input differential pair is equal to the LDMOS BVDS, e.g., 24 volts (V). However, the differential input voltage range can be approximately equal to the gate-source breakdown voltage plus the gate-source voltage (VGS) (e.g., about 6 V).

[0039] In the second transconductance circuit 404, similarly to the first transconductance circuit 304, one terminal of a first input transistor MP (e.g., the gate terminal of transistor MP) is coupled to a first input 308, where the first input transistor MP receives a first input voltage VIP. One terminal of a second input transistor MM (e.g., the gate terminal of transistor MM) is coupled to a second input 310, where the second input transistor MM receives a second input voltage VIM. A second terminal of the first input transistor MP (e.g., the drain terminal of transistor MP) is coupled to a first output 312 for providing a first output current IOP, and a second terminal of the second input transistor MM (e.g., the drain terminal of transistor MM) is coupled to a second output 314 for providing a second output current IOM.

[0040] In contrast to the example of the first transconductance circuit 304 from FIG. 3, the second transconductance circuit 404 in FIG. 4 includes a first pass stage circuit 424. The first pass stage circuit 424 is configured to provide an adjustable impedance signal path coupling the first follower circuit and the second follower circuit or the first input transistor MP and the second input transistor MM. The first pass stage circuit 424 includes a first negative feedback transistor MDP and a second negative feedback transistor MDM. The first negative feedback transistor MDP and the second negative feedback transistor MDM can function as a nonlinear negative feedback resistor.

[0041] 4, the third terminal of the first input transistor MP (e.g., the source terminal of transistor MP) is coupled to the third terminal of the first negative feedback transistor MDP (e.g., the source terminal of the first negative feedback transistor MDP, which is coupled to the backgate terminal of the first negative feedback transistor MDP). The third terminal of the second input transistor MM (e.g., the source terminal of transistor MM) is coupled to the third terminal of the second negative feedback transistor MDM (e.g., the source terminal of the second negative feedback transistor MDM, which is coupled to the backgate terminal of the second negative feedback transistor MDM). The second terminal of the first negative feedback transistor MDP (e.g., the drain terminal of the first negative feedback transistor MDP) is coupled to the second terminal of the second negative feedback transistor MDM (e.g., the drain terminal of the second negative feedback transistor MDM) at node NCM. A first terminal of the first negative feedback transistor MDP (e.g., the gate terminal of the first negative feedback transistor MDP) is coupled to a first input 308 through which the first negative feedback transistor MDP receives a first input voltage VIP, while a first terminal of the second negative feedback transistor MDM (e.g., the gate terminal of the negative feedback transistor MDM) is coupled to a second input 310 through which the second negative feedback transistor MDM receives a second input voltage VIM.

[0042] In operation of the second transconductance circuit 404, each of the first input transistor MP and the second input transistor MM can operate in the saturation region. The first negative feedback transistor MDP and the second negative feedback transistor MDM can be configured to operate in either the linear (triode) region or the saturation region. In some examples, when one of the negative feedback transistors MDP and MDM enters the saturation region, the other negative feedback transistor can continue to operate in the linear region.

[0043] During operation of the second transconductance circuit 404, the negative feedback resistor at the source terminal of the first negative feedback transistor MDP (e.g., node NCMP shown in FIG. 4) and the negative feedback resistor at the source terminal of the second negative feedback transistor MDM (e.g., node NCMM) may be symmetrical with respect to the input signal difference between VIP and VIM, i.e., ΔVI. That is, the resistance between nodes NCMP and NCMM may change according to changes in the applied input signal difference VIP-VIM. The value of this resistor may correspondingly change the value of the transconductance GM, and the change is symmetrical in that GM(VIP-VIM)=GM(VIM-VIP). Therefore, the second transconductance circuit 404 may generate the same output currents IOP and IOM when a voltage difference of 100 mV or −100 mV is applied to the inputs VIP and VIM.

[0044] In one example, the total negative feedback resistance between nodes NCMP and NCMM may be minimum when the first input voltage VIP is substantially equal to the second input voltage VIM. Furthermore, the equivalent resistance between the source terminal of the first negative feedback transistor MDP and the source terminal of the second negative feedback transistor MDM may increase as the absolute value (or magnitude) of the difference between the input voltages VIP and VIM increases. When the negative feedback transistor whose gate terminal is coupled to the lowest input voltage (which may be either the first negative feedback transistor MDP or the second negative feedback transistor MDM) transitions into the saturation region, the positive signal processing portion and the negative signal processing portion of the second transconductance circuit 404 are effectively isolated from each other. Therefore, the exemplary input stage may not require a protection device for high voltage protection and is self-protected.

[0045] Next, we will consider the aspect ratios of various transistors included in the transconductance circuit. x ) is the channel length of the FET (l x ) for the channel width (w x) In some embodiments of the transconductance circuit, the ratio of the aspect ratio of the first negative feedback transistor MDP to the aspect ratio of the first input transistor MP may be substantially equal to the ratio of the aspect ratio of the second negative feedback transistor MDM to the aspect ratio of the second input transistor MM. In some embodiments, the aspect ratio of the first input transistor MP may be substantially equal to the aspect ratio of the second input transistor MM, or equivalently, the aspect ratio of the first negative feedback transistor MDP may be substantially equal to the aspect ratio of the second negative feedback transistor MDM. For example, the aspect ratio of each of the first input transistor MP and the second input transistor MM may be approximately 1, while the aspect ratio of each of the first negative feedback transistor MDP and the second negative feedback transistor MDM may be approximately N, where N is any positive real number. However, in other embodiments, these aspect ratios may be different, as long as the ratio of the aspect ratios of the first negative feedback transistor MDP and the first input transistor MP is substantially equal to the ratio of the aspect ratios of the second negative feedback transistor MDM and the second input transistor MM.

[0046] 4, the first and second negative feedback transistors MDP and MDM reduce the equivalent transconductance GM of the differential pair of the first and second input transistors MP and MM. It can be shown that the equivalent transconductance GM for ΔVI=0 can be reduced by N / (1+N). Thus, for N=4, the equivalent transconductance GM can be reduced to 80% of its value compared to the zero negative feedback case at the same power level.

[0047] When one of the first and second negative feedback transistors MDP and MDM enters the saturation region, the drain current of the corresponding input transistor reaches a minimum drain current level, substantially equal to IT / 2*(N+1). The remainder of each input-side tail current can then be transported to the complementary input half through the negative feedback transistor operating in the saturation region. Under this condition, the ratio of the output currents can be substantially equal to 2N+1. If desired, these values can be arbitrarily set by appropriately selecting the ratio between the aspect ratio of the input transistor and the aspect ratio of the negative feedback transistor, i.e., by selecting N.

[0048] In some examples, a high small-signal gain and small input signal difference for total tail current switching objectives may favor a relatively large N value, while a reduced large-signal overdrive and reduced delay variation objectives related to NCMP / NCMM node capacitance may favor a relatively small N value. The exact value of N used for the transistors in the second transconductance circuit 404 may be determined, for example, using simulation. In some implementations, it can be shown that when N is selected to be approximately 1.5 or greater, when one of the first negative feedback transistor MDP and the second negative feedback transistor MDM enters the saturation region, the other negative feedback transistor remains in its linear operating region. A large voltage drop between the NCMP node and the NCMM node may appear primarily across the drain-source terminals of the negative feedback transistor operating in the saturation region.

[0049] Therefore, the second transconductance circuit 404 is substantially symmetrical about the input terminal and can therefore process both single-ended and differential input signals. By including the first and second negative feedback transistors MDP and MDM, the second transconductance circuit 404 can operate up to the BVDS of the transistors included in the second transconductance circuit 404 without reliability issues and in the absence of additional protection mechanisms.

[0050] However, the inventors have recognized that the second transconductance circuit 404, while providing high common-mode and differential-mode voltage tolerances, exhibits relatively low gain and low bandwidth. For example, high gain generally requires the use of physically large implementations of the first and second negative feedback transistors MDP and MDM, which capacitively load the first and second inputs 308 and 310, respectively, reducing the bandwidth of the circuit. Conversely, high bandwidth generally requires the use of physically small implementations of the first and second negative feedback transistors MDP and MDM, reducing the gain of the circuit. Thus, the circuit may not simultaneously achieve high gain and high bandwidth, which is undesirable for an ideal gain stage. The inventors have recognized that a solution to these and other problems may include or utilize gate drive circuits to control the operation of the first and second negative feedback transistors MDP and MDM, thereby more closely approximating the behavior of an ideal gain stage.

[0051] The gate drive circuits discussed herein improve gain stage circuits, providing improvements in both common-mode (CM) and differential-mode (DM) voltage tolerance. These circuits achieve this improvement, for example, by actively controlling the gate voltage of the pass stage transistors to maximize the Vgs of the pass transistors. The gate drive circuits establish the Vgs of the pass transistors at the maximum voltage allowed by a given process, minimizing the impedance of the pass transistors in their linear region and thus maximizing gain. Minimizing the impedance of the pass transistors in their linear region allows the size of the pass transistors to be reduced, thereby increasing bandwidth while maintaining sufficient gain. The gate drive circuits can also provide a buffering function, such as by isolating the load effect of the pass transistor from the input node. Thus, the gate drive circuits discussed herein help optimize circuit function by enabling bandwidth and gain manipulation while providing an excellent gain-bandwidth product.

[0052] In one example, the gate drive circuit ensures that the pass stage transistor operates at its maximum gate-source voltage (Vgs) by providing an offset voltage to the gate of the pass stage transistor while preventing Vg from exceeding a maximum threshold that could lead to device damage.

[0053] The gate drive circuitry enables the pass stage transistors to smoothly transition between linear and saturation regions of operation based on the differential input signals. When the inputs are substantially equal, the gate drive circuitry keeps the pass stage transistors in the linear region, where they act as a low-impedance path and enable high transconductance and high bandwidth. When the inputs are unequal, the gate drive circuitry forces one of the pass stage transistors into the saturation region, effectively making it a current source that holds off the differential voltage across the drain-gate junction of that pass stage transistor. This allows the circuit to withstand large differential input voltages without risk of exceeding the voltage rating of the transistors.

[0054] By decoupling the input signal from the direct control of the pass stage transistors, the gate drive circuit also reduces capacitive loading effects, thereby providing a superior gain-bandwidth product over other solutions. This decoupling is achieved through the buffering provided by the gate drive circuit, which isolates the pass stage transistors from input signal variations and associated capacitive effects.

[0055] In summary, the gate drive circuit provides the following dual functions: it buffers the pass stage transistors from the input signal while helping to establish optimal pass stage transistor Vgs characteristics, thereby maximizing gain and bandwidth performance. This, combined with the inherent voltage handling advantages of DMOS devices, results in a gain stage circuit with improved CM and DM voltage tolerance and an improved gain-bandwidth product, making the gain stage circuit highly suitable for applications requiring robust performance over a wide range of operating conditions.

[0056] 5 generally illustrates an example of a third transconductance circuit 504 having a follower circuit configured as a differential pair in a third amplification stage 502. In one example, the third amplification stage 502 includes a comparator or amplifier, such as may include the comparison stage 206 of the example comparator 200. The third amplification stage 502 may be a first preamplifier stage and may be followed by one or more other gain stages.

[0057] The example of the third transconductance circuit 504 in FIG. 5 can include the same or similar components as the second transconductance circuit 404 from the example of FIG. 4. However, the third transconductance circuit 504 includes a second pass stage circuit 510 configured to provide an adjustable impedance signal path between the follower circuits. The second pass stage circuit 510 includes a control circuit 512. The control circuit 512 is configured to receive a first input signal from the first input 308 and a second input signal from the second input 310, and in response, provide one or more control signals to the second pass stage circuit 510 to control the impedance of the signal path coupling the first follower circuit and the second follower circuit. In one example, the control circuit 512 includes a first gate drive circuit 506 and a second gate drive circuit 508.

[0058] The first gate drive circuit 506 is configured to receive the signal VIP from the first input 308 and, in response, provide a first drive signal to the first negative feedback transistor MDP. The second gate drive circuit 508 is configured to receive the signal VIM from the second input 310 and, in response, provide a second drive signal to the second negative feedback transistor MDM. The first drive signal and the second drive signal can be the same or different signals. The gate drive circuits buffer the differential inputs of the third transconductance circuit 504 and, in some examples, are configured to provide an offset to the respective signals controlling the negative feedback transistors MDP and MDM.

[0059] A first and a second operational example are provided to illustrate various functions and advantages of the third transconductance circuit 504. In the first operational example, the third transconductance circuit 504 can receive signals of substantially equal magnitude, such as signals having the same polarity, at the first input 308 and the second input 310. When the input signals are substantially equal, the voltage difference between the input nodes is within a threshold difference amount that controls the behavior of the pass stage circuitry such that the third transconductance circuit 504 exhibits desired gain and / or bandwidth characteristics.

[0060] In one example, each input can receive a +10V signal. The first gate drive circuit 506 can be configured to receive a signal from the first input 308 and provide a corresponding first offset signal at the gate of the first negative feedback transistor MDP. Similarly, the second gate drive circuit 508 can be configured to receive a signal from the second input 310 and provide a corresponding second offset signal at the gate of the second negative feedback transistor MDM. In one example, the first offset signal can be 10V+Voffset, and the second offset signal can be a similar or identical value.

[0061] In one example, Voffset can be selected to minimize the resistive characteristics of the negative feedback transistor. For example, Voffset can be selected to cause the negative feedback transistor to achieve its minimum linear region resistance. When a transistor operates in its linear region, it behaves similarly to a variable resistor. For n-channel MOSFETs such as transistors MDP and MDM, the linear region occurs when the gate-source voltage (Vgs) is greater than the threshold voltage (Vth) but the drain-source voltage (Vds) is less than the gate-source voltage minus the threshold voltage (Vgs-Vth). In this region, the current flowing through the MOSFET is linearly related to the drain-source voltage, and the device can be used to control the current flow like a resistor. The impedance of a transistor in the linear region is important because the impedance affects the circuit gain. In a first example of operation, the linear-mode impedance of the negative feedback transistors MDP and MDM can be minimized by increasing the offset voltage provided by the gate drive circuit to the maximum allowable process Vgs, which in turn helps improve the performance of the gain stage. Furthermore, using the first gate drive circuit 506 and the second gate drive circuit 508 to isolate the negative feedback transistors MDP and MDM from the first input 308 and the second input 310, respectively, helps reduce the capacitive load on the inputs and increase the bandwidth of the third amplifier stage 502.

[0062] In a second example of operation, the third transconductance circuit 504 can receive unequal magnitude signals at the first input 308 and the second input 310. For example, the first input 308 can receive a +10V signal, and the second input 310 can receive a signal of a different magnitude or can be coupled to a reference, such as 0V. In this example, the first gate drive circuit 506 can provide a first offset signal that is 10V + Voffset, and the second gate drive circuit 508 can provide a second offset signal that is 0V + Voffset. Offset signals of the same or different magnitudes can be used by each of the gate drive circuits. In the second example of operation, the negative feedback transistor with the lower gate voltage (e.g., the second negative feedback transistor MDM) maintains its maximum gate-source voltage Vgs. At the same time, the drain-source voltage across this transistor increases due to the increasing source voltage at the NCM node, which is a function of the first gate drive circuit 506 and the operating mode (triode) of the first negative feedback transistor MDP. When the drain-source voltage Vds of the second negative feedback transistor MDM is large enough, the second negative feedback transistor MDM transitions from the linear region to the saturation region. In the saturation region, the second negative feedback transistor MDM behaves more like a current source than a variable resistor, and the second negative feedback transistor MDM is configured to "hold off" the differential voltage across its gate-drain (Vdg) junction. This behavior allows the circuit to withstand high DM voltages. In other words, the transition of the second negative feedback transistor MDM from the linear region to the saturation region due to a change in Vds while the second gate drive circuit 508 provides a constant voltage at the gate of the second negative feedback transistor MDM helps to enable improved gain and bandwidth characteristics of the third transconductance circuit 504.

[0063] A gate drive circuit, such as the first gate drive circuit 506 or the second gate drive circuit 508, can be implemented in various ways to achieve the gain stage performance advantages described herein. The gate drive circuit can be configured to decouple gain and bandwidth performance characteristics so that high gain can be achieved without sacrificing bandwidth, and high bandwidth can be achieved without sacrificing gain. Because the gate drive circuit is configured to buffer the input or gate terminal of the negative feedback transistor, the gate drive circuit can be used to help reduce the capacitive load on the gain stage input. By decoupling the negative feedback transistor from the gain stage input, the capacitive load can be reduced and higher bandwidth can be achieved.

[0064] The gate drive circuit can be configured to provide an offset voltage at the input of the negative feedback transistor, which allows for minimizing the triode impedance of the device. For example, by arbitrarily increasing the offset voltage (e.g., within the limits of the process-defined maximum Vgs), the impedance of the negative feedback transistor in the triode region can be arbitrarily reduced, which helps improve bandwidth performance.

[0065] In one example, the small signal gain of the circuit can be affected by the impedance characteristics of the negative feedback transistor when the transistor operates in its linear region. When the gate drive circuit provides an offset, the resistance of the negative feedback transistor can be minimized, thus improving the small signal gain.

[0066] Therefore, the gate drive circuit helps to give the designer more flexibility in optimizing the gain and bandwidth performance of the gain stage. In other words, applying the gate drive circuit helps to improve the performance of the gain stage, and the performance approaches ideal operation by simultaneously enabling high gain, high bandwidth, and high tolerance to CM and DM operating voltages.

[0067] 6 generally illustrates an example of a gate drive circuit 600, which may include a first gate drive circuit 506 or a second gate drive circuit 508. The gate drive circuit 600 includes a current source 608 and a first PMOS device 610. The current source 608 may be configured to provide a fixed or variable current bias signal at the source terminal of the first PMOS device 610. The gate drive circuit 600 includes an input node 602 coupled to the gate terminal of the first PMOS device 610, and includes a gate drive circuit output node 606 coupled to the source terminal of the first PMOS device 610 and the current source 608. The drain terminal of the first PMOS device 610 may be coupled to a reference node or other circuitry.

[0068] In one example, an input node 602 of the gate drive circuit 600 is coupled to an input of a gain stage. For example, the input node 602 may be configured to receive one of the differential voltage signal inputs at the first input 308 or the second input 310 of the gain stage. In one example, the input node 602 may be coupled to a gate terminal or an input terminal of an input transistor of the gain stage. That is, the input node 602 may be coupled to the first input transistor MP or the second input transistor MM of the third transconductance circuit 504 from the example of FIG. 5 .

[0069] In the example gate drive circuit 600 of FIG. 6, the first PMOS device 610 provides buffering and provides an offset at the source terminal or the gate drive circuit output node 606 due to the device's Vgs characteristics. Any one or more of the inputs or outputs of the gate drive circuit 600 can be buffered separately. Furthermore, other or additional voltage offset elements can be used to adjust the offset provided by the gate drive circuit 600. For example, a resistor can be added in the signal path between the current source 608 and the first PMOS device 610 or at the source of the first PMOS device 610. In another example, one or more series diode devices can be used, or a combination of one or more resistors and one or more diodes can be used.

[0070] In one example, the output node 606 of the gate drive circuit is coupled to the gate terminal or the input terminal of the negative feedback transistor in the gain stage, i.e., the output node 606 of the gate drive circuit can be coupled to the gate terminal of the first negative feedback transistor MDP or the gate terminal of the second negative feedback transistor MDM.

[0071] Other topologies can be similarly used to provide drive signals to the negative feedback transistors of the gain stages, i.e., other circuits or controllers can be used to provide respective control signals to the inputs or gates of the first and second negative feedback transistors MDP and MDM.

[0072] In addition to the PMOS-based gate drive circuit embodiment described in FIG. 6 , various alternative topologies can achieve the same or similar function of providing a controlled offset voltage to the pass stage circuit. One alternative includes using an operational amplifier configured as a voltage follower that provides a low-impedance output to drive the pass stage circuit. The non-inverting input of the operational amplifier can receive the input signal, while a voltage divider or other reference circuit connected to the inverting input establishes the offset. Additionally or alternatively, discrete transistor amplifiers, either BJT or FET, can be arranged in various amplifier topologies, such as common-emitter or common-source, to provide both gain and offset to the input signal.

[0073] Further alternatives include level shifter circuits that adjust the voltage level of the input signal to provide the required offset, which may be implemented using diodes, resistor networks, or dedicated level shifter integrated circuits. A differential amplifier can similarly serve this purpose, with one input receiving the signal and the other a fixed voltage, and the output reflecting the voltage difference. Each topology presents its own set of benefits and considerations, including complexity, cost, power consumption, and accuracy, allowing for a customized solution based on the specific needs of the application.

[0074] 7 generally illustrates an example of a first method 700 that includes operating a gain stage with improved gain and bandwidth characteristics. In one example, the gain stage may include a portion of a comparator circuit, such as may be used in a pin driver or other automatic test equipment (ATE).

[0075] At operation 702, the first method 700 includes receiving a first gain stage input signal and a second gain stage input signal at respective first and second input nodes of respective first and second follower circuits comprising a gain stage. For example, operation 702 may include receiving the input signals as differential voltage inputs at respective input nodes of a differential pair circuit, where the follower circuits include a differential pair circuit.

[0076] At operation 704, the first method 700 includes receiving a first gain stage input signal and a second gain stage input signal at a controller. In one example, the controller includes a first control circuit and a second control circuit that receive the first input signal and the second input signal, respectively. The controller can be configured to receive the input signals and, in response, provide one or more control signals to the pass stage circuitry for controlling the impedance of a signal path coupling the follower circuit.

[0077] At operation 706, the first method 700 includes providing a first control signal to a first portion of the pass stage circuit using a first control circuit. The first control signal may be based on a first gain stage input signal and a first offset. At operation 708, the first method 700 includes providing a second control signal to a second portion of the pass stage circuit using a second control circuit. The second control signal may be based on a second gain stage input signal and a second offset. In some examples, the first offset and the second offset are the same or similar values, while in other examples, the first offset and the second offset may be different.

[0078] In one example, operations 706 and 708 may include generating the respective first and second control signals using respective control circuits or gate drive circuits. The gate drive circuits may be configured to buffer and optionally apply gain (e.g., positive or negative gain) to the input signals. The gate drive circuits may have different topologies exhibiting different buffering or gain characteristics, which may depend at least in part on the particular application or desired flexibility of the gain stage.

[0079] At operation 710, the first method 700 includes controlling an impedance characteristic of a signal path coupling a first follower circuit and a second follower circuit in the pass stage circuit using a first portion and a second portion of the pass stage circuit. The impedance of the signal path can be controlled, for example, by one or more negative feedback transistors provided in the signal path between source terminals of a device including the first follower circuit and the second follower circuit. In one example, the negative feedback transistors are controlled by first and second control signals from a control circuit. That is, operation 710 can include providing a first control signal to a gate terminal of the first negative feedback transistor and a second control signal to a gate terminal of the second negative feedback transistor, the drain terminals of the first and second negative feedback transistors being coupled at an intermediate node. At operation 712, the first method 700 includes providing a gain stage output signal using the first and second follower circuits.

[0080] In one example, when the first control signal and the second control signal (e.g., provided in operations 706 and 708) exceed a threshold voltage value, the signal path coupling the first follower circuit and the second follower circuit has a lower impedance characteristic, and as a result, the gain stage exhibits a high bandwidth processing capability. In one example, when at least one of the first control signal and the second control signal (e.g., provided in operations 706 and 708) does not exceed a threshold voltage value, the signal path coupling the first follower circuit and the second follower circuit has a higher impedance characteristic, and as a result, the gain stage exhibits a high gain capability.

[0081] Various embodiments of a transconductance circuit with a negative feedback transistor as described herein can be implemented in any type of system in which voltage-to-current conversion may be used. An example of such a system is shown in FIG. 2, where the transconductance circuit includes part of an amplifier stage and may further include a load as shown in FIG. 3, FIG. 4, or FIG. 5. Optionally, the transconductance circuit may be followed by one or more other gain stages. In some embodiments, the transconductance circuit may include part of a comparator or amplifier.

[0082] In some examples, the transconductance circuit may be included in a wireless system, such as an RF transmitter in a cellular wireless communication system. In yet other examples, the transconductance circuit may be used in a variable gain amplifier, a continuous time filter, a delta-sigma modulator, or a data converter.

[0083] Furthermore, various embodiments of the transconductance circuit having a negative feedback transistor can be implemented in various electronic devices. Examples of electronic devices can include, but are not limited to, electronic products, components of electronic products such as integrated circuits, vehicle electronics such as automotive electronics, etc. Furthermore, electronic devices can include unfinished products or other intermediate products.

[0084] Various aspects of the present disclosure can help provide solutions to the amplifier stage gain and bandwidth related problems identified herein, as described in the examples below.

[0085] Example 1 is a gain stage circuit comprising: a first follower circuit coupled to a first input node; a second follower circuit coupled to a second input node; a pass stage circuit including an adjustable impedance signal path coupling the first follower circuit and the second follower circuit; and a control circuit configured to receive a first input signal from the first input node and a second input signal from the second input node, and in response, provide a control signal to the pass stage circuit for controlling the impedance of the signal path coupling the first follower circuit and the second follower circuit.

[0086] In Example 2, the subject matter of Example 1 includes a pass stage circuit comprising a first negative feedback transistor and a second negative feedback transistor, wherein the control circuit is configured to provide a first control signal to a gate terminal of the first negative feedback transistor, the first control signal being based on a first input signal, and the control circuit is configured to provide a different second control signal to a gate terminal of the second negative feedback transistor, the second control signal being based on the second input signal.

[0087] In Example 3, the subject matter of Example 2 includes the first follower circuit comprising a first FET device having a gate terminal coupled to the first input node and a source terminal coupled to a source terminal of the first negative feedback transistor, and the second follower circuit comprising a second FET device having a gate terminal coupled to the second input node and a source terminal coupled to a source terminal of the second negative feedback transistor.

[0088] In Example 4, the subject matter of Example 3 includes wherein the drain terminals of the first negative feedback transistor and the second negative feedback transistor are coupled at an intermediate node.

[0089] In Example 5, the subject matter of Examples 2-4 includes, wherein the control circuit is configured to provide the first control signal as a combination of the first input signal and the non-zero offset signal.

[0090] In Example 6, the subject matter of Example 5 includes, wherein the control circuit is configured to provide the second control signal as a combination of the second input signal and the non-zero offset signal.

[0091] In Example 7, the subject matter of Examples 2-6 includes, wherein the control circuit is configured to provide the first control signal and the second control signal as gain-adjusted versions of the first input signal and the second input signal, respectively.

[0092] In Example 8, the subject matter of Examples 2-7 includes the control circuit comprising: a first gate drive circuit configured to receive a first input signal and, in response, provide a buffered first gate drive signal to a gate terminal of the first negative feedback transistor; and a second gate drive circuit configured to receive a second input signal and, in response, provide a buffered second gate drive signal to a gate terminal of the second negative feedback transistor.

[0093] In Example 9, the subject matter of Example 8 includes, when the magnitudes of the first gate drive signal and the second gate drive signal are substantially equal, the first negative feedback transistor and the second negative feedback transistor operate in a linear region and provide a low impedance signal path (e.g., relatively lower than the “high impedance” signal path in Example 10) in the pass stage circuit.

[0094] In Example 10, the subject matter of Examples 8-9 includes, when the magnitudes of the first gate drive signal and the second gate drive signal are not substantially equal, the first negative feedback transistor and the second negative feedback transistor operate in a saturation region to provide a high impedance signal path (e.g., relatively higher than the “low impedance” signal path in Example 9) in the pass stage circuit.

[0095] In Example 11, the subject matter of Examples 1-10 includes, when the magnitudes of the voltage signals at the first input node and the second input node are not substantially equal, the control signal is configured to control the signal path of the pass stage circuit to have low impedance characteristics.

[0096] In Example 12, the subject matter of Examples 1-11 includes, when the voltage signals at the first input node and the second input node are not substantially equal in magnitude, the control signal is configured to control the signal path of the pass stage circuit to have high impedance characteristics.

[0097] Example 13 is a method for controlling gain and bandwidth characteristics of a gain stage circuit in a pin driver system, the method including: receiving a first gain stage input signal and a second gain stage input signal at a first input node and a second input node of a respective first follower circuit and a respective second follower circuit; receiving the first gain stage input signal and the second gain stage input signal at a respective first control circuit and a second control circuit; providing, using the first control circuit, a first control signal based on the first gain stage input signal and a first offset to a first portion of the pass stage circuit; providing, using the second control circuit, a second control signal based on the second gain stage input signal and a second offset to a second portion of the pass stage circuit; adjusting an impedance characteristic of a signal path coupling the first follower circuit and the second follower circuit in response to receiving the first control signal and the second control signal at the pass stage circuit; and providing a gain stage output signal using the first follower circuit and the second follower circuit.

[0098] In Example 14, the subject matter of Example 13 includes wherein the first offset and the second offset are voltage offset signals of the same value.

[0099] In Example 15, the subject matter of Examples 13-14 includes: when the first control signal and the second control signal exceed a threshold voltage value, the signal path coupling the first follower circuit and the second follower circuit has a lower impedance characteristic and the gain stage exhibits a high BW handling capability; and when at least one of the first control signal and the second control signal does not exceed the threshold voltage value, the signal path coupling the first follower circuit and the second follower circuit has a higher impedance characteristic and the gain stage exhibits a high gain capability.

[0100] In Example 16, the subject matter of Examples 13-15 includes wherein providing the first control signal to the pass stage circuit includes providing the first control signal to a gate terminal of the first negative feedback transistor, providing the second control signal to the pass stage circuit includes providing the second control signal to a gate terminal of the second negative feedback transistor, and the drain terminals of the first negative feedback transistor and the second negative feedback transistor are coupled at an intermediate node.

[0101] In Example 17, the subject matter of Examples 13-16 includes where receiving the first gain stage input signal and the second gain stage input signal at the respective first control circuit and the second control circuit includes receiving the first gain stage input signal and the second gain stage input signal at respective gate terminals of respective PMOS devices comprising the control circuit.

[0102] In Example 18, the subject matter of Examples 13-17 includes, in a first control circuit, receiving a first gain stage input signal; providing a buffered copy of the first gain stage input signal to a first input of a summing amplifier; providing an offset signal to a second input of the summing amplifier; and providing a first control signal from an output of the summing amplifier to a first portion of the pass stage circuit.

[0103] Example 19 is a system comprising: a first portion of a transconductance circuit including a first gate drive circuit configured to provide a first gate drive signal to a pass stage circuit based on a first input signal, a first negative feedback transistor of the pass stage circuit configured to receive the first gate drive signal, and a first input transistor coupled to the first negative feedback transistor configured to provide a first output current at a first output node; and a second first portion of the transconductance circuit including a second gate drive circuit configured to provide a second gate drive signal to the pass stage circuit based on a second input signal, a second negative feedback transistor of the pass stage circuit configured to receive the second gate drive signal, and a second input transistor coupled to the second negative feedback transistor configured to provide a second output current at a second output node.

[0104] In Example 20, the subject matter of Example 19 includes wherein the drain terminals of the first negative feedback transistor and the second negative feedback transistor are coupled at an intermediate node.

[0105] In Example 21, the subject matter of Examples 19-20 includes wherein a gate terminal of the first input transistor is configured to receive a first input signal to the transconductance circuit, and a gate terminal of the second input transistor is configured to receive a second input signal to the transconductance circuit.

[0106] A twenty-second embodiment is an apparatus including the mounting means of any one of the first to twenty-first embodiments.

[0107] A twenty-third embodiment is the mounting system of any one of the first to twenty-first embodiments.

[0108] Each of these non-limiting examples may stand alone or may be combined in various permutations or with one or more of the other examples or features discussed elsewhere herein.

[0109] This detailed description includes references to the accompanying drawings, which form a part of the detailed description. The drawings show, by way of illustration, specific embodiments in which the invention may be practiced. These embodiments are also referred to herein as "examples." Such examples may include elements in addition to those shown or described. However, the inventors also contemplate examples in which only the elements shown or described are provided. The inventors contemplate examples using any combination or permutation of those elements (or one or more aspects thereof) shown or described, either with respect to a particular example (or one or more aspects thereof) or with respect to other examples (or one or more aspects thereof) shown or described herein.

[0110] In this document, the terms "a" or "an" are used, as is common in patent documents, to include one or more than one, independently of other instances or uses of "at least one" or "one or more." In this document, the term "or" is used to refer to a non-exclusive or, unless otherwise specified, such that "A or B" includes "A but not B," "B but not A," and "A and B." In this document, the terms "including" and "wherein" are used as plain English equivalents of the respective terms "comprising" and "wherein."

[0111] In the following claims, the terms "comprises" and "comprises" are open-ended, i.e., systems, devices, articles, compositions, formulations, or processes that include elements in addition to those recited after such terms in a claim are still considered to be within the scope of that claim. Further, in the following claims, the terms "first," "second," and "third," etc. are used merely as labels and are not intended to impose numerical requirements on their objects.

[0112] Examples of the methods described herein may be at least partially machine- or computer-implemented. Some examples may include computer-readable or machine-readable media encoded with instructions operable to configure an electronic device to perform the method or circuit operation or circuit configuration instructions, as described in the examples above. Implementations of such methods may include microcode, assembly language code, high-level language code, etc. Such code may include computer-readable instructions for performing various methods. The code may form part of a computer program product. Further, in one example, the code may be tangibly stored on one or more volatile, non-transitory, or non-volatile tangible computer-readable media, such as during execution or at other times. Examples of these tangible computer-readable media may include, but are not limited to, hard disks, removable magnetic disks, removable optical disks (e.g., compact disks and digital video disks), magnetic cassettes, memory cards or sticks, random access memory (RAM), read-only memory (ROM), etc.

[0113] The above description is illustrative, not limiting. For example, the above examples (or one or more aspects thereof) may be used in combination with each other. Other embodiments may be utilized, such as by one of ordinary skill in the art reviewing the above description. The Abstract is provided to enable the reader to quickly ascertain the nature of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. Also, various features may be grouped together in the above Detailed Description to streamline the disclosure. This should not be construed as intending that any unclaimed disclosed feature is essential to any claim. Rather, inventive subject matter may lie in less than all features of a particular disclosed embodiment. Accordingly, the following claims are incorporated into the Detailed Description as an example or embodiment, with each claim standing on its own as a separate embodiment, and it is contemplated that such embodiments can be combined with each other in various combinations or permutations. The scope of the invention should be determined with reference to the appended claims, along with the full range of equivalents to which such claims are entitled. [Explanation of symbols]

[0114] 100 Inspection Systems 102 First Driver AB 104 First Driver A 106 First Resistor 108 First load circuit 110 DC voltage Vih 112 DC Voltage Vil 114-pin EnAB 116-pin EnA 118 Control Signal Swing 120 First output current i_OUT 122 Comparator circuit 124 Device Under Test (DUT) 128 Comparator reference signal Vth 130 Differential comparator output signal OP 132 DUT nodes 134 Signal Path 200 Comparator Example 202 first gain stage 204 Output Stage 206 Comparison Stage 208 nth gain stage 210 Comparator input node 212 Reference signal input node 214 First Output Node 216 Second Output Node 302 First Amplification Stage 304 First Transconductance Circuit 306 Load circuit 308 First Input 310 Second Input 312 First Output 314 Second Output 316 First Current Source 318 Second Current Source 402 Second Amplification Stage 404 Second Transconductance Circuit 424 First path stage circuit 502 Third Amplification Stage 504 Third Transconductance Circuit 506 First gate drive circuit 508 Second gate drive circuit 510 second path stage circuit 512 control circuit 600 Gate drive circuit 602 input nodes 606 Gate drive circuit output node 608 Current source 610 first PMOS device

Claims

1. 1. A gain stage circuit, comprising: a first follower circuit coupled to the first input node; a second follower circuit coupled to the second input node; a pass stage circuit including a tunable impedance signal path coupling the first follower circuit and the second follower circuit; a control circuit configured to receive a first input signal from the first input node and a second input signal from the second input node, and in response to the receive signal, provide a control signal to the pass stage circuit for controlling the impedance of the signal path coupling the first follower circuit and the second follower circuit.

2. the pass stage circuit comprises a first negative feedback transistor and a second negative feedback transistor; the control circuit is configured to provide a first control signal to a gate terminal of the first negative feedback transistor, the first control signal being based on the first input signal; 2. The gain stage circuit of claim 1, wherein the control circuit is configured to provide a different second control signal to a gate terminal of the second negative feedback transistor, the second control signal being based on the second input signal.

3. the first follower circuit comprises a first FET device having a gate terminal coupled to the first input node and a source terminal coupled to a source terminal of the first negative feedback transistor; 3. The gain stage circuit of claim 2, wherein the second follower circuit comprises a second FET device having a gate terminal coupled to the second input node and a source terminal coupled to a source terminal of the second negative feedback transistor.

4. 4. The gain stage circuit of claim 3, wherein the drain terminals of the first negative feedback transistor and the second negative feedback transistor are coupled at an intermediate node.

5. 3. The gain stage circuit of claim 2, wherein the control circuit is configured to provide the first control signal as a combination of the first input signal and a non-zero offset signal.

6. 6. The gain stage circuit of claim 5, wherein the control circuit is configured to provide the second control signal as a combination of the second input signal and the non-zero offset signal.

7. 3. The gain stage circuit of claim 2, wherein the control circuit is configured to provide the first control signal and the second control signal as gain-adjusted versions of the first input signal and the second input signal, respectively.

8. The control circuit a first gate drive circuit configured to receive the first input signal and, in response, to provide a buffered first gate drive signal to the gate terminal of the first negative feedback transistor; a second gate drive circuit configured to receive the second input signal and, in response, to provide a buffered second gate drive signal to the gate terminal of the second negative feedback transistor.

9. 9. The gain stage circuit of claim 8, wherein when the magnitudes of the first gate drive signal and the second gate drive signal are substantially equal, the first negative feedback transistor and the second negative feedback transistor operate in a linear region to provide the signal path in the pass stage circuit.

10. 9. The gain stage circuit of claim 8, wherein when the magnitudes of the first gate drive signal and the second gate drive signal are not substantially equal, the first negative feedback transistor and the second negative feedback transistor operate in a saturation region and prevent signal transmission through the pass stage circuit.

11. the control signal is configured to control the signal path of the pass stage circuit to have a low impedance characteristic when the magnitudes and polarities of the voltage signals at the first input node and the second input node are substantially equal, 2. The gain stage circuit of claim 1, wherein the control signal is configured to control the signal path of the pass stage circuit to have a high impedance characteristic when the magnitudes of the voltage signals at the first input node and the second input node are not substantially equal.

12. 1. A method for controlling gain and bandwidth characteristics of a gain stage circuit in a pin driver system, comprising: receiving a first gain stage input signal and a second gain stage input signal at respective first and second input nodes of respective first and second follower circuits; receiving the first gain stage input signal and the second gain stage input signal at respective first and second control circuits; providing, using the first control circuit, a first control signal to a first portion of a pass stage circuit, the first control signal being based on the first gain stage input signal and a first offset; providing, using the second control circuit, a second control signal to a second portion of the pass stage circuit, the second control signal being based on the second gain stage input signal and a second offset; adjusting an impedance characteristic of a signal path coupling the first follower circuit and the second follower circuit in response to receiving the first control signal and the second control signal at the pass stage circuit; and providing a gain stage output signal using the first follower circuit and the second follower circuit.

13. The method of claim 12 , wherein the first offset and the second offset are voltage offset signals of the same value.

14. when the first control signal and the second control signal exceed threshold voltage values, the signal path coupling the first follower circuit and the second follower circuit has lower impedance characteristics; 13. The method of claim 12, wherein the signal path coupling the first follower circuit and the second follower circuit has a higher impedance characteristic when at least one of the first control signal and the second control signal does not exceed the threshold voltage value.

15. providing the first control signal to the pass stage circuit includes providing the first control signal to a gate terminal of a first negative feedback transistor; providing the second control signal to the pass stage circuit includes providing the second control signal to a gate terminal of a second negative feedback transistor; 13. The method of claim 12, wherein the drain terminals of the first degenerate feedback transistor and the second degenerate feedback transistor are coupled at an intermediate node.

16. 13. The method of claim 12, wherein receiving the first gain stage input signal and the second gain stage input signal at the respective first control circuit and the second control circuit comprises receiving the first gain stage input signal and the second gain stage input signal at respective gate terminals of respective PMOS devices comprising the control circuit.

17. In the first control circuit, receiving the first gain stage input signal; providing a buffered copy of the first gain stage input signal to a first input of a summing amplifier; providing an offset signal to a second input of the summing amplifier; providing the first control signal from an output of the summing amplifier to the first portion of the pass stage circuit.

18. 1. A system comprising: a first portion of the transconductance circuit, a first gate drive circuit configured to provide a first gate drive signal to the pass stage circuit based on a first input signal; a first negative feedback transistor of the pass stage circuit configured to receive the first gate drive signal; and a first input transistor coupled to the first negative feedback transistor configured to provide a first output current at a first output node; a first portion of the transconductance circuit, a second portion of the transconductance circuit, a second gate drive circuit configured to provide a second gate drive signal to the pass stage circuit based on a second input signal; a second negative feedback transistor of the pass stage circuit configured to receive the second gate drive signal; and a second input transistor coupled to the second negative feedback transistor configured to provide a second output current at a second output node; and a second portion of the transconductance circuit comprising:

19. 20. The system of claim 18, wherein the drain terminals of the first negative feedback transistor and the second negative feedback transistor are coupled at an intermediate node.

20. a gate terminal of the first input transistor configured to receive the first input signal to the transconductance circuit; 20. The system of claim 18, wherein a gate terminal of the second input transistor is configured to receive the second input signal to the transconductance circuit.

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