Method for manufacturing quantum device
By mounting the quantum bit chip using first bumps and locally heating second bumps that do not overlap, the method prevents temperature changes and warping, preserving the chip's characteristics and ensuring accurate positioning.
Patent Information
- Application Number
- JP2024017206
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- Filing Date
- 2024-02-07
- Publication Date
- 2025-08-20
AI Technical Summary
The challenge of mounting a quantum bit chip on a first substrate and then a first substrate on a second substrate results in warping due to differing linear expansion coefficients, causing temperature changes that affect the characteristics of the quantum bit chip during the heating process of bonding the second substrate.
Mount the quantum bit chip on a first substrate using first bumps and then mount the first substrate on a second substrate by locally heating second bumps that do not overlap the quantum bit chip in a planar view, without bonding material in overlapping areas, using low-heat treatment for first bumps and localized heating for second bumps.
This method prevents temperature increases in the quantum bit chip, thereby maintaining its characteristics and ensuring accurate positioning without warping.
Smart Images
Figure 2025121639000001_ABST
Abstract
Description
[Technical Field]
[0001] The present invention relates to a method for manufacturing a quantum device. [Background technology]
[0002] Configurations are known in which a substrate on which a semiconductor element or a quantum bit element is formed is mounted on another substrate using solder bumps (e.g., Patent Documents 1 and 2). Also known are quantum devices in which a quantum bit chip is mounted on a first substrate such as an interposer using first bumps, and the first substrate is mounted on a second substrate such as a printed circuit board using second bumps (e.g., Patent Documents 3-5). [Prior art documents] [Patent documents]
[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2006-310622 [Patent Document 2] US Patent Application Publication No. 2009 / 0173936 [Patent Document 3] Special Publication No. 2022-519443 [Patent Document 4] US Patent Application Publication No. 2018 / 0013052 [Patent Document 5] Japanese Patent Application Publication No. 2023-69792 Summary of the Invention [Problem to be solved by the invention]
[0004] In a configuration in which the quantum bit chip is mounted on a first substrate and the first substrate is mounted on a second substrate, it is desirable to mount the quantum bit chip on the first substrate using first bumps, and then mount the first substrate on the second substrate using second bumps. This is because if the first substrate is mounted on the second substrate first, warping will occur in the first and second substrates due to the difference in linear expansion coefficients between the first and second substrates, making it difficult to mount the quantum bit chip on the first substrate with high positional accuracy.
[0005] The process of mounting the first substrate on the second substrate using the second bumps is performed by heating the second bumps. For example, the first substrate and the second substrate, on which the quantum bit chip is mounted, are placed in a heating furnace and the second bumps are heated, thereby mounting the first substrate on the second substrate. However, when the second bumps are heated using a heating furnace, the quantum bit chip mounted on the first substrate is also heated by the furnace, causing the temperature to rise. The characteristics of the quantum bit chip change when the temperature rises.
[0006] One aspect is to suppress changes in the characteristics of the quantum bit chip. [Means for solving the problem]
[0007] In one aspect, a method for manufacturing a quantum device includes the steps of: mounting a quantum bit chip on a first substrate using a first bump; and, after mounting the quantum bit chip, mounting the first substrate on a second substrate by locally heating a second bump provided in a position that does not overlap the quantum bit chip in a planar view; wherein no bonding material for bonding the first substrate and the second substrate is provided between the first substrate and the second substrate in a position that overlaps the quantum bit chip in a planar view. [Effects of the Invention]
[0008] One aspect is that it can suppress changes in the characteristics of the quantum bit chip. [Brief explanation of the drawings]
[0009] [Figure 1] FIG. 1(a) is a plan view of a quantum device according to a first embodiment, and FIG. 1(b) is a cross-sectional view taken along the line AA in FIG. 1(a). [Figure 2] FIG. 2(a) is a plan view of a quantum bit element provided in a quantum bit chip, FIG. 2(b) is a plan view of a Josephson junction element, and FIG. 2(c) is a cross-sectional view taken along the line AA of FIG. 2(b). [Figure 3]3(a) to 3(c) are cross-sectional views illustrating a method for manufacturing a quantum device according to the first embodiment. [Figure 4] FIG. 4(a) is a plan view of a quantum device according to a second embodiment, and FIG. 4(b) is a cross-sectional view taken along the line AA in FIG. 4(a). [Figure 5] 5(a) to 5(d) are diagrams (part 1) illustrating a method for manufacturing a quantum device according to the second embodiment. [Figure 6] 6(a) to 6(d) are diagrams (part 2) illustrating a method for manufacturing a quantum device according to the second embodiment. [Figure 7] FIG. 7 is a cross-sectional view showing another example of the arrangement of the heat dissipation fins and the heat conduction members. [Figure 8] FIG. 8(a) is a plan view of a quantum device according to a third embodiment, and FIG. 8(b) is a cross-sectional view taken along the line AA in FIG. 8(a). [Figure 9] 9(a) to 9(d) are diagrams (part 1) illustrating a method for manufacturing a quantum device according to the third embodiment. [Figure 10] 10(a) to 10(d) are diagrams (part 2) illustrating a method for manufacturing a quantum device according to the third embodiment. [Figure 11] 11(a) and 11(b) are cross-sectional views showing the outer shape and the amount of warpage of the interposer. [Figure 12] FIG. 12(a) is a plan view showing a method for manufacturing a quantum device according to the fourth embodiment, and FIG. 12(b) is a cross-sectional view taken along the line AA of FIG. 12(a). [Figure 13] FIG. 13(a) is a plan view of a quantum device according to a fifth embodiment, and FIG. 13(b) is a plan view of a quantum device according to a modification of the fifth embodiment. [Figure 14] FIG. 14 is a cross-sectional view of a quantum device according to a sixth embodiment. [Figure 15] 15(a) to 15(d) are cross-sectional views showing a method for manufacturing a quantum device according to the sixth embodiment. DETAILED DESCRIPTION OF THE INVENTION
[0010] Hereinafter, embodiments of the present invention will be described with reference to the drawings. [Example]
[0011] FIG. 1(a) is a plan view of a quantum device 100 according to a first embodiment, and FIG. 1(b) is a cross-sectional view taken along line AA of FIG. 1(a). As shown in FIGS. 1(a) and 1(b), the quantum device 100 according to the first embodiment includes a printed circuit board 10, an interposer 20, and a quantum bit chip 30. The quantum bit chip 30 is mounted on the interposer 20 by first bumps 32, which are bonding members. The interposer 20 is mounted on the printed circuit board 10 by second bumps 22, which are bonding members. The first bumps 32 and the second bumps 22 are electrically connected by wiring 24 provided on the interposer 20.
[0012] The second bumps 22 that mount the interposer 20 on the printed circuit board 10 are, for example, solder bumps, and are formed of, for example, Sn-Ag-Cu solder or Sn-Cu solder. The first bumps 32 that mount the quantum bit chip 30 on the interposer 20 are bumps that can be bonded with lower heat treatment than the second bumps 22, and are, for example, indium (In) bumps, gold (Au) bumps, or copper (Cu) bumps. The first bumps 32 have a smaller height, width, and pitch than the second bumps 22. The second bumps 22 are provided in a position that does not overlap the quantum bit chip 30 in a planar view. Note that no bonding member that bonds the printed circuit board 10 and the interposer 20 is provided in a position that overlaps the quantum bit chip 30 in a planar view.
[0013] The quantum bit chip 30 includes a quantum bit element using a Josephson junction. FIG. 2(a) is a plan view of a quantum bit element 40 included in the quantum bit chip 30, FIG. 2(b) is a plan view of a Josephson junction element 45, and FIG. 2(c) is a cross-sectional view taken along line AA of FIG. 2(b). As shown in FIGS. 2(a) to 2(c), the quantum bit element 40 includes a quantum bit 41, a resonator 42, and a filter 43. The quantum bit 41 includes a Josephson junction element 45 connected between electrodes 44a and 44b. The Josephson junction element 45 includes a superconducting film 46a and a superconducting film 46b overlapping each other with an insulating film 47 interposed therebetween. The superconducting films 46a and 46b are, for example, aluminum (Al) films. The insulating film 47 is, for example, an aluminum oxide (Al2O3) film. The Josephson junction element 45 is connected between the electrodes 44a and 44b, with one of the superconducting films 46a and 46b connected to the electrode 44a and the other connected to the electrode 44b. The quantum bit 41 includes a transmon including the Josephson junction element 45 and a capacitor connected in parallel to the Josephson junction element 45 and formed by the electrodes 44a and 44b. The resonator 42 includes, for example, a coplanar line with a meander structure, and one end is electrostatically coupled to the quantum bit 41. The other end of the resonator 42 is connected to the readout unit 48 via the filter 43.
[0014] [Manufacturing method] 3(a) to 3(c) are cross-sectional views showing a manufacturing method of the quantum device 100 according to the first embodiment. As shown in FIG. 3(a), a first bump 32 is formed on the upper surface of the interposer 20, and a second bump 22 is formed on the lower surface. The second bump 22 is, for example, a solder bump. The first bump 32 is a bump that can be bonded with a lower heat treatment than the second bump 22, and is, for example, an In bump, an Au bump, or a Cu bump.
[0015] As shown in FIG. 3(b), the quantum bit chip 30 is mounted on the interposer 20 via the first bumps 32. When In bumps are used for the first bumps 32, bonding can be achieved with low-heat treatment, with a bonding temperature of approximately 140°C and a heating time of approximately 300 seconds. When ultrasonic Au bonding is used with Au bumps, bonding can be achieved with low-heat treatment, with a bonding temperature of approximately 180°C and a heating time of approximately 3 seconds. When surface activated bonding is used with Cu bumps, bonding can be achieved at room temperature. When the temperature of the quantum bit chip 30 increases, the characteristics of the quantum bit elements 40 included in the quantum bit chip 30 change. For example, when the temperature of the quantum bit chip 30 increases, the thickness of the insulating film 47 of the Josephson junction element 45 changes, causing changes in the characteristics of the quantum bit elements 40. Therefore, bonding using the first bumps 32 is achieved with low-heat treatment. This suppresses temperature increases in the quantum bit chip 30 and suppresses changes in the characteristics of the quantum bit elements 40.
[0016] The second bumps 22 on the underside of the interposer 20 are formed so as to be located outside the quantum bit chip 30 in a plan view. In other words, the second bumps 22 are located in an area that does not overlap the quantum bit chip 30 in a plan view, and no bonding material is provided in the area that overlaps the quantum bit chip 30.
[0017] As shown in FIG. 3( c), the interposer 20 is mounted on the printed circuit board 10 via the second bumps 22. The second bumps 22 are, for example, solder bumps. For example, if the printed circuit board 10, the interposer 20, and the quantum bit chip 30 are placed in a heating furnace to heat the second bumps 22, the heating process would be performed at a temperature of approximately 200°C for approximately 10 minutes. In this case, the temperature of the quantum bit chip 30 would increase, causing changes in the characteristics of the quantum bit element 40. Therefore, the interposer 20 is mounted on the printed circuit board 10 by sequentially locally heating the second bumps 22 using a heater 50 such as a heat gun or soldering iron. For example, a 300 W heat gun is used to perform local heating at a bonding temperature of approximately 200°C for approximately 10 seconds. In this way, by locally heating the second bumps 22 using the heater 50, it is possible to prevent the temperature of the quantum bit chip 30 from increasing.
[0018] According to the first embodiment, as shown in FIG. 3(b), the quantum bit chip 30 is mounted on the interposer 20 (first substrate) using the first bumps 32. As shown in FIG. 3(c), the interposer 20 is mounted on the printed circuit board 10 (second substrate) by locally heating the second bumps 22 provided in positions that do not overlap the quantum bit chip 30 in a planar view. In this way, by locally heating the second bumps 22 provided in positions that do not overlap the quantum bit chip 30 in a planar view, it is possible to prevent the temperature of the quantum bit chip 30 from increasing. Therefore, it is possible to prevent changes in the characteristics of the quantum bit chip 30.
[0019] In addition, in Example 1, the first bumps 32 for mounting the quantum bit chip 30 on the interposer 20 are In bumps, Au bumps, or Cu bumps. This allows the quantum bit chip 30 to be mounted on the interposer 20 using low-heat treatment, thereby suppressing changes in the characteristics of the quantum bit chip 30. The second bumps 22 for mounting the interposer 20 on the printed circuit board 10 are solder bumps. By locally heating these second bumps 22 to mount the interposer 20 on the printed circuit board 10, the interposer 20 can be firmly bonded to the printed circuit board 10.
[0020] Furthermore, in Example 1, a heat gun or a soldering iron is used as the heater 50 to locally heat the second bump 22. This increases the temperature only of the second bump 22 and its surroundings, and suppresses temperature increases in areas away from the second bump 22, thereby suppressing changes in the characteristics of the quantum bit chip 30.
[0021] In Example 1, the quantum bit chip 30 includes a Josephson junction device 45. The characteristics of the Josephson junction device 45 are prone to change as the temperature rises. For this reason, when the quantum bit chip 30 includes a Josephson junction device 45, it is preferable to apply the manufacturing method shown in Figures 3(a) to 3(c). [Example]
[0022] FIG. 4(a) is a plan view of a quantum device 200 according to a second embodiment, and FIG. 4(b) is a cross-sectional view taken along line AA of FIG. 4(a). As shown in FIGS. 4(a) and 4(b), in the quantum device 200 according to the second embodiment, the interposer 20 has a polygonal shape with five or more sides (e.g., a hexagonal shape) in a plan view. The printed circuit board 10 has a through-hole 11 penetrating from the top surface to the bottom surface. The through-hole 11 has, for example, the same polygonal shape (e.g., a hexagonal shape) as the interposer 20 in a plan view. The interposer 20 is mounted on the printed circuit board 10 by a second bump 22 so as to cover the through-hole 11. The quantum bit chip 30 is mounted on the interposer 20 so as to entirely overlap the through-hole 11 in a plan view. The other configurations are the same as those of the first embodiment, and therefore description thereof will be omitted.
[0023] [Manufacturing method] 5(a) to 6(d) are diagrams illustrating a method for manufacturing the quantum device 200 according to Example 2. FIGS. 5(a), 5(b), 6(a), and 6(b) are plan views illustrating the method for manufacturing the quantum device 200 according to Example 2. FIGS. 5(c), 5(d), 6(c), and 6(d) are cross-sectional views taken along the line AA of FIGS. 5(a), 5(b), 6(a), and 6(b).
[0024] 5(a) and 5(c), a first bump 32 is formed on the upper surface of an interposer 20 having a polygonal shape with five or more sides (e.g., a hexagon) in a plan view, and a second bump 22 is formed on the lower surface. The first bump 32 is formed in the central region of the upper surface of the interposer 20. The second bump 22 is formed in the peripheral region of the lower surface of the interposer 20.
[0025] As shown in Figures 5(b) and 5(d), the quantum bit chip 30 is mounted on the interposer 20 by the first bump 32. The quantum bit chip 30 is mounted on the interposer 20 by the low-temperature heating process described in Example 1. As in Example 1, the second bump 22 is located in an area that does not overlap the quantum bit chip 30 in a planar view, and no bonding material is provided in the area that overlaps the quantum bit chip 30. The distance L between the quantum bit chip 30 and the second bump 22 is, for example, 2 cm to 15 cm, or alternatively, 4 cm to 12 cm, or alternatively, 6 cm to 10 cm.
[0026] As shown in FIGS. 6( a) and 6(c), a covering portion 60 that covers the quantum bit chip 30 is placed on the upper surface of the interposer 20. The covering portion 60 has a box-like shape having a bottom portion 62 and wall portions 64. The quantum bit chip 30 is placed inside the box-like covering portion 60. The covering portion 60 is simply placed in contact with the upper surface of the interposer 20, for example, and is not bonded to the interposer 20. The covering portion 60 may be placed on the metal film 26 of the interposer 20 or on the insulating film 28. The covering portion 60 may be formed of a metallic material, or may be formed of an insulating material such as a heat-resistant plastic.
[0027] In addition, heat dissipation fins 66 are arranged on the upper surface of the interposer 20. The heat dissipation fins 66 may be formed of a metal material such as copper or aluminum. The heat dissipation fins 66 are simply placed in contact with the upper surface of the interposer 20, similar to the cover portion 60, and are not bonded to the interposer 20. The heat dissipation fins 66 may be placed on the metal film 26 of the interposer 20 or on the insulating film 28.
[0028] As shown in FIGS. 6(b) and 6(d), the printed circuit board 10 is placed on a heat dissipation stage 70, which also serves as a support base. A through hole 11 is formed in the printed circuit board 10. A columnar heat conduction member 68 is placed on the heat dissipation stage 70, positioned within the through hole 11. The heat conduction member 68 may be made of a metal material such as copper or aluminum. The heat dissipation stage 70 may be a metal block, or an insulating block with a metal film formed on its upper surface, as long as at least the upper surface is made of a metal such as copper or aluminum. The upper surface of the heat conduction member 68 protrudes from the upper surface of the printed circuit board 10.
[0029] Thereafter, the interposer 20 is placed on the heat conduction member 68. As a result, the heat conduction member 68 is positioned between the lower surface of the interposer 20 and the heat dissipation stage 70. The heat conduction member 68 is in contact with, but not bonded to, the lower surface of the interposer 20 and the upper surface of the heat dissipation stage 70, for example. The heat conduction member 68 may be in contact with the metal film 26 of the interposer 20 or the insulating film 28.
[0030] The second bumps 22 are heated locally in sequence using the heater 50, thereby mounting the interposer 20 on the printed circuit board 10. The heat from the heater 50 is transmitted through the air, but the provision of the cover 60 that covers the quantum bit chip 30 prevents the temperature of the quantum bit chip 30 from increasing due to the heat transmitted through the air. The heat from the heater 50 is also transmitted to the interposer 20. However, because the interposer 20 is provided with heat dissipation fins 66 and a thermally conductive member 68, the heat transmitted through the interposer 20 is released into the air by the heat dissipation fins 66 and to the heat dissipation stage 70 by the thermally conductive member 68. Therefore, the temperature of the quantum bit chip 30 can be prevented from increasing due to the heat transmitted through the interposer 20.
[0031] After the interposer 20 is mounted on the printed circuit board 10, the cover portion 60, the heat dissipation fins 66, and the heat conduction member 68 are removed as shown in FIGS. 4(a) and 4(b).
[0032] In Example 2, as shown in Figures 6(a) and 6(c), a cover 60 that covers the quantum bit chip 30 is arranged on the interposer 20. After the cover 60 is arranged, the second bumps 22 are locally heated as shown in Figures 6(b) and 6(d), thereby mounting the interposer 20 on the printed circuit board 10. By providing the cover 60 that covers the quantum bit chip 30, heat generated when the second bumps 22 are locally heated is prevented from traveling through the air and reaching the quantum bit chip 30. This prevents the temperature of the quantum bit chip 30 from increasing, and prevents changes in the characteristics of the quantum bit chip 30.
[0033] In Example 2, as shown in FIGS. 6( a) and 6(c), heat dissipation fins 66 (heat dissipation members) are disposed on the interposer 20. After disposing the heat dissipation fins 66, the second bumps 22 are locally heated as shown in FIGS. 6(b) and 6(d), thereby mounting the interposer 20 on the printed circuit board 10. By providing the heat dissipation fins 66 on the interposer 20, heat generated when the second bumps 22 are locally heated is prevented from traveling through the interposer 20 to the quantum bit chip 30. This prevents the temperature of the quantum bit chip 30 from increasing, thereby preventing changes in the characteristics of the quantum bit chip 30. In order to prevent a temperature increase in the quantum bit chip 30, the heat dissipation fins 66 are preferably disposed on the interposer 20 between the second bumps 22 and the quantum bit chip 30 in a plan view.
[0034] In Example 2, as shown in FIGS. 6(b) and 6(d), a heat conductive member 68 (heat dissipation member) is disposed between the interposer 20 and the heat dissipation stage 70. After disposing the heat conductive member 68, the second bumps 22 are locally heated to mount the interposer 20 on the printed circuit board 10. By providing the heat conductive member 68 between the interposer 20 and the heat dissipation stage 70, heat generated when the second bumps 22 are locally heated is prevented from traveling through the interposer 20 to the quantum bit chip 30. This prevents the temperature of the quantum bit chip 30 from increasing, thereby preventing changes in the characteristics of the quantum bit chip 30. In order to prevent a temperature increase in the quantum bit chip 30, the heat conductive member 68 is preferably disposed on the interposer 20 between the second bumps 22 and the quantum bit chip 30 in a plan view.
[0035] Furthermore, in Example 2, the second bumps 22 are provided on the periphery of the interposer 20, not in the center of the interposer 20. In other words, the second bumps 22 are provided in positions that do not overlap the quantum bit chip 30 in a plan view, and no joining material that joins the printed circuit board 10 and the interposer 20 is provided in positions that overlap the quantum bit chip 30. This makes it easier to locally heat the second bumps 22, and prevents the temperature of the quantum bit chip 30 from becoming too high.
[0036] In Example 2, an example is shown in which all of the cover portion 60, heat dissipation fins 66, and heat conduction member 68 are provided, but it is also possible that at least one of the cover portion 60, heat dissipation fins 66, and heat conduction member 68 is provided.
[0037] In the second embodiment, the heat dissipation fins 66 and the heat conduction member 68 are arranged in contact with the metal film 26 or the insulating film 28 of the interposer 20, but this is not limiting. Fig. 7 is a cross-sectional view showing another example of the arrangement of the heat dissipation fins 66 and the heat conduction member 68. As shown in FIG. 7, a thermally conductive resin film 72 (TIM (Thermal Interface Material)) may be applied to the interposer 20, and then the heat dissipation fins 66 and the heat conduction member 68 may be disposed on the thermally conductive resin film 72. The thermally conductive resin film 72 may be a resin film to which a filler such as boron nitride (BN), aluminum nitride (AlN), magnesium oxide (MgO), or aluminum oxide (Al2O3) has been added. In this way, by disposing the heat dissipation fins 66 and the heat conduction member 68 on the interposer 20 with the thermally conductive resin film 72 sandwiched between them, heat conducted through the interposer 20 can be effectively dissipated. The thermally conductive resin film 72 is removed after the interposer 20 is mounted on the printed circuit board 10. [Example]
[0038] FIG. 8(a) is a plan view of a quantum device 300 according to a third embodiment, and FIG. 8(b) is a cross-sectional view taken along the line AA of FIG. 8(a). In the quantum device 300 according to the third embodiment, as shown in FIGS. 8(a) and 8(b), the quantum bit chip 30 is mounted across multiple interposers 20 via first bumps 32. Each of the multiple interposers 20 has a triangular shape in plan view, for example. The multiple interposers 20 are grouped together with spaces between them, forming a substantially hexagonal shape in plan view, for example. Second bumps 22 are provided along the edges corresponding to the periphery of each of the multiple interposers 20, and first bumps 32 are provided near the vertex formed by the remaining two edges. The multiple interposers 20 may have other shapes, such as a rectangular shape. The printed circuit board 10 has multiple through holes 11 penetrating from the top surface to the bottom surface. Each of the multiple through holes 11 is provided at a position that overlaps with each of the multiple interposers 20 in plan view, but does not overlap with the first bump 32 and the second bump 22. The first bump 32 and the second bump 22 are positioned so as to sandwich the through hole 11 in plan view. The other configurations are the same as those in Example 1, so a description thereof will be omitted.
[0039] [Manufacturing method] 9(a) to 10(d) are diagrams illustrating a method for manufacturing a quantum device 300 according to Example 3. Figures 9(a), 9(b), 10(a), and 10(b) are plan views illustrating a method for manufacturing a quantum device 300 according to Example 3. Figures 9(c), 9(d), 10(c), and 10(d) are cross-sectional views taken along the line AA of Figures 9(a), 9(b), 10(a), and 10(b).
[0040] 9(a) and 9(c), a first bump 32 is formed on the upper surface of each of the multiple interposers 20, and a second bump 22 is formed on the lower surface. The multiple interposers 20 have, for example, a triangular shape in a plan view. The second bump 22 is formed along one side of the triangle, and the first bump 32 is formed near the vertex formed by the remaining two sides.
[0041] 9(b) and 9(d), the quantum bit chip 30 is mounted across multiple interposers 20 via first bumps 32. The quantum bit chip 30 is mounted on the interposers 20 by the low-temperature heating process described in Example 1. As in Example 1, the second bumps 22 are located in an area that does not overlap the quantum bit chip 30 in a planar view, and no bonding material for bonding the printed circuit board 10 and the interposers 20 is provided in the area that overlaps the quantum bit chip 30.
[0042] 10(a) and 10(c), a cover 60 that covers the quantum bit chips 30 is disposed across the upper surfaces of the multiple interposers 20. Furthermore, heat dissipation fins 66 are disposed on the upper surface of each of the multiple interposers 20.
[0043] As shown in FIGS. 10(b) and 10(d), the printed circuit board 10 and the heat conductive member 68 are placed on the heat dissipation stage 70. The heat conductive members 68 are placed in the multiple through holes 11 formed in the printed circuit board 10 so as to be located below the multiple interposers 20, respectively. The interposer 20 is placed on the heat conductive member 68. This positions the heat conductive member 68 between the lower surface of the interposer 20 and the heat dissipation stage 70. Next, the second bumps 22 are locally heated using a heater 50, thereby mounting the interposer 20 on the printed circuit board 10. After the interposer 20 is mounted on the printed circuit board 10, the cover 60, heat dissipation fins 66, and heat conductive member 68 are removed, as shown in FIGS. 8(a) and 8(b).
[0044] In Example 3, as shown in Figures 9(b) and 9(d), a quantum bit chip 30 is mounted across multiple interposers 20. As shown in Figures 10(b) and 10(d), multiple interposers 20 with quantum bit chips 30 mounted thereon are mounted on a printed circuit board 10. Because the interposer 20 is a substrate having a conductor layer and an insulating layer, warping occurs due to the difference in the linear expansion coefficients of the conductor layer and the insulating layer.
[0045] 11(a) and 11(b) are cross-sectional views showing the outer shape and amount of warpage of the interposer 20. When warpage of the same curvature occurs in interposers 20 of different outer shape sizes as shown in FIGS. 11(a) and 11(b), the amount of warpage A of the interposer 20 with a smaller outer shape (FIG. 11(a)) is smaller than that of the interposer 20 with a larger outer shape (FIG. 11(b)). Therefore, the amount of warpage of each of the multiple interposers 20 in Example 3 is smaller than that of the interposer 20 in Example 2 shown in FIGS. 5(b) and 5(d).
[0046] In this way, by mounting the quantum bit chip 30 across multiple interposers 20, the outer dimensions of the interposers 20 can be reduced, and the amount of warping can be kept small. This allows the interposers 20 to be mounted properly on the printed circuit board 10.
[0047] 10(b) and 10(d), the printed circuit board 10 has a through hole 11 that overlaps the interposer 20 in a plan view and is located at least between the quantum bit chip 30 and the second bump 22. Also in Example 2, as shown in FIGS. 6(b) and 6(d), the printed circuit board 10 has a through hole 11 that overlaps the interposer 20 in a plan view and is located at least between the quantum bit chip 30 and the second bump 22. Because a wiring layer is provided on the printed circuit board 10, heat generated when the second bump 22 is locally heated propagates through the printed circuit board 10. However, by providing the through hole 11 in the printed circuit board 10, it is possible to prevent the heat generated when the second bump 22 is locally heated from being transmitted to the quantum bit chip 30 via the printed circuit board 10.
[0048] Although Example 3 has been described as an example in which a plurality of through holes 11 are provided in the printed circuit board 10, it is also possible that a single through hole 11 is provided to which the plurality of through holes 11 are connected, as in Example 2. Conversely, although Example 2 has been described as an example in which a single through hole 11 is provided in the printed circuit board 10, it is also possible that a plurality of through holes 11 are provided in which one through hole 11 is divided into a plurality of parts, as in Example 3. [Example]
[0049] The quantum device according to the fourth embodiment has the same structure as the quantum device 200 according to the second embodiment shown in FIGS. 4(a) and 4(b), and therefore a description thereof will be omitted.
[0050] [Manufacturing method] Fig. 12(a) is a plan view showing a method for manufacturing a quantum device according to Example 4, and Fig. 12(b) is a cross-sectional view taken along the line AA in Fig. 12(a). First, the manufacturing steps shown in Figs. 5(a) to 5(d), 6(a), and 6(c) of Example 2 are carried out.
[0051] 12(a) and 12(b), the printed circuit board 10 is placed on the heat dissipation stage 70 via the metal portion 74 and the low thermal conductive portion 76. The metal portion 74 may be made of a metal material such as copper or aluminum. The low thermal conductive portion 76 may be made of rubber or resin such as silicone rubber or polyimide resin, or may be air. The low thermal conductive portion 76 is arranged to overlap the second bumps 22 in a planar view. Then, as in Example 2, the interposer 20 is placed on the thermal conductive member 68. This positions the thermal conductive member 68 between the underside of the interposer 20 and the heat dissipation stage 70. Next, the second bumps 22 are locally heated using the heater 50, thereby mounting the interposer 20 on the printed circuit board 10. After the interposer 20 is mounted on the printed circuit board 10, the cover portion 60, the heat dissipation fins 66, and the thermal conductive member 68 are removed, as in Example 2.
[0052] 12(a) and 12(b), the printed circuit board 10 is placed on the heat dissipation stage 70 so that the low thermal conductivity portion 76 is sandwiched therebetween. Thereafter, the interposer 20 is mounted on the printed circuit board 10 by locally heating the second bumps 22. By providing the low thermal conductivity portion 76, heat generated when the second bumps 22 are locally heated is less likely to escape to the heat dissipation stage 70 via the printed circuit board 10, making it easier to locally increase the temperature of the second bumps 22. The low thermal conductivity portion 76 may be formed of a material having a lower thermal conductivity than the material on the upper surface of the heat dissipation stage 70, such as rubber or resin.
[0053] 12(b), in Example 4, the low thermal conductive portion 76 is provided so as to overlap the second bump 22 in a plan view. This makes it easier to locally increase the temperature of the second bump 22. The distance L between the second bump 22 and the end of the low thermal conductive portion 76 is, for example, approximately 1 cm to 3 cm. Furthermore, a metal portion 74 is provided between the printed circuit board 10 and the heat dissipation stage 70 at a position that does not overlap the second bump 22 in a plan view and is outside the low thermal conductive portion 76. This makes it possible to locally increase the temperature of the second bump 22 while dissipating unnecessary heat to the heat dissipation stage 70, thereby suppressing a temperature increase in the quantum bit chip 30. [Example]
[0054] FIG. 13(a) is a plan view of a quantum device 500 according to a fifth embodiment, and FIG. 13(b) is a plan view of a quantum device 510 according to a modification of the fifth embodiment. In FIGS. 13(a) and 13(b), contour lines 80 are shown by dashed lines along which warpage occurs in the printed circuit board 10 and the heights from a reference point (for example, the lowest or highest point on the bottom or top of the printed circuit board 10) are the same. As shown in FIGS. 13(a) and 13(b), in the quantum devices 500 and 510 according to the fifth embodiment and its modification, the second bumps 22 formed on one or more interposers 20 are located near the same contour line 80 on the printed circuit board 10. In this way, the second bumps 22 are provided at positions on the printed circuit board 10 at the same height from the reference point, so that the interposer 20 can be satisfactorily mounted on the printed circuit board 10 by the second bumps 22, even when warpage occurs in the printed circuit board 10. The points at the same height from the reference point are not limited to points at exactly the same height, but also include a range where the height is slightly different as long as the second bump 22 can be bonded well.
[0055] The warpage of the printed circuit board 10 varies depending on the difference in the linear expansion coefficient between the conductor layer and the insulating layer, the shape of the conductor pattern on the conductor layer, etc. Because the difference in the linear expansion coefficient and the shape of the conductor pattern are determined by design, it is possible to calculate the warpage that occurs in the printed circuit board 10 by performing a simulation using, for example, the finite element method, and to obtain the contour lines 80. Alternatively, the contour lines 80 may be obtained by fabricating a prototype of the printed circuit board 10 and measuring the warpage that occurs in the printed circuit board 10 when heated using a shadow moiré pattern. [Example]
[0056] Fig. 14 is a cross-sectional view of a quantum device 600 according to Example 6. As shown in Fig. 14, in the quantum device 600 according to Example 6, the quantum bit chip 30 is mounted on the lower surface of the interposer 20 by means of first bumps 32. The other configurations are the same as those in Example 3, and therefore will not be described again.
[0057] [Manufacturing method] 15(a) to 15(d) are cross-sectional views showing a manufacturing method of a quantum device 600 according to Example 6. As shown in Fig. 15(a), a first bump 32 and a second bump 22 are formed on the lower surface of each of a plurality of interposers 20.
[0058] 15(b), the quantum bit chip 30 is mounted on the underside of the multiple interposers 20 so as to straddle the multiple interposers 20 via the first bumps 32. The quantum bit chip 30 is mounted on the interposers 20 by the low-heat treatment described in Example 1. As in Example 1, the second bumps 22 are located in an area that does not overlap the quantum bit chip 30 in a planar view, and no bonding material for bonding the printed circuit board 10 and the interposers 20 is provided in the area that overlaps the quantum bit chip 30.
[0059] 15(c), heat dissipation fins 66 are arranged on the upper surface of the interposer 20. A cover 60 that covers the quantum bit chip 30 is arranged on the lower surface of the interposer 20. When the quantum bit chip 30 is mounted across multiple interposers 20, a cover 60a that is located above the quantum bit chip 30 and covers the gaps between the multiple interposers 20 may be arranged on the upper surface of the interposer 20.
[0060] As shown in FIG. 15(d), the printed circuit board 10 and the thermally conductive member 68 are placed on the heat dissipation stage 70. A low thermal conductivity member 76 may be placed on the heat dissipation stage 70 so as to be located between the heat dissipation stage 70 and the cover 60. The interposer 20 is placed on the thermally conductive member 68. This positions the thermally conductive member 68 between the underside of the interposer 20 and the heat dissipation stage 70. Next, the second bumps 22 are locally heated using a heater 50, thereby mounting the interposer 20 on the printed circuit board 10. After mounting the interposer 20 on the printed circuit board 10, the cover members 60, 60a, heat dissipation fins 66, and the thermally conductive member 68 are removed, as shown in FIG.
[0061] In Examples 1 to 5, the quantum bit chip 30 is mounted on the upper surface of the interposer 20, but as in Example 6, the quantum bit chip 30 may be mounted on the lower surface of the interposer 20.
[0062] In the first to sixth embodiments, the interposer 20 is used as the first substrate on which the quantum bit chip 30 is mounted, but other substrates such as a package substrate may also be used. Also, the printed circuit board 10 is used as the second substrate on which the first substrate is mounted, but other substrates such as a package substrate may also be used. Also, one or more other substrates other than the first and second substrates may be mounted.
[0063] Although the embodiments of the present invention have been described in detail above, the present invention is not limited to such specific embodiments, and various modifications and variations are possible within the scope of the gist of the present invention as defined in the claims.
[0064] In addition, the following supplementary notes are provided in relation to the above description. (Appendix 1) A method for manufacturing a quantum device, comprising: a step of mounting a quantum bit chip on a first substrate using a first bump; and a step of mounting the first substrate on a second substrate after mounting the quantum bit chip by locally heating a second bump provided in a position that does not overlap the quantum bit chip in a planar view, wherein no bonding material for bonding the first substrate and the second substrate is provided between the first substrate and the second substrate in a position that overlaps the quantum bit chip in a planar view. (Appendix 2) A method for manufacturing a quantum device as described in Appendix 1, further comprising the step of placing a cover portion that covers the quantum bit chip on the first substrate, and the step of mounting the first substrate comprises mounting the first substrate on the second substrate by locally heating the second bump after placing the cover portion. (Appendix 3) A method for manufacturing a quantum device as described in Appendix 1 or 2, further comprising a step of arranging a heat dissipation member on the first substrate, wherein the step of mounting the first substrate comprises mounting the first substrate on the second substrate by locally heating the second bump after arranging the heat dissipation member. (Appendix 4) The method for manufacturing a quantum device according to appendix 3, wherein the heat dissipation member is a heat dissipation fin. (Supplementary Note 5) The method for manufacturing a quantum device according to Supplementary Note 3, wherein the heat dissipation member is a thermally conductive member disposed between the first substrate and a heat dissipation stage. (Appendix 6) The method for manufacturing a quantum device according to appendix 3, wherein the heat dissipation member is disposed on the first substrate between the second bump and the quantum bit chip in a plan view. (Appendix 7) The method for manufacturing a quantum device described in Appendix 5, characterized in that the step of mounting the first substrate comprises placing the second substrate on the heat dissipation stage so that a low thermal conductivity portion is sandwiched therebetween, and then mounting the first substrate on the second substrate by locally heating the second bump. (Appendix 8) The method for manufacturing a quantum device according to appendix 3, wherein the heat dissipation component is disposed on the first substrate with a thermally conductive resin film sandwiched between the heat dissipation component and the first substrate. (Appendix 9) The method for manufacturing a quantum device according to appendix 1 or 2, wherein the first bump is an indium bump, a gold bump, or a copper bump, and the second bump is a solder bump. (Appendix 10) A method for manufacturing a quantum device according to appendix 1 or 2, characterized in that the step of mounting the first substrate comprises mounting the first substrate on the second substrate by locally heating the second bumps using a heat gun or a soldering iron. (Appendix 11) The method for manufacturing a quantum device according to appendix 1 or 2, characterized in that the step of mounting the quantum bit chip comprises mounting the quantum bit chip across a plurality of the first substrates, and the step of mounting the first substrates comprises mounting the plurality of first substrates on the second substrate. (Appendix 12) The method for manufacturing a quantum device according to appendix 1 or 2, wherein the second substrate has a through hole that overlaps the first substrate in a planar view and is positioned at least between the quantum bit chip and the second bump. (Appendix 13) The method for manufacturing a quantum device according to appendix 1 or 2, wherein the second bumps are provided on the periphery of the first substrate, and not in the center of the first substrate. (Appendix 14) The method for manufacturing a quantum device described in Appendix 1 or 2, characterized in that the step of mounting the quantum bit chip comprises mounting the quantum bit chip on a first surface of the first substrate, and the step of mounting the first substrate comprises mounting a second surface of the first substrate opposite to the first surface on the second substrate. (Appendix 15) A method for manufacturing a quantum device according to appendix 1 or 2, wherein the second bumps are provided in plurality, and the plurality of second bumps are provided so as to be positioned at the same height from a reference point on the second substrate where warping has occurred. (Appendix 16) The method for manufacturing a quantum device according to appendix 1 or 2, wherein the quantum bit chip has a Josephson junction element. [Explanation of symbols]
[0065] 10...printed circuit board, 11...through hole, 20...interposer, 22...second bump, 24...wiring, 26...metal film, 28...insulating film, 30...qubit chip, 32...first bump, 40...qubit element, 41...qubit, 42...resonator, 43...filter, 44a, 44b...electrodes, 45...Josephson junction element, 46a, 46b...superconducting film, 47...insulating film, 48...readout section, 50...heater, 60, 60a...covering section, 62...bottom, 64...wall section, 66...heat dissipation fin, 68...thermal conductive member, 70...heat dissipation stage, 72...thermal conductive resin film, 74...metal section, 76...low thermal conductivity section, 80...contour line, 100, 200, 300, 500, 510, 600...quantum device
Claims
1. mounting the quantum bit chip on the first substrate using first bumps; After mounting the quantum bit chip, mounting the first substrate on the second substrate by locally heating second bumps provided at positions that do not overlap the quantum bit chip in a plan view; Equipped with 10. A method for manufacturing a quantum device, comprising: providing a first substrate and a second substrate at a position overlapping the quantum bit chip in a planar view; and providing a bonding member between the first substrate and the second substrate.
2. a step of disposing a cover portion covering the quantum bit chip on the first substrate; 2. The method for manufacturing a quantum device according to claim 1, wherein the step of mounting the first substrate comprises mounting the first substrate on the second substrate by locally heating the second bump after placing the cover portion.
3. a step of arranging a heat dissipation member on the first substrate, 3. The method for manufacturing a quantum device according to claim 1, wherein the step of mounting the first substrate comprises mounting the first substrate on the second substrate by locally heating the second bumps after arranging the heat dissipation member.
4. 4. The method for manufacturing a quantum device according to claim 3, wherein the heat dissipation member is a heat dissipation fin.
5. 4. The method for manufacturing a quantum device according to claim 3, wherein the heat dissipation member is a thermally conductive member disposed between the first substrate and a heat dissipation stage.
6. The method for manufacturing a quantum device according to claim 3 , wherein the heat dissipation member is disposed on the first substrate between the second bump and the quantum bit chip in a plan view.
7. 6. The method for manufacturing a quantum device according to claim 5, wherein the step of mounting the first substrate comprises placing the second substrate on the heat dissipation stage so that a low thermal conductivity portion is sandwiched therebetween, and then locally heating the second bumps to mount the first substrate on the second substrate.
8. The method for manufacturing a quantum device according to claim 3 , wherein the heat dissipation member is disposed on the first substrate with a thermally conductive resin film sandwiched between the heat dissipation member and the first substrate.
9. the first bump is an indium bump, a gold bump, or a copper bump; 3. The method for manufacturing a quantum device according to claim 1, wherein the second bump is a solder bump.
10. the step of mounting the quantum bit chip includes mounting the quantum bit chip across a plurality of the first substrates; 3. The method for manufacturing a quantum device according to claim 1, wherein the step of mounting the first substrates comprises mounting the plurality of first substrates on the second substrate.
11. The second bumps are provided in plurality, The method for manufacturing a quantum device according to claim 1 , wherein the plurality of second bumps are provided so as to be positioned at the same height from a reference point on the warped second substrate.
12. 3. The method for manufacturing a quantum device according to claim 1, wherein the quantum bit chip has a Josephson junction element.
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