Integrated circuit device

Abstract

To provide an integrated circuit device that can reduce the withstand voltage of a circuit element of a level shift circuit.SOLUTION: An integrated circuit device has a level shift circuit that shifts the level of the voltage value of a base drive signal, and outputs a drive signal for driving a switching circuit that outputs a switching signal changing between a first voltage value and a reference potential. The level shift circuit has: a first limiting circuit that limits the voltage value of a first node on the basis of the voltage value of the switching signal at the rise of the base drive signal; a second limiting circuit that limits the voltage value of a second node on the basis of the voltage value of the switching signal at the fall of the base drive signal; a latch circuit that holds the switching signal in the first node and holds a boot voltage signal in a second node at the rise of the base drive signal, and holds the boot voltage signal in the first node and holds the switching signal in the second node at the fall of the base drive signal; and an output circuit that outputs a drive signal obtained by shifting the level of the voltage value of the base drive signal.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The present invention relates to integrated circuit devices. [Background technology]

[0002] BACKGROUND ART Power supply circuits such as switching regulators convert the voltage value of an input signal and output a signal of a desired voltage value, and in order to ensure stable operation of a switching element, use level shift circuits that expand the amplitude of the input signal and output a signal of a voltage value that is suitable for the operation of the switching element.

[0003] For example, Patent Document 1 discloses a semiconductor integrated circuit (integrated circuit device) that incorporates a level shift circuit that expands the amplitude of a signal input from a circuit that operates on a low power supply voltage and makes it compatible with a circuit that operates on a high power supply voltage. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2011-097500 Summary of the Invention [Problem to be solved by the invention]

[0005] However, in the integrated circuit device described in Patent Document 1, the level shift circuit increases the amplitude of the input signal, which requires circuit elements with high withstand voltage, leaving room for improvement. [Means for solving the problem]

[0006] One aspect of the integrated circuit device according to the present invention is 1. An integrated circuit device used in a power supply circuit that converts a first voltage signal of a first voltage value into a second voltage signal of a second voltage value and outputs the second voltage signal, a first terminal to which the first voltage signal is supplied; a second terminal to which a reference potential signal of a reference potential is supplied; a third terminal for outputting a switching signal whose voltage value changes between the first voltage value and the reference potential; a fourth terminal to which one end of a capacitor, the other end of which is electrically connected to the third terminal, is connected and to which a boot voltage signal corresponding to the switching signal is supplied; a supply control circuit having one end electrically connected to the first terminal and the other end electrically connected to the fourth terminal, the supply control circuit controlling the supply of the first voltage signal to the fourth terminal; a switching circuit that outputs the switching signal; a drive signal output circuit that outputs a drive signal for driving the switching circuit; Equipped with The drive signal output circuit a drive control circuit that outputs a base drive signal that is the basis of the drive signal; a level shift circuit that outputs the drive signal obtained by level-shifting the voltage value of the base drive signal; and The level shift circuit includes: a first limiting circuit that limits a voltage value of a first node based on a voltage value of the switching signal at a rising edge of the basic drive signal; a second limiting circuit that limits the voltage value of a second node based on the voltage value of the switching signal at the falling edge of the basic drive signal; a latch circuit that, at the rising edge of the base drive signal, holds the voltage value of the switching signal at the first node and holds the voltage value of the boot voltage signal at the second node, and, at the falling edge of the base drive signal, holds the voltage value of the boot voltage signal at the first node and holds the voltage value of the switching signal at the second node; an output circuit that level-shifts the high-level voltage value of the base drive signal to the voltage value of the boot voltage signal and level-shifts the low-level voltage value of the base drive signal to the voltage value of the switching signal according to the voltage value of the first node and the voltage value of the second node held by the latch circuit, and outputs the drive signal; It has. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 2 is a diagram illustrating an example of the configuration of a power supply circuit. [Figure 2] FIG. 2 is a diagram for explaining the operation of the power supply circuit. [Figure 3] FIG. 2 is a diagram illustrating an example of the configuration of a level shift circuit. [Figure 4] FIG. 2 is a diagram for explaining the operation of the level shift circuit. DETAILED DESCRIPTION OF THE INVENTION

[0008] Preferred embodiments of the present invention will be described below with reference to the drawings. The drawings used are for the convenience of explanation. Note that the embodiments described below do not unduly limit the content of the present invention as defined in the claims. Furthermore, not all of the configurations described below are necessarily essential components of the present invention.

[0009] 1. Power supply circuit configuration and operation 1.1 Power supply circuit configuration 1 is a diagram showing an example of the configuration of a power supply circuit 1. The power supply circuit 1 of this embodiment is a circuit that converts a voltage signal VDD having a voltage value of voltage vd into a voltage signal VOUT having a voltage value of voltage vo and outputs the converted voltage signal. In this embodiment, a so-called step-down switching regulator is used as an example to step down the voltage vd of the input voltage signal VDD to a desired voltage value of voltage vo and output the voltage signal VOUT. As shown in FIG. 1, the power supply circuit 1 includes an integrated circuit device 10, an inductor element 2, capacitor elements 3 and 6, and resistor elements 4 and 5.

[0010] The integrated circuit device 10 has terminals tvdd, tvbt, tvsw, tvfb, tvss, tgnd, and ten electrically connected to various circuits of the power supply circuit 1. The integrated circuit device 10 operates using the potential difference between voltage vd, which is the voltage value of the voltage signal VDD input via the terminal tvdd, and voltage vg, which is the voltage value of the voltage signal GND input via the terminal tgnd, as its driving power. When an enable signal EN that enables operation of the integrated circuit device 10 is input via the terminal ten, the integrated circuit device 10 generates a switching signal VSW whose voltage value changes between voltage vd and voltage vg and outputs it from the terminal tvsw. Here, the voltage signal GND may be a signal with a constant voltage value, such as a ground signal indicating the reference potential of the power supply circuit 1. In other words, voltage vg, which is the voltage value of the voltage signal GND, may be any signal with a constant predetermined voltage value, such as the ground potential that is the reference potential of the power supply circuit 1.

[0011] The integrated circuit device 10 includes a drive signal output circuit 11 , a switching circuit 12 , and a transistor 13 .

[0012] The drive signal output circuit 11 includes a drive control circuit 100 and a level shift circuit 200. The drive control circuit 100 operates using the potential difference between voltages vd and vg as drive power to control the operation of the integrated circuit device 10. Specifically, an enable signal EN and a feedback voltage signal VFB are input to the drive control circuit 100. During the period when the enable signal EN that enables operation is input, the drive control circuit 100 outputs a basic drive signal BDS whose logic level is inverted according to the voltage value of the input feedback voltage signal VFB, with the H-level voltage value being voltage vd and the L-level voltage value being voltage vg. The basic drive signal BDS output by the drive control circuit 100 is input to the level shift circuit 200. In addition, a boot voltage signal VBT and a switching signal VSW, which will be described later, are input to the level shift circuit 200. The level shift circuit 200 shifts the H-level voltage value of the input base drive signal BDS to the voltage value of the boot voltage signal VBT, and generates and outputs a drive voltage signal HDRV by shifting the L-level voltage value of the input base drive signal BDS to the voltage value of the switching signal VSW. Furthermore, during the period when an enable signal EN that enables operation is input, the drive control circuit 100 outputs a drive voltage signal LDRV whose logical level is inverted according to the voltage value of the input feedback voltage signal VFB, and whose H-level voltage value is voltage vd and whose L-level voltage value is voltage vg.

[0013] The drive voltage signals HDRV and LDRV output by the drive signal output circuit 11 are input to the switching circuit 12. The switching circuit 12 includes transistors 121 and 122, which are n-channel FETs (Field Effect Transistors). The drive voltage signal HDRV output by the drive signal output circuit 11 is supplied to the gate terminal of the transistor 121. The drain terminal of the transistor 121 is electrically connected to the terminal tvdd, and the source terminal is electrically connected to the terminal tvsw. The drive voltage signal LDRV output by the drive signal output circuit 11 is supplied to the gate terminal of the transistor 122. The drain terminal of the transistor 122 is electrically connected to the terminal tvsw, and the source terminal is electrically connected to the terminal tvss. The voltage signal GND is supplied to the terminal tvss.

[0014] As described above, the source terminal of transistor 121 and the drain terminal of transistor 122 are connected to each other, and the connection point between the source terminal of transistor 121 and the drain terminal of transistor 122 is electrically connected to terminal tvsw of integrated circuit device 10. When an H-level drive voltage signal HDRV is supplied to switching circuit 12, the drain terminal and source terminal of transistor 121 become conductive, and when an H-level drive voltage signal LDRV is supplied to switching circuit 12, the drain terminal and source terminal of transistor 122 become conductive. Therefore, when an H-level drive voltage signal HDRV is input to switching circuit 12, switching circuit 12 outputs a switching signal VSW having a voltage value of voltage vd from terminal tvsw, and when an H-level drive voltage signal LDRV is input, switching circuit 12 outputs a switching signal VSW having a voltage value of voltage vg from terminal tvsw.

[0015] That is, the switching circuit 12 controls the conduction states of the transistors 121 and 122 in accordance with the drive voltage signals HDRV and LDRV output by the drive signal output circuit 11, and outputs the switching signal VSW from a terminal tvsw, which is a connection point between the source terminal of the transistor 121 and the drain terminal of the transistor 122. Here, in the following description, a state in which the drain terminals and source terminals of the transistors 121 and 122 are controlled to be conductive will sometimes be referred to as "on," and a state in which the drain terminals and source terminals of the transistors 121 and 122 are controlled to be non-conductive will sometimes be referred to as "off."

[0016] The drive control circuit 100 also outputs a boost control signal BC whose logic level is inverted in synchronization with at least one of the base drive signal BDS and the drive voltage signal LDRV. The boost control signal BC is a signal whose H-level voltage value is voltage vd and whose L-level voltage value is voltage vg, and is supplied to the gate terminal of the transistor 13. The transistor 13 is a p-channel FET, with its source terminal electrically connected to the terminal tvdd and its drain terminal electrically connected to the terminal tvbt. When the gate terminal of the transistor 13 is supplied with a low-level boost control signal BC, the source and drain terminals are electrically connected, and when the gate terminal is supplied with a high-level boost control signal BC, the source and drain terminals are electrically disconnected. Therefore, when the gate terminal of the transistor 13 is supplied with a low-level boost control signal BC, the transistor 13 supplies the voltage signal VDD to the terminal tvbt, and when the gate terminal is supplied with a high-level boost control signal BC, the transistor 13 stops supplying the voltage signal VDD to the terminal tvbt. In the following description, the state in which the source terminal and drain terminal of transistor 13 are controlled to be conductive may be referred to as "on," and the state in which the drain terminal and source terminal of transistor 13 are controlled to be non-conductive may be referred to as "off."

[0017] One end of the inductor element 2 is electrically connected to the terminal tvsw, and the other end is electrically connected to one end of the capacitor element 3. A voltage signal GND is supplied to the other end of the capacitor element 3. That is, the inductor element 2 and the capacitor element 3 form a low-pass filter circuit. The switching signal VSW output via the terminal tvsw of the integrated circuit device 10 is smoothed by the low-pass filter circuit formed by the inductor element 2 and the capacitor element 3. The power supply circuit 1 outputs the signal smoothed by the low-pass filter circuit as a voltage signal VOUT.

[0018] One end of the resistance element 4 is electrically connected to the other end of the inductor element 2, and the other end is electrically connected to one end of the resistance element 5. A voltage signal GND is supplied to the other end of the resistance element 5. A connection point where the other end of the resistance element 4 and one end of the resistance element 5 are connected is electrically connected to the terminal tvfb of the integrated circuit device 10. That is, the resistance elements 4 and 5 divide the voltage value of the voltage signal VOUT and feed the divided signal back to the integrated circuit device 10 as a feedback voltage signal VFB.

[0019] The drive control circuit 100 controls at least one of the time when the base drive signal BDS is at a high level, the time when the base drive signal BDS is at a low level, the time when the drive voltage signal LDRV is at a high level, and the time when the drive voltage signal LDRV is at a low level, so that the voltage value of the input feedback voltage signal VFB becomes a predetermined value.

[0020] Specifically, when the voltage value of the input feedback voltage signal VFB is smaller than a predetermined voltage value, the drive control circuit 100 increases the on-duty of the output basic drive signal BDS, and when the voltage value of the input feedback voltage signal VFB is larger than the predetermined voltage value, the drive control circuit 100 increases the on-duty of the output drive voltage signal LDRV, thereby controlling the voltage value of the voltage signal VOUT smoothed by the low-pass filter circuit formed by the inductor element 2 and the capacitor element 3.

[0021] Here, the on-duty is the proportion of the time during which an H-level signal is output relative to the time from when the output signal changes from H level to when it changes from L level to H level again. For example, if the time from when the output signal changes from H level to when it changes from L level to H level again is 100 ms, and the time during which the signal is at H level is 30 ms, the on-duty is 30%. Increasing the on-duty means increasing the proportion of the time during which an H-level signal is output relative to the time during which the output signal changes from H level to when it changes from L level to H level again. For example, the time during which the output signal changes from H level to when it changes from L level to H level again may be fixed and the time during which the signal is at H level may be lengthened; the time during which the signal is at L level may be fixed and the time during which the signal is at H level may be lengthened during the period from when the output signal changes from H level to when it changes from L level to H level again; or the time during which the signal is at H level may be fixed and the time during which the signal is at H level during the period from when the output signal changes from H level to when it changes from L level to H level again.

[0022] One end of the capacitor element 6 is electrically connected to the terminal tvsw that outputs the switching signal VSW, and the other end is electrically connected to the terminal tvbt. A charge corresponding to the potential difference between one end and the other end is accumulated in the capacitor element 6. The capacitor element 6 generates a boot voltage signal VBT whose voltage value changes in accordance with changes in the voltage value of the switching signal VSW output from the terminal tvsw, and outputs the signal from the other end.

[0023] Specifically, when a switching signal VSW having a voltage value of vg is supplied to one end, the voltage value at the other end of the capacitor element 6 becomes voltage vd. When a switching signal VSW having a voltage value of vd is supplied to one end, the voltage value at the other end becomes the sum of the voltage vd supplied to the one end and the voltage vd supplied to the other end due to the accumulated charge. This voltage value at the other end of the capacitor element 6 corresponds to the boot voltage signal VBT. In other words, the capacitor element 6 accumulates charge corresponding to the voltage signal VDD supplied to the other end and functions as a bootstrap capacitor that changes the voltage value of the boot voltage signal VBT output from the other end according to the voltage value of the switching signal VSW supplied to the one end. Furthermore, the transistor 13 controls the supply of the voltage signal VDD to the other end of the capacitor element 6 according to a boost control signal BC input from the drive control circuit 100. In other words, the capacitor element 6 and the transistor 13 form a bootstrap circuit.

[0024] In the bootstrap circuit, the transistor 13 only needs to control the supply of the voltage signal VDD to the terminal tvbt in accordance with the voltage value of the switching signal VSW. Therefore, instead of the transistor 13, a diode element having an anode terminal electrically connected to the terminal tvdd and a cathode terminal electrically connected to the terminal tvbt may be used.

[0025] 1.2 Power supply circuit operation A specific example of the operation of the power supply circuit 1 configured as above will be described below. Fig. 2 is a diagram for explaining the operation of the power supply circuit 1. Note that the following description will be given taking as an example a case where the power supply circuit 1 and the integrated circuit device 10 are operating, and a voltage signal VDD having a voltage value of voltage vd and an enable signal EN that enables the operation of the integrated circuit device 10 are input to the power supply circuit 1 and the integrated circuit device 10.

[0026] As shown in FIG. 2, just before any time t10, the drive control circuit 100 of the drive signal output circuit 11 of the integrated circuit device 10 outputs a low-level base drive signal BDS, a high-level drive voltage signal LDRV, and a low-level boost control signal BC.

[0027] The L-level base drive signal BDS output by the drive control circuit 100 has its voltage value shifted by the level shift circuit 200 and is supplied to the gate terminal of the transistor 121 as the L-level drive voltage signal HDRV. This controls the transistor 121 to be OFF. Furthermore, the H-level drive voltage signal LDRV output by the drive control circuit 100 is supplied to the gate terminal of the transistor 122. This controls the transistor 122 to be ON. Therefore, just before time t10, the integrated circuit device 10 outputs an L-level switching signal VSW having a voltage value of voltage vg from the terminal tvsw.

[0028] Furthermore, the L-level boost control signal BC output by the drive control circuit 100 is supplied to the gate terminal of the transistor 13. This controls the transistor 13 to be on. Therefore, the voltage signal VDD is supplied to the terminal tvbt.

[0029] That is, just before time t10, voltage vd is supplied to the other end of capacitor element 6. At this time, voltage vg, which is the voltage value of switching signal VSW, is supplied to one end of capacitor element 6. Therefore, just before time t10, charge corresponding to the potential difference between voltage vd and voltage vg is accumulated in capacitor element 6, and boot voltage signal VBT of voltage vd is input to integrated circuit device 10.

[0030] Then, at time t10, the drive control circuit 100 sets the boost control signal BC to H level, the drive voltage signal LDRV to L level, and the base drive signal BDS to H level.

[0031] The high-level boost control signal BC output by the drive control circuit 100 is supplied to the gate terminal of the transistor 13. This controls the transistor 13 to be turned off. As a result, the supply of the voltage signal VDD to the terminal tvbt is stopped. At this time, the voltage value of the terminal tvbt, which is the voltage value of the boot voltage signal VBT, is maintained at the voltage vd, which is the voltage value of the voltage signal VDD.

[0032] The L-level drive voltage signal LDRV output by the drive control circuit 100 is supplied to the gate terminal of the transistor 122. This controls the transistor 122 to be turned off.

[0033] The H-level base drive signal BDS output by the drive control circuit 100 is input to the level shift circuit 200. The level shift circuit 200 generates an H-level drive voltage signal HDRV by level-shifting the voltage value of the H-level base drive signal BDS input to the voltage value of the boot voltage signal VBT. Then, at time t20 after time t10, the H-level drive voltage signal HDRV generated by the level shift circuit 200 is output from the integrated circuit device 10 and supplied to the gate terminal of the transistor 121. This controls the transistor 121 to be turned on.

[0034] Then, at time t20, transistor 121 is controlled to be turned on and transistor 122 is controlled to be turned off, causing the voltage value of switching signal VSW to rise toward voltage vd, which is the voltage value of voltage signal VDD. At this time, transistor 13 is controlled to be turned off, causing the voltage value of the other end of capacitor element 6, that is, the voltage value of boot voltage signal VBT, to rise from voltage vd toward voltage vb due to the charge accumulated in capacitor element 6. Therefore, the voltage value of H-level drive voltage signal HDRV output by integrated circuit device 10 also rises toward voltage vb.

[0035] As described above, at time t20, the transistor 121 is controlled to be on, the transistor 122 is controlled to be off, and the transistor 13 is controlled to be off, causing the integrated circuit device 10 to output a switching signal VSW whose voltage value is the voltage vd.

[0036] At a subsequent time t30, the drive signal output circuit 11 sets the reference drive signal BDS to an L level. The L-level reference drive signal BDS output by the drive signal output circuit 11 is input to the level shift circuit 200. The level shift circuit 200 generates an L-level drive voltage signal HDRV by level-shifting the voltage value of the input L-level reference drive signal BDS to the voltage value of the switching signal VSW. Then, at time t40 after time t30, the L-level drive voltage signal HDRV generated by the level shift circuit 200 is supplied to the gate terminal of the transistor 121. This controls the transistor 121 to be turned off.

[0037] Furthermore, at time t40, the drive control circuit 100 sets the drive voltage signal LDRV to an H level and the boost control signal BC to an L level. At this time, the drive control circuit 100 sets the drive voltage signal LDRV to an H level at a timing when the drive voltage signals LDRV and HDRV do not simultaneously go to an H level. Specifically, the drive control circuit 100 may detect that the drive voltage signal HDRV output by the level shift circuit 200 has gone to an L level, and, depending on the detection result, set the drive voltage signal LDRV to an H level and the boost control signal BC to an L level. Alternatively, the drive control circuit 100 may set the drive voltage signal LDRV to an H level and the boost control signal BC to an L level after a certain period has elapsed after time t30. Hereinafter, the drive control circuit 100 will be described as controlling the logical levels of the basic drive signal BDS and the drive voltage signal LDRV so that the drive voltage signals LDRV and HDRV are exclusively at an H level. That is, in this embodiment, the drive voltage signal LDRV and the drive voltage signal HDRV being exclusively at the H level means that the drive voltage signal LDRV and the drive voltage signal HDRV are not at the H level at the same time, and includes the case where the drive voltage signal LDRV and the drive voltage signal HDRV are at the L level at the same time.

[0038] The L-level boost control signal BC output by the drive control circuit 100 is supplied to the gate terminal of the transistor 13. This controls the transistor 13 to be turned on. In addition, the H-level drive voltage signal LDRV output by the drive control circuit 100 is supplied to the gate terminal of the transistor 122. This controls the transistor 122 to be turned on.

[0039] Therefore, at time t40, transistor 121 is controlled to be turned off, and transistor 122 is controlled to be turned on. As a result, the voltage value of the switching signal VSW output by integrated circuit device 10 decreases toward voltage vg. At this time, because transistor 13 is controlled to be turned on, the voltage value of the boot voltage signal VBT, which is the voltage value of the other end of capacitor element 6, also decreases toward voltage vd, which is the voltage value of the voltage signal VDD supplied via transistor 13.

[0040] As described above, at time t40, the transistor 121 of the integrated circuit device 10 is controlled to be off, the transistor 122 is controlled to be on, and the transistor 13 is controlled to be on, causing the integrated circuit device 10 to output a switching signal VSW whose voltage value is the voltage vg.

[0041] At a subsequent time t50, the drive control circuit 100 sets the boost control signal BC to H level, the drive voltage signal LDRV to L level, and the base drive signal BDS to H level. That is, at time t50, the power supply circuit 1 performs the same operation as at time t10 described above. In other words, the power supply circuit 1 repeatedly performs the operation from time t10 to t50. Hereinafter, the period from time t10 to t50 will be referred to as the drive period Dc of the power supply circuit 1.

[0042] In the power supply circuit 1, the integrated circuit device 10 outputs a switching signal VSW from the terminal tvsw, whose voltage value changes between voltage vd and voltage vg for each drive period Dc. The switching signal VSW output by the integrated circuit device 10 is smoothed by a low-pass filter circuit formed by an inductor element 2 and a capacitor element 3, causing the power supply circuit 1 to output a voltage signal VOUT.

[0043] At this time, the integrated circuit device 10 controls the on-duty of the base drive signal BDS and the on-duty of the drive voltage signal LDRV based on the voltage value of the feedback voltage signal VFB that is fed back in accordance with the voltage value of the voltage signal VOUT output by the power supply circuit 1.

[0044] Specifically, when the voltage value of the input feedback voltage signal VFB is smaller than a predetermined voltage value, the integrated circuit device 10 delays the timing at which the drive control circuit 100 sets the reference drive signal BDS to the L level at time t30 in the drive period Dc. This increases the on-duty of the reference drive signal BDS and decreases the on-duty of the drive voltage signal LDRV. Therefore, the on-duty of the switching signal VSW output by the integrated circuit device 10 increases. As a result, the voltage value of the voltage signal VOUT, which is a smoothed version of the switching signal VSW, increases.

[0045] On the other hand, when the voltage value of the input feedback voltage signal VFB is greater than a predetermined voltage value, the integrated circuit device 10 advances the timing at which the drive control circuit 100 sets the reference drive signal BDS to L level at time t30 in the drive period Dc. This reduces the on-duty of the reference drive signal BDS and increases the on-duty of the drive voltage signal LDRV. Therefore, the on-duty of the switching signal VSW output by the integrated circuit device 10 decreases. As a result, the voltage value of the voltage signal VOUT, which is a smoothed version of the switching signal VSW, decreases.

[0046] As described above, in the power supply circuit 1 of this embodiment, the integrated circuit device 10 controls the on-duty of the basic drive signal BDS and the on-duty of the drive voltage signal LDRV in accordance with the input feedback voltage signal VFB, thereby controlling the on-duty of the switching signal VSW. Then, a low-pass filter circuit formed by the inductor element 2 and the capacitor element 3 smoothes the on-duty controlled switching signal VSW, and the power supply circuit 1 outputs a voltage signal VOUT having a desired voltage value, vo.

[0047] That is, the power supply circuit 1 of this embodiment is a circuit that converts a voltage signal VDD having a voltage value of voltage vd into a voltage signal VOUT having a voltage value of voltage vo and outputs the converted voltage signal, and the integrated circuit device 10 included in the power supply circuit 1 has a terminal tvdd to which the voltage signal VDD is supplied, a terminal tvss to which a voltage signal GND having a voltage vg that is a reference potential is supplied, a terminal tvsw to which a switching signal VSW having a voltage value that changes between voltage vd and voltage vg is output, and a terminal tv bt, a transistor 13 having one end electrically connected to terminal tvdd and the other end electrically connected to terminal tvbt and controlling the supply of a voltage signal VDD to terminal tvbt, a switching circuit 12 that outputs a switching signal VSW, and a drive signal output circuit 11 that outputs drive voltage signals HDRV, LDRV that drive the switching circuit 12, and the drive signal output circuit 11 has a drive control circuit 100 that outputs a base drive signal BDS that is the basis of the drive voltage signal HDRV, and a level shift circuit 200 that outputs a drive voltage signal HDRV that is a level-shifted voltage value of the base drive signal BDS.

[0048] The power supply circuit 1 is not limited to a step-down switching regulator, but may be, for example, a step-up switching regulator.

[0049] 2. Level shift circuit configuration 2.1 Level shift circuit configuration Next, a description will be given of the configuration and operation of the level shift circuit 200 included in the integrated circuit device 10. Fig. 3 is a diagram showing an example of the configuration of the level shift circuit 200. As shown in Fig. 3, the level shift circuit 200 includes a pulse signal output circuit 210, detection circuits 220 and 230, a latch circuit 240, and an output circuit 250.

[0050] A reference drive signal BDS is input to the pulse signal output circuit 210. The pulse signal output circuit 210 outputs pulse signals VIN1 and VIN2 whose H-level voltage value is voltage vd and whose L-level voltage value is voltage vg. Specifically, the pulse signal output circuit 210 outputs an L-level pulse signal VIN1 and an L-level pulse signal VIN2 while the reference drive signal BDS input is at L or H level for a certain period of time. The pulse signal output circuit 210 inverts the logic level of the pulse signal VIN1 to be output to H level for a certain period of time at the rising edge where the logic level of the reference drive signal BDS input switches from L level to H level, and inverts the logic level of the pulse signal VIN2 to be output to H level for a certain period of time at the falling edge where the logic level of the reference drive signal BDS input switches from H level to L level. That is, the level shift circuit 200 has a pulse signal output circuit 210 that outputs a pulse signal VIN1 whose logic level is inverted for a certain period at the rising edge of the base drive signal BDS, and a pulse signal VIN2 whose logic level is inverted for a certain period at the falling edge of the base drive signal BDS.

[0051] The detection circuit 220 includes a transistor 221, which is a p-channel FET, and a transistor 222, which is an n-channel FET. A switching signal VSW is supplied to a gate terminal of the transistor 221. A source terminal of the transistor 221 is electrically connected to a node W1. A drain terminal of the transistor 221 is electrically connected to a drain terminal of the transistor 222. A voltage signal GND is supplied to a source terminal of the transistor 222. A pulse signal VIN1 is supplied to a gate terminal of the transistor 222.

[0052] The transistor 221 is conductive between its source terminal and drain terminal when the voltage value of the node W1 is greater than the voltage value of the switching signal VSW, and is non-conductive between its source terminal and drain terminal when the voltage value of the node W1 is equal to or less than the voltage value of the switching signal VSW. The transistor 222 is conductive between its drain terminal and source terminal when an H-level pulse signal VIN1 is supplied to its gate terminal, and is non-conductive between its drain terminal and source terminal when an L-level pulse signal VIN1 is supplied to its gate terminal. That is, at the rising edge of the basic drive signal BDS, the drain terminal and source terminal of the transistor 222 are controlled to be conductive. Hereinafter, a state in which the drain terminals and source terminals of the transistors 221 and 222 are controlled to be conductive will be referred to as "on," and a state in which the drain terminals and source terminals of the transistors 221 and 222 are controlled to be non-conductive will be referred to as "off."

[0053] The detection circuit 220 configured as described above operates in response to the potential difference between the voltage signal GND and the switching signal VSW. When an H-level pulse signal VIN1 is input to the detection circuit 220, the transistor 222 is turned on. At this time, if the voltage value of the node W1 is greater than the voltage value of the switching signal VSW, the transistor 221 is turned on. This causes the voltage value of the node W1 to decrease toward the voltage vg. When the voltage value of the node W1 decreases and becomes substantially equal to the voltage value of the switching signal VSW, the transistor 221 is turned off. In other words, the voltage value of the node W1 is limited to the voltage value of the switching signal VSW. In other words, the detection circuit 220 limits the voltage value of the node W1 based on the voltage value of the switching signal VSW at the rising edge of the base drive signal BDS.

[0054] The detection circuit 230 includes a transistor 231, which is a p-channel FET, and a transistor 232, which is an n-channel FET. A switching signal VSW is supplied to a gate terminal of the transistor 231. A source terminal of the transistor 231 is electrically connected to a node W2. A drain terminal of the transistor 231 is electrically connected to a drain terminal of the transistor 232. A voltage signal GND is supplied to a source terminal of the transistor 232. A pulse signal VIN2 is supplied to a gate terminal of the transistor 232.

[0055] The transistor 231 is conductive between its source terminal and drain terminal when the voltage value of the node W2 is greater than the voltage value of the switching signal VSW, and is non-conductive between its source terminal and drain terminal when the voltage value of the node W2 is equal to or less than the voltage value of the switching signal VSW. The transistor 232 is conductive between its drain terminal and source terminal when an H-level pulse signal VIN2 is supplied to its gate terminal, and is non-conductive between its drain terminal and source terminal when an L-level pulse signal VIN2 is supplied to its gate terminal. That is, at the falling edge of the basic drive signal BDS, the drain terminal and source terminal of the transistor 232 are controlled to be conductive. Hereinafter, a state in which the drain terminals and source terminals of the transistors 231 and 232 are controlled to be conductive will be referred to as "on," and a state in which the drain terminals and source terminals of the transistors 231 and 232 are controlled to be non-conductive will be referred to as "off."

[0056] The detection circuit 230 configured as described above operates in response to the potential difference between the voltage signal GND and the switching signal VSW. When an H-level pulse signal VIN2 is input to the detection circuit 230, the transistor 232 is turned on. At this time, if the voltage value of the node W2 is greater than the voltage value of the switching signal VSW, the transistor 231 is turned on. This causes the voltage value of the node W2 to decrease toward the voltage vg. When the voltage value of the node W2 decreases and becomes substantially equal to the voltage value of the switching signal VSW, the transistor 231 is turned off. In other words, the voltage value of the node W2 is limited to the voltage value of the switching signal VSW. In other words, the detection circuit 230 limits the voltage value of the node W2 based on the voltage value of the switching signal VSW at the falling edge of the basic drive signal BDS.

[0057] The latch circuit 240 includes transistors 241 and 243, which are p-channel FETs, and transistors 242 and 244, which are n-channel FETs.

[0058] The transistor 241 has a gate terminal electrically connected to the node W2, a drain terminal electrically connected to the node W1, and a source terminal supplied with the boot voltage signal VBT. The transistor 242 has a gate terminal electrically connected to the node W2, a drain terminal electrically connected to the node W1, and a source terminal supplied with the switching signal VSW. The transistor 243 has a gate terminal electrically connected to the node W1, a drain terminal electrically connected to the node W2, and a source terminal supplied with the boot voltage signal VBT. The transistor 244 has a gate terminal electrically connected to the node W1, a drain terminal electrically connected to the node W2, and a source terminal supplied with the switching signal VSW. The latch circuit 240 holds one of the voltage values ​​of the boot voltage signal VBT and the switching signal VSW at the node W1 and the other of the voltage values ​​of the boot voltage signal VBT and the switching signal VSW at the node W2, depending on the operation of the detection circuits 220 and 230. In the following description, the signal held at node W1 is referred to as a latch signal VND, and the signal held at node W2 is referred to as a latch signal VxND.

[0059] Specifically, when an H-level pulse signal VIN1 is input to the detection circuit 220, if the voltage value of node W1 is greater than the voltage value of the switching signal VSW, the voltage value of node W1 is limited by the transistor 221 and becomes approximately equal to the voltage value of the switching signal VSW. When the voltage value of node W1 becomes approximately equal to the voltage value of the switching signal VSW, the source terminal and drain terminal of transistor 243 become conductive, and the drain terminal and source terminal of transistor 244 become non-conductive. As a result, the boot voltage signal VBT is supplied to node W2 via transistor 243, and the voltage value of node W2 becomes approximately equal to the voltage value of the boot voltage signal VBT. That is, the latch circuit 240 holds the voltage value of the boot voltage signal VBT as the latch signal VxND.

[0060] Then, when the voltage value of node W2 becomes approximately equal to the voltage value of the boot voltage signal VBT, the source terminal and drain terminal of transistor 241 become non-conductive, and the drain terminal and source terminal of transistor 242 become conductive. As a result, the switching signal VSW is supplied to node W1 via transistor 242, and the voltage value of node W1 becomes approximately equal to the voltage value of the switching signal VSW. That is, the latch circuit 240 holds the voltage value of the switching signal VSW as the latch signal VND.

[0061] As described above, when the voltage value of node W1 is greater than the voltage value of the switching signal VSW, if an H-level pulse signal VIN1 is input to the detection circuit 220, the latch circuit 240 holds the voltage value of the switching signal VSW as the latch signal VND and holds the voltage value of the boot voltage signal VBT as the latch signal VxND.

[0062] Furthermore, when an H-level pulse signal VIN2 is input to the detection circuit 230, if the voltage value of node W2 is greater than the voltage value of the switching signal VSW, the voltage value of node W2 is limited by the transistor 231 and becomes approximately equal to the voltage value of the switching signal VSW. When the voltage value of node W2 becomes approximately equal to the voltage value of the switching signal VSW, the source terminal and drain terminal of transistor 241 become conductive, and the drain terminal and source terminal of transistor 242 become non-conductive. As a result, the boot voltage signal VBT is supplied to node W1 via transistor 241, and the voltage value of node W1 becomes approximately equal to the voltage value of the boot voltage signal VBT. That is, the latch circuit 240 holds the voltage value of the boot voltage signal VBT as the latch signal VND.

[0063] Then, when the voltage value of node W1 becomes approximately equal to the voltage value of the boot voltage signal VBT, the source terminal and drain terminal of transistor 243 become non-conductive, and the drain terminal and source terminal of transistor 244 become conductive. As a result, the switching signal VSW is supplied to node W2 via transistor 244, and the voltage value of node W2 becomes approximately equal to the voltage value of the switching signal VSW. That is, the latch circuit 240 holds the voltage value of the switching signal VSW as the latch signal VxND.

[0064] As described above, when the voltage value of node W2 is greater than the voltage value of the switching signal VSW, if an H-level pulse signal VIN2 is input to the detection circuit 230, the latch circuit 240 holds the voltage value of the boot voltage signal VBT as the latch signal VND, and holds the voltage value of the switching signal VSW as the latch signal VxND.

[0065] That is, the latch circuit 240 operates in accordance with the potential difference between the switching signal VSW and the boot voltage signal VBT, based on the operations of the detection circuits 220 and 230. The latch circuit 240 includes a node W1 at which the latch signal VND is latched and a node W2 at which the latch signal VxND is latched, and when an H-level pulse signal VIN1 is input to the detection circuit 220, during a period in which the logic level of the base drive signal BDS inverts from an L level to an H level, the latch circuit 240 holds the voltage value of the switching signal VSW as the latch signal VND at the node W1 and holds the voltage value of the boot voltage signal VBT as the latch signal VxND at the node W2, and when an H-level pulse signal VIN2 is input to the detection circuit 230, during a period in which the logic level of the base drive signal BDS inverts from an H level to an L level, the latch circuit 240 holds the voltage value of the boot voltage signal VBT as the latch signal VND at the node W1 and holds the voltage value of the switching signal VSW as the latch signal VxND at the node W2. In the following description, the state in which the drain terminals and source terminals of transistors 241 to 244 are controlled to be conductive may be referred to as "on," and the state in which the drain terminals and source terminals of transistors 241 to 244 are controlled to be non-conductive may be referred to as "off."

[0066] The output circuit 250 includes a level shift signal output circuit 260 and an inverter circuit 270 .

[0067] The level shift signal output circuit 260 generates and outputs a level shift signal LSO according to the latch signals VND and VxND held by the latch circuit 240. The level shift signal output circuit 260 includes transistors 261 and 262, which are n-channel FETs, and transistors 263 and 264, which are p-channel FETs.

[0068] The transistor 261 has a gate terminal electrically connected to the node W1, a drain terminal electrically connected to the node W3, and a source terminal supplied with the switching signal VSW. The transistor 262 has a gate terminal electrically connected to the node W2, a drain terminal electrically connected to the node W4, and a source terminal supplied with the switching signal VSW. The transistor 263 has a gate terminal electrically connected to the node W4, a drain terminal electrically connected to the node W3, and a source terminal supplied with the boot voltage signal VBT. The transistor 264 has a gate terminal electrically connected to the node W3, a drain terminal electrically connected to the node W4, and a source terminal supplied with the boot voltage signal VBT. The level shift signal output circuit 260 outputs the voltage value of the node W4 as the level shift signal LSO.

[0069] When the voltage value of the switching signal VSW as the latch signal VND and the voltage value of the boot voltage signal VBT as the latch signal VxND are input to the level shift signal output circuit 260 configured as described above, i.e., when an H-level pulse signal VIN1 is input to the detection circuit 220, the drain terminal and source terminal of the transistor 261 become non-conductive and the drain terminal and source terminal of the transistor 262 become conductive. Then, when the drain terminal and source terminal of the transistor 262 become conductive, the voltage value of the switching signal VSW is supplied to the node W4 via the transistor 262. Furthermore, when the voltage value of the switching signal VSW is supplied to the node W4, the source terminal and drain terminal of the transistor 263 become conductive. As a result, the voltage value of the boot voltage signal VBT is supplied to the node W3 via the transistor 263. Therefore, the source terminal and drain terminal of the transistor 264 become non-conductive. As a result, the level shift signal output circuit 260 outputs the voltage value of the switching signal VSW as the level shift signal LSO.

[0070] Furthermore, when the voltage value of the boot voltage signal VBT as the latch signal VND and the voltage value of the switching signal VSW as the latch signal VxND are input to the level shift signal output circuit 260, i.e., when an H-level pulse signal VIN2 is input to the detection circuit 230, conduction occurs between the drain terminal and the source terminal of the transistor 261, and conduction does not occur between the drain terminal and the source terminal of the transistor 262. Then, as the drain terminal and the source terminal of the transistor 261 become conductive, the voltage value of the switching signal VSW is supplied to the node W3 via the transistor 261. Furthermore, as the voltage value of the switching signal VSW is supplied to the node W3, conduction occurs between the source terminal and the drain terminal of the transistor 264. As a result, the voltage value of the boot voltage signal VBT is supplied to the node W4 via the transistor 264. Therefore, conduction does not occur between the source terminal and the drain terminal of the transistor 263. As a result, the level shift signal output circuit 260 outputs the voltage value of the boot voltage signal VBT as the level shift signal LSO.

[0071] As described above, when the latch circuit 240 holds the voltage value of the switching signal VSW as the latch signal VND and holds the voltage value of the boot voltage signal VBT as the latch signal VxND, and the logic level of the base drive signal BDS input to the level shift circuit 200 changes from L level to H level, the level shift signal output circuit 260 outputs the voltage value of the switching signal VSW as the level shift signal LSO, and when the latch circuit 240 holds the voltage value of the boot voltage signal VBT as the latch signal VND and holds the voltage value of the switching signal VSW as the latch signal VxND, and the logic level of the base drive signal BDS input to the level shift circuit 200 changes from H level to L level, the level shift signal output circuit 260 outputs the voltage value of the boot voltage signal VBT as the level shift signal LSO. Here, in the following description, a state in which the drain terminals and source terminals of the transistors 261 to 264 are controlled to be conductive is sometimes referred to as "on," and a state in which the drain terminals and source terminals of the transistors 261 to 264 are controlled to be non-conductive is sometimes referred to as "off."

[0072] The level shift signal LSO output by the level shift signal output circuit 260 is input to the inverter circuit 270. The inverter circuit 270 includes inverters 280, 290-1 to 290-4. The inverter circuit 270 inverts the logic level of the input level shift signal LSO using each of the inverters 280, 290-1 to 290-4, and outputs the inverted signal as the drive voltage signal HDRV.

[0073] The inverter 280 includes transistors 281, 282, and 285, which are p-channel FETs, and transistors 283, 284, and 286, which are n-channel FETs.

[0074] The level shift signal LSO output by the level shift signal output circuit 260 is supplied to the gate terminal of a transistor 281, a gate terminal of a transistor 282, a gate terminal of a transistor 283, and a gate terminal of a transistor 284. A boot voltage signal VBT is supplied to the source terminal of the transistor 281. A drain terminal of the transistor 281 is electrically connected to the source terminal of the transistor 282. A drain terminal of the transistor 282 is electrically connected to the drain terminal of the transistor 283. A source terminal of the transistor 283 is electrically connected to the drain terminal of the transistor 284. A switching signal VSW is supplied to the source terminal of the transistor 284. That is, the transistors 281 and 282 are cascade-connected, and the transistors 283 and 284 are cascade-connected. This reduces the possibility that unintended noise superimposed on the level shift signal LSO will exceed the breakdown voltage of the transistors 281 to 286. Then, the inverter 280 outputs the signal at the connection point between the drain terminal of the transistor 282 and the drain terminal of the transistor 283 as the inverted level shift signal xLSO.

[0075] The transistor 285 has a source terminal supplied with a boot voltage signal VBT, a drain terminal electrically connected to the drain terminal of the transistor 281 and the source terminal of the transistor 282, and a gate terminal supplied with a signal output by an inverter 290-1 (described later). That is, the transistor 285 is connected in parallel with the transistor 281, and the conduction state between the drain terminal and the source terminal is switched in accordance with the signal output by the inverter 290-1. Also, the transistor 286 has a source terminal supplied with a switching signal VSW, a drain terminal electrically connected to the source terminal of the transistor 283 and the drain terminal of the transistor 284, and a gate terminal supplied with a signal output by the inverter 290-1 (described later). That is, the transistor 286 is connected in parallel with the transistor 284, and the conduction state between the drain terminal and the source terminal is switched in accordance with the signal output by the inverter 290-1.

[0076] This makes it possible to increase the amount of current flowing into the connection point between the drain terminal of the transistor 282 and the drain terminal of the transistor 283 when the level shift signal LSO is input to the inverter 280. As a result, the rising edge of the level shift signal LSO can be made steeper, improving the waveform accuracy of the level shift signal LSO and the waveform accuracy of the drive voltage signal HDRV.

[0077] The inverter 290-1 includes a transistor 291-1, which is a p-channel FET, and a transistor 292-1, which is an n-channel FET. The inverted level shift signal xLSO output by the inverter 280 is supplied to the gate terminal of the transistor 291-1 and the gate terminal of the transistor 292-1. The source terminal of the transistor 291-1 is supplied with the boot voltage signal VBT. The drain terminal of the transistor 291-1 is electrically connected to the drain terminal of the transistor 292-1. The source terminal of the transistor 292-1 is supplied with the switching signal VSW. The inverter 290-1 outputs a signal at the connection point between the drain terminal of the transistor 291-1 and the drain terminal of the transistor 292-1.

[0078] The inverter 290-2 includes a transistor 291-2, which is a p-channel FET, and a transistor 292-2, which is an n-channel FET. The signal output by the inverter 290-1 is supplied to the gate terminal of the transistor 291-2 and the gate terminal of the transistor 292-2. The source terminal of the transistor 291-2 is supplied with a boot voltage signal VBT. The drain terminal of the transistor 291-2 is electrically connected to the drain terminal of the transistor 292-2. The source terminal of the transistor 292-2 is supplied with a switching signal VSW. The inverter 290-2 outputs a signal at the connection point between the drain terminal of the transistor 291-2 and the drain terminal of the transistor 292-2.

[0079] The inverter 290-3 includes a transistor 291-3, which is a p-channel FET, and a transistor 292-3, which is an n-channel FET. The signal output by the inverter 290-3 is supplied to the gate terminal of the transistor 291-3 and the gate terminal of the transistor 292-3. The boot voltage signal VBT is supplied to the source terminal of the transistor 291-3. The drain terminal of the transistor 291-3 is electrically connected to the drain terminal of the transistor 292-3. The switching signal VSW is supplied to the source terminal of the transistor 292-3. The inverter 290-3 outputs a signal at the connection point between the drain terminal of the transistor 291-3 and the drain terminal of the transistor 292-3.

[0080] The inverter 290-4 includes a transistor 291-4, which is a p-channel FET, and a transistor 292-4, which is an n-channel FET. The signal output by the inverter 290-3 is supplied to the gate terminal of the transistor 291-4 and the gate terminal of the transistor 292-4. The source terminal of the transistor 291-4 is supplied with a boot voltage signal VBT. The drain terminal of the transistor 291-4 is electrically connected to the drain terminal of the transistor 292-4. The source terminal of the transistor 292-4 is supplied with a switching signal VSW. The inverter 290-4 outputs the signal at the connection point between the drain terminal of the transistor 291-4 and the drain terminal of the transistor 292-4 as a drive voltage signal HDRV.

[0081] As described above, the output circuit 250 operates in accordance with the voltage values ​​of the latch signals VND and VxND latched by the latch circuit 240, and in response to the potential difference between the switching signal VSW and the boot voltage signal VBT.

[0082] Specifically, when the logic level of the base drive signal BDS input to the level shift circuit 200 changes from L level to H level and a level-shift signal LSO having the voltage value of the switching signal VSW is input to the inverter circuit 270, the source terminals and drain terminals of the transistors 281 and 282 are controlled to be conductive, and the drain terminals and source terminals of the transistors 283 and 284 are controlled to be non-conductive. Therefore, the boot voltage signal VBT is supplied to the connection point between the drain terminal of the transistor 282 and the drain terminal of the transistor 283 via the transistors 281 and 282. That is, the inverter 280 outputs an inverted level-shift signal xLSO whose voltage value is the boot voltage signal VBT.

[0083] The inverter 280 outputs an inverted level-shifted signal xLSO, whose voltage value is the boot voltage signal VBT, which is input to the inverter 290-1. This causes the source terminal and drain terminal of the transistor 291-1 to be non-conductive, and the drain terminal and source terminal of the transistor 292-1 to be conductive. Therefore, the inverter 290-1 outputs a signal whose voltage value is the switching signal VSW.

[0084] The signal output from inverter 290-1, whose voltage value is the switching signal VSW, is input to inverter 290-2. This causes conduction between the source terminal and drain terminal of transistor 291-2, and causes non-conduction between the drain terminal and source terminal of transistor 292-2. Therefore, inverter 290-2 outputs a signal whose voltage value is the boot voltage signal VBT.

[0085] The signal output by inverter 290-2, whose voltage value is the boot voltage signal VBT, is input to inverter 290-3. This causes the source terminal and drain terminal of transistor 291-3 to be non-conductive, and the drain terminal and source terminal of transistor 292-3 to be conductive. Therefore, inverter 290-3 outputs a signal whose voltage value is the switching signal VSW.

[0086] The signal output by inverter 290-3, whose voltage value is the switching signal VSW, is input to inverter 290-4. As a result, the source terminal and drain terminal of transistor 291-4 are controlled to be conductive, and the drain terminal and source terminal of transistor 292-4 are controlled to be non-conductive. Therefore, inverter 290-4 outputs a signal whose voltage value is the boot voltage signal VBT. The signal output by inverter 290-4 is output from output circuit 250 and level shift circuit 200 as drive voltage signal HDRV.

[0087] Furthermore, when the logic level of the base drive signal BDS input to the level shift circuit 200 changes from H level to L level and a level-shift signal LSO having the voltage value of the boot voltage signal VBT is input to the inverter circuit 270, the source terminals and drain terminals of the transistors 281 and 282 are controlled to be non-conductive, and the drain terminals and source terminals of the transistors 283 and 284 are controlled to be conductive. Therefore, the switching signal VSW is supplied to the connection point between the drain terminal of the transistor 282 and the drain terminal of the transistor 283 via the transistors 283 and 284. That is, the inverter 280 outputs an inverted level-shift signal xLSO whose voltage value is the same as that of the switching signal VSW.

[0088] The inverter 280 outputs an inverted level-shifted signal xLSO, whose voltage value is the switching signal VSW, and the inverted level-shifted signal xLSO is input to the inverter 290-1. This causes the source terminal and drain terminal of the transistor 291-1 to be electrically connected, and the drain terminal and source terminal of the transistor 292-1 to be electrically disconnected. Therefore, the inverter 290-1 outputs a signal whose voltage value is the boot voltage signal VBT.

[0089] The signal output by inverter 290-1, whose voltage value is the boot voltage signal VBT, is input to inverter 290-2. This causes the source terminal and drain terminal of transistor 291-2 to be non-conductive, and the drain terminal and source terminal of transistor 292-2 to be conductive. Therefore, inverter 290-2 outputs a signal whose voltage value is the switching signal VSW.

[0090] The signal output from inverter 290-2, whose voltage value is the switching signal VSW, is input to inverter 290-3. This controls conduction between the source terminal and the drain terminal of transistor 291-3, and controls non-conduction between the drain terminal and the source terminal of transistor 292-3. Therefore, inverter 290-3 outputs a signal whose voltage value is the boot voltage signal VBT.

[0091] The signal output by inverter 290-3, whose voltage value is the boot voltage signal VBT, is input to inverter 290-4. As a result, the source terminal and drain terminal of transistor 291-4 are controlled to be non-conductive, and the drain terminal and source terminal of transistor 292-4 are controlled to be conductive. Therefore, inverter 290-4 outputs a signal whose voltage value is the switching signal VSW. The signal output by inverter 290-4 is output from output circuit 250 and level shift circuit 200 as drive voltage signal HDRV.

[0092] In the following description, the state in which the drain terminals and source terminals of transistors 281 to 286, 291-1 to 291-4, and 292-1 to 292-4 are controlled to be conductive may be referred to as "on," and the state in which the drain terminals and source terminals of transistors 281 to 286, 291-1 to 291-4, and 292-1 to 292-4 are controlled to be non-conductive may be referred to as "off."

[0093] As described above, the output circuit 250 outputs, as the drive voltage signal HDRV, a signal whose voltage value becomes the boot voltage signal VBT when the logical level of the reference drive signal BDS input to the level shift circuit 200 changes from L level to H level, and outputs, as the drive voltage signal HDRV, a signal whose voltage value becomes the switching signal VSW when the logical level of the reference drive signal BDS input to the level shift circuit 200 changes from H level to L level. That is, when the reference drive signal BDS is at H level, the output circuit 250 outputs a drive voltage signal HDRV whose voltage value becomes the voltage value of the boot voltage signal VBT, and when the reference drive signal BDS is at L level, the output circuit 250 outputs a drive voltage signal HDRV whose voltage value becomes the voltage value of the switching signal VSW. In other words, the output circuit 250 level-shifts the voltage vd, which is the H-level voltage value of the reference drive signal BDS, to the voltage value of the boot voltage signal VBT, and level-shifts the voltage vg, which is the L-level voltage value of the reference drive signal BDS, to the voltage value of the switching signal VSW, to generate a drive voltage signal HDRV.

[0094] As described above, in the output circuit 250, the conduction state between the drain terminal and source terminal of the transistor 261, the conduction state between the drain terminal and source terminal of the transistor 262, the conduction state between the drain terminal and source terminal of the transistor 263, and the conduction state between the drain terminal and source terminal of the transistor 264 change in response to the latch signal VND and the latch signal VxND latched by the latch circuit 240. As a result, the voltage value of the node W4 changes between the voltage value of the boot voltage signal VBT and the voltage value of the switching signal VSW. Then, the output circuit 250 outputs a signal according to the voltage value of the fourth node as the drive voltage signal HDRV. That is, the output circuit 250 operates according to the potential difference between the voltage value of the switching signal VSW and the voltage value of the boot voltage signal VBT, and level-shifts the high-level voltage value of the base drive signal BDS to the voltage value of the boot voltage signal VBT according to the voltage value of the latch signal VND held at node W1 and the latch signal VxND held at node W2, and outputs a drive voltage signal HDRV that has level-shifted the low-level voltage value of the base drive signal BDS to the voltage value of the switching signal VSW.

[0095] The drive voltage signal HDRV output from the output circuit 250 is output from the level shift circuit 200 and input to the switching circuit 12.

[0096] In the following description, the state in which the drain terminal and source terminal of each transistor in the level shift circuit 200 are controlled to be conductive may be referred to as "on," and the state in which the drain terminal and source terminal of the transistor are controlled to be non-conductive may be referred to as "off."

[0097] 2.2 Operation of the level shift circuit A specific example of the operation of the level shift circuit 200 configured as above will be described. Fig. 4 is a diagram for explaining the operation of the level shift circuit 200. Here, times t10, t20, t30, and t40 shown in Fig. 4 correspond to times t10, t20, t30, and t40 shown in Fig. 2, respectively.

[0098] As shown in FIG. 4, just before time t10, the drive control circuit 100 outputs an L-level basic drive signal BDS with a voltage value of voltage vg. Therefore, just before time t10, the voltage value of the drive voltage signal HDRV output by the level shift circuit 200 becomes the voltage value of the switching signal VSW just before time t10. As a result, just before time t10, the transistor 121 is controlled to be on. Also, just before time t10, the drive control circuit 100 outputs an H-level drive voltage signal LDRV with a voltage value of voltage vd. As a result, just before time t10, the transistor 122 is controlled to be off. Therefore, just before time t10, the voltage value of the switching signal VSW becomes voltage vg, and the voltage value of the boot voltage signal VBT becomes voltage vd. That is, immediately before time t10, the voltage value of the drive voltage signal HDRV output by the drive signal output circuit 11 is voltage vg, and the voltage value of the drive voltage signal LDRV is voltage vd.

[0099] Also, just before time t10, node W1 holds voltage vd, which is the voltage value of the boot voltage signal VBT, as latch signal VND, and node W2 holds voltage vg, which is the voltage value of the switching signal VSW, as latch signal VxND. Therefore, just before time t10, the voltage value of the level shift signal LSO output by the level shift signal output circuit 260 becomes voltage vd, which is the voltage value of the boot voltage signal VBT, and the voltage value of the inverted level shift signal xLSO output by the inverter 280 becomes voltage vg, which is the voltage value of the switching signal VSW.

[0100] Also, just before time t10, the drive control circuit 100 continues to output an L-level reference drive signal BDS. That is, an L-level reference drive signal BDS is continuously input to the pulse signal output circuit 210. Therefore, just before time t10, the pulse signal output circuit 210 outputs an L-level pulse signal VIN1 having a voltage value of voltage vg, and an L-level pulse signal VIN2 having a voltage value of voltage vg.

[0101] Then, at time t10, the drive control circuit 100 sets the master drive signal BDS to H level. This causes the pulse signal output circuit 210 to invert the logic level of the pulse signal VIN1 to H level. Then, by inverting the logic level of the pulse signal VIN1 to H level, the transistor 222 is controlled to be turned on. As a result, the voltage value of the node W1, which is the voltage value of the latch signal VND, decreases toward the voltage vg, which is the voltage value of the switching signal VSW at time t10. Also, at time t10, the drive control circuit 100 sets the drive voltage signal LDRV to L level. This controls the transistor 122 to be turned off.

[0102] At time t11 when the voltage value of the latch signal VND falls below the threshold voltages of the transistors 243 and 244, the transistor 243 is controlled to be on and the transistor 244 is controlled to be off. As a result, the voltage value of the node W2, which is the voltage value of the latch signal VxND, rises toward the voltage vd, which is the voltage value of the boot voltage signal VBT at time t11.

[0103] At time t12 when the voltage value of the latch signal VxND exceeds the threshold voltage of the transistor 262, the transistor 262 is controlled to be turned on. As a result, the voltage value of the node W4, which is the voltage value of the level shift signal LSO, decreases toward the voltage vg, which is the voltage value of the switching signal VSW at time t12.

[0104] At time t13 when the voltage value of the level shift signal LSO falls below the threshold voltages of the transistors 281 to 284, the transistors 281 and 282 are controlled to be on and the transistors 283 and 284 are controlled to be off, causing the voltage value of the inverted level shift signal xLSO to rise toward the voltage vd, which is the voltage value of the boot voltage signal VBT at time t13.

[0105] The inverted level shift signal xLSO output by the inverter 280 is sequentially inverted by the inverters 290-1 to 290-4. Specifically, at time t13, the voltage value of the inverted level shift signal xLSO output by the inverter 280 is inverted to the voltage value of the switching signal VSW by the inverter 290-1, and the inverter 290-1 outputs a signal having the voltage value of the switching signal VSW. The voltage value of the signal output by the inverter 290-1 is inverted to the voltage value of the boot voltage signal VBT by the inverter 290-2. The inverter 290-2 outputs the voltage value of the boot voltage signal VBT. The voltage value of the signal output by the inverter 290-2 is inverted to the voltage value of the switching signal VSW by the inverter 290-3. The inverter 290-3 outputs a signal having the voltage value of the switching signal VSW. The voltage value of the signal output by the inverter 290-3 is inverted by the inverter 290-4 to the voltage value of the boot voltage signal VBT. Then, the inverter 290-4 outputs a signal having the voltage value of the boot voltage signal VBT as the drive voltage signal HDRV at time t14.

[0106] That is, at time t14, the voltage value of the drive voltage signal HVDR output by the level shift circuit 200 rises toward the voltage vd, which is the voltage value of the boot voltage signal VBT at time t14.

[0107] Then, at time t15 when the voltage value of the drive voltage signal HVDR output by the level shift circuit 200 exceeds the threshold voltage of the transistor 121, the transistor 121 is controlled to be turned on. At this time, the transistor 122 is controlled to be turned off. Therefore, the voltage value of the switching signal VSW increases toward voltage vd, and as the voltage value of the switching signal VSW increases, the voltage value of the boot voltage signal VBT increases toward voltage vb. As a result, at time t15, the voltage value of the latch signal VND, which is the voltage value of the switching signal VSW, and the voltage value of the level shift signal LSO increase toward voltage vd, and the voltage value of the latch signal VxND, which is the voltage value of the boot voltage signal VBT, the voltage value of the inverted level shift signal xLSO, and the voltage value of the drive voltage signal HVDR increase toward voltage vb.

[0108] Then, at time t20 after time t15, the voltage value of the switching signal VSW, the voltage value of the latch signal VND, and the voltage value of the level shift signal LSO become voltage vd, and the voltage value of the boot voltage signal VBT, the voltage value of the latch signal VxND, the voltage value of the inverted level shift signal xLSO, and the voltage value of the drive voltage signal HVDR become voltage vb, so that the level shift circuit 200 outputs a drive voltage signal HDRV obtained by level-shifting the H-level voltage value of the input base drive signal BDS to voltage vb, which is the voltage value of the boot voltage signal VBT. In other words, the level shift circuit 200 generates and outputs a drive voltage signal HDRV obtained by level-shifting voltage vd, which is the H-level voltage value of the input base drive signal BDS, to voltage vb, which is the voltage value of the boot voltage signal VBT.

[0109] Thereafter, the logic level of the pulse signal VIN1 output by the pulse signal output circuit 210 becomes L level. Here, the timing at which the logic level of the pulse signal VIN1 output by the pulse signal output circuit 210 becomes L level is not limited to the timing exemplified in Fig. 4. Specifically, it is sufficient that the pulse signal VIN1 output by the pulse signal output circuit 210 continues to be H level at least longer than the period until the voltage value of the node W1, that is, the voltage value of the latch signal VND, is limited to the voltage value of the switching signal VSW, and switches to L level before the pulse signal VIN2 switches from L level to H level.

[0110] At time t30, which is after time t20, the drive control circuit 100 sets the master drive signal BDS to the L level. This causes the pulse signal output circuit 210 to invert the logic level of the pulse signal VIN2 to the H level. Then, by inverting the logic level of the pulse signal VIN2 to the H level, the transistor 232 is controlled to be turned on. As a result, the voltage value of the node W2, which is the voltage value of the latch signal VxND, decreases toward the voltage vd, which is the voltage value of the switching signal VSW at time t30.

[0111] At time t31 when the voltage value of the latch signal VxND falls below the threshold voltages of the transistors 241 and 242, the transistor 241 is controlled to be turned on and the transistor 242 is controlled to be turned off, causing the voltage value of the node W1, which is the voltage value of the latch signal VND, to rise toward the voltage vb, which is the voltage value of the boot voltage signal VBT at time t31.

[0112] At time t32 when the voltage value of the latch signal VxND falls below the threshold voltage of the transistor 262 and exceeds the threshold voltage of the transistor 261, the transistor 261 is controlled to be on and the transistor 262 is controlled to be off. This controls the transistor 263 to be off and the transistor 264 to be on. As a result, the voltage value of the node W4, which is the voltage value of the level shift signal LSO, rises toward the voltage vb, which is the voltage value of the boot voltage signal VBT at time t32.

[0113] At time t33 when the voltage value of the level shift signal LSO exceeds the threshold voltages of the transistors 281 to 284, the transistors 281 and 282 are controlled to be turned off, and the transistors 283 and 284 are controlled to be turned on. As a result, the voltage value of the inverted level shift signal xLSO decreases toward the voltage vd, which is the voltage value of the switching signal VSW at time t33.

[0114] The inverted level shift signal xLSO output by the inverter 280 is inverted sequentially by the inverters 290-1 to 290-4. Specifically, at time t33, the voltage value of the inverted level shift signal xLSO output by the inverter 280 is inverted by the inverter 290-1 to the voltage value of the boot voltage signal VBT. The inverter 290-1 then outputs a signal having the voltage value of the boot voltage signal VBT. The voltage value of the signal output by the inverter 290-1 is inverted by the inverter 290-2 to the voltage value of the switching signal VSW. The inverter 290-2 then outputs a signal having the voltage value of the switching signal VSW. The voltage value of the signal output by the inverter 290-2 is inverted by the inverter 290-3 to the voltage value of the boot voltage signal VBT. The inverter 290-3 then outputs a signal having the voltage value of the boot voltage signal VBT. The voltage value of the signal output by inverter 290-3 is inverted to the voltage value of switching signal VSW by inverter 290-4. Then, inverter 290-4 outputs a signal having the voltage value of switching signal VSW as drive voltage signal HDRV at time t34.

[0115] That is, at time t34, the voltage value of the drive voltage signal HVDR output by the level shift circuit 200 decreases toward the voltage vd, which is the voltage value of the switching signal VSW at time t34.

[0116] Then, at time t35, when the voltage value of the drive voltage signal HVDR output by the level shift circuit 200 falls below the threshold voltage of the transistor 121, the transistor 121 is controlled to be turned off. At this time, the drive control circuit 100 sets the drive voltage signal LDRV to the H level. This controls the transistor 122 to be turned on. Therefore, the voltage value of the switching signal VSW decreases toward voltage vg, and as the voltage value of the switching signal VSW decreases, the voltage value of the boot voltage signal VBT decreases toward voltage vd. As a result, at time t35, the voltage value of the latch signal VxND, which is the voltage value of the switching signal VSW, the voltage value of the inverted level shift signal xLSO, and the voltage value of the drive voltage signal HVDR decrease toward voltage vg, and the voltage value of the latch signal VND, which is the voltage value of the boot voltage signal VBT, and the voltage value of the level shift signal LSO decrease toward voltage vd.

[0117] Then, at time t40 after time t35, the voltage value of the switching signal VSW, the voltage value of the drive voltage signal HVDR, the voltage value of the latch signal VxND, and the voltage value of the inverted level shift signal xLSO become voltage vg, and the voltage value of the boot voltage signal VBT, the voltage value of the latch signal VND, and the voltage value of the level shift signal LSO become voltage vd, so that the level shift circuit 200 outputs a drive voltage signal HDRV obtained by level-shifting the L-level voltage value of the input master drive signal BDS to voltage vg, which is the voltage value of the switching signal VSW. In other words, the level shift circuit 200 generates and outputs a drive voltage signal HDRV obtained by level-shifting voltage vg, which is the L-level voltage value of the input master drive signal BDS, to voltage vg, which is the voltage value of the switching signal VSW.

[0118] Thereafter, the logic level of the pulse signal VIN2 output by the pulse signal output circuit 210 becomes L level. Here, the timing at which the logic level of the pulse signal VIN2 output by the pulse signal output circuit 210 becomes L level is not limited to the timing exemplified in Fig. 4. Specifically, it is sufficient that the pulse signal VIN2 output by the pulse signal output circuit 210 continues to be H level at least longer than the period until the voltage value of the node W2, that is, the voltage value of the latch signal VxND, is limited to the voltage value of the switching signal VSW, and switches to L level before the pulse signal VIN1 switches from L level to H level.

[0119] Here, the terminal tvdd of the integrated circuit device 10 is an example of a first terminal, the terminal tvss is an example of a second terminal, the terminal tvsw is an example of a third terminal, the terminal tvbt is an example of a fourth terminal, the capacitor element 6 is an example of a capacitor, the transistor 13 is an example of a supply control circuit, the detection circuit 220 is an example of a first limiting circuit, and the detection circuit 230 is an example of a second limiting circuit. Furthermore, transistor 221 is an example of a first transistor, transistor 222 is an example of a second transistor, transistor 231 is an example of a third transistor, transistor 232 is an example of a fourth transistor, transistor 241 is an example of a fifth transistor, transistor 242 is an example of a sixth transistor, transistor 243 is an example of a seventh transistor, transistor 244 is an example of an eighth transistor, transistor 261 is an example of a ninth transistor, transistor 262 is an example of a tenth transistor, transistor 263 is an example of an eleventh transistor, and transistor 264 is an example of a twelfth transistor. Furthermore, node W1 is an example of a first node, node W2 is an example of a second node, node W3 is an example of a third node, and node W4 is an example of a fourth node.

[0120] The voltage signal VDD is an example of a first voltage signal, the voltage vd, which is the voltage value of the voltage signal VDD, is an example of the first voltage value, the voltage signal VOUT is an example of a second voltage signal, the voltage vo, which is the voltage value of the voltage signal VOUT, is an example of a second voltage value, the voltage signal GND is an example of a reference potential signal, the voltage vg, which is the voltage value of the voltage signal GND, is an example of a reference potential, the drive voltage signal HDRV is an example of a drive signal, the pulse signal VIN1 is an example of a first pulse signal, and the pulse signal VIN2 is an example of a second pulse signal.

[0121] 3. Effects The power supply circuit 1 and integrated circuit device 10 of this embodiment configured as described above include a terminal tvdd to which a voltage signal VDD is supplied, a terminal tvss to which a voltage signal GND of voltage vg is supplied, a terminal tvsw to which a switching signal VSW whose voltage value changes between voltage vd and voltage vg is output, a terminal tvbt to which one end of a capacitor element 6, the other end of which is electrically connected to terminal tvsw, is connected and to which a boot voltage signal VBT corresponding to the switching signal VSW is supplied, a switching circuit 12 to output the switching signal VSW, and a drive signal output circuit 11 to output a drive voltage signal HDRV that drives the switching circuit 12. The drive signal output circuit 11 also includes a drive control circuit 100 to output a base drive signal BDS that is the basis of the drive voltage signal HDRV, and a level shift circuit 200 to output a drive voltage signal HDRV obtained by level-shifting the voltage value of the base drive signal BDS. The level shift circuit 200 has a detection circuit 220 that limits the voltage value of node W1 based on the voltage value of the switching signal VSW at the rising edge of the base drive signal BDS, a detection circuit 230 that limits the voltage value of node W2 based on the voltage value of the switching signal VSW at the falling edge of the base drive signal BDS, a latch circuit 240 that holds the voltage value of the switching signal VSW at node W1 and the voltage value of the boot voltage signal VBT at node W2 at the rising edge of the base drive signal BDS, and holds the voltage value of the boot voltage signal VBT at node W1 and the voltage value of the switching signal VSW at node W2 at the falling edge of the base drive signal BDS, and an output circuit 250 that level-shifts the high-level voltage value of the base drive signal BDS to the voltage value of the boot voltage signal VBT and level-shifts the low-level voltage value of the base drive signal BDS to the voltage value of the switching signal VSW according to the voltage value of node W1 and the voltage value of node W2 held by the latch circuit 240, and outputs a drive voltage signal HDRV.

[0122] In the integrated circuit device 10 configured as above, the detection circuits 220, 230 can operate using the potential difference between voltages vd and vg, which are the high-level and low-level voltage values ​​of the master drive signal BDS and the voltage values ​​of the switching signal VSW, as drive power. Therefore, in the level shift circuit 200 of the integrated circuit device 10 of this embodiment, the circuit elements constituting the detection circuits 220, 230 only need to withstand at least the potential difference between voltages vd and vg.

[0123] Furthermore, the latch circuit 240 only needs to be able to hold the voltage value of the switching signal VSW and the voltage value of the boot voltage signal VBT at the corresponding nodes W1 and W2 while the voltage value of the node W1 is limited by the voltage value of the switching signal VSW by the detection circuit 220 and the voltage value of the node W2 is limited by the voltage value of the switching signal VSW by the detection circuit 220. Therefore, the latch circuit 240 can operate at the potential difference between the voltage value of the switching signal VSW and the voltage value of the boot voltage signal VBT, with the voltage value of the switching signal VSW as the reference.

[0124] The output circuit 250 level-shifts the high-level voltage value of the base drive signal BDS to the voltage value of the boot voltage signal VBT and outputs a drive voltage signal HDRV obtained by level-shifting the low-level voltage value of the base drive signal BDS to the voltage value of the switching signal VSW, according to the voltage values ​​of the node W1 and node W2 held by the latch circuit 240. Therefore, the output circuit 250 can operate at the potential difference between the voltage value of the switching signal VSW and the voltage value of the boot voltage signal VBT, with the voltage value of the switching signal VSW as the reference.

[0125] Here, the integrated circuit device 10 has a terminal tvsw from which a switching signal VSW, whose voltage value changes between voltage vd and voltage vg, is output, and a terminal tvbt to which one end of a capacitor element 6, one end of which is electrically connected to the terminal tvsw, is connected and to which a boot voltage signal VBT corresponding to the switching signal VSW is supplied. Therefore, the potential difference between the voltage value of the switching signal VSW and the voltage value of the boot voltage signal VBT is approximately equal to voltage vd. In other words, the circuit elements constituting the latch circuit 240 and the output circuit 250 only need to withstand at least voltage vd, which is the potential difference between the voltage value of the switching signal VSW and the voltage value of the boot voltage signal VBT.

[0126] Therefore, in the integrated circuit device 10 of this embodiment, it is possible to reduce the withstand voltage of the circuit elements of the detection circuits 220 and 230, the latch circuit 240, and the output circuit 250 of the level shift circuit 200. This makes it possible to reduce the size of the circuit elements that make up the level shift circuit 200, and thus makes it possible to reduce the size of the level shift circuit 200.

[0127] Furthermore, in the power supply circuit 1 and integrated circuit device 10 of this embodiment, the latch circuit 240 and the output circuit 250 operate in response to the switching signal VSW output by the power supply circuit 1 and the boot voltage signal VBT, the voltage value of which changes in response to the switching signal VSW, eliminating the need to provide new components for controlling the operations of the latch circuit 240 and the output circuit 250. Therefore, in the power supply circuit 1 and integrated circuit device 10 of this embodiment, the level shift circuit 200 can be further miniaturized.

[0128] 4. Variations Here, the level shift circuit 200 of the integrated circuit device 10 of this embodiment has been described as the pulse signal output circuit 210 controlling the transistor 222 to be on for a fixed period by inverting the logic level of the pulse signal VIN1 to a H level for a fixed period at the rising edge of the master drive signal BDS, and controlling the transistor 232 to be on for a fixed period by inverting the logic level of the pulse signal VIN2 to a H level for a fixed period at the falling edge of the master drive signal BDS, but it is sufficient for the level shift circuit 200 to be able to control the transistor 222 to be on for a fixed period at the rising edge of the master drive signal BDS, and to control the transistor 232 to be on for a fixed period at the falling edge of the master drive signal BDS.

[0129] Therefore, for example, the level shift circuit 200 may have an inverter that inverts the logic level instead of the pulse signal output circuit 210, and the base drive signal BDS may be input to the gate terminal of the transistor 222, and the base drive signal BDS may be input to the gate terminal of the transistor 232 via the inverter.

[0130] Furthermore, the connection relationship between nodes W1 and W2 and the connection relationship between nodes W3 and W4 in the level shift circuit 200 are not limited to the example shown in Fig. 4. For example, node W1 may be electrically connected to the gate terminal of transistor 262, and node W2 may be electrically connected to the gate terminal of transistor 261. Furthermore, the level shift signal output circuit 260 may output the voltage value of node W3 as the level shift signal LSO. In this case, the level shift circuit 200 may have an inverter that inverts the logic level and has a configuration similar to that of inverters 290-1 to 290-4, located downstream of inverter 290-4, so that the level shift circuit 200 outputs the boot voltage signal VBT when the input base drive signal BDS is at an H level and outputs the switching signal VSW when the input base drive signal BDS is at an L level.

[0131] Although the embodiments and modifications have been described above, the present invention is not limited to these embodiments and can be embodied in various forms without departing from the spirit of the present invention. For example, the above embodiments can be combined as appropriate.

[0132] The present invention includes configurations that are substantially the same as the configurations described in the embodiments (for example, configurations with the same functions, methods, and results, or configurations with the same purpose and effects). The present invention also includes configurations in which non-essential parts of the configurations described in the embodiments are replaced. The present invention also includes configurations that achieve the same effects as the configurations described in the embodiments or that can achieve the same purpose. The present invention also includes configurations in which publicly known technology is added to the configurations described in the embodiments.

[0133] The following can be derived from the above-described embodiment.

[0134] One aspect of the integrated circuit device is 1. An integrated circuit device used in a power supply circuit that converts a first voltage signal of a first voltage value into a second voltage signal of a second voltage value and outputs the second voltage signal, a first terminal to which the first voltage signal is supplied; a second terminal to which a reference potential signal of a reference potential is supplied; a third terminal for outputting a switching signal whose voltage value changes between the first voltage value and the reference potential; a fourth terminal to which one end of a capacitor, the other end of which is electrically connected to the third terminal, is connected and to which a boot voltage signal corresponding to the switching signal is supplied; a supply control circuit having one end electrically connected to the first terminal and the other end electrically connected to the fourth terminal, the supply control circuit controlling the supply of the first voltage signal to the fourth terminal; a switching circuit that outputs the switching signal; a drive signal output circuit that outputs a drive signal for driving the switching circuit; Equipped with The drive signal output circuit a drive control circuit that outputs a base drive signal that is the basis of the drive signal; a level shift circuit that outputs the drive signal obtained by level-shifting the voltage value of the base drive signal; and The level shift circuit includes: a first limiting circuit that limits a voltage value of a first node based on a voltage value of the switching signal at a rising edge of the basic drive signal; a second limiting circuit that limits the voltage value of a second node based on the voltage value of the switching signal at the falling edge of the basic drive signal; a latch circuit that, at the rising edge of the base drive signal, holds the voltage value of the switching signal at the first node and holds the voltage value of the boot voltage signal at the second node, and, at the falling edge of the base drive signal, holds the voltage value of the boot voltage signal at the first node and holds the voltage value of the switching signal at the second node; an output circuit that level-shifts the high-level voltage value of the base drive signal to the voltage value of the boot voltage signal and level-shifts the low-level voltage value of the base drive signal to the voltage value of the switching signal according to the voltage value of the first node and the voltage value of the second node held by the latch circuit, and outputs the drive signal; It has.

[0135] According to this integrated circuit device, the first limiting circuit and the second limiting circuit constituting the level shift circuit 200 operate with the potential difference between the high-level voltage value and the low-level voltage value of the master drive signal, and the latch circuit and the output circuit operate with the potential difference between the boot voltage signal and the switching signal. This makes it possible to reduce the withstand voltage of the circuit elements of the first limiting circuit, the second limiting circuit, the latch circuit, and the output circuit of the level shift circuit. This makes it possible to miniaturize the circuit elements constituting the level shift circuit, thereby realizing a miniaturized level shift circuit.

[0136] In one aspect of the integrated circuit device, the first limiting circuit includes a first transistor and a second transistor; The switching signal is supplied to a gate terminal of the first transistor, a drain terminal of the first transistor electrically connected to a drain terminal of the second transistor; a source terminal of the first transistor electrically connected to the first node; At the rising edge of the basic drive signal, the drain terminal and the source terminal of the second transistor are controlled to be conductive; the second limiting circuit includes a third transistor and a fourth transistor; The switching signal is supplied to a gate terminal of the third transistor, a drain terminal of the third transistor electrically connected to a drain terminal of the fourth transistor; a source terminal of the third transistor electrically connected to the second node; At the falling edge of the basic drive signal, the drain terminal and the source terminal of the fourth transistor may be controlled to be conductive.

[0137] According to this integrated circuit device, even if the level shift circuit has the first limiting circuit and the second limiting circuit having such a configuration, the withstand voltage of the circuit elements of the first limiting circuit and the second limiting circuit of the level shift circuit can be reduced, thereby enabling the circuit elements constituting the level shift circuit to be miniaturized, thereby realizing miniaturization of the level shift circuit.

[0138] In one aspect of the integrated circuit device, the latch circuit includes a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor; the fifth transistor has a gate terminal electrically connected to the second node, a drain terminal electrically connected to the first node, and a source terminal to which the boot voltage signal is supplied; the sixth transistor has a gate terminal electrically connected to the second node, a drain terminal electrically connected to the first node, and a source terminal to which the switching signal is supplied; the seventh transistor has a gate terminal electrically connected to the first node, a drain terminal electrically connected to the second node, and a source terminal to which the boot voltage signal is supplied; The eighth transistor may have a gate terminal electrically connected to the first node, a drain terminal electrically connected to the second node, and a source terminal to which the switching signal is supplied.

[0139] According to this integrated circuit device, even if the level shift circuit has a latch circuit having such a configuration, the withstand voltage of the circuit elements of the latch circuit of the level shift circuit can be reduced, thereby making it possible to miniaturize the circuit elements that make up the level shift circuit, and thereby achieving a miniaturized level shift circuit.

[0140] In one aspect of the integrated circuit device, the output circuit includes a ninth transistor, a tenth transistor, an eleventh transistor, and a twelfth transistor; the ninth transistor has a gate terminal electrically connected to the first node, a drain terminal electrically connected to a third node, and a source terminal to which the switching signal is supplied; the tenth transistor has a gate terminal electrically connected to the second node, a drain terminal electrically connected to the fourth node, and a source terminal to which the switching signal is supplied; the eleventh transistor has a gate terminal electrically connected to the fourth node, a drain terminal electrically connected to the third node, and a source terminal to which the boot voltage signal is supplied; the twelfth transistor has a gate terminal electrically connected to the third node, a drain terminal electrically connected to the fourth node, and a source terminal to which the boot voltage signal is supplied; a conduction state between the drain terminal and the source terminal of the ninth transistor, a conduction state between the drain terminal and the source terminal of the tenth transistor, a conduction state between the drain terminal and the source terminal of the eleventh transistor, and a conduction state between the drain terminal and the source terminal of the twelfth transistor change according to a voltage value of the first node and a voltage value of the second node held by the latch circuit, The output circuit may output the drive signal based on a voltage value of the fourth node.

[0141] According to this integrated circuit device, even if the level shift circuit has an output circuit with such a configuration, the withstand voltage of the circuit elements of the output circuit of the level shift circuit can be reduced, thereby enabling the circuit elements constituting the level shift circuit to be miniaturized, thereby realizing miniaturization of the level shift circuit.

[0142] In one aspect of the integrated circuit device, the level shift circuit has a pulse signal output circuit that outputs a first pulse signal whose logic level is inverted for a fixed period at the rising edge of the basic drive signal, and a second pulse signal whose logic level is inverted for a fixed period at the falling edge of the basic drive signal, The latch circuit may hold the voltage value of the switching signal at the first node and the voltage value of the boot voltage signal at the second node during a period when the logical level of the first pulse signal is inverted, and may hold the voltage value of the boot voltage signal at the first node and the voltage value of the switching signal at the second node during a period when the logical level of the second pulse signal is inverted.

[0143] In one aspect of the integrated circuit device, the latch circuit and the output circuit operate in response to a potential difference between the switching signal and the boot voltage signal; The first limiting circuit and the second limiting circuit may operate in response to a potential difference between the reference potential signal and the switching signal.

[0144] According to this integrated circuit device, the first limiting circuit and the second limiting circuit constituting the level shift circuit 200 operate with the potential difference between the high-level voltage value and the low-level voltage value of the master drive signal, and the latch circuit and the output circuit operate with the potential difference between the boot voltage signal and the switching signal. This makes it possible to reduce the withstand voltage of the circuit elements of the first limiting circuit, the second limiting circuit, the latch circuit, and the output circuit of the level shift circuit. This makes it possible to miniaturize the circuit elements constituting the level shift circuit, thereby realizing a miniaturized level shift circuit. [Explanation of symbols]

[0145] 1...power supply circuit, 2...inductor element, 3...capacitor element, 4, 5...resistance element, 6...capacitor element, 10...integrated circuit device, 11...drive signal output circuit, 12...switching circuit, 13...transistor, 100...drive control circuit, 121, 122...transistor, 200...level shift circuit, 210...pulse signal output circuit, 220...detection circuit, 221, 222...transistor, 230...detection circuit, 231, 232...transistor, 240...latch Circuit, 241 to 244...transistor, 250...output circuit, 260...level shift signal output circuit, 261 to 264...transistor, 270...inverter circuit, 280...inverter, 281 to 286...transistor, 290-1 to 290-4...inverter, 291-1 to 291-4...transistor, 292-1 to 292-4...transistor, W1 to W4...node, ten, tgnd, tvbt, tvdd, tvfb, tvss, tvsw...terminal

Claims

1. 1. An integrated circuit device used in a power supply circuit that converts a first voltage signal having a first voltage value into a second voltage signal having a second voltage value and outputs the second voltage signal, a first terminal to which the first voltage signal is supplied; a second terminal to which a reference potential signal of a reference potential is supplied; a third terminal for outputting a switching signal whose voltage value changes between the first voltage value and the reference potential; a fourth terminal to which one end of a capacitor, the other end of which is electrically connected to the third terminal, is connected and to which a boot voltage signal corresponding to the switching signal is supplied; a supply control circuit having one end electrically connected to the first terminal and the other end electrically connected to the fourth terminal, the supply control circuit controlling the supply of the first voltage signal to the fourth terminal; a switching circuit that outputs the switching signal; a drive signal output circuit that outputs a drive signal for driving the switching circuit; Equipped with The drive signal output circuit a drive control circuit that outputs a base drive signal that is the basis of the drive signal; a level shift circuit that outputs the drive signal obtained by level-shifting the voltage value of the base drive signal; and The level shift circuit includes: a first limiting circuit that limits a voltage value of a first node based on a voltage value of the switching signal at a rising edge of the basic drive signal; a second limiting circuit that limits a voltage value of a second node based on a voltage value of the switching signal at a falling edge of the basic drive signal; a latch circuit that, at the rising edge of the base drive signal, holds the voltage value of the switching signal at the first node and holds the voltage value of the boot voltage signal at the second node, and, at the falling edge of the base drive signal, holds the voltage value of the boot voltage signal at the first node and holds the voltage value of the switching signal at the second node; an output circuit that level-shifts the high-level voltage value of the base drive signal to the voltage value of the boot voltage signal and level-shifts the low-level voltage value of the base drive signal to the voltage value of the switching signal according to the voltage value of the first node and the voltage value of the second node held by the latch circuit, and outputs the drive signal; having 1. An integrated circuit device comprising:

2. the first limiting circuit includes a first transistor and a second transistor; The switching signal is supplied to a gate terminal of the first transistor, a drain terminal of the first transistor electrically connected to a drain terminal of the second transistor; a source terminal of the first transistor electrically connected to the first node; At the rising edge of the basic drive signal, the drain terminal and the source terminal of the second transistor are controlled to be conductive; the second limiting circuit includes a third transistor and a fourth transistor; The switching signal is supplied to a gate terminal of the third transistor, a drain terminal of the third transistor electrically connected to a drain terminal of the fourth transistor; a source terminal of the third transistor electrically connected to the second node; At the falling edge of the basic drive signal, the drain terminal and the source terminal of the fourth transistor are controlled to be conductive.

2. The integrated circuit device according to claim 1.

3. the latch circuit includes a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor; the fifth transistor has a gate terminal electrically connected to the second node, a drain terminal electrically connected to the first node, and a source terminal to which the boot voltage signal is supplied; the sixth transistor has a gate terminal electrically connected to the second node, a drain terminal electrically connected to the first node, and a source terminal to which the switching signal is supplied; the seventh transistor has a gate terminal electrically connected to the first node, a drain terminal electrically connected to the second node, and a source terminal to which the boot voltage signal is supplied; the eighth transistor has a gate terminal electrically connected to the first node, a drain terminal electrically connected to the second node, and a source terminal to which the switching signal is supplied; 2. The integrated circuit device according to claim 1.

4. the output circuit includes a ninth transistor, a tenth transistor, an eleventh transistor, and a twelfth transistor; the ninth transistor has a gate terminal electrically connected to the first node, a drain terminal electrically connected to a third node, and a source terminal to which the switching signal is supplied; the tenth transistor has a gate terminal electrically connected to the second node, a drain terminal electrically connected to a fourth node, and a source terminal to which the switching signal is supplied; the eleventh transistor has a gate terminal electrically connected to the fourth node, a drain terminal electrically connected to the third node, and a source terminal to which the boot voltage signal is supplied; the twelfth transistor has a gate terminal electrically connected to the third node, a drain terminal electrically connected to the fourth node, and a source terminal to which the boot voltage signal is supplied; a conduction state between the drain terminal and the source terminal of the ninth transistor, a conduction state between the drain terminal and the source terminal of the tenth transistor, a conduction state between the drain terminal and the source terminal of the eleventh transistor, and a conduction state between the drain terminal and the source terminal of the twelfth transistor change according to a voltage value of the first node and a voltage value of the second node held by the latch circuit, the output circuit outputs the drive signal based on a voltage value of the fourth node.

2. The integrated circuit device according to claim 1.

5. the level shift circuit has a pulse signal output circuit that outputs a first pulse signal whose logic level is inverted for a fixed period at the rising edge of the basic drive signal, and a second pulse signal whose logic level is inverted for a fixed period at the falling edge of the basic drive signal, the latch circuit holds the voltage value of the switching signal at the first node and the voltage value of the boot voltage signal at the second node during a period when the logic level of the first pulse signal is inverted, and holds the voltage value of the boot voltage signal at the first node and the voltage value of the switching signal at the second node during a period when the logic level of the second pulse signal is inverted.

2. The integrated circuit device according to claim 1.

6. the latch circuit and the output circuit operate in response to a potential difference between the switching signal and the boot voltage signal; the first limiting circuit and the second limiting circuit operate in response to a potential difference between the reference potential signal and the switching signal.

6. The integrated circuit device according to claim 1, wherein the first and second electrodes are electrically connected to each other.

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