Pulse power supply device for plasma etching device and pulse voltage generating method

Abstract

To apply a well-shaped pulse voltage with fast rise and fall times to a substrate.SOLUTION: In a pulse power supply unit 100 according to an embodiment of the present invention, a ramp voltage generation unit 2 generates a ramp voltage corresponding to the linear voltage increase of the potential gradient portion that contributes to substantial etching. An auxiliary voltage generation unit 4 generates a constant auxiliary voltage during the potential gradient portion and a DC voltage used as an initial resonant voltage for the rising and falling edges of the pulse voltage. A pulse generation unit 5 uses the initial resonant voltage to generate half-wave resonance in a resonant loop that includes the capacitor of the plasma reactor and the inductor, primarily the wiring between the plasma reactor and the device, thereby forming voltage waveforms corresponding to the rising and falling edges, and also uses the ramp voltage to form the potential gradient portion and output a pulse voltage that combines these.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The present invention relates to a pulse power supply device used in a plasma etching device for semiconductor manufacturing and the like, and a voltage generation method for the device. [Background technology]

[0002] In semiconductor manufacturing processes, plasma etching systems are widely used to etch semiconductor substrates using plasma. Reactive ion etching systems typically generate plasma from an etching gas in a chamber using high-frequency inductive coupling or electron cyclotron resonance, and apply a bias voltage, such as a high-frequency voltage, to a substrate placed in the chamber. This generates a self-bias potential between the substrate and the plasma, causing ion and radical species in the plasma to accelerate toward the substrate and collide with its surface, resulting in etching.

[0003] As disclosed in Patent Document 1, it is important to properly control the ion energy distribution (IED) on the substrate surface to perform precise etching. Generally, it is desirable for the IED on the substrate surface to be a single IED with a peak width as narrow as possible. To achieve such an IED, the substrate surface voltage must be kept nearly constant. However, because the ion current derived from the plasma continuously charges the dielectric substrate surface, the substrate surface voltage does not remain constant even when a constant voltage is applied to the substrate. For this reason, a pulsed bias voltage with a waveform in which the voltage at the top of the pulse changes in a ramp waveform, as disclosed in FIG. 1(a) of the document, is generally used as the voltage applied to the substrate. By applying such a pulsed bias voltage to the substrate, the influence of the ion current can be compensated for and the substrate surface voltage can be maintained constant.

[0004] Generally, the waveform of the pulse bias voltage in a plasma etching apparatus is a negative pulse waveform in which the voltage changes in the negative direction (downward in a typical waveform diagram), and the actual etching process occurs at the peak of this negative pulse waveform. Therefore, in the following description, the edge of the pulse waveform where the voltage changes in the negative direction toward the peak of the pulse waveform where the etching process occurs will be referred to as a rising edge, and conversely, the edge of the pulse waveform where the voltage changes in the positive direction from the peak of the pulse waveform where the etching process occurs will be referred to as a falling edge. Similarly, the change in pulse (i.e., rising) or its operation toward the period where the actual etching process is performed will be referred to as pulse-on, and the change in pulse (i.e., falling) or its operation after the period where the actual etching process is performed has ended will be referred to as pulse-off. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Special Publication No. 2020-501351 [Patent Document 2] Patent No. 7011118 Summary of the Invention [Problem to be solved by the invention]

[0006] Patent Document 1 does not propose a circuit for generating a pulse bias voltage having the above-described shape. To generate a pulse voltage having such a shape, it is possible to use, for example, the power supply device described in Patent Document 2. The power supply device described in that document utilizes PWM (pulse width modulation) control to flexibly form various pulse waveforms, including the rising portion, falling portion, and pulse crest of a high-voltage pulse, with low loss. Meanwhile, further enhancement of etching efficiency is required to improve the manufacturing efficiency of semiconductor devices. To achieve this, it is necessary to further speed up the rise and fall of the pulse voltage and increase the proportion of the potential gradient portion that actually contributes to etching within one cycle of the pulse voltage. However, the method described in Patent Document 2 has limitations in accelerating the rise and fall.

[0007] Furthermore, the peak value of the pulse bias voltage is high, ranging from several hundred volts to several kilovolts. To generate such a high voltage using PWM control, a large voltage is applied to the switching element for PWM, necessitating the use of relatively expensive elements with a high voltage rating. Such elements with a high voltage rating are expensive, and elements with both a high voltage rating and fast switching speeds are difficult to obtain. This results in problems such as high circuit costs and difficulty in circuit design.

[0008] The present invention has been made to solve these problems, and one object of the present invention is to provide a pulse power supply apparatus and a voltage generation method for a plasma etching apparatus that can generate, at low cost, a pulse voltage whose rise and fall are steep and whose pulse peak, which is essentially for etching, has a highly accurate constant slope. [Means for solving the problem]

[0009] One aspect of the present invention made to solve the above problems is a pulsed power supply for a plasma etching apparatus, which outputs a pulsed voltage exhibiting a waveform including a rising portion, in which the voltage rises rapidly from a rising-time reference voltage (+ΔV in the example of FIG. 3(b1) described later) to a first voltage (0V in the example of FIG. 3(b1)), between a ground terminal and an output terminal of the pulsed power supply, a potential gradient portion, in which the voltage increases substantially linearly from the first voltage to a falling-time reference voltage (−Vc in the example of FIG. 3(b1)), and a falling portion, in which the voltage falls rapidly from the falling-time reference voltage to the rising-time reference voltage, in order to apply a pulsed bias voltage to a plasma reactor including a processing object in a plasma etching apparatus, a) a ramp voltage generating unit that generates a ramp voltage corresponding to a substantially linear voltage increase of the potential gradient portion; b) a first voltage source (voltage source 15 in the example of FIG. 6 described later) for generating a first auxiliary voltage which is a voltage value (ΔV) corresponding to the voltage difference between the rising-time reference voltage (+ΔV) and the first voltage (0V); a second voltage source (voltage source 13 in the example of FIG. 6) for generating a second auxiliary voltage which is a voltage value (ΔV / 2) half the voltage value (ΔV) of the first auxiliary voltage in order to obtain a rising-time resonant initial voltage; a second voltage source (voltage source 14 in the example of FIG. 6) for generating a second auxiliary voltage which is a voltage value (ΔV / 2) half the voltage value (ΔV) of the first auxiliary voltage in order to obtain a rising-time resonant initial voltage; an auxiliary voltage generating unit including a third voltage source (voltage source 14 in the example of FIG. 6) that generates a third auxiliary voltage having a voltage value (Va) corresponding to the difference between a potential (+Va in the example of FIG. 3(b1)) corresponding to half the voltage value ((ΔV+Vc) / 2) of the voltage difference and ground potential (0 V) in order to obtain the falling-time resonance initial voltage 2), and a fourth voltage source (voltage source 16 in the example of FIG. 6) that generates a fourth auxiliary voltage corresponding to the amount of level shift of the pulse voltage waveform in the potential gradient portion (0 in the example of FIG. 3(b1)); c) a pulse generating unit that generates a voltage waveform corresponding to the rising portion by generating a half-wave resonance using the rising-portion initial voltage (ΔV / 2) from the rising-portion reference voltage (+ΔV) in a resonant loop including a capacitor of a plasma reactor, an inductor including wiring between the pulse power supply device and the plasma reactor, and the second voltage source, using a voltage determined by the first auxiliary voltage as the rising-portion reference voltage (+ΔV), and subsequently generates a voltage waveform corresponding to the potential gradient portion by further increasing the voltage over time from the first voltage which is the end point of the rising portion using a ramp voltage output from the ramp voltage generating unit and level-shifted by the fourth auxiliary voltage; and then generates a voltage waveform corresponding to the falling portion by generating a half-wave resonance using the falling-portion initial voltage ((ΔV+Vc) / 2) from the falling-portion reference voltage (-Vc) in a resonant loop including the capacitor, the inductor, the third voltage source, and an inductor formed by a coil added as necessary; Equipped with.

[0010] Here, the first to fourth voltage sources generate first to fourth auxiliary voltages, respectively, and these auxiliary voltages may include 0 V. When a certain auxiliary voltage is 0 V, the first to fourth voltage sources generating that auxiliary voltage do not exist, and the circuit can be considered to be short-circuited.

[0011] Furthermore, the term "half" in descriptions such as "half the voltage value of the first auxiliary voltage" and "half the voltage difference between the falling reference voltage and the rising reference voltage" does not mean strictly 1 / 2, but can naturally be adjusted appropriately in accordance with various deviations caused by variations in the parameters and characteristics of circuit elements.

[0012] In the pulse power supply for a plasma etching apparatus according to the present invention, the rising and falling edges are accelerated by utilizing half-wave resonance in a resonant loop including a capacitor in a plasma reactor, an inductor mainly consisting of wiring, etc. Meanwhile, the potential gradient in the potential gradient section for maintaining the surface voltage of an etching target such as a substrate substantially constant during etching is formed by a ramp voltage generated by a ramp voltage generator.

[0013] Furthermore, one aspect of a pulse voltage generation method for a plasma etching apparatus according to the present invention is a method for generating a pulse voltage in the pulse power supply of the above aspect, in order to apply a pulse bias voltage to a plasma reactor including a processing object in the plasma etching apparatus, the method outputting a pulse voltage exhibiting a waveform including: a holding section that maintains a predetermined rise-time reference voltage (+ΔV in the example of FIG. 3(b1) described later) between a ground terminal and an output terminal of the pulse power supply; a rise section in which the voltage rises rapidly from the rise-time reference voltage to a first voltage (0 V in the example of FIG. 3(b1)); a potential ramp section in which the voltage increases approximately linearly from the first voltage to a fall-time reference voltage (−Vc in the example of FIG. 3(b1)); and a fall section in which the voltage falls rapidly from the fall-time reference voltage to the rise-time reference voltage, the method includes a plurality of steps of selectively coupling to the output terminal a ramp voltage whose voltage increases with the lapse of time, a first DC voltage (ΔV) corresponding to a voltage difference between the rising reference voltage (+ΔV) and the first voltage (0V), a second DC voltage (ΔV / 2) corresponding to half the voltage difference between the rising reference voltage and the first voltage, and a third DC voltage (Va) corresponding to a difference between a potential (+Va in the example of FIG. 3(b1)) corresponding to half the voltage value ((ΔV+Vc) / 2) of the voltage difference (ΔV+Vc) between the falling reference voltage and the rising reference voltage and a ground potential (0V); a first step of maintaining the voltage at the output terminal at a level corresponding to the rising reference voltage (+ΔV) by coupling the first DC voltage (ΔV) to the output terminal and holding the first DC voltage in a capacitor of a plasma reactor, which is a load; a second step following the first step of coupling the second DC voltage (ΔV / 2) to the output terminal, and causing a current to flow by half-wave resonance using a rise-time resonance initial voltage (ΔV / 2) corresponding to a voltage difference between the rise-time reference voltage and the second DC voltage in a resonance loop including at least the capacitor and an inductor including a wiring between the pulse power supply device and a plasma reactor, thereby increasing the voltage at the output terminal from the rise-time reference voltage (+ΔV); a third step of coupling the ramp voltage to the output terminal when the voltage at the output terminal reaches a first voltage by the second step, and further increasing the voltage at the output terminal over time; a fourth step of coupling the third DC voltage to the output terminal after the voltage at the output terminal has increased to the falling-time reference voltage by the third step, and causing a current to flow by half-wave resonance using a falling-time resonance initial voltage, which is half the voltage value of the voltage difference (ΔV+Vc) between the falling-time reference voltage and the rising-time reference voltage, in a resonance loop including at least the capacitor and the inductor, thereby decreasing the voltage at the output terminal from the falling-time reference voltage (−Vc); It has. [Effects of the Invention]

[0014] According to the present invention, by using half-wave resonance to form the waveform of the rising and falling portions, the rising and falling portions can be made steep. This increases the proportion of the potential gradient portion that actually contributes to etching within one pulse voltage cycle, thereby improving etching efficiency. Furthermore, by accelerating the rising and falling edges, the repetition frequency of the pulse voltage can be increased. Furthermore, since only the ramp voltage portion, whose voltage changes over time, needs to be generated by, for example, PWM to generate a voltage waveform corresponding to the potential gradient portion, the required degree of voltage change can be reduced, thereby reducing the voltage rating required for circuit components such as switching elements for PWM. This reduces circuit costs and allows the application of a pulse voltage with a good waveform shape to the target, enabling a single IED with a narrow peak width on the target surface. Furthermore, the wider selection of switching elements also simplifies circuit design. [Brief explanation of the drawings]

[0015] [Figure 1] 1 is a conceptual diagram showing an example of the overall configuration of a plasma etching apparatus including a pulse power supply device according to the present invention. [Figure 2] FIG. 2 is a diagram showing a simplified electrical equivalent circuit of a plasma reactor, which is a load of a pulsed power supply device. [Figure 3] 3A and 3B are diagrams showing examples of waveforms of a substrate surface voltage Vsub, an output voltage Vop1, and a stage voltage Vop2. [Figure 4] FIG. 2 is a schematic block diagram of a bias pulse power supply unit according to the first embodiment. [Figure 5] 5 is a schematic circuit diagram of the high voltage generation unit in Figure 4. [Figure 6] 5 is a schematic circuit diagram mainly showing the pulse generation section in FIG. 4. [Figure 7] 4 is a time chart showing an example of voltage waveforms and current waveforms of essential parts during a commutation period Ta when a pulse is on. [Figure 8] 4 is a time chart showing an example of voltage waveforms and current waveforms of main parts during a commutation period Tb when the pulse is off. [Figure 9] FIG. 1 is a schematic circuit diagram showing the current flow during the commutation period Ta (times t0 to t1) when the pulse is on. [Figure 10] FIG. 4 is a schematic circuit diagram showing the current flow during the etching treatment period Tp (times t1 to t2). [Figure 11] FIG. 10 is a schematic circuit diagram showing the current flow during a commutation period Tb (times t2 to t3) when the pulse is off. [Figure 12] FIG. 10 is a schematic circuit diagram showing the current flow during a commutation period Tb (times t3 to t4) when the pulse is off. [Figure 13] FIG. 10 is a schematic circuit diagram showing the current flow during a commutation period Tb (times t4 to t5) when the pulse is off. [Figure 14] FIG. 7 is a diagram showing an example of a schematic circuit of an auxiliary voltage generating unit in FIGS. 4 and 6. [Figure 15] FIG. 10 is a schematic circuit diagram mainly showing a pulse generating section in a pulse power supply section according to a first modified example. [Figure 16] FIG. 16 is a diagram showing an example of a schematic circuit of an auxiliary voltage generating unit in FIG. 15. [Figure 17] FIG. 10 is a schematic circuit diagram mainly showing a pulse generating section in a pulse power supply section according to a second modified example. [Figure 18] FIG. 18 is a diagram showing an example of a schematic circuit of an auxiliary voltage generating unit in FIG. 17. [Figure 19] FIG. 10 is a schematic block diagram of a pulse power supply unit according to a second embodiment. [Figure 20] 6 is a time chart showing an example of voltage waveforms and current waveforms of main parts in a pulse power supply unit according to a second embodiment. [Figure 21] FIG. 11 is a schematic circuit diagram mainly showing a pulse generating section in a pulse power supply section according to a third modified example. DETAILED DESCRIPTION OF THE INVENTION

[0016] [Overall configuration of an example of a plasma etching device] FIG. 1 is a conceptual diagram showing a typical overall configuration of a plasma etching apparatus using a pulse power supply device according to the present invention. As shown in FIG. 1, the plasma etching apparatus includes a process control unit 110, an ion source plasma power supply unit 120, a bias pulse power supply unit 100, and a processing chamber 130 containing a substrate 150 as an object to be processed.

[0017] Although not shown, the processing chamber 130 has an ion source that receives power from the ion source plasma power supply unit 120 and generates plasma 160 from the supplied etching gas using various methods, such as inductively coupled plasma (ICP), electron cyclone resonance (ECR) plasma, and helicon wave plasma (HWP).

[0018] The bias pulse power supply unit 100 applies a pulsed bias voltage to the substrate 150 via the stage 140 to attract ions in the plasma 160 by providing them with kinetic energy. To obtain a desired (usually narrow, single) IED on the surface of the dielectric substrate 150, the bias pulse power supply unit 100 applies a pulse voltage to the substrate 150 such that the voltage value on the surface of the substrate 150 remains substantially constant and negative during a predetermined processing period. In this plasma etching apparatus, the ion source plasma power supply unit 120 and the bias pulse power supply unit 100 are provided separately, and the process control unit 110 independently controls the power supplies 100 and 120, thereby increasing the flexibility of the etching process. In the following description, the entire processing chamber 130 containing the plasma 160 will be referred to as the plasma reactor Pr, as is customary.

[0019] FIG. 2 is a simplified electrical equivalent circuit diagram of the plasma reactor Pr, which is the load of the bias pulse power supply unit (hereinafter simply referred to as the "pulse power supply unit") 100. In FIG. 2, the equivalent circuit of the substrate-side ion sheath and the equivalent circuit of the wall-side ion sheath in the plasma reactor Pr are combined, and some of the circuits are omitted. FIG. 3 is a diagram showing exemplary waveforms of the substrate surface voltage Vsub, the output voltage Vop1, and the stage voltage Vop2 shown in FIG. 2. The output voltage Vop1 shown in (b1) to (b3) in FIG. 3 is the output voltage in the apparatus of different embodiments described below. In the following description, symbols indicating each component or symbols specifying the voltage or current at a specific location are also used to represent the numerical values ​​of parameters of the component itself. For example, a symbol indicating a specific capacitor, such as Cp described below, is also used to represent the capacitance value of the capacitor, and a symbol indicating a voltage at a specific location, such as Vop1, is also used to represent the voltage value of that voltage.

[0020] 2, Rp is the DC resistance of the ion sheath (hereinafter referred to as "sheath resistance"), Cp is the capacitor of the dielectric substrate 150 (hereinafter referred to as "substrate capacitor"), Dp is a diode due to the rectification action of the ion sheath (hereinafter referred to as "sheath diode"), Cs is the capacitor of the ion sheath (hereinafter referred to as "sheath capacitor"), Zp is the plasma bulk resistance (hereinafter referred to as "plasma resistance"), and Cn is the total floating-to-ground capacitor (hereinafter referred to as "floating capacitor"). Furthermore, Ln is an inductor (hereinafter referred to as "wiring inductor") that is mainly made up of wiring connecting the pulse power supply unit 100 and the plasma reactor Pr, and Cb is a blocking capacitor.

[0021] In Figure 2, the ion sheath rectification caused by the difference in mobility between ions and electrons in plasma is represented by a parallel circuit consisting of a sheath diode Dp and a sheath resistance Rp. The sheath resistance Rp corresponds to the ion current, and the forward resistance of the sheath diode Dp corresponds to the electron current, each as a DC resistance. These elements, plus a sheath capacitor Cs, are connected in parallel. A plasma resistance Zp is connected to one end of this parallel circuit, and a substrate capacitor Cp is connected to the other end. A floating capacitor Cn is also connected to both ends of this series circuit. The junction between the plasma resistance Zp and the floating capacitor Cn is connected to a ground terminal 10, which is one output terminal of the pulse power supply unit 100, and is also grounded. The junction between the substrate capacitor Cp and the floating capacitor Cn is connected to an output terminal 11 of the pulse power supply unit 100 via a series circuit consisting of a blocking capacitor Cb and a wiring inductor Ln.

[0022] The surface of the substrate 150 is the connection point between the other end of the parallel circuit of the sheath diode Dp, sheath resistor Rp, and sheath capacitor Cs and the substrate capacitor Cp, and the voltage between this connection point and ground (0 V) is the substrate surface voltage Vsub. Here, the floating capacitor Cn, substrate capacitor Cp, and sheath capacitor Cs form a capacitor load, and as a typical example, their capacitance ratios are Cn ≈ 5 Cp, Cp ≈ 20 Cs. Normally, the capacitance of the sheath capacitor Cs is significantly smaller than that, so it can be substantially ignored in circuit operation.

[0023] As described above, when a narrow single IED is required on the substrate 150, as shown in FIG. 3(a), the substrate surface voltage Vsub must be maintained at a certain voltage value during the etching process period Tp (excluding Ta). During this etching process period Tp, the etching process is essentially performed on the substrate 150. Between two adjacent etching process periods Tp, a discharge period Td is provided to discharge the charge accumulated in the substrate capacitor Cp and the floating capacitor Cn during the etching process. Ta is the commutation period (pulse-on commutation period) from the end of the discharge period Td to the etching process period Tp, and Tb is the commutation period (pulse-off commutation period) from the end of the etching process period Tp to the discharge period Td. The period T is one cycle of the pulse waveform. For example, when the repetition frequency is 400 kHz, the period T is 2.5 μs. In this case, if the maximum duty ratio of the etching process period Tp is 80%, Tp = 2 μs and Td = 0.5 μs. To increase the width of the effective etching period Tp for a narrow single IED while keeping the width of the period T the same, it is desirable to make the commutation periods Ta, Tb as short as possible.

[0024] Vop1 shown in Figures 3(b1) to 3(b3) is an example of the output voltage from the pulsed power supply unit 100, and Vop2 shown in Figure 3(c) is the voltage applied to the stage 140. The numbers in brackets [ ] shown on the right side of Figures 3(b1) to 3(b3) correspond to the symbols indicating the voltage sources that generate the voltages shown in the waveform diagrams in the schematic circuit diagrams of the pulsed power supply unit shown in Figures 6, 17, and 15, which will be described later.

[0025] For the substrate surface voltage Vsub to be a negative pulse voltage whose peak voltage remains constant during the etching process period Tp, as shown in FIG. 3(a), the current Icp flowing through the substrate capacitor Cp must be a constant negative pulse current during the etching process period Tp. For this current Icp to be a constant negative pulse current, the applied voltage must be a linear function voltage with a constant slope -dv / dt corresponding to the value of the current Icp, i.e., a ramp voltage. That is, during the etching process period Tp, excluding the pulse-on commutation period Ta, the waveform of the output voltage Vop1 increases approximately linearly (the absolute value of the voltage increases in FIG. 3) from a first voltage (0 V in FIG. 3(b1)) to a second voltage (the falling reference voltage of the present invention, -Vc in FIG. 3(b1)). Here, Tp·(-dv / dt)=Vc.

[0026] During pulse-on, the starting voltage value of the ramp voltage is ΔV≈Vsub (both absolute values), so the auxiliary charging voltage ΔV for rapidly raising the substrate surface voltage Vsub from a zero potential (reference voltage) state to a predetermined value is ΔV≈Vsub. In the example of FIG. 3(b1), the voltage value of the rising reference voltage in the present invention is +ΔV, and the voltage rapidly rises from this +ΔV in the negative direction to approximately 0 V, which is the first voltage in the present invention. This corresponds to the rising portion of the pulse voltage in the present invention. Following this voltage rise, the voltage value is increased approximately linearly using a ramp voltage with a slope of -dv / dt corresponding to the required Vsub value. Then, at the end of the etching process period Tp, the voltage rapidly falls in the positive direction from the voltage value -Vc on the potential gradient portion, which is the falling reference voltage in the present invention, to the rising reference voltage (ΔV). This corresponds to the falling portion of the pulse voltage in the present invention. During the discharge period Td excluding the commutation period Tb, the potential of the output voltage Vop1 is maintained near the level of the rising reference voltage in the present invention, which corresponds to the holding section in the present invention.

[0027] Returning to Figure 2, the substrate surface voltage Vsub is expressed as the voltage drop across the sheath resistance Rp and plasma resistance Zp due to the current Icp flowing through the substrate capacitor Cp (assuming that the forward resistance of the diode Dp is zero and the reverse resistance is infinity). During the etching processing period Tp, when the current Icp is constant, Vsub = -Icp · (Rp + Zp). Furthermore, after the sheath diode Dp becomes conductive during the discharge period Td, Vsub = Icp · Zp. The plasma resistance Zp is a low resistance of a few ohms, and the charge stored in the substrate capacitor Cp can be discharged in a short time by the current Icp.

[0028] The current Icp flowing through the substrate capacitor Cp and the current Icn flowing through the floating capacitor Cn independently due to the output voltage Vop1 described above are respectively expressed as follows: Icp=Cp·(-dv / dt) Icn=Cn·(-dv / dt) The output current Io is the current output from the pulse power supply unit 100. Io=(Cp+Cn)·(-dv / dt) That is, the output current Io is the sum of the currents Icp and Icn. This current Icp is not affected by changes in the floating capacitor Cn, while the current Icn is a substantially reactive current that flows in the bypass path of the substrate capacitor Cp due to the floating capacitor Cn.

[0029] The stage voltage Vop2 applied to the stage 140 represents the voltage between the junction of the three capacitors Cp, Cn, and Cb and ground. This stage voltage Vop2 is obtained by simply shifting the waveform of the output voltage Vop1, which has been given a floating zero potential by the blocking capacitor Cb, in the negative direction by a DC voltage that is the average voltage of the substrate surface voltage Vsub. The blocking capacitor Cb is provided to prevent DC current generated by an external voltage from flowing into the pulsed power supply unit 100, and its capacitance is set to, for example, Cb ≈ 50 · Cn. However, it will be clear to those skilled in the art that the blocking capacitor Cb is not an essential component of the present invention and can be omitted as appropriate.

[0030] [First embodiment of pulse power supply unit] The following describes an example of the specific configuration and operation of the pulsed power supply unit 100. Figure 4 is a schematic block diagram of one embodiment of the pulsed power supply unit 100. The voltage waveform of the output voltage Vop1 of the pulsed power supply unit 100 in this embodiment is the waveform shown in Figure 3(b1).

[0031] This pulse power supply unit 100 includes: a high voltage generation unit 1 that receives power from a three-phase AC power supply 7 and generates a high voltage Vs; a ramp voltage generation unit 2 that receives the high voltage Vs as an input and outputs a ramp voltage Vm / Tm that changes periodically and has a constant negative slope -dv / dt through pulse width modulation (PWM) switching operation; a filter 3 that removes carrier signal components superimposed on this ramp voltage; an auxiliary voltage generation unit 4 that receives a DC voltage Vrec obtained by the high voltage generation unit 1 as an input and generates three types of auxiliary voltages Va, ΔV, and ΔV / 2 that are locally set voltages by a bidirectional DC / DC converter; a pulse generation unit 5 that generates an output voltage Vop1 having a negative pulse voltage during the etching treatment period Tp based on the ramp voltage Vm / Tm output from the filter 3 and the auxiliary voltages Va, ΔV, and ΔV / 2 output from the auxiliary voltage generation unit 4; and a control unit 6 that controls the operations of the high voltage generation unit 1, the ramp voltage generation unit 2, the auxiliary voltage generation unit 4, and the pulse generation unit 5, respectively. The output from the pulse generating unit 5 is output between the ground terminal 10 and the output terminal 11 of the pulse power supply unit 100, and is supplied to the plasma reactor Pr through a series circuit of a wiring inductor Ln and a blocking capacitor Cb.

[0032] The control unit 6 receives an instruction signal from the process control unit 110, which includes various set values ​​such as the substrate surface voltage Vsub, the period T, and the etching treatment period Tp, and determines various set values ​​such as the set value of the high voltage Vs in the high voltage generation unit 1, the set value of the period T in the ramp voltage generation unit 2, the set value of the ramp voltage slope dv / dt, the set values ​​of the voltages Va, ΔV, and (Va: auxiliary voltage during resonant commutation in the period Tb, which will be described later) in the auxiliary voltage generation unit 4, and the period Tp including information on the period T in the pulse generation unit 5. Preferably, the result of detecting the ramp voltage Vm / Tm output from the filter 3 is fed back to the control unit 6, and the control unit 6 compares the detection result with the set value dv / dt and operates to reduce the error between them and to reduce the output impedance through feedback.

[0033] The control unit 6 also detects the substrate surface voltage Vsub, and the output voltage Vop1 and output current Io (=Ic) of the pulse power supply unit 100 over time during the etching processing period Tp at predetermined time intervals, and variably controls the set values ​​of -dv / dt, Va, and ΔV so that they become optimal values.

[0034] In the waveform of the output voltage Vop1 shown in Figure 3(b1), the straight dashed line represents the high voltage Vs generated by the high voltage generator 1. Based on the applied voltage, determined by Vs ≈ T·(-dv / dt), the waveform of the ramp voltage Vm / Tm output by the ramp voltage generator 2 is shown by the dashed line. The ramp voltage Vm / Tm satisfies the maximum voltage Vm due to the maximum PWM modulation factor for the high voltage Vs, the maximum period Tm for the period T, and the voltage slope -dv / dt for the substrate surface voltage Vsub, and repeats with a period T. As described above, the pulse generator 5 generates a negative pulse voltage based on the ramp voltage Vm / Tm, the auxiliary charging voltage ΔV provided by the auxiliary voltage generator 4, and the set value of Tp instructed by the controller 6. During this process, resonant commutation is performed during the commutation periods Ta and Tb using the auxiliary voltages Va and ΔV / 2 to generate the initial resonant voltages at the rising edge and the falling edge.

[0035] The control unit 6 may include, for example, a high-speed logic circuit using an FPGA (Field Programmable Gate Array), a microcomputer (microcomputer) consisting of a CPU, ROM, RAM, timer, etc., an A / D converter, etc., and may be configured to generate the above-mentioned control signals by executing processing according to a pre-given program.

[0036] Next, the detailed configuration and operation of each part will be explained in order. <Configuration and Operation of High Voltage Generator 1> For example, the high voltage generating unit 1 can be configured almost as it is in the high voltage generating unit of the pulse power supply device described in Patent Document 2. FIG.

[0037] The high voltage generation unit 1 includes a step-down converter (CONV) 1A and a high-frequency inverter (INV) 1B. A three-phase AC voltage supplied from a three-phase AC power supply 7 is input to a rectifier circuit consisting of a bridge diode 101 and a capacitor 102. The voltage across the capacitor 102 is input to a step-down converter 1A that is configured with a complementary switch 103 consisting of two series-connected switching elements 131 and 132, a reactor 104, and a capacitor 106. The on / off operation of the complementary switch 103 in the step-down converter 1A is controlled by a control unit 6, thereby obtaining a P / N bus line voltage of a predetermined voltage value across the capacitor 106. A current transformer 105 is inserted between the reactor 104 and the capacitor 106, and the current value detected by the current transformer 105 is fed back to the control unit 6.

[0038] Both ends of the P / N bus line are connected to one end and the other end of a bridge circuit configured with a first leg 107 including switching elements 171 and 172 connected in series and a second leg 108 including switching elements 181 and 182 similarly connected in series. This bridge circuit configures a high-frequency inverter 1B, and a high-frequency high voltage with variable amplitude is output between the midpoint e of the first leg 107 and the midpoint f of the second leg 108 in response to changes in the P / N bus line voltage.

[0039] The above circuit method is known as the PAM (Pulse Amplitude Modulation) method. As is well known, commercial ripple caused by three-phase AC voltage can be improved by combining the above PWM control with peak current mode control.

[0040] <Configurations and Operations of the Ramp Voltage Generator 2 and the Filter 3> The ramp voltage generation unit 2 and filter 3 can be configured substantially as is with the waveform shaping unit and filter 3 in the pulsed power supply described in, for example, Patent Document 2. In brief, specifically, the control unit 6 includes a voltage pattern setting unit including a nonvolatile semiconductor memory such as a flash memory. This semiconductor memory stores voltage value data corresponding to the time lapse within one cycle of the pulse voltage, in this case, voltage value data corresponding to a ramp function. The main body of the ramp voltage generation unit 2 can be a multilevel cascade converter using a phase-shift PWM method, as in the example described in Patent Document 2, in which multiple waveform shaping units are connected in series, each including at least one pair of complementary switches or a combination of one switch and one diode in place of the complementary switches. The control unit 6 instructs the ramp voltage generation unit 2 on the period T and the ramp voltage slope -dv / dt based on the voltage value data stored in the semiconductor memory. The ramp voltage generation unit 2 then turns on and off the voltage provided by the high voltage generation unit 1 by controlling the complementary switches included in each waveform shaping unit based on the instructed information. The four waveform shaping units operate with a phase shift of 90° from each other, and the PWM output voltages of these waveform shaping units are added together to obtain a periodic ramp voltage.

[0041] However, in the pulse power supply device described in Patent Document 2, the voltage input to the waveform shaping unit is a high voltage of up to several kV, whereas here, the voltage Vs input to the ramp voltage generation unit 2 is a smaller voltage. This is because, as described above, the ramp voltage generation unit 2 only needs to generate a ramp voltage with a maximum amplitude of Vc; in other words, it does not need to generate a constant voltage equivalent to ΔV. Therefore, it is less subject to the constraints of the voltage ratings of circuit components such as switching elements, and the circuit can be simplified by mitigating the degree of required voltage change.

[0042] The filter 3 is an LC low-pass filter, which removes carrier frequency components and the like generated by PWM switching control in the lamp voltage generating section 2 and outputs the signal.

[0043] <Configuration and Operation of Pulse Generator 5> FIG. 6 is a schematic circuit diagram mainly showing the pulse generating section. As described above, the ramp voltage Vm / Tm obtained after the carrier frequency component has been removed by the filter 3 is output between the ground terminal 30 and the output terminal 31 of the filter 3. Meanwhile, the auxiliary voltage generating unit 4, which will be described in detail later, includes four voltage sources 13, 14, 15, and 16. The voltage source 15 outputs a voltage ΔV for obtaining a first auxiliary voltage corresponding to the substrate surface voltage Vsub. The voltage source 13 outputs a voltage ΔV / 2 for obtaining an initial resonant voltage during the pulse-on commutation period Ta (the initial resonant voltage during the rising edge of the present invention). The voltage source 14 outputs a predetermined voltage Va for obtaining an initial resonant voltage during the pulse-off commutation period Tb (the initial resonant voltage during the falling edge of the present invention). Furthermore, the voltage source 16 primarily obtains a voltage corresponding to the amount of level shift of the ramp voltage obtained by the ramp voltage generating unit 2. However, in the first embodiment, the voltage generated by the voltage source 16 is zero, and the voltage source 16 is essentially non-existent. The positive and negative terminals of the voltage source 16 may be considered to be short-circuited. For this reason, voltage source 16 is shown by a dashed line in Fig. 6. This is also the case in Fig. 16 and Fig. 17, which will be described later, where voltage sources whose positive and negative poles can be considered to be short-circuited are shown by dashed lines.

[0044] A first series circuit including a voltage source 14, a switching unit S2, a forward diode Db, and a reverse diode D3, and a second series circuit including a voltage source 15, a switching unit S4, a damping resistor Rd2, a damping resistor Rd1, and a switching unit S1 are connected in parallel between a ground terminal 30 and an output terminal 31 of the filter 3. A third series circuit including a voltage source 13, a switching unit S5, and a reverse diode Da is connected between the ground terminal 30 and a node N3 which is the connection point of the two damping resistors Rd1 and Rd2 of the second series circuit. The ground terminal 30 of the filter 3 and the negative terminals of the voltage sources 13, 14, and 15, which are one end of the first to third series circuits, are connected to a ground terminal 10 of the pulse power supply unit 100.

[0045] An inductor Li is provided between a node N2, which is the connection point between diode Db and diode D3 in the first series circuit, and a node N3, which is the connection point between resistors Rd2 and Rd1 in the second series circuit. Node N3 is connected to the other end of the third series circuit and to an output terminal 11 of the pulse power supply unit 100. A node N4, which is the connection point between the other ends of the first and second series circuits, is connected to an output terminal 31 of the filter 3. A first current sensor Ct1 is provided on the wiring connecting the output terminal 31 of the filter 3 and node N4. A second current sensor Ct2 is provided on the wiring connecting diode Da and node N3. A third current sensor Ct3 is provided on the wiring connecting diode Db and node N2. Switching units S1, S2, S4, and S5 each comprise a semiconductor switching element such as a power MOSFET, and anti-parallel diodes D1, D2, D4, and D5 are parasitic diodes of the respective semiconductor switching elements.

[0046] The pulse generating unit control unit 65 included in the control unit 6 receives commands from the control unit 6 and outputs control signals G1, G2, G4, and G5 to control the on / off operation of the switching units S1, S2, S4, and S5, respectively. The first current sensor Ct1 detects a constant current Ic that flows during the etching process period Tp due to the voltage applied to the substrate capacitor Cp and the floating capacitor Cn, and feeds back the detected value to the control unit 6. By detecting zero of the output current Io (strictly speaking, the resonance currents Ida and Idb) during the pulse-on commutation period Ta using the second current sensor Ct2 and during the pulse-off commutation period Tb using the third current sensor Ct3, it is possible to control the control signals G5 and G1 during the pulse-on commutation period Ta and the control signals G2 and G4 during the pulse-off commutation period Tb at appropriate timings.

[0047] Figure 7 is a time chart of waveforms including the output current Io, output voltage Vop1, current Icp of the substrate capacitor Cp, substrate surface voltage Vsub, and control signals G1, G2, G4, and G5 of the switching unit during the pulse-on commutation period Ta (t0 to t1). FIG. 9 shows the current paths of the output current Io, current Icp, and current Icn during the pulse-on commutation period Ta.

[0048] 7, just before time t0, the control signal G4, which is in a high state, goes low, and after the dead time Te has elapsed, the control signal G5 changes to high at time t0. When the control signal G4 goes low, the switching unit S4 turns off, but the output voltage Vop1, which is shifted by the voltage of the floating capacitor Cn from the stage voltage Vop2, which is the voltage of the floating capacitor Cn (in this case, substantially the same as the voltage of the substrate capacitor Cp), maintains a voltage level that is higher by the voltage value ΔV from the voltage source 15 with respect to the ground point.

[0049] At time t0, when the control signal G5 goes high and the switching unit S5 turns on, the following resonant current flows as the output current Io along the path shown by the solid arrow in Figure 9, due to the voltage value ΔV of the output voltage Vop1 maintained as described above, the voltage value ΔV / 2 from the voltage source 13, the combined value Cre (≒Cn) of each capacitor Cn, Cp, Cs, and Cb, and the wiring inductor Ln. Io=Ida=-[(ΔV / 2) / √(Ln / Cre)]·sinθ

[0050] Moreover, the change in output voltage at this resonance is as follows: Vop1=(ΔV / 2)(1+cosθ) Therefore, the output voltage Vop1 changes from a voltage value ΔV, which is the rising reference voltage at time t0, to 0V at time t1. The initial resonant voltage at this time is ΔV / 2, and the voltage change over the entire pulse-on commutation period Ta is ΔV, twice the initial resonant voltage. On the other hand, the stage voltage Vop2 is zero-point floating, so as shown in Figure 3(c), it is determined only by its absolute value, regardless of polarity.

[0051] The length of the pulse-on commutation period Ta depends on the LC constant and is calculated using the following equation for the half-wave resonance period: Ta=π√(Ln·Cre) The difference between the stage voltage Vop2, which is the voltage value of the floating capacitor Cn and changes rapidly due to resonance, and the voltage value of the substrate capacitor Cp, which changes slowly due to the action of the sheath resistance Rp, is the substrate surface voltage Vsub. The current Icp flowing through the path indicated by the dashed arrow in Figure 9 is roughly the substrate surface voltage Vsub at this time divided by the load resistance value (Rp + Zp), and is branched from the output current Io to the current Icn flowing through the floating capacitor Cn.

[0052] At time t1, the control signal G5 goes low, turning off the switching unit S5. At approximately the same time, the control signal G1 goes high, turning on the switching unit S1. Based on the detection result of the second current sensor Ct2, the control unit 6 can synchronize the time when the resonant current Ida is detected to be zero with the operating time at time t1. This means that π√(Ln·Cre), which is the half-wave resonant period (t0 to t1) of the on-time commutation period Ta, is matched with the resonant current flow period of the output current Io.

[0053] At this time, the output voltage Vop1 ideally changes from ΔV to 0 V due to resonant commutation, becoming equal to the zero potential, which is the output voltage of the ramp voltage generator 2 at time t1. Therefore, the current Ird1 of the switching unit S1 does not flow. However, if the output voltage Vop1 does not reach 0 V, then at some point after time t1, the current Ird1 flows from the composite capacitor Cre (≒Cn) along the same path as the current path (solid arrow) from the filter 3 (not shown in Figure 10). On the other hand, if the output voltage Vop1 exceeds 0 V, the direction of the current Ird1 reverses, and the output voltage Vop1 is clamped to the zero potential, which is the output voltage of the filter 3. As a result, the output voltage Vop1 converges to 0 V. The damping resistor Rd1 functions to suppress unnecessary oscillations of the current Ird1 that flows at this time. The resistance of this damping resistor Rd1 should be set to approximately 2·√(Ln / Cre).

[0054] During the etching process period Tp after time t1, the ramp voltage -dv / dt of the ramp voltage Vm / Tm generated by the ramp voltage generator 2 is applied to both the floating capacitor Cn and the substrate capacitor Cp. As a result, currents Icn and Icp flow through the paths indicated by the two-dot chain arrow and dashed arrow in Fig. 10 to the floating capacitor Cn and the substrate capacitor Cp, respectively. The output current Io (constant current Ic) flowing through the path indicated by the solid arrow in Fig. 10 is the sum of the currents Icn and Icp. As a result, the output voltage Vop1 during this etching process period Tp has a voltage waveform in which the voltage increases at a constant slope in the negative direction from approximately 0 V, which is higher in the negative direction by ΔV than the reference voltage at the time of rise, as described above.

[0055] Figure 8 is a time chart of waveforms during the pulse-off commutation period Tb, including the output current Io, output voltage Vop1, current Icp in substrate capacitor Cp, substrate surface voltage Vsub, branch currents Idb, Id3, and Ird2 of output current Io, and control signals G1, G2, G4, and G5 of the switching unit. Figures 11 to 13 are schematic diagrams showing the current paths for the output current Io, its branch currents Idb, Id3, and Ird (Ird1 and Ird2), current Icp in substrate capacitor Cp, and constant current Ic due to lamp voltage dv / dt, during the pulse-off commutation period Tb.

[0056] In Figure 8, just before time t2, the control signal G1 is high, and the other control signals G5, G2, and G4 are low. The control signal G1 changes from high to low, and at time t2, after the dead time Te has elapsed, the control signal G2 changes to high. Next, at time t4, the control signal G2 changes to low, and the control signal G4 changes to high. From then on, the state in which the control signals G1, G2, and G5 are low and the control signal G4 is high is maintained until just before time t0 in Figure 7, as already explained.

[0057] To be specific, at the end of the steady etching processing period Tp, the control signal G1 is high, so that the switching unit S1 is in the on state, and the currents Io, Icp, substrate surface voltage Vsub, and output voltage Vop1 are as follows: Io = Ic = (Cn + Cp)·(-dv / dt) Icp = Cp·(-dv / dt) Vsub = Icp·(Rp + Zp) Vop1 = -Vc = -Tp·dv / dt

[0058] At time t2, when the control signal G2 changes to high and the switching unit S2 turns on, the resonance current Io generated by the combined capacitor Cre ≒ Cn and the combined inductor (Ln + Li) mainly flows through the floating capacitor Cn along the path indicated by the arrow in Fig. 11. Here, the resonance initial voltage is half of the value of the resonance amplitude (ΔV + Vc) to which the value of the output voltage Vop1 (=-Vc) becomes ΔV due to resonance, i.e., (ΔV + Vc) / 2. The voltage value Va of the voltage source 14 is a correction value based on the node N1 for obtaining the value of the resonance initial voltage ((falling resonance initial voltage) (ΔV + Vc) / 2) from the voltage value (-Vc here) of the output voltage Vop1 at time t2. Since the potential of the node N1 is 0V here, as shown in Fig. 8, Va is the difference between the voltage value corresponding to (ΔV - Vc) / 2 and the ground potential, which is (ΔV - Vc) / y in this case. The value of the resonance current Io at this time is as follows. Io = Idb = [{(ΔV + Vc) / 2} / √{(Ln + Li) / Cre}]·sinθ In Figs. 3(b1) and 8(b), Va is a positive value because ΔV > Vc, but it is also possible that ΔV < Vc, and in that case, Va is a negative value. That is, the voltage value Va can be either positive or negative depending on the magnitude relationship between ΔV and Vc.

[0059] That is, the inductor Li is intended to correct the increase in resonant current due to the difference Vc / 2 between the initial voltage at the rise time of the resonant voltage at time t0 (here, ΔV / 2) and the initial voltage at the fall time of the resonant voltage at time t2 (here, (ΔV-Vc) / 2), by increasing the characteristic impedance. Therefore, if the rated values ​​of the elements in the path, including the switching unit S2, are sufficient to withstand this increase in resonant current, the inductor Li can be omitted. Furthermore, the difference between the stage voltage Vop2, which is the voltage value of the floating capacitor Cn and changes rapidly due to resonance, and the voltage value of the substrate capacitor Cp, which changes slowly due to the action of the sheath resistance Rp, is the substrate surface voltage Vsub, and the value of the current Icp of the substrate capacitor Cp, which flows through the path indicated by the dashed arrow in Figure 11, is approximately the substrate surface voltage Vsub in this case divided by the combined resistance (Rp+Zp).

[0060] At time t3, when the substrate surface voltage Vsub becomes 0, the diode Dp becomes conductive due to the rectification action of the ion sheath. As a result, as shown by the dashed arrow in Figure 12, the current Icp flowing through the substrate capacitor Cp increases and flows as a resonant current Io together with the current Icn flowing through the floating capacitor Cn. The value of the current Icp at this time is the substrate surface voltage Vsub divided by the plasma resistance Zp.

[0061] At time t4, the control signal G2 changes to low, turning off the switching unit S2. At approximately the same time, the control signal G4 changes to high, turning on the switching unit S4. Based on the detection signal from the third current sensor Ct3, the control unit 6 can synchronize the time point at which the resonant current Idb is detected to be zero with the time point of operation at time t4. This means that the half-wave resonant period π√[(Li + Ln) · Cre] in the pulse-off commutation period Tb is matched with the resonant current flow period of Io = Idb.

[0062] At this time, the value of output voltage Vop1 is ideally ΔV, which is the same potential as the voltage ΔV from voltage source 15. Therefore, Ird2, which is both the output current Io and the current of switching unit S4, does not flow. However, if the value of output voltage Vop1 is less than ΔV, current Ird2 flows from voltage source 15 through the path shown by the dashed dotted line in Figure 13. On the other hand, if the value of output voltage Vop1 exceeds ΔV, current Ird2 flows in the reverse direction, and its voltage is clamped to the voltage value ΔV of voltage source 15. Therefore, in either case, the value of output voltage Vop1 converges to the voltage of voltage source 15, i.e., the rising-time reference voltage ΔV. Damping resistor Rd2 suppresses excessive oscillations in current Ird2, and its resistance is preferably set to approximately 2·√(Ln / Cre).

[0063] Furthermore, if the operation at time t4 occurs earlier than the time when the resonant current Idb is detected to be zero due to a timing discrepancy or the like in the control signal from the control unit 6, the diode D3 will be conductive. Then, a current Id3 having a value substantially equal to the resonant current Idb that had been flowing up until then will flow through the path indicated by the solid arrow in Fig. 13, and the energy stored in the composite inductor Li+Ln will be regenerated in a capacitor (not shown) in the filter 3. This prevents problems such as excessive voltage from occurring in the switching unit S2 that was turned off earlier, and the pulse generating unit 5 can operate safely and stably.

[0064] Needless to say, the values ​​given by the various formulas and the like described above are ideal values ​​that do not include resistance components of wiring and circuit elements, unless explicitly stated. Therefore, these values, including the set values ​​Va, ΔV, ΔV / 2, etc., can be appropriately corrected from the ideal values ​​depending on the actual operating conditions.

[0065] <Configuration and Operation of Auxiliary Voltage Generator 4> 14 is a diagram showing an example of a schematic circuit of the auxiliary voltage generating unit 4. The primary winding n1 of the high-frequency switching transformer T41 for the auxiliary voltage generating unit is connected in parallel with the primary winding of a high-frequency switching transformer provided in the output stage of the high-voltage generating unit 1. A high-frequency high voltage Vq with variable amplitude, which is the voltage between the midpoint e of the first leg 107 and the midpoint f of the second leg 108 of the high-voltage generating unit, is applied to this primary winding n1. A voltage Vs is generated in the secondary winding of the high-frequency switching transformer, which is connected to the lamp voltage generating unit 2.

[0066] The voltage generated across the secondary winding n2 of the transformer T41 based on the voltage Vq is rectified by a bridge rectifier circuit formed by high-frequency diodes D41-D44. A predetermined DC voltage Vr is obtained across the capacitor C41, whose cathode is the positive electrode (node ​​N5 in FIG. 6) and whose anode is the ground voltage (node ​​N1 in FIG. 6). This voltage Vr is stepped down by three bidirectional buck-boost converters 402a, 402b, and 402c, which independently step it down to a voltage value Va of voltage source 14, a voltage value ΔV of voltage source 15, and a voltage value ΔV / 2 of voltage source 13. The detected values ​​of Va, ΔV, and ΔV / 2 are input to an auxiliary power supply control unit 47 for the auxiliary voltage generator 4 and are feedback-controlled relative to the set values ​​instructed by the control unit 6.

[0067] The bidirectional buck-boost converters 402a, 402b, and 402c are used to regenerate and reuse the energy generated by commutation of floating capacitor Cn and substrate capacitor Cp to the power supply. For example, during the on-time commutation period Ta, a half-wave resonant current Io=Ida flows from floating capacitor Cn through the path indicated by the solid arrow in Figure 9 in a direction that charges capacitor C42c of voltage source 13. This causes the voltage of capacitor C42c to rise above the set value ΔV / 2. In response, bidirectional buck-boost converter 402c performs a boost operation to maintain ΔV / 2 through feedback control, and the accumulated charge corresponding to the voltage increase in capacitor C42c is regenerated to capacitor C41 on the input side, which is common to bidirectional buck-boost converters 402c, 402a, and 402b. Subsequently, the voltage of capacitor C41 rises, exceeding its set value Vr.

[0068] Here, during the pulse-off commutation period Tb, half-wave resonant current Io=Idb flows from floating capacitor Cn through the path indicated by the solid arrows in Figures 11 and 12 in the direction discharging capacitor C42a of voltage source 14. As a result, bidirectional buck-boost converter 402a of voltage source 14 performs a step-down operation, and the charge accumulated in input-side capacitor C41, which has risen above voltage Vr, is released and reused. In this way, the voltage increases of voltage Va of voltage source 14, voltage ΔV of voltage source 15, and voltage ΔV / 2 of voltage source 13 due to the regenerative energy of floating capacitor Cn are eliminated.

[0069] As described above, the pulse power supply unit 100 of this embodiment applies a pulse voltage of nearly ideal shape to the substrate 150 via the stage 140 in the plasma reactor Pr, and can maintain the substrate surface voltage Vsub at a substantially constant value during the etching process. Furthermore, the commutation period of the pulse voltage is shortened, that is, the rise and fall of the pulse voltage become steeper and the time required for this is shorter, so that the etching process period can be extended accordingly, enabling efficient etching.

[0070] [Variations] The pulse power supply unit 100 according to the embodiment described above can be modified as appropriate. These modifications will be described below. Fig. 15 is a schematic circuit diagram mainly showing the pulse generating unit in a pulse power supply unit 100A according to a first modification.

[0071] In this pulse generating unit, the voltage value of voltage source 15, which outputs voltage ΔV and was connected in series with switching unit S4 in pulse generating unit 5 shown in FIG. 6, is set to 0, and the positive and negative terminals of voltage source 15 are short-circuited (hence voltage source 15 is shown by a dashed line in FIG. 15). Accordingly, switching unit S4 is directly connected to node N1. Voltage source 13 has the same voltage value as in the example shown in FIG. 6, ΔV / 2, but its polarity is inverted. Voltage source 14, which outputs a predetermined voltage Va, also has its polarity and voltage value changed. Furthermore, voltage source 16, which was essentially non-existent in the example shown in FIG. 6, has a voltage value of ΔV and is connected between ground terminal 30 of filter 3 and node N1 so that the node N1 side is positive. Apart from these changes to voltage sources 13 to 16, the configuration is essentially the same as that of pulse generating unit 5 shown in FIG. 6.

[0072] The operation timing of the control signals that turn on and off the switching elements included in each switching unit remains unchanged from the time charts shown in Figures 7 and 8. However, the vertical axes showing voltage and current values ​​change, and the voltage value of the output voltage Vop1 at time t5 during the pulse-off commutation period Tb in the time chart shown in Figure 8 is changed from ΔV to 0 as shown in Figure 3(b3), and the 0 level of the output voltage Vop1 in the time chart shown in Figure 7 is similarly changed. That is, the difference in operation between the above embodiment and this first modified example is that the waveform of the output voltage Vop1 is shifted by ΔV in the negative voltage direction, and the waveform of the output voltage Vop1 becomes as shown in Figure 3(b3).

[0073] Therefore, only the operation related to the output voltage Vop1, which is different from the above embodiment, will be described here. For the description, although the voltage values ​​and polarities of the voltage sources 13 to 16 are partially different, Figures 9 to 13 will be used.

[0074] Immediately before time t0, output voltage Vop1 maintains the rising reference voltage of 0 V. At time t0, when control signal G5 changes to high and switching unit S5 turns on, the next resonant current flows as output current Io from voltage source 13, whose voltage value is ΔV / 2, via wiring inductor Ln to capacitor 12, whose composite value Cre≈Cn has the voltage value (0 V) of output voltage Vop1 that had been maintained up until then, via the path indicated by the solid arrow in Fig. 9. Io=Ida=-[(ΔV / 2) / √(Ln / Cre)]·sinθ The change in output voltage Vop1 due to this resonance is Vop1=-(ΔV / 2)(1-cosθ) and as described above, it changes from 0 V at time t0 to −ΔV (first voltage in the present invention) at time t1.

[0075] At time t1, when the control signal G5 changes to low and the switching unit S5 turns off, almost simultaneously the control signal G1 changes to high and the switching unit S1 turns on. In this case, too, the control unit 6 can perform synchronization control based on the detection signal of the second current sensor Ct2 to match the time when the resonant current Ida is detected to be zero with the time of operation at time t1.

[0076] As shown in FIG. 8, immediately before time t2, the currents Io, Icp, the substrate surface voltage Vsub, and the output voltage Vop1 are in the following states, respectively. Io=Ic=(Cn+Cp)·(-dv / dt) Icp=Cp·(-dv / dt) Vsub=Icp·(Rp+Zp) Vop1=-(ΔV+Vc)=-[ΔV+Tp·(dv / dt)]

[0077] At time t2, the capacitors Cp and Cn charged by the output voltage Vop1 begin to discharge. At this time, the voltage value of the falling-time resonance initial voltage due to the resonance amplitude value at which the value of output voltage Vop1, which is the falling-time reference voltage, becomes 0 V, which is the rising-time reference voltage, due to resonance is (ΔV+Vc) / 2. Therefore, the voltage value Va=-(ΔV+Vc) / 2 of voltage source 14 in this modified example is a correction value based on the potential (0 V) of node N1 to obtain the falling-time resonance initial voltage (ΔV+Vc) / 2 from the voltage value of -(ΔV+Vc).

[0078] At time t3, the diode Dp becomes conductive, and the current Icp flows as indicated by the dashed arrow in FIG.

[0079] At time t4, the control signal G2 changes to low, turning off the switching unit S2, and at substantially the same time, the control signal G4 changes to high, turning on the switching unit S4. At this time, the control unit 6 can perform synchronization control based on the detection signal from the third current sensor Ct3, so as to match the time when the resonant current Idb is detected to be zero with the time of operation at time t4. This allows the pulse power supply unit of this modified example to operate safely and stably.

[0080] FIG. 16 is a diagram showing an example of a schematic circuit of the auxiliary voltage generating unit 4A in FIG. Bridge rectifier circuit 401 generates DC voltage Vr with its cathode connected to node N1, which is the ground potential, and its anode connected to node N5, which is the negative polarity. Bidirectional buck-boost converters 402aA, 402bA, and 402cA operate to output from DC voltage Vr a voltage value Va from voltage source 14, a voltage value ΔV from voltage source 16, and a voltage value ΔV / 2 from voltage source 13, each of which is negative with respect to node N1.

[0081] FIG. 17 is a schematic circuit diagram mainly showing a pulse generating section in a pulse power supply section 100B according to a second modification.

[0082] In this pulse generating unit, the voltage value of voltage source 13, which outputs a voltage ΔV / 2 and was connected in series with switching unit S5 in the pulse generating unit 5 shown in FIG. 6, is set to 0, and the positive and negative terminals of voltage source 13 are short-circuited (hence, voltage source 13 is shown by a dashed line in FIG. 17). Accordingly, switching unit S5 is directly connected to node N1. Furthermore, voltage source 15 has the same polarity as in the example shown in FIG. 6, but its voltage value has been changed to ΔV / 2. Voltage source 14, which outputs a predetermined voltage Va, also has a different polarity and voltage value from the example shown in FIG. 6. Furthermore, voltage source 16, which was essentially non-existent in the example shown in FIG. 6, has a voltage value of ΔV / 2 and is connected between the ground terminal 30 of filter 3 and node N1 so that the node N1 side is positive. Other than these changes to voltage sources 13-16, the configuration is essentially the same as that of pulse generating unit 5 shown in FIG. 6. The operation timing of the control signals that turn on and off the switching elements included in each switching unit remains unchanged from the time charts shown in FIGS. 7 and 8.

[0083] However, the vertical axes indicating voltage and current values ​​change, and the voltage value of the output voltage Vop1 at time t5 during the pulse-off commutation period Tb in the time chart shown in Fig. 8 is changed from ΔV to ΔV / 2 as shown in Fig. 3(b2), and the 0 level of the output voltage Vop1 in the time chart shown in Fig. 7 is similarly changed. That is, the difference in operation between the above embodiment and this modified example is that the waveform of the output voltage Vop1 is shifted by ΔV / 2 in the negative voltage direction, and the waveform of the output voltage Vop1 becomes as shown in Fig. 3(b2).

[0084] Therefore, as in the first modification, only the operation related to the output voltage Vop1, which differs from the above embodiment, will be described here. For this description, although the voltage values ​​and polarities of the voltage sources 13 to 16 are partially different, Figures 9 to 13 will be used.

[0085] Immediately before time t0, the output voltage Vop1 maintains the rising reference voltage ΔV / 2. At time t0, when the control signal G5 changes to high and the switching unit S5 turns on, the next resonant current flows as the output current Io via the wiring inductor Ln from the capacitor with a composite value Cre≈Cn that has been charged to the voltage value ΔV / 2 of the output voltage Vop1 that has been maintained up until then, via the path indicated by the solid arrow in Figure 9. Io=Ida=-[(ΔV / 2) / √(Ln / Cre)]·sinθ The change in output voltage Vop1 due to this resonance is Vop1=(ΔV / 2)·cosθ As described above, the output voltage Vop1 changes from ΔV / 2 at time t0 to −ΔV / 2 (first voltage in the present invention) at time t1.

[0086] At time t1, when the control signal G5 changes to low and the switching unit S5 turns off, almost simultaneously the control signal G1 changes to high and the switching unit S1 turns on. In this case, too, the control unit 6 can perform synchronization control based on the detection signal of the second current sensor Ct2 to match the time when the resonant current Ida is detected to be zero with the time of operation at time t1.

[0087] As shown in FIG. 8, immediately before time t2, the currents Io, Icp, the substrate surface voltage Vsub, and the output voltage Vop1 are in the following states, respectively. Io=Ic=(Cn+Cp)·(-dv / dt) Icp=Cp·(-dv / dt) Vsub=Icp·(Rp+Zp) Vop1=-[(ΔV / 2)+Vc]=-[(ΔV / 2)+Tp·(dv / dt)]

[0088] At time t2, the capacitors Cp and Cn charged by the output voltage Vop1 begin to discharge. At this time, the voltage value of the falling-time resonance initial voltage due to the resonance amplitude value at which the value of output voltage Vop1, which is the falling-time reference voltage, becomes ΔV / 2, which is the rising-time reference voltage, is (Vc+ΔV) / 2. Therefore, the voltage value Va=-Vc / 2 of voltage source 14 in this modified example is a correction value based on the potential (0V) of node N1 to obtain the falling-time resonance initial voltage (ΔV+Vc) / 2 from the voltage value of -Vc-(ΔV / 2).

[0089] At time t3, the diode Dp becomes conductive, and the current Icp flows as indicated by the dashed arrow in FIG.

[0090] At time t4, the control signal G2 changes to low, turning off the switching unit S2, and at substantially the same time, the control signal G4 changes to high, turning on the switching unit S4. At this time, the control unit 6 can perform synchronization control based on the detection signal from the third current sensor Ct3 to match the time when the resonant current Idb is detected to be zero with the time of operation at time t4. This allows the pulse power supply unit 100B of this second modified example to operate safely and stably.

[0091] FIG. 18 is a diagram showing an example of a schematic circuit of the auxiliary voltage generating unit 4B in FIG. Here, the secondary winding of transformer T41 is divided into two, n2a and n2b, with a center tap, which serves as the ground terminal at node N1. Bridge rectifier circuit 401 generates two DC voltages Vr and -Vr, with its cathode connected to node N5a (positive polarity) and its anode connected to node N5b (negative polarity). Bidirectional buck-boost converters 402aB, 402bB, and 402cB operate from DC voltages Vr and -Vr to output voltages Va, ΔV / 2, and ΔV / 2, respectively, from voltage source 14, voltage source 16, and voltage source 15, respectively, with node N1 as the reference.

[0092] 21 is a schematic circuit diagram mainly showing the pulse generating unit in a pulse power supply unit 100D according to a third modification. The basic configuration of the pulse generating unit in this third modification is the same as that of the pulse generating unit 5 of the embodiment shown in FIG. 6, except that a high-speed constant current source Ap is connected between nodes N1 and N4. This high-speed constant current source Ap adds a current +Ic to the current Ic (output current Io) output from the ground terminal 10 in accordance with a current setting value +Ic instructed by the control unit 6. This current +Ic can be applied and adjusted in response to a command to correct the substrate surface voltage Vsub from the process control unit 110 when the sheath conditions change due to fluctuations in the gas pressure in the plasma reactor Pr or fluctuations in the output of the ion source plasma power supply unit 120, causing the substrate surface voltage Vsub to change.

[0093] That is, the set value of this current +Ic corresponds to the change in the substrate surface voltage Vsub that accompanies changes in the sheath conditions, and is a smaller current than the output current Io shown in Figure 10. Therefore, the high-speed constant current source Ap can have a small power capacity. This allows the use of a switching element with a small capacity and good high-frequency characteristics, such as a gallium nitride (GaN) FET, and high-speed control is possible by increasing the PWM switching frequency and using a multi-phase converter such as a phase-shift multilevel cascade converter.

[0094] [Pulse power supply unit according to further embodiments] FIG. 19 is a block diagram of a bias pulse power supply unit 100C according to still another embodiment of the present invention. The pulse power supply unit 100C of this embodiment includes a plurality (two sets here) of high voltage generating units 1, lamp voltage generating units 2, filters 3, auxiliary voltage generating units 4, and pulse generating units 5. In Fig. 19, the components of each set are distinguished by the symbols X and Y, and a set with a symbol X attached to it will be called an X set, and a set with a symbol Y attached to it will be called a Y set. Note that the two high voltage generating units 1X and 1Y can share part of the circuit, but are shown here as completely separate units.

[0095] Each group can generate a predetermined pulse voltage as described above, but depending on the control method, either a method in which the X group and Y group of circuits are operated at the same timing to generate pulse voltages that are superimposed in series in phase and output, or a method in which the X group and Y group of circuits are operated in a time-division manner to generate pulse voltages that are alternately output and combined can be adopted.

[0096] As shown in Figure 19, in either of the above two methods, the output voltages of the pulse generating units 5X and 5Y, which have the same configuration, are simply added together, and the resulting voltage is output between the ground terminal 10 and the output terminal 11 of the pulse power supply unit 100C.

[0097] Although the output voltage Vop1, stage voltage Vop2, and substrate surface voltage Vsub of this pulse power supply unit 100C are not shown, referring to FIGS. 3 and 4, it is clear that the capacitor load voltage Vc (=-Tp·(-dv / dt)) that changes over time from the end of the rising portion in the X group and the capacitor load voltage Vc (=-Tp·(-dv / dt)) that changes over time from the end of the rising portion in the Y group are added together and output. As a result, the values ​​of both the output voltage Vop1 and the stage voltage Vop2 are doubled compared to the configuration with only one group as in the first embodiment, and as a result, the substrate surface voltage Vsub is also doubled. In other words, to obtain a pulse voltage of the same voltage value, the voltage value of the pulse voltage generated by the circuit in each group can be halved, which has the advantage that, for example, as a switching element, it is possible to use an element that has a low voltage rating, is inexpensive, and has good switching characteristics. Furthermore, elements with low voltage ratings and good switching characteristics are more readily available, which reduces constraints on circuit design and simplifies design.

[0098] On the other hand, Fig. 20 is a time chart when the X and Y circuits of the pulse power supply unit 100C shown in Fig. 19 are operated in a time-division manner, that is, alternately, rather than in the same phase. The ramp voltage generating units 2X and 2Y generate symmetrical triangular waves with a period T that are 180° out of phase with each other, and in the T / 2 period from time t0 to time t5, the ramp voltage generating unit 2X generates a ramp voltage waveform that is Vm / Tm, and in the T / 2 period from time t5 to time t10, the ramp voltage generating unit 2Y generates a ramp voltage waveform that is Vm / Tm.

[0099] The etching process period Tp is divided into Tp(X) from time t0 to t2 and Tp(Y) from time t5 to t7, and the pulse generation unit 5X alternately outputs output voltages Vop1(X) and Vop1(Y) based on the set values ​​of Vm / Tm(X) and Tp(X) instructed by the control unit 6 and the voltages Va, ΔV, and ΔV / 2 provided by the auxiliary voltage generation unit 4X, while the pulse generation unit 5Y alternately outputs output voltages Vop1(X) and Vop1(Y) based on the set values ​​of Vm / Tm(Y) and Tp(Y) instructed by the control unit 6 and the voltages Va, ΔV, and ΔV / 2 provided by the auxiliary voltage generation unit 4Y. As a result, in addition to the stage voltage Vop2, the output current Io, Ic flowing through capacitors Cn and Cp, the substrate surface voltage Vsub, and the like are similarly supplied independently and alternately in time from the X and Y circuits. That is, the output voltage Vop1 of the pulse power supply unit 100C is obtained by inserting (interleaving) the pulse voltage output from one pulse generating unit 5X between the next pulse voltage output from the other pulse generating unit 5Y.

[0100] The waveform of the output voltage Vop1 shown in FIG. 20(b) is the same as that of the output voltage Vop1 shown in FIG. 3(b3). However, the symmetrical triangular wave with a period T of the ramp voltage generators 2X and 2Y only needs to have half the frequency of the output voltage Vop1, which has a period T / 2. For example, if the pulse frequency of the output voltage Vop1 is 400 kHz, the frequency of the symmetrical triangular wave of the ramp voltage generators 2X and 2Y only needs to be 200 kHz. Furthermore, compared to the ramp waveform shown by the dashed line in FIG. 3(b3), the waveform shown by the dashed line in FIG. 20(b) is a nearly symmetrical triangular waveform, which eliminates abrupt waveform changes and facilitates switching control. Furthermore, the pulse frequency of the pulse generators 5X and 5Y is also sufficient, which halves the switching loss per element and provides advantages such as easier heat dissipation. It goes without saying that the waveform shape of the output voltage Vop1 shown in FIG. 20(b) may be the same as the waveform shape of the output voltage shown in FIG. 3(b1) or (b2).

[0101] It should be noted that the above-described embodiment and modified examples are merely examples of the present invention, and it is clear that any modifications, changes, or additions made within the spirit of the present invention will fall within the scope of the claims of the present application. [Explanation of symbols]

[0102] 1, 1X, 1Y...High voltage generation unit Ct1, Ct2, Ct3...Current sensors Rd1, Rd2...Resistors 10...Grounding end 11...Output terminal 13, 14, 15, 16...Voltage source 1A...Step-down converter 1B...High frequency inverter 2, 2X, 2Y... Lamp voltage generator 3...Filter 4, 4A, 4B, 4X, 4Y...Auxiliary voltage generator 5, 5X, 5Y...Pulse generation section 6...Control section 7…Three-phase AC power supply 30...Grounding end 31...Output terminal 47...Auxiliary power supply control unit 65...Pulse generating unit control unit 100, 100A, 100B, 100C, 100D...Bias pulse power supply 110...Process control unit 120...Plasma power supply unit for ion source 130...Processing chamber 140...Stage 150...Substrate 160...Plasma 101...Bridge diode 103...Complementary switch 104...Reactor 105...Current transformer 107, 108...Leg 131, 171, 181...Switching elements 401...Bridge rectifier circuit 402a, 402b, 402c, 402aA, 402bA, 402cA, 402aB, 402bB, 402cB...Bidirectional buck-boost converter T41...High frequency switching transformer 102, 105, 106, Cn, Cp, Cb, C41, C42a, C42b, C42c... Capacitors S1, S2, S4, S5...Switching section D3, Da, Db, 41...Diodes Li, Ln...inductors Pr...Plasma reactor Ap…High speed constant current source

Claims

1. A pulse power supply for a plasma etching apparatus outputs a pulse voltage having a waveform including a rising portion where the voltage rises rapidly from a reference voltage to a first voltage at the rising time, a potential gradient portion where the voltage increases linearly from the first voltage to a reference voltage at the falling time, and a falling portion where the voltage falls rapidly from the reference voltage at the falling time to the rising time reference voltage, between a ground terminal and an output terminal of the pulse power supply, in order to apply a pulse bias voltage to a plasma reactor including an object to be processed in a plasma etching apparatus, a) a ramp voltage generating unit that generates a ramp voltage corresponding to a linear voltage increase of the potential gradient unit; b) an auxiliary voltage generating unit including a first voltage source for generating a first auxiliary voltage having a voltage value corresponding to the voltage difference between the rising-time reference voltage and the first voltage, a second voltage source for generating a second auxiliary voltage having a voltage value half the voltage value of the first auxiliary voltage in order to obtain a rising-time resonance initial voltage, a third voltage source for generating a third auxiliary voltage having a voltage value corresponding to the difference between a potential corresponding to half the voltage value of the voltage difference between the falling-time reference voltage and the rising-time reference voltage in order to obtain a falling-time resonance initial voltage which is half the voltage value of the voltage difference, and ground potential, and a fourth voltage source for generating a fourth auxiliary voltage corresponding to the amount of level shift of the pulse voltage waveform in the potential gradient portion; c) a pulse generating unit that generates a voltage waveform corresponding to the rising portion by generating a half-wave resonance using the rising-portion reference voltage and the rising-portion initial voltage in a resonant loop including a capacitor of a plasma reactor, an inductor including wiring between the pulse power supply device and the plasma reactor, and the second voltage source, using a voltage determined by the first auxiliary voltage as the rising-portion reference voltage; subsequently, using a ramp voltage output from the ramp voltage generating unit and level-shifted by the fourth auxiliary voltage, the voltage is further increased over time from the first voltage, which is the end point of the rising portion, to form a voltage waveform corresponding to the potential gradient portion; and then, using an inductor including the capacitor, the inductor, the third voltage source, and an inductor formed by a coil added as necessary, by generating a half-wave resonance using the falling-portion reference voltage and the falling-portion initial voltage in a resonant loop including the capacitor, the inductor, the third voltage source, and an inductor formed by a coil added as necessary, the pulse generating unit generates a half-wave resonance using the falling-portion reference voltage and the falling-portion initial voltage in a resonant loop including the capacitor, the inductor, the third voltage source, and an inductor formed by an additional coil as necessary; A pulse power supply device for a plasma etching apparatus comprising:

2. A pulse voltage generation method for a plasma etching apparatus, for applying a pulse bias voltage to a plasma reactor including a processing object in a plasma etching apparatus, comprising: a holding section for maintaining a predetermined rise-time reference voltage between a ground terminal and an output terminal of a pulse power supply; a rise section in which the voltage rises rapidly from the rise-time reference voltage to a first voltage; a potential ramp section in which the voltage increases linearly from the first voltage to a fall-time reference voltage; and a fall section in which the voltage falls rapidly from the fall-time reference voltage to the rise-time reference voltage, the method includes a plurality of steps of selectively coupling to the output terminal a ramp voltage that increases with the lapse of time, a first DC voltage corresponding to a voltage difference between the rising reference voltage and the first voltage, a second DC voltage corresponding to half the voltage difference between the rising reference voltage and the first voltage, and a third DC voltage corresponding to a difference between a potential corresponding to half the voltage difference between the falling reference voltage and the rising reference voltage and ground potential, a first step of coupling the first DC voltage to the output terminal and holding the first DC voltage across a capacitor of a plasma reactor as a load, thereby maintaining a voltage at the output terminal at a level corresponding to the rise-time reference voltage; a second step following the first step of coupling the second DC voltage to the output terminal, and causing a current to flow by half-wave resonance using a rise-time resonance initial voltage corresponding to a voltage difference between the rise-time reference voltage and the second DC voltage in a resonance loop including at least the capacitor and an inductor including a wiring between the pulse power supply device and a plasma reactor, thereby increasing the voltage at the output terminal from the rise-time reference voltage; a third step of coupling the ramp voltage to the output terminal when the voltage at the output terminal reaches a first voltage by the second step, and further increasing the voltage at the output terminal over time; a fourth step of coupling the third DC voltage to the output terminal after the voltage at the output terminal has risen to the falling-time reference voltage, and causing a current to flow by half-wave resonance in a resonance loop including at least the capacitor and the inductor, the current utilizing a falling-time resonance initial voltage, the falling-time reference voltage being half the voltage difference between the falling-time reference voltage and the rising-time reference voltage, thereby causing the voltage at the output terminal to fall from the falling-time reference voltage; A pulse voltage generating method for a plasma etching apparatus comprising:

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