Wafer and semiconductor device

Abstract

To provide a wafer and a semiconductor device capable of improving characteristics.SOLUTION: A wafer includes a substrate and first to fourth layers. The fourth layer includes a plurality of first films including Aly1Ga1-y1 N (0<y1≤1) and a plurality of second films including Aly2Ga1-y2 N (0≤y2<1, and y2<y1). One of the plurality of first films is disposed between one of the plurality of second films and another one of the plurality of second films. One of the plurality of second films is provided between one of the plurality of first films and another one of the plurality of first films. A second carbon concentration in the second layer is higher than a first carbon concentration in the first layer. A third carbon concentration in the third layer is lower than the second carbon concentration. A fourth carbon concentration in the fourth layer is lower than the second carbon concentration.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] Embodiments of the present invention relate to wafers and semiconductor devices.

Background Art

[0002] For example, in a semiconductor device based on a wafer containing nitrides, improvement in characteristics is desired.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] Embodiments of the present invention provide a wafer and a semiconductor device capable of improving characteristics.

Means for Solving the Problems

[0005] According to an embodiment of the present invention, a wafer includes a substrate, a first layer containing Al z1 Ga 1-z1 N (0 < z1 < 1), a second layer containing Al z2 Ga 1-z2 N (0 < z2 < z1), a third layer containing Al z3 Ga 1-z3 N (0 < z3 < z2), and a fourth layer. The first layer is between the substrate and the fourth layer in a first direction. The second layer is between the first layer and the fourth layer in the first direction. The third layer is between the second layer and the fourth layer in the first direction. The fourth layer includes a plurality of first films containing Al y1 Ga 1-y1 N (0 < y1 ≤ 1), and Al y2 Ga 1-y2A plurality of second films including N(0≦y2<1, y2<y1), are included. One of the plurality of first films is provided between one of the plurality of second films and another one of the plurality of second films in the first direction. One of the plurality of second films is provided between one of the plurality of first films and another one of the plurality of first films in the first direction. The second carbon concentration in the second layer is higher than the first carbon concentration in the first layer. The third carbon concentration in the third layer is lower than the second carbon concentration. The fourth carbon concentration in the fourth layer is lower than the second carbon concentration.

Brief Description of the Drawings

[0006] [Figure 1] FIG. 1 is a schematic cross-sectional view illustrating a wafer according to the first embodiment. [Figure 2] FIGS. 2(a) and 2(b) are schematic views illustrating a wafer according to the first embodiment. [Figure 3] FIG. 3 is a graph illustrating the characteristics of a wafer. [Figure 4] FIG. 4 is a graph illustrating the characteristics of a wafer. [Figure 5] FIG. 5 is a graph illustrating the characteristics of a wafer. [Figure 6] FIG. 6 is a schematic cross-sectional view illustrating a semiconductor device according to the second embodiment. [Figure 7] FIG. 7 is a schematic cross-sectional view illustrating a semiconductor device according to the second embodiment.

Embodiments for Carrying Out the Invention

[0007] Hereinafter, each embodiment of the present invention will be described with reference to the drawings. The drawings are schematic or conceptual, and the relationships between the thickness and width of each part, the ratio of the sizes between parts, etc. are not necessarily the same as those in reality. Even when representing the same part, the dimensions and ratios may be represented differently in the drawings. In the present specification and each figure, the same elements as those described above with respect to the previously shown figures are denoted by the same reference numerals, and detailed descriptions thereof are omitted as appropriate.

[0008] (First Embodiment) FIG. 1 is a schematic cross-sectional view illustrating a wafer according to the first embodiment. FIGS. 2(a) and 2(b) are schematic views illustrating a wafer according to the first embodiment. As shown in FIG. 1, the wafer 210 according to the embodiment includes a substrate 60, a first layer 61, a second layer 62, a third layer 63, and a fourth layer 64.

[0009] The first layer 61 contains Al z1 Ga 1-z1 N (0 < z1 < 1). The second layer 62 contains Al z2 Ga 1-z2 N (0 < z2 < z1). The third layer 63 contains Al z3 Ga 1-z3 N (0 < z3 < z2).

[0010] The first layer 61 is located between the substrate 60 and the fourth layer 64 in the first direction D1.

[0011] The first direction D1 is the Z-axis direction. One direction perpendicular to the Z-axis direction is the X-axis direction. The direction perpendicular to the Z-axis direction and the X-axis direction is the Y-axis direction. The substrate 60, the first layer 61, the second layer 62, the third layer 63, and the fourth layer 64 are layered along the X-Y plane.

[0012] The second layer 62 is located between the first layer 61 and the fourth layer 64 in the first direction D1. The third layer 63 is located between the second layer 62 and the fourth layer 64 in the first direction D1.

[0013] The fourth layer 64 includes a plurality of first films 64a and a plurality of second films 64b. The plurality of first films 64a contain Al y1 Ga 1-y1 N (0 < y1 ≤ 1). The plurality of second films 64b contain Al y2 Ga 1-y2 N (0 ≤ y2 < 1, y2 < y1).

[0014] One of the plurality of first films 64a is provided between one of the plurality of second films 64b and another one of the plurality of second films 64b in the first direction D1. One of the plurality of second films 64b is provided between one of the plurality of first films 64a and another one of the plurality of first films 64a in the first direction D1. For example, the first films 64a and the second films 64b may be arranged alternately.

[0015] The plurality of first films 64a contain Al y1 Ga 1-y1 N (0 < y1 ≤ 1). The plurality of second films 64b contain Al y2 Ga 1-y2 N (0 ≤ y2 < 1, y2 < y1). For example, the plurality of first films 64a may be AlGaN layers or AlN layers. For example, the plurality of second films 64b may be AlGaN layers or GaN layers. The fourth layer 64 is, for example, a superlattice layer.

[0016] For example, the second layer 62 is formed on the first layer 61. The third layer 63 is formed on the second layer 62. The fourth layer 64 is formed on the third layer 63. The first layer 61, the second layer 62, the third layer 63, and the fourth layer 64 contain, for example, crystals.

[0017] For example, the third layer 63 may be in contact with the second layer 62 and the fourth layer 64.

[0018] FIG. 2(a) and FIG. 2(b) illustrate the carbon concentration profiles in the wafer 210. The horizontal axis in FIGS. 2(a) and 2(b) is the position pZ in the Z-axis direction. The vertical axis in FIG. 2(a) is the carbon concentration CC. The vertical axis in FIG. 2(b) is the Al composition ratio C(Al).

[0019] As shown in FIG. 2(a), the second carbon concentration C2 in the second layer 62 is higher than the first carbon concentration C1 in the first layer 61. The third carbon concentration C3 in the third layer 63 is lower than the second carbon concentration C2. The fourth carbon concentration C4 in the fourth layer 64 is lower than the second carbon concentration C2.

[0020] In the embodiment, the first carbon concentration C1 is low in the first layer 61. This allows high flatness to be obtained in the first layer 61. For example, high crystal quality can be obtained in a layer formed on the first layer 61.

[0021] In the embodiment, the second carbon concentration C2 is high in the second layer 62. This allows, for example, a semiconductor device based on the wafer 210 to have a high breakdown voltage.

[0022] In the embodiment, the fourth carbon concentration C4 in the fourth layer 64 is lower than the second carbon concentration C2. This allows, for example, leakage current to be suppressed in a semiconductor device based on the wafer 210.

[0023] In the embodiment, the third carbon concentration C3 in the third layer 63 is lower than the second carbon concentration C2. This, for example, suppresses current collapse in a semiconductor device based on the wafer 210. For example, leakage current is suppressed.

[0024] According to the embodiment, it is possible to provide a wafer for a semiconductor device whose characteristics can be improved.

[0025] In the embodiment, the third carbon concentration C3 may be lower than the fourth carbon concentration C4. This, for example, suppresses current collapse. For example, stable operation is easily obtained. Fluctuations in on-resistance can be suppressed.

[0026] For example, the fourth carbon concentration C4 may be higher than the first carbon concentration C1. For example, the third carbon concentration C3 may be higher than the first carbon concentration C1. A low first carbon concentration C1 can result in higher crystal quality. For example, high flatness can be easily obtained.

[0027] For example, the second carbon concentration C2 may be 10 times or more and 500 times or less than the first carbon concentration C1. For example, the second carbon concentration C2 may be 2 times or more and 10 times or less than the fourth carbon concentration C4. For example, the second carbon concentration C2 may be 2 times or more and 15 times or less than the third carbon concentration C3.

[0028] In the embodiment, the composition ratio z1 may be, for example, 0.6 or more and less than 0.9. The composition ratio z2 may be, for example, 0.3 or more and less than 0.6. The composition ratio z3 may be, for example, 0.1 or more and 0.3 or less. The composition ratio y1 may be, for example, 0.8 or more and 1 or less. The composition ratio y2 may be, for example, 0 or more and 0.4 or less.

[0029] As shown in FIG. 1 , the first layer 61 has a first thickness t1 in the first direction D1. The second layer 62 has a second thickness t2 in the first direction D1. The third layer 63 has a third thickness t3 in the first direction D1. The fourth layer 64 has a fourth thickness t4 in the first direction D1. In this embodiment, the fourth thickness t4 is preferably smaller than the sum of the first thickness t1, the second thickness t2, and the third thickness t3. The thin fourth thickness t4 of the fourth layer 64, which includes a plurality of first films 64a and a plurality of second films 64b, allows for high manufacturing efficiency. For example, this facilitates short-time manufacturing.

[0030] In an embodiment, the fourth thickness t4 may be less than the sum of the second thickness t2 and the third thickness t3, which facilitates more efficient manufacturing.

[0031] As already explained, for example, the third layer 63 may be in contact with the second layer 62 and the fourth layer 64. In this example, the second layer 62 is in contact with the first layer 61. In an embodiment, the Al composition ratio in the first layer 61 may decrease in the direction from the substrate 60 to the second layer 62.

[0032] 1 , the wafer 210 may further include a fifth layer 65. The fifth layer 65 is provided between the base 60 and the first layer 61 in the first direction D1. For example, the fifth layer 65 contacts the base 60 and the first layer 61. For example, the fifth layer 65 is formed on the base 60. For example, the first layer 61 is formed on the fifth layer 65.

[0033] The fifth layer 65 is Al z5 Ga 1-z5It includes N(z3 < z5 ≤ 1). The composition ratio z5 is, for example, 0.9 or more and 1 or less. The composition ratio z5 may be 1. The fifth layer 65 may be, for example, an AlN layer. For example, the fifth carbon concentration C5 in the fifth layer 65 is lower than the second carbon concentration C2. The fifth carbon concentration C5 may be substantially the same as the first carbon concentration C1.

[0034] For example, the substrate 60 may be a silicon substrate. The substrate 60 may contain GaN or SiC, etc. When the substrate 60 contains silicon, melt-back etching is suppressed, for example, by the fifth layer 65.

[0035] In an embodiment, the concentration of Fe in the fifth layer 65 is 1×10 17 cm -3 or less. The concentrations of Fe in the first layer 61, the second layer 62, the third layer 63, and the fourth layer 64 may be 1×10 17 cm -3 or less. These layers may not substantially contain Fe. For example, it is easy to obtain high crystal quality. For example, it is easy to obtain high carrier mobility.

[0036] In an embodiment, for example, the first thickness t1 may be 500 nm or more and less than 1200 nm. The second thickness t2 may be 500 nm or more and less than 1200 nm. The third thickness t3 may be 500 nm or more and less than 1200 nm. Or, the first thickness t1 may be 300 nm or more and less than 800 nm. The second thickness t2 may be 300 nm or more and less than 800 nm. The third thickness t3 may be 300 nm or more and less than 800 nm. The fourth thickness t4 may be 300 nm or more and less than 800 nm. The fifth thickness t5 may be, for example, 100 nm or more and 400 nm or less.

[0037] In an embodiment, the thickness ta3 along one first direction D1 of a plurality of first films 64a is, for example, 3 nm or more and 10 nm or less. The thickness tb3 along one first direction D1 of a plurality of second films 64b is, for example, 15 nm or more and 35 nm or less. The number of a plurality of first films 64a may be, for example, 17 or more and 40 or less. <​​1, the wafer 210 may further include a semiconductor member 10M. The fourth layer 64 is provided between the third layer 63 and the semiconductor member 10M in the first direction D1. For example, the third layer 63 is formed on the second layer 62. The fourth layer 64 is provided on the third layer 63. The semiconductor member 10M is formed on the fourth layer 64.

[0039] The semiconductor member 10M includes, for example, Ga and nitrogen. The semiconductor member 10M includes a crystal. The semiconductor member 10M includes, for example, GaN. The semiconductor member 10M may function as a functional layer of a semiconductor device.

[0040] For example, the first carbon concentration C1 is 1×10 17 cm -3 Over 2×10 18 cm -3 For example, the second carbon concentration C2 is preferably less than 2×10 19 cm -3 Over 2×10 20 cm -3 For example, the third carbon concentration is preferably 1×10 18 cm -3 7x10 or more 18 cm -3 For example, the quaternary carbon concentration is preferably less than 5×10 18 cm -3 Over 2×10 19 cm -3 It is preferable that it is less than 10 ...

[0041] As shown in FIG. 2(b), in a structure including the fifth layer 65, the first layer 61, the second layer 62, and the third layer 63, the Al composition ratio C(Al) may decrease in the direction from the substrate 60 to the fourth layer 64.

[0042] Examples of the characteristics of the wafer 210 will now be described. FIG. 3 is a graph illustrating the characteristics of the wafer. The horizontal axis of FIG. 3 is the first carbon concentration C1 in the first layer 61. The vertical axis is the number Np1 of pits per unit area on the surface of the wafer 210. As can be seen from FIG. 3, when the first carbon concentration C1 is low, the number Np1 of pits is small. As shown in FIG. 3, when the first carbon concentration C1 is 3×10 18 cm -3 Below this, the number of pits Np1 drops sharply. 18 cm -3 In the following, the number of pits Np1 is further reduced. 17 cm -3 Over 1.5 x 10 18 cm -3 It is preferable that the surface roughness is 1×10 or less. Pits can be suppressed. For example, high flatness can be obtained. 17 cm -3 Over 2×10 18 cm -3 Less than is fine.

[0043] FIG. 4 is a graph illustrating the characteristics of the wafer. 4, the horizontal axis represents the second carbon concentration C2 in the second layer 62. The vertical axis represents the pinch-off voltage V1. The pinch-off voltage V1 is the voltage at which the drain current in the semiconductor device based on the wafer 210 decreases rapidly. The pinch-off voltage V1 corresponds to, for example, the pitch-off voltage of a two-dimensional electron gas.

[0044] As can be seen from Figure 4, the second carbon concentration C2 is 3 × 10 19 cm -3 Over 1.2 x 10 20 cm -3 A high pinch-off voltage V1 can be obtained in the following range. Taking into account the error, the second carbon concentration C2 is 2 × 10 19 cm -3 Over 2×10 20 cm -3 It is preferable that the following conditions are satisfied: For example, a high breakdown voltage can be obtained; and a stable operation can be obtained.

[0045] FIG. 5 is a graph illustrating the characteristics of the wafer. The horizontal axis of FIG. 5 represents the fourth carbon concentration C4 in the fourth layer 64. The vertical axis represents the leakage current density J1. The leakage current density J1 is the density of the current flowing between the electrode provided on the semiconductor member 10M and the base body 60. As can be seen from FIG. 5, when the fourth carbon concentration C4 is 5×10 18 cm -3 Over 1.6 x 10 19 cm -3 A low leakage current density J1 can be obtained in the following range: In the embodiment, the fourth carbon concentration C4 is 5×10 18 cm -3 In the embodiment, the fourth carbon concentration C4 is preferably 5×10 18 cm -3 Over 2×10 19 cm -3 In an embodiment, the fourth carbon concentration C4 may be less than 5×10 18 cm -3 Over 1.6 x 10 19 cm -3 The following is also fine.

[0046] (Second embodiment) The second embodiment relates to a semiconductor device, which includes the wafer 210 described in relation to the first embodiment and variations thereof.

[0047] FIG. 6 is a schematic cross-sectional view illustrating the semiconductor device according to the second embodiment. As shown in FIG. 6, the semiconductor device 110 according to the embodiment includes a wafer 210 according to the first embodiment, a semiconductor member 10M, a first electrode 51, a second electrode 52, and a third electrode 53.

[0048] The semiconductor member 10M includes, for example, a first semiconductor layer 10 and a second semiconductor layer 20. The first semiconductor layer 10 is made of Al x1 Ga 1-x1 The second semiconductor layer 20 contains Al x2 Ga 1-x2It includes N(0 < x2 ≤ 1, x1 < x2). The composition ratio x1 may be, for example, 0 or more and 0.15 or less. The first semiconductor layer 10 is, for example, a GaN layer. The composition ratio x2 may be, for example, more than 0.15 and 0.3 or less. The second semiconductor layer 20 is, for example, an AlGaN layer.

[0049] The first semiconductor layer 10 is provided between the fourth layer 64 and the second semiconductor layer 20.

[0050] The second direction D2 from the first electrode 51 to the second electrode 52 intersects the first direction D1. The second direction D2 is, for example, the X-axis direction. The position of the third electrode 53 in the second direction D2 is between the position of the first electrode 51 in the second direction D2 and the position of the second electrode 52 in the second direction D2.

[0051] The second semiconductor layer 20 includes a first semiconductor portion 21 and a second semiconductor portion 22. The direction from the first semiconductor portion 21 to the second semiconductor portion 22 is along the second direction D2. The first electrode 51 is electrically connected to the first semiconductor portion 21. The second electrode 52 is electrically connected to the second semiconductor portion 22.

[0052] The current flowing between the first electrode 51 and the second electrode 52 is controlled by the potential of the third electrode 53. The potential of the third electrode 53 may be, for example, a potential based on the potential of the first electrode 51. The first electrode 51 functions as, for example, a source electrode. The second electrode 52 functions as a drain electrode. The third electrode 53 functions as a gate electrode. The semiconductor device 110 is, for example, a transistor.

[0053] The first semiconductor layer 10 includes a region facing the second semiconductor layer 20. A carrier region is formed in this region. The carrier region is, for example, a two-dimensional electron gas. The semiconductor device 110 is, for example, a HEMT (High Electron Mobility Transistor).

[0054] In the semiconductor device 110 according to the embodiment, for example, a high breakdown voltage can be obtained. For example, a low leakage current can be obtained. For example, a low on-resistance can be obtained due to high crystallinity. For example, a large on-current can be easily obtained. According to the embodiment, a semiconductor device capable of improving characteristics can be provided.

[0055] 6, in this example, at least a portion of the third electrode 53 is provided between the first semiconductor portion 21 and the second semiconductor portion 22 in the second direction D2. The third electrode 53 is, for example, a recessed gate electrode. For example, a high threshold voltage can be obtained. For example, a normally-off operation can be obtained.

[0056] For example, the first semiconductor layer 10 includes a first partial region 10a, a second partial region 10b, a third partial region 10c, a fourth partial region 10d, and a fifth partial region 10e. The direction from the first partial region 10a to the first electrode 51 is along the first direction D1. The direction from the second partial region 10b to the second electrode 52 is along the first direction D1. The direction from the third partial region 10c to the third electrode 53 is along the first direction D1.

[0057] The position of the fourth partial region 10d in the second direction D2 is between the position of the first partial region 10a in the second direction D2 and the position of the third partial region 10c in the second direction D2. The position of the fifth partial region 10e in the second direction D2 is between the position of the third partial region 10c in the second direction D2 and the position of the second partial region 10b in the second direction D2.

[0058] The direction from the fourth partial region 10d to the first semiconductor portion 21 is along the first direction D1. The direction from the fifth partial region 10e to the second semiconductor portion 22 is along the first direction D1. In this example, a portion of the third electrode 53 is located between the fourth partial region 10d and the fifth partial region 10e in the second direction D2. A high threshold voltage is obtained. For example, normally-off operation is stably achieved.

[0059] As shown in FIG. 6, the semiconductor device 110 may further include a first insulating member 41. The first insulating member 41 includes a first insulating portion 41p. The first insulating portion 41p is provided between the third electrode 53 and the semiconductor member 10M. The first insulating portion 41p functions as, for example, a gate insulating film.

[0060] As shown in FIG. 6, the semiconductor member 10M may further include an intermediate layer 15. The intermediate layer 15 is provided between the fourth layer 64 and the first semiconductor layer 10. The intermediate layer 15 contains, for example, Al x3 Ga 1-x3 N (0 ≦ x1 < 1, x3 < x2). The composition ratio x3 may be, for example, 0 or more and 0.25 or less. The intermediate layer 15 is, for example, a GaN layer.

[0061] For example, the concentration of carbon in the intermediate layer 15 is higher than the concentration of carbon in the first semiconductor layer 10. Or, the intermediate layer 15 contains carbon and the first semiconductor layer 10 does not contain carbon. The intermediate layer 15 containing carbon makes it easier to obtain, for example, high carrier mobility.

[0062] FIG. 7 is a schematic cross-sectional view illustrating a semiconductor device according to the second embodiment. As shown in FIG. 7, the semiconductor device 111 according to the embodiment includes the wafer 210, the semiconductor member 10M, the first electrode 51, the second electrode 52, and the third electrode 53 according to the first embodiment. In the semiconductor device 111, the third electrode 53 does not overlap the second semiconductor layer 20 in the second direction D2. The configuration of the semiconductor device 111 except this may be the same as that of the semiconductor device 110.

[0063] In the semiconductor device 111, for example, normal ion operation can be obtained. In the semiconductor device 111, the first insulating member 41 may be omitted. The semiconductor device 111 can be used, for example, as a high-frequency switching element.

[0064] In an embodiment, information regarding the shape of the nitride region, etc. can be obtained, for example, by electron microscope observation or the like. Information regarding the composition and element concentration in the nitride region can be obtained, for example, by EDX (Energy Dispersive X-ray Spectroscopy), or SIMS (Secondary Ion Mass Spectrometry) or the like. Information regarding the composition in the nitride region may be obtained, for example, by reciprocal lattice space mapping or the like.

[0065] The embodiment may include the following technical solutions. (Technical Solution 1) A substrate, Al z1 Ga 1-z1 A first layer containing N (0 < z1 < 1), Al z2 Ga 1-z2 A second layer containing N (0 < z2 < z1), Al z3 Ga 1-z3 A third layer containing N (0 < z3 < z2), A fourth layer, and comprising, The first layer is between the substrate and the fourth layer in a first direction, The second layer is between the first layer and the fourth layer in the first direction, The third layer is between the second layer and the fourth layer in the first direction, The fourth layer Al y1 Ga 1-y1 A plurality of first films containing N (0 < y1 ≤ 1), Al y2 Ga 1-y2 A plurality of second films containing N (0 ≤ y2 < 1, y2 < y1), and including, One of the plurality of first films is provided between one of the plurality of second films and another one of the plurality of second films in the first direction, The one of the plurality of second films is provided between the one of the plurality of first films and another one of the plurality of first films in the first direction, the second carbon concentration in the second layer is higher than the first carbon concentration in the first layer; a third carbon concentration in the third layer is lower than the second carbon concentration; A wafer, wherein the fourth carbon concentration in the fourth layer is lower than the second carbon concentration.

[0066] (Technical proposal 2) The wafer according to Technical Scheme 1, wherein the third carbon concentration is lower than the fourth carbon concentration.

[0067] (Technical proposal 3) The wafer according to Technical Scheme 1 or 2, wherein the fourth carbon concentration is higher than the first carbon concentration.

[0068] (Technical proposal 4) 4. The wafer according to any one of Technical Schemes 1 to 3, wherein the second carbon concentration is 10 times or more and 500 times or less than the first carbon concentration.

[0069] (Technical proposal 5) 5. The wafer according to any one of Technical Schemes 1 to 4, wherein the second carbon concentration is two to ten times the fourth carbon concentration.

[0070] (Technical proposal 6) the first layer has a first thickness in the first direction; the second layer has a second thickness in the first direction; the third layer has a third thickness in the first direction; the fourth layer has a fourth thickness in the first direction; 6. The wafer according to any one of Technical Schemes 1 to 5, wherein the fourth thickness is smaller than the sum of the first thickness, the second thickness, and the third thickness.

[0071] (Technical proposal 7) A wafer according to Technical Solution 6, wherein the fourth thickness is smaller than the sum of the second thickness and the third thickness.

[0072] (Technical proposal 8) The third layer is the wafer according to any one of Technical Solutions 1 to 7, which is in contact with the second layer and the fourth layer.

[0073] (Technical Solution 9) Al z5 Ga 1-z5 Further includes a fifth layer containing N(z3 < z5 ≤ 1), The fifth layer is the wafer according to any one of Technical Solutions 1 to 8, which is provided between the substrate and the first layer.

[0074] (Technical Solution 10) In the wafer according to Technical Solution 9, z5 is 0.9 or more and 1 or less.

[0075] (Technical Solution 11) The concentration of Fe in the fifth layer is 1×10 17 cm -3 Less than that in the wafer according to Technical Solution 9 or 10.

[0076] (Technical Solution 12) z1 is 0.6 or more and less than 0.9, z2 is 0.3 or more and less than 0.6, z3 is 0.1 or more and 0.3 or less, y1 is 0.8 or more and 1 or less, y2 is 0 or more and 0.4 or less in the wafer according to any one of Technical Solutions 1 to 11.

[0077] (Technical Solution 13) The concentration of Fe in the first layer, the second layer, the third layer and the fourth layer is 1×10 17 cm -3 Less than that in the wafer according to any one of Technical Solutions 1 to 12.

[0078] (Technical Solution 14) The first carbon concentration is 1×10 17 cm -3 Or more and 2×10 18 cm -3 [[ID=6〕Less than that in the wafer according to any one of Technical Solutions 1 to 13.

[0079] (Technical Proposal 15) The second carbon concentration is 2×10 19 cm -3 or more and 2×10 20 cm -3 or less, the wafer according to any one of Technical Proposals 1 to 14.

[0080] (Technical Proposal 16) The third carbon concentration is 1×10 18 cm -3 or more and 7×10 18 cm -3 less than, the wafer according to any one of Technical Proposals 1 to 15.

[0081] (Technical Proposal 17) The fourth carbon concentration is 5×10 18 cm -3 or more and 2×10 19 cm -3 less than, the wafer according to any one of Technical Proposals 1 to 16.

[0082] (Technical Proposal 18) Further comprising a semiconductor member containing Ga and nitrogen, The fourth layer is provided between the third layer and the semiconductor member in the first direction, the wafer according to any one of Technical Proposals 1 to 17.

[0083] (Technical Proposal 19) The wafer according to any one of Technical Proposals 1 to 17, a semiconductor member, a first electrode, a second electrode, a third electrode, and comprising, The semiconductor member is Al x1 Ga 1-x1 N (0≦x1<1) containing a first semiconductor layer, Al x2 Ga 1-x2 N (0<x2≦1, x1<x2) containing a second semiconductor layer, and containing, the first semiconductor layer is provided between the fourth layer and the second semiconductor layer, a second direction from the first electrode to the second electrode intersects with the first direction; a position of the third electrode in the second direction is between a position of the first electrode in the second direction and a position of the second electrode in the second direction; the second semiconductor layer includes a first semiconductor portion and a second semiconductor portion; a direction from the first semiconductor portion to the second semiconductor portion is along the second direction; the first electrode is electrically connected to the first semiconductor portion; The second electrode is electrically connected to the second semiconductor portion.

[0084] (Technical proposal 20) A semiconductor device described in Technical Proposal 19, wherein at least a portion of the third electrode is provided between the first semiconductor portion and the second semiconductor portion in the second direction.

[0085] According to the embodiment, it is possible to provide a wafer and a semiconductor device that can improve characteristics.

[0086] In this specification, "electrically connected" includes a state in which multiple conductors are physically in contact with each other and a current flows between these multiple conductors. "Electrically connected" also includes a state in which multiple conductors are connected to each other and a current flows between these multiple conductors.

[0087] The embodiments of the present invention have been described above with reference to specific examples. However, the present invention is not limited to these specific examples. For example, the specific configurations of the elements included in the wafer and semiconductor device, such as the substrate, layers, and electrodes, are within the scope of the present invention as long as a person skilled in the art can implement the present invention in a similar manner and obtain similar effects by appropriately selecting them from known ranges.

[0088] Furthermore, any combination of two or more elements of each specific example within the scope of technical feasibility is also included within the scope of the present invention as long as it includes the gist of the present invention.

[0089] In addition, all wafers and semiconductor devices that can be implemented by a person skilled in the art by appropriately modifying the design based on the wafers and semiconductor devices described above as embodiments of the present invention also fall within the scope of the present invention, as long as they include the gist of the present invention.

[0090] In addition, within the scope of the concept of the present invention, a person skilled in the art may come up with various modifications and alterations, and these modifications and alterations are also considered to fall within the scope of the present invention.

[0091] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as defined in the claims. [Explanation of symbols]

[0092] 10, 20: first and second semiconductor layers, 10M: semiconductor member, 10a to 10e: first to fifth partial regions, 15: intermediate layer, 21, 22: first and second semiconductor portions, 41: first insulating member, 41p: first insulating portion, 51 to 53: first to third electrodes, 60: base, 61 to 65: first to fifth layers, 64a, 64b: first and second films, 110, 111: semiconductor device, 210: wafer, C1 to C5: first to fifth carbon concentrations, C(Al): composition ratio, CC: carbon concentration, D1, D2: first and second directions, pZ: position, t1 to t5: first to fifth thicknesses, ta3, tb3: thickness

Claims

1. a substrate; Al ｚ１ Ga １－ｚ１ a first layer including N (0<z1<1); Al ｚ２ Ga １－ｚ２ a second layer including N (0<z2<z1); Al ｚ３ Ga １－ｚ３ a third layer including N (0<z3<z2); The fourth layer, Equipped with the first layer is between the substrate and the fourth layer in a first direction; the second layer is between the first layer and the fourth layer in the first direction; the third layer is located between the second layer and the fourth layer in the first direction; The fourth layer is Al ｙ１ Ga １－ｙ１ a plurality of first films including N (0<y1≦1); Al ｙ２ Ga １－ｙ２ a plurality of second films including N (0≦y<1, y<y); Including, one of the plurality of first films is provided between one of the plurality of second films and another of the plurality of second films in the first direction; the one of the plurality of second films is provided between the one of the plurality of first films and another one of the plurality of first films in the first direction, the second carbon concentration in the second layer is higher than the first carbon concentration in the first layer; a third carbon concentration in the third layer is lower than the second carbon concentration; A wafer, wherein the fourth carbon concentration in the fourth layer is lower than the second carbon concentration.

2. The wafer according to claim 1 , wherein the third carbon concentration is lower than the fourth carbon concentration.

3. The wafer according to claim 1 , wherein the fourth carbon concentration is higher than the first carbon concentration.

4. the first layer has a first thickness in the first direction; the second layer has a second thickness in the first direction; the third layer has a third thickness in the first direction; the fourth layer has a fourth thickness in the first direction; 4. The wafer according to claim 1, wherein the fourth thickness is smaller than the sum of the first thickness, the second thickness, and the third thickness.

5. The wafer of claim 4 , wherein the fourth thickness is less than the sum of the second thickness and the third thickness.

6. The wafer of claim 1 , wherein the third layer contacts the second layer and the fourth layer.

7. Al ｚ５ Ga １－ｚ５ N (z3<z5≦1), The wafer of claim 1 , wherein the fifth layer is provided between the substrate and the first layer.

8. The concentration of Fe in the first layer, the second layer, the third layer, and the fourth layer is 1×10 １７ cm －３ The wafer of claim 1 , wherein the thickness is less than 100 nm.

9. The wafer according to claim 1; A semiconductor member; A first electrode; A second electrode; A third electrode; Equipped with The semiconductor member is Al ｘ１ Ga １－ｘ１ a first semiconductor layer including N (0≦x1<1); Al ｘ２ Ga １－ｘ２ a second semiconductor layer including N (0<x2≦1, x1<x2); Including, the first semiconductor layer is provided between the fourth layer and the second semiconductor layer, a second direction from the first electrode to the second electrode intersects with the first direction; a position of the third electrode in the second direction is between a position of the first electrode in the second direction and a position of the second electrode in the second direction; the second semiconductor layer includes a first semiconductor portion and a second semiconductor portion; a direction from the first semiconductor portion to the second semiconductor portion is along the second direction; the first electrode is electrically connected to the first semiconductor portion; The second electrode is electrically connected to the second semiconductor portion.

10. The semiconductor device according to claim 9 , wherein at least a portion of the third electrode is provided between the first semiconductor portion and the second semiconductor portion in the second direction.

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