Manufacturing method of semiconductor device

Abstract

To provide a semiconductor device in which reliability and manufacturing yield are improved, and a manufacturing method thereof.SOLUTION: A manufacturing method of a semiconductor device comprises: preparing a substrate that has a processed film; forming a recessed part in the processed film by performing first etching by means of plasma using a gas containing hydrogen fluoride; forming a first protective layer containing nitrogen, hydrogen and fluorine by supplying a gas containing nitrogen and hydrogen in the recessed part in a state where high-frequency power is not applied; and performing second etching by means of the plasma in the recessed part in which the first protective layer is formed.SELECTED DRAWING: Figure 4E

Description

[Technical Field]

[0001] TECHNICAL FIELD An embodiment of the present disclosure relates to a method for manufacturing a semiconductor device. [Background technology]

[0002] Semiconductor packages using NAND flash memory as a semiconductor device are known. To increase the capacity of such NAND flash memory, 3D NAND flash memory, which has a configuration in which many memory cells are stacked, has been put into practical use. In such stacked 3D NAND flash memory, the number of stacked layers continues to increase to achieve high integration, and a corresponding technology for forming high aspect ratio patterns (holes and trenches) is required. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] US Patent Application Publication No. 2020 / 0006079 [Patent Document 2] US Patent Application Publication No. 2022 / 0068659 [Patent Document 3] US Patent Application Publication No. 2023 / 0128868 Summary of the Invention [Problem to be solved by the invention]

[0004] Embodiments according to the present disclosure provide a method for manufacturing a semiconductor device with improved reliability and manufacturing yield. [Means for solving the problem]

[0005] A method for manufacturing a semiconductor device according to one embodiment includes preparing a substrate having a film to be processed, forming a recess in the film to be processed by performing a first etching process using a plasma containing a gas containing hydrogen fluoride, forming a first protective layer containing nitrogen, hydrogen, and fluorine by supplying a gas containing nitrogen and hydrogen to the recess without applying high-frequency power, and performing a second etching process using the plasma in the recess where the first protective layer has been formed. [Brief explanation of the drawings]

[0006] [Figure 1] 1 is a perspective view showing an overall configuration of a semiconductor device according to an embodiment; [Figure 2] 1 is a cross-sectional view showing an overall configuration of a semiconductor device according to an embodiment; [Figure 3] 1 is a cross-sectional view showing a configuration of a memory cell of a semiconductor device according to an embodiment. [Figure 4A] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment. [Figure 4B] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment. [Figure 4C] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment. [Figure 4D] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment. [Figure 4E] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment. [Figure 5] 1A to 1C are diagrams illustrating a method for manufacturing a semiconductor device according to an embodiment. [Figure 6A] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment. [Figure 6B] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment. [Figure 7] 1A to 1C are diagrams illustrating a method for manufacturing a semiconductor device according to an embodiment. [Figure 8A] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment. [Figure 8B]1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment. [Figure 9] 1A to 1C are diagrams illustrating a method for manufacturing a semiconductor device according to an embodiment. [Figure 10] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment. [Figure 11] 1A to 1C are diagrams illustrating a method for manufacturing a semiconductor device according to an embodiment. [Figure 12] 1 is a schematic diagram showing a configuration of a semiconductor manufacturing apparatus according to an embodiment; DETAILED DESCRIPTION OF THE INVENTION

[0007] The semiconductor device manufacturing method according to this embodiment will be described in detail below with reference to the drawings. In the following description, elements having substantially the same functions and configurations are designated by the same reference numerals or the same reference numerals followed by an alphabetical character, and will be described again only when necessary. The following embodiments exemplify devices and methods for embodying the technical ideas of this embodiment. Various modifications can be made to one embodiment without departing from the spirit of the invention. These embodiments and their variations are included within the scope of the invention described in the claims and their equivalents.

[0008] In order to clarify the description, the drawings may show the width, thickness, shape, etc. of each part schematically compared to the actual embodiment, but these are merely examples and do not limit the interpretation of the present invention. In this specification and each drawing, elements having the same functions as those explained with reference to the previous drawings may be assigned the same reference numerals, and duplicate explanations may be omitted.

[0009] In each embodiment of the present invention, the direction from the substrate toward the memory cell is referred to as "upward." Conversely, the direction from the memory cell toward the substrate is referred to as "downward." While the terms "upward" and "downward" are used for convenience of explanation, the vertical relationship between the substrate and the memory cell may be reversed from that shown in the drawings. In addition, in the following explanation, the expression "memory cell on a substrate" merely describes the vertical relationship between the substrate and the memory cell as described above, and other components may be disposed between the substrate and the memory cell.

[0010] In this specification, unless otherwise specified, an expression such as "α includes A, B, or C" does not exclude the case where α includes multiple combinations of A to C. Furthermore, these expressions do not exclude the case where α includes other elements.

[0011] The following embodiments can be combined with each other unless a technical contradiction occurs.

[0012] In the following embodiments, a memory cell array will be described as an example of a semiconductor device, but the technology of the present disclosure can be applied to semiconductor devices other than memory cell arrays (for example, CPUs, displays, interposers, etc.).

[0013] In addition, in the following embodiments, no particular reference is made to the configuration of the peripheral (CMOS) circuit. In the semiconductor device, the CMOS circuit may be partitioned in another region on the semiconductor substrate. In addition, in the semiconductor device, the CMOS circuit chip and the memory cell array chip may be formed separately on different semiconductor substrates. In this case, the upper surfaces of the memory cell array chip and the CMOS circuit chip may be bonded together. In addition, in the semiconductor device, the memory cell array may be formed integrally on the CMOS circuit chip.

[0014] First Embodiment [Configuration of semiconductor device] The configuration of the semiconductor device according to this embodiment will be described with reference to Fig. 1. Fig. 1 is a schematic perspective view showing the arrangement of each element of a semiconductor device 1 according to this embodiment.

[0015] 1, two directions parallel to the main surface of the substrate 10 and perpendicular to each other are called the X direction and the Y direction, and a plane parallel to the main surface of the substrate 10 is called the XY plane. The direction perpendicular to both the X direction and the Y direction is called the Z direction (stacking direction).

[0016] As shown in FIG. 1, the semiconductor device 1 includes a substrate 10, a stacked body 100 provided on the substrate 10, a plurality of columnar body portions CL, and a plurality of bit lines BL provided on the stacked body 100.

[0017] The substrate 10 is a semiconductor substrate made of P-type silicon (Si) containing P-type impurities such as boron (B), etc. On the surface of the substrate 10, for example, a P-type well region containing P-type impurities is provided.

[0018] The laminate 100 has a plurality of conductive layers 70 that are insulated from one another, and openings ST and MH that are common to the plurality of conductive layers 70. The openings ST and MH extend in the stacking direction (Z direction) and penetrate the laminate 100 to reach the substrate 10. The openings ST extend in the X direction and separate the laminate 100 into a plurality of blocks in the Y direction. As will be described in detail later, columnar body portions CL are formed in the openings MH (see FIG. 2).

[0019] The columnar body portions CL are formed as cylinders extending in the stacking direction within the laminate 100. The columnar body portions CL are arranged, for example, in a staggered pattern. Alternatively, the columnar body portions CL may be arranged in a square lattice pattern along the X and Y directions.

[0020] The plurality of bit lines BL are separated from one another in the X direction, and each bit line BL extends in the Y direction.

[0021] The upper ends of the semiconductor layer 20 (see FIG. 2), which will be described later, of the columnar body portions CL are connected to a bit line BL via contact portions Cb. A plurality of columnar body portions CL, each selected one from each block separated in the Y direction by an opening ST, are connected to a common bit line BL. Note that an insulating layer 40 is formed in the opening ST, and an insulating layer 41 is formed on the stacked body 100 (FIG. 2), but for ease of explanation, these insulating layers are omitted from FIG. 1.

[0022] 2 is a schematic cross-sectional view of the semiconductor device 1. The X direction and Z direction shown in FIG.

[0023] The laminate 100 has a plurality of conductive layers 70 stacked on a substrate 10. The plurality of conductive layers 70 are periodically stacked in a direction (stacking direction) perpendicular to the main surface of the substrate 10, with a plurality of insulating layers 40 interposed therebetween. Each conductive layer 70 is a single layer. That is, when the cross-sectional shape of one conductive layer 70 is observed, a single material may be continuous in the film thickness direction (Z direction) of the conductive layer 70. Furthermore, there may not be an interface within one conductive layer 70. The material of the conductive layer 70 may be, for example, tungsten.

[0024] An insulating layer 40 is formed between adjacent conductive layers 70 in the stacking direction. The multiple conductive layers 70 and the multiple insulating layers 40 are alternately arranged. An insulating layer 40 is also formed between the substrate 10 and the lowermost conductive layer 70. An insulating layer 40 is also formed on the uppermost conductive layer 70. An insulating layer 41 is provided on the uppermost insulating layer 40. It is sufficient that adjacent conductive layers 70 in the stacking direction are insulated from each other, and the material of the insulating layer 40 may be, for example, silicon dioxide (SiO2) or silicon oxide such as TEOS (Tetra Ethyl Ortho Silicate). The insulating layer 40 is deposited using, for example, a CVD (Chemical Vapor Deposition) apparatus.

[0025] A columnar body CL is formed in the opening MH. The columnar body CL includes an epitaxial growth layer 60, a memory layer 30, a semiconductor layer 20, and an insulating core layer 50. The columnar body CL includes the epitaxial growth layer 60 in the vicinity of the substrate 10. This epitaxial growth layer 60 is formed, for example, by epitaxially growing a silicon single crystal on the substrate 10 including a silicon single crystal.

[0026] The epitaxial growth layer 60 includes an insulating layer 62 at the connection portion with the conductive layer 70. The insulating layer 62 is formed by, for example, subjecting the epitaxial growth layer 60 to an oxidation treatment or the like.

[0027] On the epitaxial growth layer 60, a memory layer 30, a semiconductor layer 20, and an insulating core layer 50 are formed, extending in the stacking direction (Z direction). The core layer 50 is provided in a columnar shape near the center of the opening MH. The semiconductor layer 20 is provided in a cylindrical shape with a bottom around the core layer 50. The lower end of the semiconductor layer 20 is connected to the epitaxial growth layer 60. The memory layer 30 is provided in a cylindrical shape around the semiconductor layer 20. The memory layer 30 is in contact with the inner side of the opening MH (the conductive layers 70 and insulating layers 40 that are alternately stacked). The memory layer 30 is in contact with the semiconductor layer 20. In other words, the semiconductor layer 20 penetrates the stacked body 100. The memory layer 30 (including the charge storage layer 32 described later) is provided between the conductive layer 70 and the semiconductor layer 20.

[0028] FIG. 3 is an enlarged cross-sectional view of a portion of FIG. 2. The columnar body portion CL is a structure having a memory layer 30, a semiconductor layer 20, and an insulating core layer 50. The semiconductor layer 20 extends continuously in the stacking direction (Z direction) within the stacked body 100. The material of the semiconductor layer 20 includes, for example, amorphous or polycrystalline silicon. The core layer 50 is provided inside the cylindrical semiconductor layer 20. The material of the core layer 50 includes, for example, silicon oxide. The memory layer 30 is provided between the conductive layer 70 and the semiconductor layer 20. The memory layer 30 surrounds the semiconductor layer 20 from the outer periphery side of the semiconductor layer 20.

[0029] The memory layer 30 has a tunnel insulating layer 31, a charge storage layer 32, and a block insulating layer 33 (when there is no need to distinguish between the tunnel insulating layer 31, the charge storage layer 32, and the block insulating layer 33, they are referred to as the memory layer 30). The block insulating layer 33, the charge storage layer 32, and the tunnel insulating layer 31 extend continuously together with the semiconductor layer 20 in the stacking direction of the stacked body 100. Between the conductive layer 70 and the semiconductor layer 20, the block insulating layer 33, the charge storage layer 32, and the tunnel insulating layer 31 are provided, in this order from the conductive layer 70 side. The tunnel insulating layer 31 is in contact with the semiconductor layer 20. The block insulating layer 33 is in contact with the conductive layer 70. The charge storage layer 32 is provided between the block insulating layer 33 and the tunnel insulating layer 31.

[0030] The semiconductor layer 20, the memory layer 30, and the conductive layer 70 constitute a memory cell MC. In Figure 3, one memory cell MC is schematically represented by a dashed line. The memory cell MC has a vertical transistor structure in which the conductive layer 70 surrounds the semiconductor layer 20 with the memory layer 30 interposed therebetween.

[0031] In the memory cell MC having the vertical transistor structure, the semiconductor layer 20 functions as a channel, and the conductive layer 70 functions as a control gate. The charge storage layer 32 functions as a data layer that stores charges injected from the semiconductor layer 20.

[0032] As described above, the memory cells MC are arranged in the stacking direction of the conductive layers 70, and the conductive layers 70 are connected to the memory cells MC, respectively. The conductive layers 70 near the block insulating layer 33 function as control gates. By controlling the voltage to the conductive layers 70 connected to the memory cells MC, it is possible to control writing or erasing to the memory cells MC.

[0033] The semiconductor device of the embodiment is a nonvolatile semiconductor device in which data can be freely written or erased electrically to the memory cells MC and the contents can be retained even when the power is turned off.

[0034] The memory cell MC is, for example, a charge trap memory cell. The charge storage layer 32 has a large number of trap sites that trap charges in an insulating layer. The material of the charge storage layer 32 includes, for example, silicon nitride.

[0035] The tunnel insulating layer 31 serves as a potential barrier when charges are injected from the semiconductor layer 20 into the charge storage layer 32 or when charges stored in the charge storage layer 32 diffuse toward the semiconductor layer 20. The material of the tunnel insulating layer 31 includes, for example, silicon oxide.

[0036] The block insulating layer 33 prevents the charges stored in the charge storage layer 32 from diffusing into the conductive layer 70. The material of the block insulating layer 33 includes, for example, silicon oxide.

[0037] As shown in FIG. 1, a source-side select transistor STS is provided in the lower layer of the stacked body 100. A drain-side select transistor STD is provided in the upper layer of the stacked body 100. For example, the conductive layer 70 in the lowermost layer functions as a control gate of the source-side select transistor STS. For example, the conductive layer 70 in the uppermost layer functions as a control gate of the drain-side select transistor STD. A plurality of memory cells MC are provided between the source-side select transistor STS and the drain-side select transistor STD.

[0038] A plurality of memory cells MC are provided between the drain side select transistor STD and the source side select transistor STS. The plurality of memory cells MC, the drain side select transistor STD, and the source side select transistor STS are connected in series through the semiconductor layer 20 to form one memory string. This memory string is arranged, for example, in a staggered manner in a plane direction parallel to the XY plane, and the plurality of memory cells MC are provided three-dimensionally in the X, Y, and Z directions.

[0039] [Method of manufacturing semiconductor device] Next, a method for manufacturing the semiconductor device 1 according to the first embodiment will be described with reference to Figures 4A to 4E and 5. Figures 4A to 4E are cross-sectional views illustrating the method for manufacturing the semiconductor device according to this embodiment. Figure 5 is a view illustrating the method for manufacturing the semiconductor device according to this embodiment.

[0040] As shown in FIG. 4A, first, insulating layers 40 (TEOS films) and sacrificial layers 71 (SiN films) are alternately formed on a substrate 10 to form a stacked body 11. The insulating layers 40 and the sacrificial layers 71 are deposited, for example, using a CVD apparatus. The alternately stacked insulating layers 40 and the sacrificial layers 71 are formed so as to be in contact with each other. In this embodiment, silicon dioxide (SiO2) is exemplified as the material for the insulating layers 40, but the material for the insulating layers 40 is not limited thereto and may be, for example, a TEOS film. In this embodiment, silicon nitride (SiN) is exemplified as the material for the sacrificial layers 71, but the material for the sacrificial layers 71 is not limited thereto and may be, for example, silicon. In the following description, when there is no need to distinguish between the insulating layers 40 and the sacrificial layers 71, the stacked body 11 will be described without mentioning the stacked structure.

[0041] Next, as shown in FIG. 4B, a mask 12 having a pattern of memory holes MH is formed on the upper surface of the stack 11 (the surface opposite to the substrate 10). The mask 12 is preferably a hard mask, and the material of the mask 12 may be, for example, carbon. The material of the mask 12 may include two or more materials with different compositions. In this case, the mask 12 may have a stacked structure including two or more layers containing materials with different compositions. The mask 12 is deposited using, for example, a CVD apparatus. The pattern of the mask 12 is formed by dry etching using a resist mask formed by photolithography of a resist and an intermediate layer (not shown) such as a silicon oxide film formed between the mask 12 and the resist. The pattern of the mask 12 has an opening pattern 13 that exposes the surface of the stack 11 (insulating layer 40) in the region where the memory holes MH are to be formed.

[0042] Next, as shown in FIG. 4C, plasma etching is performed using a gas containing hydrogen fluoride (HF) (hereinafter also referred to as "etching"). For example, the stacked body 11 may be etched by dry etching using hydrogen fluoride / phosphorus trifluoride (HF / PF3) mixed gas plasma. By etching the insulating layers 40 and the sacrificial layers 71 by plasma etching, recesses 11a are formed in the stacked body 11 in areas where the opening patterns 13 of the mask 12 are exposed. At this time, modified layers 14 are formed on the surfaces of the insulating layers 40 (e.g., silicon dioxide (SiO2)) exposed on the side surfaces of the recesses 11a of the stacked body 11. The modified layers 14 contain fluorine (F) and hydrogen (H). Note that in FIG. 4C, the modified layers 14 are selectively formed on the surfaces of the silicon oxide insulating layers 40, but are less likely to be formed on the surfaces of the silicon nitride sacrificial layers 71 exposed on the side surfaces of the recesses 11a. An example of forming the modified layers 14 on the surfaces of the silicon nitride will be described later.

[0043] The RF power and RF frequency for plasma generation during plasma etching are not particularly limited. It is preferable to use a capacitively coupled plasma in which two or more RF frequencies are superimposed. For example, the high-frequency RF frequency is preferably in the range of 50 MHz to 100 MHz, and the low-frequency RF frequency is preferably in the range of 0.1 MHz to 5 MHz. The input power is preferably in the range of several kW or several tens of kW or more. Even higher power may be input depending on the aspect ratio of the workpiece. The pressure is preferably in the range of 10 mT to 50 mT, and the temperature of the substrate mounting table is preferably controlled to, for example, -10°C or less to -50°C or more during etching. During etching, the substrate receives heat from the plasma, and the substrate temperature, for example, may be several tens of degrees Celsius higher than the temperature of the mounting table. In etching using hydrogen fluoride (HF) plasma, the etching rate of the laminate 11 can be improved by lowering the substrate temperature. In this embodiment, the substrate temperature is, for example, approximately 20°C.

[0044] Next, etching is stopped before the diameter of the recess 11a exceeds the allowable dimension. With the substrate remaining on the mounting table, the gas supply and the application of high-frequency power are stopped (plasma is turned off), and a vacuum is drawn. However, this is not limited to this, and may be omitted if the gas, temperature, etc. can be switched instantaneously. On the other hand, an inert gas such as argon (Ar) may be purged to reliably eliminate the effects of residual gas.

[0045] Next, as shown in FIG. 4D, a gas containing nitrogen and hydrogen (e.g., hydrogen nitride molecules) is supplied to form a protective layer 15 containing nitrogen, hydrogen, and fluorine (hereinafter also referred to as "surface modification"). For example, ammonia (NH3) gas, which is a gas containing nitrogen and hydrogen, is introduced without applying high-frequency power, and the substrate is exposed to an ammonia (NH3) atmosphere. At this time, the modified layer 14 formed by the HF plasma and HF gas is transformed into a protective layer 15 containing nitrogen, hydrogen, and fluorine. The protective layer 15 may contain ammonium hexafluorosilicate ((NH4)2SiF6).

[0046] Here, when forming the protective layer 15, it is preferable to raise the temperature of the substrate support table to, for example, about 25°C using a chiller, and to bring the substrate temperature to about room temperature. The temperature when forming the protective layer 15 is preferably higher than the temperature during etching. Furthermore, to promote the formation reaction of the protective layer 15 containing ammonium hexafluorosilicate ((NH4)2SiF6), it is preferable to raise the pressure when introducing ammonia (NH3) gas to about 500 mT. For example, the pressure when introducing ammonia (NH3) gas is preferably 100 mT or higher. For example, the pressure when introducing ammonia (NH3) gas is preferably 500 mT or higher. In other words, it is preferable that the pressure when forming the protective layer 15 is at least one order of magnitude higher than the pressure during etching. Figure 5 shows the relationship between the gas type, pressure, plasma, and temperature during etching and when forming the protective layer 15.

[0047] In this embodiment, the application of high-frequency power was stopped (plasma was turned off) when ammonia (NH3) gas was introduced. Because plasma generation requires power, stopping the application of high-frequency power (plasma was turned off) can reduce energy and costs. Furthermore, stopping the application of high-frequency power (plasma was turned off) can suppress the generation of various active species that result from the plasma generation of ammonia (NH3). By suppressing the generation of active species, it is possible to avoid problems such as these reacting with the substrate or the surface of the vacuum chamber to form unnecessary reaction products and generating particles in the chamber.

[0048] After this, the supply of ammonia (NH3) gas is stopped and a vacuum is drawn. However, this is not limited to this, and this step may be omitted if the gas and temperature can be switched reliably. On the other hand, an inert gas such as argon (Ar) may be purged to reliably eliminate the influence of residual gas.

[0049] Next, as shown in FIG. 4E, plasma etching is resumed using a gas containing hydrogen fluoride (HF). The plasma etching conditions may be the same as those described above. Plasma etching removes the protective layer 15 from the bottom of the recess 11a, which is subjected to perpendicular ion incidence, and etching of the recess 11b progresses. The protective layer 15 remains on the side of the recess 11a, suppressing lateral etching caused by obliquely incident ions. By suppressing lateral etching (enlargement of the pattern dimensions), it is possible to suppress contact between adjacent patterns and pattern collapse. In other words, the bottom of the recess 11a is lowered, allowing the formation of a recess 11b with a higher aspect ratio. At this time, a modified layer 14 is formed on the side and bottom of the recess 11b where the protective layer 15 is not present.

[0050] Thereafter, when the recess 11b reaches the desired depth of the memory hole MH, the plasma etching is terminated. If the recess 11b does not reach the desired depth of the memory hole MH, the formation of the protective layer 15 shown in FIG. 4D and the plasma etching and the formation of the modified layer 14 shown in FIG. 4E are repeated until the recess 11b reaches the desired etching depth.

[0051] After the recess reaches the desired depth of the memory hole MH, ashing is performed at 200° C. to 300° C. to remove the mask 12. By heating to at least 100° C. or higher, the protective layer 15 remaining on the side surface of the recess 11a can also be removed.

[0052] The method for forming the columnar body portion CL is not particularly limited. The columnar body portion CL can be formed using an existing method. After forming the columnar body portion CL, the sacrificial layer 71 is removed with an etching solution, and the conductive layer 70 is formed, whereby the semiconductor device 1 shown in FIG. 2 can be manufactured.

[0053] As described above, according to the method for manufacturing a semiconductor device of this embodiment, by performing the second and subsequent plasma etchings after forming the protective layer 15, it becomes possible to perform etching with a high aspect ratio while suppressing the enlargement of the pattern dimensions, and it is possible to form memory holes MH with a high aspect ratio. Therefore, it is possible to improve the reliability and manufacturing yield of the semiconductor device.

[0054] Although the present embodiment has been described by exemplifying a method for forming memory holes MH, the technology of the present disclosure is not limited to this and can be applied to the formation of any pattern, such as a contact hole, a line pattern, a square pad pattern, etc. Furthermore, the stacked body 11 may be replaced by a single layer of silicon oxide.

[0055] <Variation 1> 4C shows an example in which the modified layer 14 is formed on the surface of the recess 11a of the laminate 11 by plasma etching using a gas containing hydrogen fluoride (HF). However, to more reliably form the modified layer 14, after the plasma etching and before the protective layer 15 is formed, surface treatment may be performed by supplying a gas containing hydrogen fluoride (HF) with the application of high-frequency power stopped (plasma turned off). To promote the reaction of forming the modified layer 14, the temperature during the formation of the modified layer 14 is preferably higher than the temperature during etching, and the pressure during the formation of the modified layer 14 is preferably higher by one order of magnitude or more than the pressure during etching.

[0056] <Variation 2> More specifically, Figure 4C shows an example of plasma etching using a hydrogen fluoride / phosphorus trifluoride (HF / PF3) mixed gas. However, to promote surface adsorption of hydrogen fluoride (HF), at least one of phosphorus trichloride (PCl3), phosphorus pentafluoride (PF5), boron trifluoride (BF3), water (HO), and various alcohols may be added. To control the shape of low aspect ratio portions, at least one of carbon tetrafluoride (CF4), trifluoromethane (CHF3), difluoromethane (CH2F2), fluoromethane (CH3F), octafluorocyclobutane (CF4F8), hexafluoro-1,3-butadiene (CF4F6), hydrogen bromide (HBr), trifluoroiodomethane (CF3I), and iodine heptafluoride (IF7) may be added. To supplement the fluorine supply, at least one of sulfur hexafluoride (SF6), nitrogen trifluoride (NF3), fluorine (F2), and xenon difluoride (XeF2) may be added. At least one of chlorine (Cl2), hydrogen chloride (HCl), and boron trichloride (BCl3) may be added to control the shape of the high aspect ratio portion.

[0057] <Variation 3> Figure 4C shows an example of plasma etching using a hydrogen fluoride / phosphorus trifluoride (HF / PF3) mixed gas plasma. However, mixed gas plasmas that generate hydrogen fluoride (HF) in the plasma can also be used. For example, by mixing fluorine-containing gases (NF3, SF6, fluorocarbon gases in general) with hydrogen-containing gases (H2, H2O, etc.), such as carbon tetrafluoride / hydrogen (CF4 / H2) mixed gas, nitrogen trifluoride / hydrogen (NF3 / H2), or sulfur hexafluoride / hydrogen (SF6 / H2), hydrogen fluoride (HF) can be generated in the gas phase or on the wafer surface.

[0058] <Variation 4> 4D shows an example of forming the protective layer 15 using ammonia (NH3) gas. However, instead of ammonia (NH3) gas, deuterium ammonia (ND3) gas, which is less likely to desorb from the surface after adsorption, can also be used.

[0059] Second Embodiment [Method of manufacturing semiconductor device] A manufacturing method of the semiconductor device 1 according to the second embodiment will be described using Figures 6A, 6B, and 7. The semiconductor device 1 according to the second embodiment is the same as the semiconductor device 1 according to the first embodiment. The manufacturing method of the semiconductor device 1 according to the second embodiment is the same as the manufacturing method of the semiconductor device 1 according to the first embodiment, except that an oxide layer and a modified layer are formed before forming a protective layer. In the following explanation, a description of manufacturing methods similar to those in the first embodiment will be omitted, and manufacturing methods different from those in the first embodiment will mainly be described. Figures 6A and 6B are cross-sectional views showing the manufacturing method of the semiconductor device according to this embodiment. Figure 7 is a view explaining the manufacturing method of the semiconductor device according to this embodiment.

[0060] First, the laminate 11 is formed as described in Fig. 4A, the mask 12 is formed as described in Fig. 4B, and the recess 11a is formed by plasma etching using a gas containing hydrogen fluoride (HF) as described in Fig. 4C. At this time, although not shown, a modified layer 14 may be formed on the surface of the silicon oxide serving as the insulating layer 40.

[0061] 6A, a plasma treatment using oxygen gas is performed to selectively form a silicon oxide layer 34 on the surface of the sacrificial layer 71 (e.g., a silicon nitride film (SiN)) exposed on the side surface of the recess 11a of the laminate 11 (hereinafter also referred to as "oxidation"). As conditions for the oxygen gas plasma, it is preferable to perform the treatment for a short time at a power about 1 / 10 of that used during etching so as to minimize consumption of the mask 12.

[0062] Next, as shown in FIG. 6B, after the plasma treatment, the application of high-frequency power is stopped (the plasma is turned off), and a surface treatment is performed using a gas containing hydrogen fluoride (HF) to form a modified layer 35 (hereinafter also referred to as "pre-treatment"). The modified layer 35 is formed on the surfaces of the silicon oxide layer 34 and the insulating layer 40 exposed on the side surfaces of the recess 11a of the laminate 11. The modified layer 35 may contain fluorine (F) or hydrogen (H). To promote the formation of the modified layer 35, the temperature during the formation of the modified layer 35 is preferably higher than the temperature during the etching and silicon oxide layer 34 formation. The pressure during the formation of the modified layer 35 is preferably at least one order of magnitude higher than the pressure during the etching and silicon oxide layer 34 formation. FIG. 7 shows the relationship between the gas type, pressure, plasma, and temperature during the etching, silicon oxide layer 34 formation, modified layer 35 formation, and protective layer 15 formation.

[0063] Next, a protective layer 15 is formed as described in FIG. 4D, and plasma etching is resumed using a gas containing hydrogen fluoride (HF) as described in FIG. 4E.

[0064] In this embodiment, a silicon oxide layer 34 is formed on the surface of the sacrificial layer 71 by performing a plasma treatment using oxygen gas. This allows the modified layer 35 to be formed on both the silicon oxide layer 34 and the insulating layer 40 exposed on the side surfaces of the recess 11a of the laminate 11, thereby enabling the protective layer 15 to be formed over a wider area. The protective layer 15 on the side surfaces of the recess 11a can suppress lateral etching caused by obliquely incident ions. By suppressing lateral etching (enlargement of the pattern dimensions), it is possible to suppress contact between adjacent patterns and pattern collapse. In other words, the bottom surface of the recess 11a can be lowered, allowing the formation of a recess 11b with a higher aspect ratio. In this case, the modified layer 14 is formed on the side surfaces and bottom surfaces of the recess 11b where the protective layer 15 is not present.

[0065] Thereafter, when the recess 11b reaches the desired depth of the memory hole MH, the plasma etching is terminated. If the recess 11b does not reach the desired depth of the memory hole MH, the formation of the silicon oxide layer 34 shown in Fig. 6A, the formation of the modified layer 35 shown in Fig. 6B, the formation of the protective layer 15 shown in Fig. 4D, and the plasma etching shown in Fig. 4E are repeated until the recess 11b reaches the desired etching depth.

[0066] As described above, according to the method for manufacturing a semiconductor device of this embodiment, by performing the second and subsequent plasma etchings after forming the protective layer 15, it becomes possible to perform etching with a high aspect ratio while suppressing the enlargement of the pattern dimensions, and it is possible to form memory holes MH with a high aspect ratio. Therefore, it is possible to improve the reliability and manufacturing yield of the semiconductor device.

[0067] Although the present embodiment has been described by exemplifying a method for forming memory holes MH, the technology of the present disclosure is not limited to this and can be applied to the formation of any pattern, such as contact holes, line patterns, square pad patterns, etc. Furthermore, the stacked body 11 may be replaced by a single layer of silicon nitride.

[0068] Third Embodiment [Method of manufacturing semiconductor device] A manufacturing method of the semiconductor device 1 according to the third embodiment will be described using Figures 8A, 8B, and 9. The semiconductor device 1 according to the third embodiment is the same as the semiconductor device 1 according to the first embodiment. The manufacturing method of the semiconductor device 1 according to the third embodiment is the same as the manufacturing method of the semiconductor device 1 according to the first embodiment, except for the etching method and the formation of a modified layer before forming a protective layer. In the following explanation, a description of manufacturing methods similar to those in the first embodiment will be omitted, and manufacturing methods different from those in the first embodiment will mainly be described. Figures 8A and 8B are cross-sectional views showing the manufacturing method of the semiconductor device according to this embodiment. Figure 9 is a view explaining the manufacturing method of the semiconductor device according to this embodiment.

[0069] First, the laminate 11 is formed as described in FIG. 4A, and then the mask 12 is formed as described in FIG. 4B.

[0070] Next, as shown in Figure 8A, plasma etching is performed using a fluorocarbon gas containing fluorine and carbon, or a hydrofluorocarbon gas containing fluorine, carbon, and hydrogen. For example, the laminate 11 may be etched by dry etching using a hexafluoro-1,3-butadiene / oxygen / argon (C4F6 / O2 / Ar) mixed gas plasma or a trifluoromethane / oxygen / argon (CHF3 / O2 / Ar) mixed gas plasma. Plasma etching forms recesses 11a in the laminate 11 in areas where the opening pattern 13 of the mask 12 is exposed.

[0071] There are no particular limitations on the RF power or RF frequency used to generate the plasma. It is preferable to use a capacitively coupled plasma in which two or more RF frequencies are superimposed. For example, the RF frequency on the high frequency side is preferably in the range of 50 MHz to 100 MHz, and the RF frequency on the low frequency side is preferably in the range of 0.1 MHz to 5 MHz, and the input power is preferably in the range of several kW to several tens of kW. The pressure is preferably in the range of 10 mT to 50 mT, and the temperature of the substrate stage is preferably about 25°C. For example, when using a trifluoromethane / oxygen / argon (CHF3 / O2 / Ar) mixed gas plasma, it is preferable to perform etching by controlling the temperature of the substrate stage to a range of -10°C to -50°C.

[0072] Next, etching is stopped before the diameter of the recess 11a exceeds the allowable dimension. With the substrate remaining on the mounting table, the gas supply and the application of high-frequency power are stopped (plasma is turned off), and a vacuum is drawn. However, this is not limited to this, and may be omitted if the gas, temperature, etc. can be switched. On the other hand, an inert gas such as argon (Ar) may be purged to completely eliminate the influence of residual gas.

[0073] Next, as shown in FIG. 8B, after the plasma etching, the application of high-frequency power is stopped (the plasma is turned off) and a surface treatment using a gas containing hydrogen fluoride (HF) is performed to form a modified layer 24 (pre-treatment). The modified layer 24 is formed on the surface of the insulating layer 40 (e.g., silicon dioxide (SiO2)) exposed on the side surface of the recess 11a of the laminate 11. The modified layer 24 may contain fluorine (F) or hydrogen (H). To promote the reaction that forms the modified layer 24, the temperature during the formation of the modified layer 24 is preferably higher than the temperature during etching, and the pressure during the formation of the modified layer 24 is preferably at least one order of magnitude higher than the pressure during etching. Note that in FIG. 8B, the modified layer 24 is selectively formed on the surface of the silicon oxide insulating layer 40, but is unlikely to be formed on the surface of the silicon nitride sacrificial layer 71 exposed on the side surface of the recess 11a. FIG. 9 shows the relationship between the type of gas, pressure, plasma, and temperature during etching, the formation of the modified layer 24, and the formation of the protective layer 15.

[0074] Next, protective layer 15 is formed as described in FIG. 4D, and plasma etching is resumed using fluorocarbon gas or hydrofluorocarbon gas as described in FIG. 8A. The plasma etching conditions may be the same as those described above. By the plasma etching, protective layer 15 is removed from the bottom surface of recess 11a, which is subjected to perpendicular ion incidence, and etching of recess 11b progresses.

[0075] In this embodiment, the protective layer 15 on the side surface of the recess 11a can suppress lateral etching caused by obliquely incident ions. By suppressing lateral etching (expansion of the pattern dimensions), it is possible to prevent adjacent patterns from coming into contact with each other and collapsing the patterns. In other words, it is possible to lower the bottom surface of the recess 11a and form a recess 11b with a higher aspect ratio.

[0076] Thereafter, when the recess 11b reaches the desired depth of the memory hole MH, the plasma etching is terminated. If the recess 11b does not reach the desired depth of the memory hole MH, the formation of the modified layer 24 shown in Fig. 8B, the formation of the protective layer 15 shown in Fig. 4D, and the plasma etching shown in Fig. 8A are repeated until the recess 11b reaches the desired etching depth.

[0077] As described above, according to the method for manufacturing a semiconductor device of this embodiment, by performing the second and subsequent plasma etchings after forming the protective layer 15, it becomes possible to perform etching with a high aspect ratio while suppressing the enlargement of the pattern dimensions, and it is possible to form memory holes MH with a high aspect ratio. Therefore, it is possible to improve the reliability and manufacturing yield of the semiconductor device.

[0078] Although the present embodiment has been described by exemplifying a method for forming memory holes MH, the technology of the present disclosure is not limited to this and can be applied to the formation of any pattern, such as a contact hole, a line pattern, a square pad pattern, etc. Furthermore, the stacked body 11 may be replaced by a single layer of silicon oxide.

[0079] <Fourth embodiment> [Method of manufacturing semiconductor device] A manufacturing method of the semiconductor device 1 according to the fourth embodiment will be described with reference to FIGS. 10 and 11. The semiconductor device 1 according to the fourth embodiment is the same as the semiconductor device 1 according to the first embodiment. The manufacturing method of the semiconductor device 1 according to the fourth embodiment is the same as the manufacturing method of the semiconductor device 1 according to the third embodiment, except that an oxide layer is formed before forming a modified layer. In the following description, manufacturing methods similar to those of the first and third embodiments will be omitted, and manufacturing methods different from those of the first and third embodiments will mainly be described. FIG. 10 is a cross-sectional view showing the manufacturing method of the semiconductor device according to this embodiment. FIG. 11 is a view explaining the manufacturing method of the semiconductor device according to this embodiment.

[0080] First, the laminate 11 is formed as described in FIG. 4A, the mask 12 is formed as described in FIG. 4B, and the recess 11a is formed by plasma etching using a fluorocarbon gas or a hydrofluorocarbon gas as described in FIG. 8A.

[0081] 10, a plasma treatment using oxygen gas is performed to form a silicon oxide layer 44 (oxidation) on the surface of the sacrificial layer 71 (e.g., a silicon nitride (SiN) film) exposed on the side surface of the recess 11a of the laminate 11. As conditions for the oxygen gas plasma, it is preferable to perform the treatment for a short time at about 1 / 10 of the power used during etching so as to minimize consumption of the mask 12.

[0082] Next, as shown in FIG. 8B, after the plasma treatment, the application of high-frequency power is stopped (the plasma is turned off) and a surface treatment using a gas containing hydrogen fluoride (HF) is performed to form a modified layer 24 (pre-treatment). The modified layer 24 is formed on the surfaces of the silicon oxide layer 44 and the insulating layer 40 exposed on the side surfaces of the recess 11a of the laminate 11. The modified layer 24 may contain fluorine (F) or hydrogen (H). To promote the reaction that forms the modified layer 24, the temperature during the formation of the modified layer 24 is preferably higher than the temperature during etching and the formation of the silicon oxide layer 44. The pressure during the formation of the modified layer 24 is preferably at least one order of magnitude higher than the pressure during etching and the formation of the silicon oxide layer 44. FIG. 11 shows the relationship between the type of gas, pressure, plasma, and temperature during etching, the formation of the silicon oxide layer 44, the formation of the modified layer 24, and the formation of the protective layer 15.

[0083] Next, protective layer 15 is formed as described in FIG. 4D, and plasma etching is resumed using a gas containing fluorocarbon gas or hydrofluorocarbon gas as described in FIG. 8A. The plasma etching conditions may be the same as those described above. By the plasma etching, protective layer 15 is removed from the bottom surface of recess 11a, which is subjected to perpendicular ion incidence, and etching of recess 11b progresses.

[0084] In this embodiment, a silicon oxide layer 44 is formed on the surface of the sacrificial layer 71 by performing a plasma treatment using oxygen gas. This allows the modified layer 24 to be formed on both the silicon oxide layer 44 and the insulating layer 40 exposed on the side surfaces of the recesses 11a of the laminate 11, thereby enabling the protective layer 15 to be formed over a wider area. The protective layer 15 on the side surfaces of the recesses 11a can suppress lateral etching caused by obliquely incident ions. By suppressing lateral etching (enlargement of the pattern dimensions), it is possible to suppress contact between adjacent patterns and pattern collapse. In other words, the bottom surface of the recesses 11a can be lowered, allowing the formation of recesses 11b with a higher aspect ratio.

[0085] Thereafter, when the recess 11b reaches the desired depth of the memory hole MH, the plasma etching is terminated. If the recess 11b does not reach the desired depth of the memory hole MH, the formation of the silicon oxide layer 44 shown in Fig. 10, the formation of the modified layer 24 shown in Fig. 8B, the formation of the protective layer 15 shown in Fig. 4D, and the plasma etching shown in Fig. 8A are repeated until the recess 11b reaches the desired etching depth.

[0086] As described above, according to the method for manufacturing a semiconductor device of this embodiment, by performing the second and subsequent plasma etchings after forming the protective layer 15, it becomes possible to perform etching with a high aspect ratio while suppressing the enlargement of the pattern dimensions, and it is possible to form memory holes MH with a high aspect ratio. Therefore, it is possible to improve the reliability and manufacturing yield of the semiconductor device.

[0087] Although the present embodiment has been described by exemplifying a method for forming memory holes MH, the technology of the present disclosure is not limited to this and can be applied to the formation of any pattern, such as contact holes, line patterns, square pad patterns, etc. Furthermore, the stacked body 11 may be replaced by a single layer of silicon nitride.

[0088] Fifth Embodiment [Example of semiconductor manufacturing equipment configuration] 12 is a schematic diagram showing an example of the configuration of a semiconductor manufacturing apparatus that can be used in a semiconductor manufacturing process. The semiconductor manufacturing apparatus 1000 includes a processing chamber 2, an electrode 3, an electrode 4, a gas supply unit 5, a gas exhaust unit 6, a cooling device 7, a power supply unit 8, and a control circuit 9.

[0089] The processing chamber 2 is a space in which it is possible to etch a film to be processed on the substrate 10 by reactive ion etching using plasma, perform plasma processing using oxygen gas (forming a silicon oxide layer), perform surface processing using a gas containing hydrogen fluoride (HF) (forming a modified layer), and supply hydrogen nitride molecules (forming a protective layer). Each process can be performed alternately within the same chamber. The processing chamber 2 may have a door (gate) for loading and unloading the substrate 10.

[0090] The electrode 3 is a lower electrode and functions as a stage for placing the substrate 10. The electrode 3 has a surface 3a that is a surface for placing the substrate 10. The semiconductor manufacturing apparatus 1000 may also have an electrostatic chuck for holding the substrate 10.

[0091] The electrode 4 is an upper electrode. The electrode 4 has a surface 4a and an opening 4b for introducing a gas into the processing chamber 2 through the electrode 4. The opening 4b has a plurality of inlets on the surface 4a.

[0092] The gas supply unit 5 includes a gas supply source 51 such as a cylinder cabinet, and a mass flow controller 52. The gas supply unit 5 supplies gas from the gas supply source 51 to the processing chamber 2.

[0093] The gas supply source 51 contains a first gas (GAS1), a second gas (GAS2), and a third gas (GAS3). The first gas, the second gas, and the third gas are each contained in a container such as a gas cylinder.

[0094] The first gas includes hydrogen fluoride (HF). The first gas may include, for example, a hydrogen fluoride / phosphorus trifluoride (HF / PF3) mixed gas. The second gas includes, for example, an inert gas such as argon gas. The third gas includes hydrogen nitride molecules. The third gas may include ammonia (NH3) gas.

[0095] The mass flow controller 52 adjusts the flow rates of the first gas and the second gas introduced from the gas supply source 51 into the processing chamber 2 .

[0096] The gas exhaust unit 6 has a valve 61, a turbo molecular pump 64, and a dry pump 63. The gas exhaust unit 6 has a function of reducing the pressure inside the processing chamber 2 to create a vacuum state, and also a function of exhausting gas inside the processing chamber 2.

[0097] The cooling device 7 includes, for example, a chiller 73 and a refrigerant pipe 72 inside the electrode 3. The chiller 73 cools the substrate 10 by circulating a refrigerant through the refrigerant pipe 72. If another chiller is installed and given a refrigerant switching function, the instantaneous temperature change as in this embodiment can be efficiently performed.

[0098] The power supply unit 8 has a power supply 81 that supplies an AC voltage, and a matching circuit 82 such as a matching box. The power supply unit 8 has a function of matching the impedance between the processing chamber 2 and the power supply 81 using the matching circuit 82, and supplying a radio frequency (RF) voltage to the processing chamber 2. The radio frequency voltage is an AC voltage having a frequency of, for example, 200 kHz or more and 200 MHz or less.

[0099] The control circuit 9 controls the mass flow controller 52 and the power supply 81. The control circuit 9 is configured using hardware such as a processor. Each operation may be stored as an operation program in a computer-readable recording medium such as a memory, and each operation may be executed by the hardware appropriately reading out the operation program stored in the recording medium.

[0100] Although several embodiments have been described above, these embodiments are presented only as examples and are not intended to limit the scope of the invention. The novel apparatus and method described herein may be embodied in various other forms. Furthermore, various omissions, substitutions, and modifications may be made to the forms of the apparatus and method described herein without departing from the spirit of the invention. The appended claims and their equivalents are intended to cover such forms and modifications that fall within the scope and spirit of the invention.

[0101] Even if there are other effects and advantages different from those brought about by the aspects of each of the above-mentioned embodiments, those that are clear from the description in this specification or that can be easily predicted by a person skilled in the art are naturally understood to be brought about by the present invention. [Explanation of symbols]

[0102] 1: semiconductor device, 10: substrate, 11: laminate, 11a: recess, 11b: recess, 12: mask, 13: opening pattern, 14: modified layer, 15: protective layer, 34: silicon oxide layer, 20: semiconductor layer, 30: memory layer, 31: tunnel insulating layer, 32: charge storage layer, 33: block insulating layer, 40, 41, 62: insulating layer, 50: core layer, 70: conductive layer, 71: sacrificial layer, 100: laminate, 1000: semiconductor manufacturing equipment

Claims

1. A substrate having a film to be processed is prepared; forming a recess in the workpiece film by performing a first etching process using a plasma containing a gas containing hydrogen fluoride; supplying a gas containing nitrogen and hydrogen into the recess without applying high frequency power to form a first protective layer containing nitrogen, hydrogen, and fluorine; performing a second etching process using the plasma on the recessed portion on which the first protective layer is formed; A method for manufacturing a semiconductor device, comprising:

2. After the second etching, supplying a gas containing nitrogen and hydrogen into the recess without applying high frequency power to form a second protective layer containing nitrogen, hydrogen, and fluorine; a third etching step using the plasma to the recessed portion on which the second protective layer is formed; The method for manufacturing a semiconductor device according to claim 1 , further comprising:

3. 3. The method for manufacturing a semiconductor device according to claim 1, wherein the gas containing nitrogen and hydrogen is ammonia gas or deuterium ammonia gas.

4. After the first etching and before forming the first protective layer, The gas containing hydrogen fluoride is supplied to the recessed portion without applying high frequency power. The method for manufacturing a semiconductor device according to claim 1 , further comprising:

5. 2. The method for manufacturing a semiconductor device according to claim 1, wherein the temperature when said first protective layer is formed is higher than the temperature when said recess is formed.

6. 2. The method for manufacturing a semiconductor device according to claim 1, wherein a pressure when said first protective layer is formed is higher than a pressure when said recess is formed.

7. before forming the first protective layer and after the first etching, forming an oxide layer in the recess by performing a plasma treatment using oxygen gas; supplying the gas containing hydrogen fluoride to the recessed portion on which the oxide layer has been formed without applying high frequency power, thereby forming a modified layer containing fluorine and hydrogen. The method for manufacturing a semiconductor device according to claim 1 , further comprising:

8. 8. The method for manufacturing a semiconductor device according to claim 7, wherein the temperature when forming said modified layer is higher than the temperature when forming said recess.

9. 8. The method for manufacturing a semiconductor device according to claim 7, wherein a pressure when the modified layer is formed is higher than a pressure when the recess is formed.

10. 2. The method for manufacturing a semiconductor device according to claim 1, wherein said processing target film includes a silicon oxide film and a silicon nitride film, said silicon oxide film and said silicon nitride film being alternately stacked.

11. 2. The method for manufacturing a semiconductor device according to claim 1, wherein the formation of the recess and the formation of the first protective layer are carried out in the same chamber.

12. A substrate having a film to be processed is prepared; forming a recess in the film to be processed by performing a first etching process using plasma containing a fluorocarbon gas or a hydrofluorocarbon gas; supplying a gas containing hydrogen fluoride to the recess without applying high frequency power to form a first modified layer containing fluorine and hydrogen; a gas containing nitrogen and hydrogen is supplied to the recess in which the first modified layer is formed without applying high frequency power, thereby forming a first protective layer containing nitrogen, hydrogen, and fluorine; performing a second etching process using the plasma on the recessed portion on which the first protective layer is formed; A method for manufacturing a semiconductor device, comprising:

13. After the second etching, supplying a gas containing hydrogen fluoride to the recess in a state where high frequency power is not applied, thereby forming a second modified layer containing fluorine; a gas containing nitrogen and hydrogen is supplied to the recess in which the second modified layer is formed without applying high frequency power, thereby forming a second protective layer containing nitrogen, hydrogen, and fluorine; performing a third etching process on the recessed portion on which the second protective layer is formed using the plasma; The method for manufacturing a semiconductor device according to claim 12, further comprising:

14. 14. The method for manufacturing a semiconductor device according to claim 12, wherein the gas containing nitrogen and hydrogen is ammonia gas or deuterium ammonia gas.

15. 13. The method for manufacturing a semiconductor device according to claim 12, wherein a temperature when the first protective layer is formed is higher than a temperature when the recess is formed.

16. 13. The method for manufacturing a semiconductor device according to claim 12, wherein a pressure when the first protective layer is formed is higher than a pressure when the recess is formed.

17. After the first etching and before forming the first modified layer forming an oxide layer in the recess by performing a plasma treatment using oxygen gas; The method for manufacturing a semiconductor device according to claim 12, further comprising:

18. 18. The method for manufacturing a semiconductor device according to claim 17, wherein the temperature when forming the first modified layer is higher than the temperature when forming the recess, and the pressure when forming the first modified layer is higher than the pressure when forming the recess.

19. 13. The method for manufacturing a semiconductor device according to claim 12, wherein the film to be processed includes a silicon oxide film and a silicon nitride film, and the silicon oxide film and the silicon nitride film are alternately stacked.

20. The method for manufacturing a semiconductor device according to claim 12, wherein the formation of the recess and the formation of the first protective layer are performed in the same chamber.

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