Integrated multi-component hall effect sensor

Abstract

To provide: multi-component Hall effect sensors and sensing methods suitable for embedding within integrated circuitry; and integrated circuit manufacturing methods that enables embedding of such sensors and sensing methods.SOLUTION: A transducer 112 as an integrated circuit device includes: a substrate comprising a semiconductive body material 302 with an upper surface 304; a focus contact 306 on the upper surface that connects, via an electrically isolated path, to an embedded current focus 310 within the semiconductive body material; one or more distributed current contacts 314 on the upper surface that operate in combination with the embedded current focus to form a distributed current flow through the semiconductive body material; and an arrangement of sensing contacts 316 on the upper surface to detect a set of voltages representing a Hall effect measurement for each three-dimensional vector component of a magnetic field acting on the distributed current flow.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] FIELD OF THE DISCLOSURE This disclosure relates generally to integrated circuit electronics, and more particularly to multi-component Hall effect sensors and sensing methods suitable for embedding within integrated circuits on semiconductor chips. [Background technology]

[0002] The manufacturing process of integrated circuits involves applying repeated patterning, deposition, and etching steps to semiconductor wafers or other substrates to form interconnected structures that operate as analog and / or digital components of electronic circuits. Integrated circuits can be made more versatile, and therefore more valuable, with the embedding of sensing technologies, particularly sensing technologies that can be incorporated by adapting existing steps in the manufacturing process, thereby avoiding significant increases in manufacturing costs. Such embedding can require compact sensor implementations that use existing process steps. Summary of the Invention

[0003] Accordingly, disclosed herein are exemplary multi-component Hall effect sensors and sensing methods suitable for embedding within integrated circuits, as well as exemplary integrated circuit fabrication methods that can enable the embedding of such sensors and sensing methods.

[0004] One exemplary integrated circuit device includes a substrate including a semiconductive body material having a top surface, focus contacts on the top surface connecting to embedded current focuses via electrically isolated paths within the body material, one or more distributed current contacts on the top surface operating in combination with the embedded current focuses to form a distributed current flow through the body material, and an arrangement of sense contacts on the top surface for detecting a set of voltages representing Hall effect measurements for each three-dimensional vector component of a magnetic field acting on the distributed current flow.

[0005] An exemplary sensing method includes forming a distributed current flow between the embedded current focus and one or more distributed current contacts on the surface of the body, the distributed current flow exhibiting the Hall effect when acted upon by a magnetic field, and detecting a set of voltages using an arrangement of sensing contacts on the surface of the body that provides distinguishable sensitivity to the Hall effect induced by two components of the magnetic field parallel to the surface and a component of the magnetic field perpendicular to the surface.

[0006] An exemplary sensor fabrication method includes forming an electrically isolated path to an embedded current focus in a semiconductor body material having a top surface and providing a set of contacts on the surface, the set of contacts including a focus contact connected to the embedded current focus via the electrically isolated path, one or more distributed current contacts configured to form a distributed current flow through the body material to or from the embedded current focus, and a plurality of sense contacts configured to provide voltages sensitive to Hall effect measurements for each three-dimensional vector component of a magnetic field acting on the distributed current flow.

[0007] Each of the above can be used individually or in combination and may include one or more of the following optional features in any appropriate combination: 1. The semiconductor body material is one of a substrate bulk material, an electrically isolated epitaxial material on the substrate, and an electrically isolated semiconductor well. 2. The semiconductor body material is electrically isolated from the substrate bulk material using at least one of trench isolation and a reverse-biased PN junction. 3. The electrically isolated current path is electrically isolated from the body material using at least one of trench isolation and a reverse-biased PN junction. 4. The electrically isolated current path extends at least 5 microns perpendicular to the surface. 5. The one or more distributed current contacts are each spaced at least 3 microns from the focus contact. 6. The sense contact arrangement is located between the focus contact and the one or more distributed current contacts. 7. The sense contact arrangement and the one or more distributed current contacts each have four-fold rotational symmetry about the focus contact. 8. The semiconductor body material is substantially homogeneous. 9. The semiconductor body material has at least one of an opening or an isolation barrier to increase the sensitivity of the Hall Effect measurement. 10. The semiconductor body material has a square mesh configuration with at least eight openings around a filled center containing an embedded current focus. 11. The square mesh configuration includes trenches extending diagonally from the electrically isolated current paths to the periphery of the mesh. 12. The method includes converting a set of voltages into measurements of two components of a magnetic field parallel to the surface and a component of the magnetic field perpendicular to the surface. 13. The method includes converting the set of voltages into measurements of a magnetic field magnitude. 14. The magnitude measurements are binary values ​​indicating the presence or absence of a magnetic field having a magnitude above a given threshold. 15. The distributed current flow is confined within a rectangular body region having a given depth and having the surface as a square. 16. The one or more distributed current contacts include four edge contacts, one adjacent each edge of the square. 17. The sense contact arrangement includes four pairs of sense contacts, each pair positioned between a focus contact and a respective one of the four edge contacts.18. The sensing method of claim 15, wherein the sensing contact arrangement has two vertical mirror symmetries. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a block diagram of an example BCD integrated circuit. [Figure 2] FIG. 1 is a block diagram of an example integrated Hall effect sensor. [Figure 3] FIG. 1 is an isometric view of a first exemplary multi-component Hall effect sensor transducer. [Figure 4] FIG. 1 is a plan view of a first exemplary multi-component Hall effect sensor transducer. [Figure 5A] FIG. 1 is a vector diagram of the single-component Hall effect. [Figure 5B] FIG. 1 is a vector diagram of the single-component Hall effect. [Figure 5C] FIG. 1 is a vector diagram of the single-component Hall effect. [Figure 6] FIG. 10 is an isometric view of a second exemplary multi-component Hall effect sensor transducer. [Figure 7] FIG. 10 is a plan view of a second exemplary multi-component Hall effect sensor transducer. [Figure 8] FIG. 1 is a flow diagram of an exemplary manufacturing method. [Figure 9A] 1 is an exemplary initial cross section. [Figure 9B] 8A is an exemplary cross-sectional view of FIG. 8 after step 806. [Figure 9C] 8A is an exemplary cross-sectional view of FIG. 8 after step 818. FIG. [Figure 9D] 8A is an exemplary cross-sectional view after step 820 of FIG. 8. [Figure 9E] 8A is an exemplary cross-sectional view after step 821 of FIG. 8. [Figure 9F] 8A-8C are cross-sectional views of an exemplary embodiment of FIG. 8 during step 822. DETAILED DESCRIPTION OF THE INVENTION

[0009] The following description and the accompanying drawings are provided for purposes of explanation, not limitation, of the present disclosure, but rather provide a basis for those skilled in the art to understand all modifications, equivalents, and alternatives falling within the scope of the appended claims.

[0010] For simplicity and clarity of illustration, elements in the figures are not necessarily drawn to scale, and like reference numerals in different figures refer to like elements. Furthermore, descriptions and details of well-known processes and components have been omitted for simplicity. While devices are described herein as having certain n-type or p-type doped regions, those skilled in the art will understand that complementary devices are also possible in accordance with embodiments of the present invention. As used herein, the terms "during," "while," and "when" are not precise terms meaning that an action occurs immediately based on an initiating action, but rather, those skilled in the art will recognize that there may be some small but reasonable delay, e.g., a propagation delay between a response initiated by an initial action. The use of the terms "approximately," "about," or "substantially" means that the value of an element has a parameter that is expected to be very close to the stated value or location. However, as is well known in the art, there is usually a small variance that prevents an action from occurring exactly as stated. It is well established in the art that a variance of up to about ten percent (10%) (and for semiconductor doping concentrations, up to twenty percent (20%)) is considered a reasonable variance from a precisely described ideal target.

[0011] As used herein, the term "oxide" is shorthand for silicon oxide, or more appropriately, silicon dioxide. "Nitride" may be used as shorthand for silicon nitride, or more appropriately, trisilicon tetranitride. "Silicide" may be used as a term for WSi2, TaSi2, CrSi2, NiSi, or other metal-silicon compounds that may be deposited to act as a surface contact or as an interface between exposed silicon and a metal surface contact. As used herein, the term "vertical" means along the z-axis, which is typically oriented perpendicular to the surface of the substrate or device body. The term "horizontal" means along an axis perpendicular to the z-axis, and thus parallel to the surface of the substrate or device body. When the term is applied to a Cartesian coordinate system, the x-axis and y-axis are each horizontal.

[0012] 1 is a diagram of an exemplary BCD (bipolar, CMOS, DMOS) integrated circuit 100 having a monolithic semiconductor substrate 101 hosting multiple semiconductor device technologies. The integrated circuit 100 may include analog circuitry 102 implemented using bipolar junction transistors and other bipolar junction devices (e.g., PN diodes, NPN transistors, PNP transistors, silicon-controlled rectifiers, JFETs), power management circuitry 104 implemented using DMOS (double-diffused metal-oxide-semiconductor) devices, digital circuitry 106 implemented using MOS (metal-oxide-semiconductor) devices (e.g., NMOS, PMOS, CMOS), and one or more embedded sensors 108, which may be implemented in the same steps used to form other devices on the substrate 101. The various device types may be isolated from one another using isolation trenches, buried layers, tubs, or other functionally similar isolation structures, but may be interconnected via appropriately patterned metal or other conductive layers deposited on the surface of the substrate, as described further below.

[0013] FIG. 2 is a block diagram of an exemplary implantable sensor 108 having an interface logic circuit 110 that controls various signal lines for a sensor transducer 112, allowing the interface logic circuit 110 to acquire sensor measurements. In this embodiment, the interface logic circuit 110 is intended to provide a bias between the focus contact signal line and the current contact signal line to provide a distributed current within the sensor transducer. Measurements of the sensor contact signal line voltage can then be used to determine the vector components of the magnetic field. The interface logic circuit 110 can include current sources that provide the desired bias and various buffers with high input impedances to detect the sense contact voltage. One or more comparators or analog-to-digital converters can be provided to convert the detected voltage into a measurement of the magnetic field component or magnitude.

[0014] FIG. 3 is an isometric view of an exemplary implementation of the sensor transducer 112. This exemplary implementation includes a mass of semiconductor body material 302 having a top surface 304. The semiconductor body material 302 may be a bulk substrate material, but preferably is an electrically isolated mass of semiconductor body material. Such isolation may be achieved, for example, by using a doped well or buried layer on the side opposite the body material 302 to provide a PN junction that can be reverse biased to prevent current from escaping the isolated mass. Alternatively, the semiconductor body material 302 may be epitaxially deposited on an insulating layer or non-conductive substrate to prevent vertical current flow into or out of the body material. To prevent horizontal current flow into or out of the body material 302, the material may be surrounded by one or more isolation trenches extending from the surface 304 to a buried layer or underlying insulator. Optionally, such isolation trenches may be filled with oxide or other insulating material to allow conductive paths to be formed between surface contacts on the semiconductor body material 302 and elsewhere on the substrate. Such isolation structures are omitted from FIG. 3, but illustrative examples are further described below in connection with FIGS. 8 and 9D.

[0015] A focus contact 306 is provided at the center of the surface 304. An isolation trench or other isolation structure 308 extends downward from the periphery of the focus contact 306, forming an electrically isolated path between the focus contact and a buried current focus 310 disposed within the semiconductor body material 302. The buried current focus 310 is an opening formed by the isolation structure 308 to allow current flow between the electrically isolated path and the surrounding material 302. The electrically isolated path extends vertically from the top surface 304, but as indicated by dimension line 312, the isolation structure 308 does not reach the isolation boundary below the semiconductor body material 302, as this would prevent current flow and therefore would not be able to provide the buried current focus 310. The interior of the isolation structure 308 includes a conductive or semiconductive material to facilitate current flow along the electrically isolated path.

[0016] One or more distributed current contacts 314 are provided on the top surface 304 that operate in combination with the embedded current focus 310 to create a distributed current flow within the semiconductor body material 302. The distributed current flow includes current flow components along each of the x-, y-, and z-axes. In FIG. 3, four contacts 314 are provided, one along each edge of the square top surface 304. An arrangement of sense contacts 316 is also provided on the top surface 304 to detect a set of voltages representing Hall Effect measurements for each three-dimensional vector component of the magnetic field acting on the distributed current flow.

[0017] In FIG. 4 , the focus contact 306 is labeled “C.” The four distributed current contacts 314 are labeled “D1,” “D2,” “D3,” and “D4.” A pair of sense contacts 316 is provided between each distributed current contact 314 and the focus contact 306. The pair of sense contacts “S11” and “S12” corresponds to the current contact D1, the pair of sense contacts “S21” and “S22” corresponds to the current contact D2, and the pairs “S31,” “S32,” and “S41,” “S42” correspond to the current contacts D3 and D4, respectively. The current contacts may be electrically connected to have the same voltage, e.g., ground. The voltage of the sense contact S is hereinafter referred to as V, e.g., V is the voltage of the sense contact S.

[0018] When the semiconductor body material 302 has p-type doping (causing valence band holes to act as majority charge carriers), the focus contact 306 is biased positively with respect to the distributed current contact 314, causing majority charge carriers to migrate outward and upward from the buried current focus 310. In this case, the sense contact 316 detects a positive voltage with respect to the current contact 314. When the semiconductor body material is n-doped (causing conduction band electrons to act as majority charge carriers), the focus contact is biased negatively with respect to the distributed current contact 314, again causing majority carriers to migrate outward and upward from the buried current focus 310. In this case, the sense contact 316 detects a negative voltage with respect to the current contact 314. The following description assumes p-type doping, but the calculations of magnetic field strength and direction remain the same for both p-type and n-type semiconductor body materials.

[0019] As shown in Figure 5A, a magnetic field oriented along the x-axis has a velocity component along the z-axis, i.e., holes moving upward from the embedded current focus experience a force along the y-axis. This induces a Hall effect voltage that is proportional to the magnetic field strength:

[0020]

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[0021]

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[0022]

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[0023] The transducer dimensions are assumed to vary based on manufacturing constraints and desired sensitivity. Figure 3 illustrates an example in which the horizontal dimension of the semiconductor body material 302 is 12 microns, the vertical dimension of the body material 302 is 10 microns, the horizontal dimension of the isolated via is 1 micron, the width of the isolation trench around the isolated via is 0.5 microns, and the vertical dimension of the via and trench is 6 microns. The current contacts are centered on each edge with a length of 4 microns and a width of 0.3 microns. The sensor contacts may each have a length of approximately 1 micron and a width of 0.3 microns and be spaced approximately 1 micron apart from the corresponding current contact. A separation of at least 3 microns may be provided between the distributed current contact and the focus contact, and the electrically isolated vias may extend at least 5 microns perpendicular to the top surface. Note that these dimensions were used to establish a proof-of-concept. It is expected that improved performance may be achieved through further optimization.

[0024] In the example of Figure 3, the semiconductor body material 302 is substantially homogeneous. This is not a requirement, and Figure 6 shows an example of a transducer 112 that includes a pattern of at least eight recesses or filled openings 622 around a filled center that contains an embedded current focus. The openings 622 form a ridge 624 having a square mesh, or "waffle," configuration. The openings 622 act as barriers to restrict and shape current flow, but the semiconductor body material may also include a floor 626 that allows current to flow beneath the openings 622. In either case, current will preferentially flow along the ridges.

[0025] Similar to the transducer of FIG. 3 , the transducer of FIG. 6 includes a current focus contact 606 and an isolation trench or other isolation structure 608 extending downward from around the focus contact to form an electrically isolated path to the buried current focus. Majority current carriers travel upward and outward from the buried current focus to reach distributed current contacts 614 on each edge of the transducer. Diagonal trenches 28 may extend from the path isolation structure 608 to the periphery of the square mesh at the corners of the semiconductor body material to enhance sensitivity to the z-axis component of the magnetic field. While not shown in FIG. 6 , it is contemplated that the various openings and trenches may be filled with oxide or other insulating material to provide a smooth top surface for supporting additional interconnect layers.

[0026] FIG. 7 is a plan view of the transducer 112 of FIG. 6. The distributed current contacts 614 are labeled D11, D12, D13, and D14 for the first edge, D21, D22, D23, and D24 for the second edge, D31, D32, D33, and D34 for the third edge, and D41, D42, D43, and D44 for the fourth edge. As previously mentioned, the distributed current contacts 614 may be interconnected and maintained at the same voltage. The sense contacts 616 are labeled S11 and S12 for the first edge, S21 and S22 for the second edge, S31 and S32 for the third edge, and S41 and S42 for the fourth edge. The current focus contact 606 is labeled C. While improved sensitivity is expected, the same principles and equations apply as in the previous transducer examples.

[0027] As previously mentioned, transducer dimensions are design parameters that are assumed to vary based on manufacturing constraints and sensitivities. Figure 7 may represent an example in which the horizontal dimensions of the transducer are approximately 140 microns, the ridge is approximately 10 microns wide, and the opening is approximately 20 microns by 20 microns square. The current focus contact C may be 8 microns by 8 microns square, and the trenches 608, 628 may be approximately 1 or 2 microns wide. The vertical dimensions of the semiconductor body material may be approximately 10 microns, and the depth of the opening 622 and trenches 608, 628 may be approximately 8 microns. The size and placement of the contacts may be parameters that are empirically optimized, for example, through simulation.

[0028] Each of the example transducers provided herein has four-fold rotational symmetry (and mirror symmetry across two perpendicular axes), which may facilitate the derivation of magnetic field components from sensing contact voltage measurements. Other symmetries, such as three-fold rotational symmetry, are also feasible. Further simplifications of the transducer geometry are possible, but such simplifications may reduce sensitivity and / or increase the complexity of the magnetic field component calculations. Instead of, or in addition to, measuring the magnetic field components, the sensor transducer can be used to determine the magnitude and direction of the magnetic field. In some contemplated examples, the calculated component or magnitude may be compared to a threshold, and a binary output may be used to indicate the presence or absence of a field strength above the threshold.

[0029] FIG. 8 is a flow diagram illustrating a sequence of process operations that may be used in an exemplary integrated circuit fabrication method. As various blocks are described, reference is made to FIGS. 9A-9F, which illustrate the formation of a sensor transducer through various steps of the method. These figures are not drawn to scale, and certain dimensions are exaggerated for the purpose of illustrating certain features. FIG. 9A is a cross-sectional view of a portion of a semiconductor wafer or other suitable substrate 902 before the fabrication process begins. The substrate material may be a single-crystal semiconductor material, a semiconductor-on-insulator substrate, a silicon layer on a glass plate, an epitaxial layer grown on a semiconductor substrate, a semiconductor material containing a Group 14 element, such as carbon, silicon, germanium, or a combination thereof, or another semiconductor material conventionally used in the fabrication of semiconductor components. According to one embodiment, the semiconductor material is lightly doped with an impurity material of p-type conductivity, i.e., a p-type dopant. Alternatively, the semiconductor material may be doped with an impurity material of n-type conductivity.

[0030] 8 shows a sequence of process operations 802-822 for providing bipolar, CMOS, and DMOS devices on a monolithic integrated circuit substrate. Some of these operations can be utilized to fabricate sensor transducers in designated areas of the substrate. It is expected that many existing processes can be adapted in this manner to provide integrated magnetic field sensors without requiring additional masks, implants, or thermal budgets.

[0031] The manufacturing process begins in block 802 by forming one or more shallow isolation structures, e.g., isolation trenches, between different regions of a semiconductor substrate to provide isolation between the multiple regions. Trenches can be formed between any adjacent regions to keep the adjacent regions electrically isolated. The isolation trenches may be formed using shallow trench isolation (STI), deep trench isolation, or local oxidation of silicon (LOCOS) techniques. During or after trench formation, a thin pad layer is formed on the surface of the semiconductor substrate using, for example, a wet oxidation technique such as an in-situ steam generation (ISSG) operation. The pad layer is preferably silicon oxide, but in practice can be any suitable dielectric material, e.g., silicon nitride. In some cases, the pad layer may be supplemented with a stop layer, e.g., a polish stop layer or an etch stop layer, that is sequentially formed on or from the semiconductor substrate material using thermal growth techniques, deposition techniques, a combination of thermal growth and deposition techniques, etc. The pad layer may be the same material as the stop layer or a different material from the stop layer.

[0032] In block 804, deep ion implantation operations may be performed to create buried layers, wells, and field plates for regions of the substrate requiring such features (e.g., at least one well or buried layer in each of at least one MOS device region and non-volatile memory region). The ability to form wells and buried layers in each of multiple regions is an advantage of the BCD process. Each feature type may be created using a corresponding photoresist layer combined with a corresponding photolithography operation to pattern the layer, creating a mask with exposed regions that allow implanted ions to reach only the regions where the feature is desired. Thus, the buried layer 904 shown in FIG. 9B may be created using a buried n-layer mask that exposes the sensor transducer region and any other areas where a buried n-layer is desired. An n-well mask may be used to create n-wells in bipolar regions, power regions, and other desired locations. A p-well mask 906 may be used to create p-wells 908 in the sensor transducer region and other desired locations. The buried layer, n-well, and p-well are doped with impurities ("dopants"), which may be implanted ions that provide the desired conductivity type, and the associated masks are removed after each use.

[0033] These deep implant operations can be followed by an annealing cycle 806 to allow the dopants to integrate with the substrate's crystalline structure while repairing dislocations and other crystallographic damage introduced during the implantation process. In block 808, the pad layer can be removed using, for example, a wet etch, before a new pad oxide or other suitable gate dielectric layer is deposited over the exposed silicon surface of the substrate. A photolithography operation, i.e., creation of a patterned mask layer with openings, is performed to allow removal of the new pad oxide or other suitable dielectric layer where no gate dielectric is desired. The exposed dielectric layer areas are removed, and the patterned mask layer is stripped. These steps can be repeated to provide additional gate oxide or dielectric layers if different thicknesses are desired (e.g., for operation at different voltage regimes).

[0034] In block 810, a layer of doped polysilicon (short for polycrystalline silicon) or another suitable conductive gate material is deposited. In block 812, another photolithography operation is performed to pattern a layer of photoresist material to form openings for removing the gate material layer where gates are not desired. Removal may be performed using reactive ion etching. Collectively, blocks 808-812 are gate formation operations that serve to form gates on the gate dielectric layer at each location for the MOSFET and DMOS devices. (The sensor transducer 112 does not include a transistor, and therefore no gates are formed in the transducer region.)

[0035] After the photoresist is stripped, another photolithography operation is performed in block 814 to create a source-drain mask with openings that expose areas where it is desired to provide the transistor's source and drain or other shallow-doped regions. Ion implantation can be used to form these shallow-doped regions. The existing gate structure provides screening for the channel region, allowing the source and drain regions to be self-aligned. The mask is then stripped, followed by the optional deposition of a conformal oxide or suitable dielectric layer, e.g., on the order of 20 nm to 500 nm, to insulate the sides of the gate electrode. An etching or polishing operation can then be performed to expose at least a portion of the top surface of the gate electrode.

[0036] At block 816, another photolithography operation is performed to form an n+ region mask, i.e., a patterned layer exposing regions where it is desired to provide heavy n-type doping for ohmic contact between the n-type region and the conductive overlayer. An ion implantation operation may be performed to form these n+ ohmic regions.

[0037] After stripping the patterned layer, similar operations can be performed in block 818 to form a p+ region mask 910 and provide heavily p-type doped regions 912, 914 as shown in FIG. 9C for ohmic contact between the p-type region and the conductive overlayer.

[0038] In block 820, another photolithography operation is performed using etching and oxidation to provide subsequent trench isolation in a manner similar to the operation of block 802. The trenches formed in block 820 may be wider and deeper than the shallow trenches of block 802, which could potentially cause problems with thermal expansion mismatch if performed earlier in the manufacturing process. Figure 9D shows isolation trenches 916 extending from the top surface downward toward the buried layer 904 to define a buried current focus 917 just above the buried layer 904, and deeper isolation trenches 918 reaching into the buried layer 904 to separate the transducer's semiconductor body material 902 from the bulk material of the substrate.

[0039] In block 821, as shown in Figure 9E, similar photolithographic operations using silicide, refractory metals (e.g., nickel, titanium, platinum, cobalt, tungsten, iridium), or other suitable conductive contact materials can be used to form conductive surface contacts 920 and gate contacts after surface exposure etching. These surface contacts 920 connect to ohmic contacts in the transducer and other device regions of the substrate.

[0040] Thereafter, in block 822, a thicker oxide or other suitable dielectric layer 922 (e.g., on the order of 20 nm to about 500 nm) may be deposited and planarized prior to the formation and filling of vias 924 that provide electrical connection to surface contacts 920, as shown in Figure 9F. The via filling may be performed simultaneously with the deposition of a first layer of metal or other conductive material, which may be patterned using standard photolithography operations to form connections between transistors and other devices formed in the substrate.

[0041] Additional layers and "metal" layers may be provided in block 822 before forming a final passivation layer with openings for external connections to the integrated circuit. Standard packaging techniques may be applied, such as wire bonding to a lead frame during the encapsulation process, or multi-chip manufacturing where a chip is bonded to another chip or an interposer that provides additional lead routing.

[0042] Note that FIG. 9F also shows the confined current flow in the electrically isolated path defined by trench 916 to reach buried current focus 917, and further shows dashed lines indicating distributed current flow from buried current focus 917. The distributed current flow is directed upward along the z-axis and outward along the x- and y-axes to reach the distributed current contacts. The dashed lines indicate the movement of holes in p-type semiconductor material. In n-type semiconductor material, the majority carriers are electrons moving upward and outward in this manner. It is the effect of a magnetic field on this distributed current that produces a set of voltages that can be detected by the sense contacts and converted into a measurement of the magnetic field.

Claims

1. 1. An integrated circuit device comprising: a substrate comprising a semiconductor body material having a top surface; a focus contact on the top surface connecting to an embedded current focus through an electrically isolated path within the body material; one or more distributed current contacts on the top surface configured to operate in combination with the embedded current focus to form a distributed current flow through the body material; an arrangement of sense contacts on the top surface configured to detect a set of voltages representing Hall effect measurements for each three-dimensional vector component of a magnetic field acting on the distributed current flow.

2. the semiconductor body material is one of a bulk material of the substrate, an electrically isolated epitaxial material on the substrate, and an electrically isolated semiconductor well; 10. The integrated circuit device of claim 1, wherein the semiconductor body material is electrically isolated from the substrate bulk material using at least one of trench isolation and a reverse-biased PN junction.

3. 10. The integrated circuit device of claim 1, wherein the electrically isolated path is electrically isolated from the body material using at least one of trench isolation and a reverse-biased PN junction.

4. the electrically isolated vias extend perpendicular to the top surface for at least 5 microns; each of the one or more distributed current contacts is spaced at least 3 microns from the focus contact; and the sensing contact is positioned between the focus contact and the one or more distributed current contacts; 2. The integrated circuit device of claim 1, wherein the arrangement of the sense contacts and the one or more distributed current contacts each have four-fold rotational symmetry about the focus contact.

5. forming a distributed current flow between the embedded current focus and one or more distributed current contacts on a surface of the body, the distributed current flow exhibiting a Hall effect when acted upon by a magnetic field; detecting a set of voltages using an arrangement of sense contacts on the surface of the body, the arrangement providing distinguishable sensitivity to the Hall effect induced by two components of the magnetic field parallel to the surface and by one component of the magnetic field perpendicular to the surface.

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