Signal output device

Abstract

To provide a signal output device capable of outputting a desired input signal from a multiplexer stably with good accuracy.SOLUTION: The signal output device comprises a multiplexer, a control circuit, and a delay circuit. The control circuit is capable of outputting, to the multiplexer, a selection signal for the multiplexer to select an input signal to be outputted among a plurality of input signals, and an enable signal for enabling or disabling the multiplexer. The multiplexer is disabled when the voltage level of the enable signal is at a first level and enabled when the voltage level of the enable signal is at a second level different from the first level, and selects and outputs one of the plurality of input signals in accordance with the selection signal. The delay circuit delays a transition from the first level to the second level of the enable signal outputted from the control circuit before outputting the enable signal to the multiplexer.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a signal output device including a multiplexer. [Background technology]

[0002] Conventionally, multiplexers that select and output one of a plurality of input signals have been known (see, for example, Patent Document 1). A multiplexer receives control signals, such as a selection signal and an enable signal, output from a control circuit such as a microcomputer. The selection signal is a control signal that causes the multiplexer to select an input signal to output from the plurality of input signals. The enable signal is a control signal that indicates whether the multiplexer is enabled or disabled. When the input enable signal indicates that the multiplexer is enabled, the multiplexer selects and outputs one of the plurality of input signals in accordance with the input selection signal. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 9-246928 Summary of the Invention [Problem to be solved by the invention]

[0004] When switching the input signals to be output from a multiplexer, a control circuit may switch the voltage levels of multiple control signals, such as a select signal and an enable signal, that are output to the multiplexer. However, due to the characteristics of the control circuit, it is difficult for the control circuit to simultaneously switch the voltage levels of multiple control signals, and a time lag generally occurs during the switching. In the past, this time lag in switching the voltage levels of the control signals has caused a problem in that the desired input signals cannot be accurately and stably output from the multiplexer. For example, during a transition when switching the input signals to be output from the multiplexer, the voltage level of the enable signal switches first to enable the multiplexer, and then the voltage level of the select signal switches later, resulting in a problem of the input signals being switched multiple times.

[0005] SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a signal output device that can output a desired input signal from a multiplexer with high accuracy and stability. [Means for solving the problem]

[0006] In order to solve the above problems, the signal output device of the present invention comprises a multiplexer capable of selecting and outputting one of a plurality of input signals, a control circuit for controlling the multiplexer, and a delay circuit arranged between the multiplexer and the control circuit, wherein the control circuit is capable of outputting to the multiplexer a selection signal for causing the multiplexer to select an input signal to be output from the plurality of input signals, and an enable signal indicating whether the multiplexer is enabled or disabled, the multiplexer is disabled when the voltage level of the enable signal is at a first level, and is enabled when the voltage level of the enable signal is at a second level different from the first level, and selects and outputs one of the plurality of input signals in accordance with the selection signal, and the delay circuit delays the transition of the enable signal output from the control circuit from the first level to the second level, and outputs the enable signal to the multiplexer.

[0007] According to the above configuration, the transition of the enable signal input to the multiplexer from the first level to the second level is delayed, so that the point in time at which the multiplexer is enabled can be delayed. This allows the multiplexer to be enabled after the switching of the selection signal input to the multiplexer is completed, so that the desired input signal can be output from the multiplexer with high accuracy and stability.

[0008] Furthermore, the signal output device of the present invention may include a plurality of the multiplexers, a plurality of the delay circuits corresponding to each of the plurality of multiplexers, the control circuit may be capable of outputting the enable signal individually to each of the plurality of multiplexers, and each of the plurality of delay circuits may delay the transition from the first level to the second level in the enable signal output from the control circuit to the corresponding multiplexer, and output the enable signal to the corresponding multiplexer.

[0009] According to the above configuration, even when desired input signals are output from each of a plurality of multiplexers, the input signals can be output stably with high accuracy.

[0010] In addition, in the signal output device of the present invention, each of the plurality of delay circuits may output the enable signal to the corresponding multiplexer without delaying the transition from the second level to the first level in the enable signal output from the control circuit to the corresponding multiplexer.

[0011] According to the above configuration, it is possible to reduce the possibility that a plurality of multiplexers will be enabled at the same time, and therefore it is possible to prevent the input signal output from the signal output device from becoming unstable. [Effects of the Invention]

[0012] According to the present invention, a desired input signal can be output from a multiplexer with high accuracy and stability. [Brief explanation of the drawings]

[0013] [Figure 1] 1 is a block diagram showing an electrical configuration of a signal output device according to an embodiment of the present invention. [Figure 2] FIG. 2 is a diagram illustrating a truth table of the multiplexer illustrated in FIG. [Figure 3] FIG. 2 is an electrical configuration diagram of the delay circuit shown in FIG. [Figure 4] 4 is a timing chart of control signals input to a multiplexer according to the present embodiment. [Figure 5] FIG. 10 is a block diagram showing the electrical configuration of a signal output device according to a comparative example. [Figure 6] 10 is a timing chart of control signals input to a multiplexer according to a comparative example. DETAILED DESCRIPTION OF THE INVENTION

[0014] An embodiment of the present invention will be described with reference to FIGS. 1 to 6. A signal output device 1 of this embodiment is a device that selects and outputs one of a plurality of input signals. For example, in a charging device capable of charging a plurality of storage batteries, the signal output device 1 is provided in the upstream stage of a monitoring mechanism that monitors the voltage values ​​of each storage battery during charging. In the charging device, the signal output device 1 receives a plurality of input signals indicating the voltage values ​​of each storage battery, selects one of them, and outputs it to the downstream monitoring mechanism. The signal output device 1 also sequentially switches the input signals to be output. This enables the monitoring mechanism to sequentially monitor the voltage values ​​of each of the plurality of storage batteries during charging.

[0015] The signal output device 1 of this embodiment shown in FIG. 1 selects and outputs one of 32 input signals. The signal output device 1 includes two multiplexers 2a and 2b, a control circuit 3, and two delay circuits 4a and 4b. Hereinafter, when the multiplexers 2a and 2b are not distinguished from each other or are referred to collectively, they will be referred to as "multiplexer 2." Furthermore, when the two delay circuits 4a and 4b are not distinguished from each other or are referred to collectively, they will be referred to as "delay circuit 4."

[0016] The multiplexer 2 is a circuit that selects and outputs one of a plurality of input signals supplied from an external device. In this embodiment, the multiplexer 2 is a 16-input, 1-output multiplexer that receives 16 input signals, selects one of the input signals, and outputs the selected signal. For example, when the signal output device 1 is installed in a multi-output power supply device, the input signal is an analog signal indicating an output voltage value.

[0017] The multiplexer 2 is provided with 16 input terminals S1 to S16, one output terminal D, one enable terminal EN, and four address terminals A0 to A3.

[0018] Each of the input terminals S1 to S16 is a terminal to which an externally supplied input signal is input. The output terminal D is a terminal that outputs an input signal selected by the multiplexer 2. The output terminals D of the two multiplexers 2a and 2b are connected to a common circuit in the subsequent stage (for example, an A / D converter that converts an analog signal into a digital signal).

[0019] The enable terminal EN is a terminal to which an enable signal output from the control circuit 3 is input. The enable signal is a binary digital signal that indicates whether the multiplexer 2 is enabled (active) or disabled (inactive) (see FIG. 2).

[0020] Each of the address terminals A0 to A3 is a terminal to which a selection signal output from the control circuit 3 is input. The selection signal is a binary digital signal that causes the multiplexer 2 to select one input signal from among 16 input signals (see FIG. 2).

[0021] Fig. 2 is a truth table of the multiplexer 2 of this embodiment. The truth table in Fig. 2 shows the relationship between the voltage levels of the enable terminal EN and address terminals A0 to A3 of the multiplexer 2 and the input terminals S1 to S16 to which the input signals output from the multiplexer 2 are input. In Fig. 2, "1" indicates a high-level voltage level, and "0" indicates a low-level voltage level.

[0022] 2, multiplexer 2 is disabled when the voltage level of the enable signal input to enable terminal EN is low (corresponding to "first level"), and does not output a signal from output terminal D regardless of the selection signals input to address terminals A0 to A3. On the other hand, multiplexer 2 is enabled when the voltage level of the enable signal input to enable terminal EN is high (corresponding to "second level"), and selects an input signal to output from among 16 input signals according to the four selection signals input to address terminals A0 to A3.

[0023] The control circuit 3 is a microcomputer equipped with a processor such as a CPU, and memories such as a Read Only Memory (ROM) and a Random Access Memory (RAM). The CPU executes various programs stored in the ROM while utilizing the temporary storage function of the RAM, thereby performing various processes such as the switching process described below.

[0024] 1, the control circuit 3 is provided with two enable terminals MEN0 and MEN1 and four address terminals MA0 to MA3. The two enable terminals MEN0 and MEN1 correspond to the two multiplexers 2 and are terminals for outputting enable signals to the corresponding multiplexers 2. Each of the four address terminals MA0 to MA3 is a terminal for outputting a common selection signal to the two multiplexers 2. That is, the control circuit 3 outputs the enable signal individually to each of the multiplexers 2 via the enable terminals MEN0 and MEN1. On the other hand, the control circuit 3 outputs the four selection signals commonly to the two multiplexers 2 via the address terminals MA0 to MA3.

[0025] In the above configuration, the control circuit 3 executes a program stored in the ROM to perform a switching process for switching the input signal to be output from the signal output device 1. Specifically, the control circuit 3 sets the voltage level of the enable signal to be output to one of the two multiplexers 2, the multiplexer 2 having input terminals S1 to S16 to which the input signal to be output is input (hereinafter also referred to as the multiplexer 2 to be output), to a High level, and sets the voltage level of the enable signal to be output to the other multiplexer 2 to a Low level. The control circuit 3 also switches the voltage levels of the four selection signals so that the input signal to be output is output from the multiplexer 2. In this way, the input signal to be output from the signal output device 1 can be switched.

[0026] The two delay circuits 4a, 4b correspond to the two multiplexers 2 and are respectively arranged between the corresponding multiplexers 2 and the control circuit 3. Specifically, the delay circuit 4a corresponds to the multiplexer 2a and is arranged between the enable terminal EN of the multiplexer 2a and one enable terminal MEN0 of the control circuit 3. The delay circuit 4b corresponds to the multiplexer 2b and is arranged between the enable terminal EN of the multiplexer 2b and the other enable terminal MEN1 of the control circuit 3.

[0027] Each of the delay circuits 4 is a circuit that delays the rising edge (transition from low level to high level) of the enable signal output from the control circuit 3 to the corresponding multiplexer 2, but does not delay the falling edge (transition from high level to low level).

[0028] As shown in Figure 3, the delay circuit 4 includes resistors R1 and R2, Schmitt trigger inverters STI1 and STI2, diodes DO1 and DO2, and a capacitor C. One end of the resistor R1 is connected to a node N1, and the other end is grounded. The node N1 is the input node of the delay circuit 4, and is connected to enable terminals MEN0 and MEN1 of the control circuit 3. The Schmitt trigger inverter STI1 has one end connected to the node N1 and the other end connected to a node N2.

[0029] The anode of the diode DO1 is connected to the node N2 and the cathode is connected to the node N3. The resistor R2 and the capacitor C form an RC circuit, and one end of the resistor R2 is connected to the node N2. The anode of the diode DO2 is connected to the node N3 and the cathode is connected to the common node of the resistor R2 and the capacitor C.

[0030] The Schmitt trigger inverter STI2 has one end connected to the node N3 and the other end connected to a node N4, which is the output node of the delay circuit 4 and is connected to the enable terminal EN of the multiplexer 2.

[0031] In the above configuration of delay circuit 4, we will first explain what happens when the enable signal input to delay circuit 4 from control circuit 3 falls from high to low. When the enable signal output from control circuit 3 falls, the voltage at node N1, which is the input terminal of delay circuit 4, also changes from high to low. When the voltage at node N1 changes from high to low, the Schmitt trigger inverter STI1 causes the voltage at node N2 to change from low to high. At this time, diode DO1 connected to node N2 becomes forward biased, allowing current to flow, and the voltage at node N3 also immediately changes from low to high. Then, the voltage at node N4 changes from high to low due to the Schmitt trigger inverter STI2. As described above, when the enable signal input to delay circuit 4 falls from high to low, the enable signal output from delay circuit 4 to multiplexer 2 also immediately falls from high to low.

[0032] Next, we will explain what happens when the enable signal input from the control circuit 3 to the delay circuit 4 rises from low to high. When the enable signal output from the control circuit 3 rises, the voltage at node N1, which is the input terminal of the delay circuit 4, also changes from low to high. When the voltage at node N1 changes from low to high, the Schmitt trigger inverter STI1 causes the voltage at node N2 to change from high to low. At this time, the diode DO1 connected to node N2 becomes reverse biased, and no current flows through the diode DO1. Therefore, the voltage at node N3 changes from high to low with a delay from the point at which the voltage at node N2 changes, due to the RC circuit of resistor R2 and capacitor C. Then, when the voltage at node N3 changes from high to low, the Schmitt trigger inverter STI2 causes the voltage at node N4 to change from low to high. As described above, when the enable signal input to the delay circuit 4 rises from low to high, the enable signal output from the delay circuit 4 to the multiplexer 2 rises from low to high after a predetermined delay time. The delay time is determined by the time constant of the RC circuit of the resistor R2 and the capacitor C.

[0033] As described above, in the signal output device 1 of this embodiment, the delay circuit 4 delays the rising edge of the enable signal output from the control circuit 3, and the enable signal is output to the multiplexer 2. On the other hand, the falling edge of the enable signal output from the control circuit 3 to the multiplexer 2 is not delayed. Furthermore, the four selection signals output from the control circuit 3 to the multiplexer 2 are not delayed.

[0034] Before describing the effects of the signal output device 1 of this embodiment, we will now describe problems that arise in a signal output device (hereinafter referred to as a comparative example) that does not have the delay circuit 4. In the signal output device 100 of the comparative example, the enable signal and the selection signal output from the control circuit 3 are both input to the multiplexer 2 without being delayed. As shown in FIG. 5, the signal output device 100 of the comparative example is substantially similar to the signal output device 1 of this embodiment, except that it does not have the delay circuit 4. Therefore, in the signal output device 100 of the comparative example, components that correspond to those of the signal output device 1 of this embodiment are assigned the same reference numerals, and descriptions thereof will be omitted.

[0035] As described above, when the control circuit 3 executes the switching process to switch the input signals to be output from the signal output device 100, it switches the voltage levels of the enable signals output individually to each of the two multiplexers 2 and the four selection signals output commonly to the two multiplexers 2. However, due to the characteristics of the control circuit 3, it is difficult for the control circuit 3 to simultaneously switch the voltage levels of these multiple control signals, and a time lag generally occurs in the switching. For example, a time lag of the order of 10 μs due to software inside the control circuit 3 and a time lag of the order of 1 μs due to hardware may occur.

[0036] Furthermore, due to its characteristics, the control circuit 3 may switch the voltage levels of the four selection signals after the switching of the voltage level of the enable signal is completed during the switching process. In this case, the voltage level of the enable signal switches from low to high first, enabling the multiplexer 2, and then the voltage levels of the four selection signals input to the multiplexer 2 are switched. As a result, the input signal output from the multiplexer 2 switches multiple times. Furthermore, it may also occur that the enable signal input to the multiplexer 2 targeted for output in a subsequent switching process rises before the enable signal input to the multiplexer 2 targeted for output in a previous switching process falls. In this case, two multiplexers 2 are enabled simultaneously, which may cause the input signal output from the signal output device 100 to become unstable.

[0037] Specifically, the following description will be given of an example in which the control circuit 3 switches the input signal to be output from the signal output device 100 from the input signal input to the input terminal S12 (A0=1, A1=0, A2=1, A3=1) of the multiplexer 2a to the input signal input to the input terminal S1 (A0=0, A1=0, A2=0, A3=0) of the multiplexer 2b during the switching process. This switching process requires changing the voltage levels of the enable signals input to the enable terminals EN of the two multiplexers 2a and 2b and the voltage levels of the selection signals input to the address terminals A0, A2, and A3. However, as described above, the control circuit 3 cannot simultaneously switch the voltage levels of these multiple control signals. As a result, for example, as shown in FIG. 6, the enable signal input to the enable terminal EN of the multiplexer 2b rises before the enable signal input to the enable terminal EN of the multiplexer 2a falls. In this case, the two multiplexers 2a and 2b are enabled at the same time, and the input signals are output from the two multiplexers 2a and 2b, which may cause the input signals output from the signal output device 100 to become unstable.

[0038] Furthermore, after the enable signal input to the enable terminal EN of the multiplexer 2b rises, the voltage levels of the selection signals input to the address terminals A0, A2, and A3 of the multiplexer 2b are switched in sequence. Therefore, after the multiplexer 2b is enabled, the input signal output from the multiplexer 2b is switched multiple times in sequence, such as "the input signal input to the input terminal S12 (A0=1, A1=0, A2=1, A3=1)", "the input signal input to the input terminal S4 (A0=0, A1=0, A2=1, A3=1)", "the input signal input to the input terminal S2 (A0=0, A1=0, A2=0, A3=1)", and "the input signal input to the input terminal S1 (A0=0, A1=0, A2=0, A3=0)". In this way, after the multiplexer 2b is enabled, an input signal different from the input signal to be output is output from the multiplexer 2b, which causes a problem of a decrease in the output accuracy of the signal output device 100.

[0039] As described above, the configuration of the signal output device 100 of the comparative example poses a problem in that when the control circuit 3 performs switching processing, the signal output device 100 cannot output a desired input signal accurately and stably.

[0040] In contrast to this, the signal output device 1 of this embodiment includes a delay circuit 4 that delays only the rising edge of the enable signal output from the control circuit 3 and outputs the enable signal to the multiplexer 2.

[0041] As shown in Figure 4, when the control circuit 3 performs a switching process to change the multiplexer 2 to be the output target, the delay circuit 4 can delay the point in time when the enable signal input to the multiplexer 2 to be the output target of the subsequent switching process goes high. In other words, the period from when the control circuit 3 starts the switching process to when the multiplexer 2 to be the output target of the switching process becomes enabled can be lengthened. As a result, the enable signals input to both multiplexers 2 go low, creating a period in which all multiplexers 2 are disabled (hereinafter referred to as the non-output period). During this non-output period, no input signal is output from the signal output device 1.

[0042] Then, by the time the non-output period ends, the voltage levels of the four selection signals output from the control circuit 3 to the multiplexer 2 are switched. As a result, by the time the multiplexer 2 to be output in the subsequent switching process becomes enabled, the other multiplexers 2 are disabled and the switching of the voltage levels of the four selection signals has been completed. This allows the input signals output from the signal output device 1 to be output accurately and stably.

[0043] The delay time by which the delay circuit 4 delays the rising edge of the enable signal is set as follows: That is, when the control circuit 3 performs switching processing, the time points at which the voltage levels of each control signal change are actually confirmed in advance using a measuring device or the like. Then, the delay time is set so that the enable signal rises with a predetermined margin from the time point at which the voltage levels of all four selection signals change.

[0044] The margin is set to a time that does not adversely affect other circuits, such as circuits downstream of the signal output device 1. Specifically, the longer the margin, the more accurately and stably the input signal can be output from the signal output device 1; however, the longer the time required for one switching process. Therefore, when the control circuit 3 executes a switching process at predetermined intervals to sequentially switch the input signal to be output, the shorter the period from the end of one switching process to the start of the next switching process. In other words, the period during which the input signal to be output from the signal output device 1 is output is shortened. As a result, for example, a circuit downstream of the signal output device 1 may not be able to reliably acquire the input signal output from the signal output device 1. Therefore, the margin is set to a time that does not adversely affect other circuits. Note that the delay time of the delay circuit 4 is determined by the time constant of the RC circuit of the resistor R2 and the capacitor C, as described above. Therefore, the delay time may be determined taking into account the availability of the resistance value of the resistor R2 and the capacitance of the capacitor C.

[0045] As in the comparative example described above, the following describes an example in which the control circuit 3 switches the input signal to be output from the signal output device 1 during the switching process in this embodiment from the input signal input to the input terminal S12 (A0=1, A1=0, A2=1, A3=1) of the multiplexer 2a to the input signal input to the input terminal S1 (A0=0, A1=0, A2=0, A3=0) of the multiplexer 2b.

[0046] 4, the rising edge of the enable signal input to the enable terminal EN of multiplexer 2b is delayed by delay circuit 4. On the other hand, the falling edge of the enable signal input to the enable terminal EN of multiplexer 2a is not delayed. As a result, after the enable signal input to the enable terminal EN of multiplexer 2a falls, the enable signal input to the enable terminal EN of multiplexer 2b rises. This prevents the two multiplexers 2a and 2b from being enabled at the same time.

[0047] Furthermore, by the time the non-output period in which the two multiplexers 2a and 2b are disabled ends, the switching of the voltage level of the selection signal input to the address terminals A0, A2, and A3 of the multiplexer 2b has been completed. Therefore, after the multiplexer 2b is enabled, the only input signal output from the multiplexer 2b is the input signal input to the input terminal S1. In this way, after the multiplexer 2b is enabled, only the input signal to be output is output from the multiplexer 2b.

[0048] As described above, in the configuration of the signal output device 1 of this embodiment, when the control circuit 3 performs a switching process to change the multiplexer 2 to which the output is to be made, the desired input signal can be output from the signal output device 100 with high accuracy and stability.

[0049] Next, a case will be described in which the control circuit 3 performs switching processing without changing the multiplexer 2 to be output. In this switching processing, it is not necessary to switch the voltage levels of the enable signals output to each of the two multiplexers 2a and 2b, but it is necessary to switch only the voltage levels of the four selection signals. Due to the characteristics of the control circuit 3, there is a time difference in the timing at which the voltage levels of the four selection signals switch. Therefore, even in this switching processing that does not change the multiplexer 2 to be output, strictly speaking, the input signal output from the signal output device 1 may switch multiple times, and an input signal different from the output target may be output.

[0050] However, due to the characteristics of the control circuit 3, there is a time difference between the timing at which the voltage levels of the four selection signals change, but this time difference is not very large. That is, the time difference between the timing at which the voltage levels of the four selection signals change is smaller than the time difference between the timing at which the voltage level of the enable signal changes and the timing at which the voltage levels of each selection signal change. Therefore, during the switching process, the period during which an input signal different from the input signal to be output is output from the signal output device 1 is relatively short, and the impact on other circuits is also relatively small. Therefore, if the impact on other circuits is within an acceptable range, in a switching process that does not change the multiplexer 2 to be output, the voltage level of the enable signal output to the multiplexer 2 to be output is maintained at a high level, and the voltage levels of the four selection signals are switched while the multiplexer 2 to be output is kept enabled.

[0051] On the other hand, if the effect on other circuits is outside the acceptable range, the control circuit 3 temporarily sets the voltage level of the enable signal output to the multiplexer 2 to a low level at the start of the switching process, thereby disabling all multiplexers 2, including the multiplexer 2 to be output. The control circuit 3 then switches the voltage level of the enable signal output to the multiplexer 2 to be output from a low level to a high level and switches the voltage levels of the four selection signals. At this time, the rising edge of the enable signal output to the multiplexer 2 to be output is delayed by the delay circuit 4, so that the multiplexer 2 to be output is enabled after the switching of the voltage levels of the four selection signals is completed. As a result, although the processing time is increased by the amount of time required to temporarily disable all multiplexers 2, the possibility of the input signal output from the signal output device 1 being switched multiple times can be reliably reduced, allowing the signal output device 1 to accurately and stably output the desired input signal.

[0052] As described above, in the signal output device 1 of this embodiment, by arranging a delay circuit 4 that delays the rising edge of the enable signal between the control circuit 3 and the multiplexer 2, the input signal can be output from the signal output device 1 with high accuracy and stability.

[0053] Although the preferred embodiments of the present invention have been described above, the present invention is not limited to the above-described embodiments and various modifications are possible within the scope of the claims. For example, in the above-described embodiments, the number of multiplexers 2 provided in the signal output device 1 is two, but this is not limiting and the number of multiplexers may be three or more.

[0054] The signal output device may also include only one multiplexer. When there is only one multiplexer, the multiplexer to which signals are output does not change, so essentially, it is sufficient to always output an enable signal with a high voltage level to that single multiplexer. However, as described above, due to the characteristics of the control circuit, a time lag occurs in the timing at which the voltage levels of the selection signals change during the switching process. This could result in an input signal different from the input signal to be output from the signal output device, affecting other circuits. Therefore, at the start of the switching process, the control circuit temporarily sets the voltage level of the enable signal output to the multiplexer to a low level to disable the multiplexer. Then, the control circuit switches the voltage level of the enable signal output to the multiplexer from a low level to a high level and switches the voltage level of the selection signal. At this time, the rising edge of the enable signal output to the multiplexer is delayed by the delay circuit, so the multiplexer is enabled after the voltage level of the selection signal has changed. As a result, it is possible to reduce the possibility that the input signal output from the multiplexer will be switched multiple times, and it is possible to output the desired input signal from the signal output device with high accuracy and stability.

[0055] In the above embodiment, the delay circuit 4 is a circuit that delays only the rising edge of the enable signal to prevent multiple multiplexers 2 from being simultaneously enabled. However, this is not limited to this, and the delay circuit may be a circuit that delays both the rising edge and the falling edge. For example, if the signal output device has only one multiplexer, the delay circuit may be a circuit that delays both the rising edge and the falling edge. Even if the signal output device has multiple multiplexers, the time difference between the timing at which the voltage levels of multiple enable signals change during the switching process may not be very large due to the characteristics of the control circuit. In other words, even if the delay circuit delays the falling edge of the enable signal as well as the rising edge, the period during which multiple multiplexers are simultaneously enabled may be very short, and the impact on other circuits may be relatively small. In such cases, the delay circuit may delay the falling edge of the enable signal as well as the rising edge.

[0056] The delay circuit may be any circuit that can at least delay the rising edge of the enable signal, and the circuit configuration is not limited to the circuit configuration of the above-described embodiment.

[0057] In the above embodiment, the multiplexer 2 is a circuit that is enabled when the enable signal is at a high level and disabled when the enable signal is at a low level, but this is not limiting, and the multiplexer may be a circuit that is enabled when the enable signal is at a low level and disabled when the enable signal is at a high level. In this case, the delay circuit delays the fall of the enable signal output from the control circuit from a high level (corresponding to a "first level") to a low level (corresponding to a "second level") and outputs the enable signal to the multiplexer.

[0058] In the above-described embodiment, the delay time by which the delay circuit 4 delays the rising edge of the enable signal is fixed, but it may be variable. For example, a detection device may be provided that detects the time difference in the timing at which the voltage levels of the control signals output from the control circuit are switched, and the control circuit may be configured to automatically change the delay time of the delay circuit according to the time difference detected by the detection device. [Explanation of symbols]

[0059] 1 Signal output circuit 2 Multiplexer 3 Control Circuit 4 Delay Circuit

Claims

1. a multiplexer capable of selecting and outputting one of a plurality of input signals; a control circuit for controlling the multiplexer; a delay circuit disposed between the multiplexer and the control circuit; Equipped with The control circuit a selection signal for causing the multiplexer to select an input signal to be output from among the plurality of input signals, and an enable signal indicating whether the multiplexer is enabled or disabled, The multiplexer When the voltage level of the enable signal is at a first level, the enable signal is disabled; The enable signal is enabled when the voltage level of the enable signal is a second level different from the first level, Selecting and outputting one of the plurality of input signals in response to the selection signal; The delay circuit a signal output device that delays a transition from the first level to the second level in the enable signal output from the control circuit and outputs the enable signal to the multiplexer;

2. The multiplexer is provided in plurality, a plurality of the delay circuits are provided corresponding to the plurality of multiplexers, the control circuit is capable of outputting the enable signal individually to each of the plurality of multiplexers; 2. The signal output device according to claim 1, wherein each of the plurality of delay circuits delays a transition from the first level to the second level in the enable signal output from the control circuit to the corresponding multiplexer, and outputs the enable signal to the corresponding multiplexer.

3. 3. The signal output device according to claim 2, wherein each of the plurality of delay circuits outputs the enable signal to the corresponding multiplexer without delaying a transition from the second level to the first level in the enable signal output from the control circuit to the corresponding multiplexer.

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