Differential amplifier, offset adjusting device, and adjusting method for input offset voltage of differential amplifier using the same

Abstract

To provide a technique enabling the reduction of an input offset voltage of a differential amplifier with a simpler structure.SOLUTION: A differential amplifier 10 includes a non-inversion input terminal INP that receives a first input voltage, an inversion input terminal INN that receives a second input voltage, and an input stage 100 including an input differential pair 102 including a first MOS transistor with a base connected to the non-inversion input terminal and a second MOS transistor with a base connected to the inversion input terminal. In the input stage 100, when the non-inversion input terminal INP and the inversion input terminal INN receive the first input voltage and the second input voltage according to the result of measuring the input offset voltage of the differential amplifier 10, respectively, the voltage is applied between a source and a drain of the first MOS transistor or the second MOS transistor so that the input offset voltage of the differential amplifier 10 is reduced.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present disclosure relates to a differential amplifier, an offset adjustment device, and a method for adjusting the input offset voltage of a differential amplifier using the same. [Background technology]

[0002] A differential amplifier (op-amp) is used to amplify the difference between two input voltages. For example, Patent Document 1 discloses an op-amp that amplifies two input voltages input to an input differential pair to generate an output voltage. This input differential pair has two MOS (Metal Oxide Semiconductor) transistors. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2019-96970

[0004] [overview] However, the inventors have come to recognize the following problem: In the operational amplifier described in Patent Document 1, the pairing of the threshold voltages of the two MOS transistors in the input differential pair is important, and if this pairing is misaligned, an input offset voltage occurs in the operational amplifier.

[0005] The present disclosure has been made in light of these circumstances, and one of its exemplary purposes is to provide a technique that can reduce the input offset voltage of a differential amplifier with a simpler configuration.

[0006] One aspect of the present disclosure is a differential amplifier. The differential amplifier includes a non-inverting input terminal receiving a first input voltage, an inverting input terminal receiving a second input voltage, and an input stage including an input differential pair having a first MOS transistor whose base is connected to the non-inverting input terminal and a second MOS transistor whose base is connected to the inverting input terminal. The input stage is configured such that, when the non-inverting input terminal and the inverting input terminal receive the first input voltage and the second input voltage corresponding to a measurement result of the input offset voltage of the differential amplifier, respectively, a voltage is applied between the source and drain of the first MOS transistor or the second MOS transistor so as to reduce the input offset voltage of the differential amplifier.

[0007] Another aspect of the present disclosure is an offset adjustment device that adjusts the input offset voltage of the differential amplifier. The offset adjustment device includes an input voltage source that generates a first input voltage and the second input voltage, an offset measuring device that measures the input offset voltage of the differential amplifier, and a voltage control unit that controls the source-drain voltages of the first MOS transistor and the second MOS transistor. The input voltage source generates the first input voltage and the second input voltage according to a measurement result of the input offset voltage by the offset measuring device. The voltage control unit controls the source-drain voltage of the first MOS transistor or the second MOS transistor so as to reduce the input offset voltage of the differential amplifier when the non-inverting input terminal and the inverting input terminal receive the first input voltage and the second input voltage according to the measurement result of the input offset voltage of the differential amplifier, respectively.

[0008] Another aspect of the present disclosure is a method for adjusting the input offset voltage of the differential amplifier using the offset adjustment device, the adjustment method including: the offset measuring device measuring the input offset voltage of the differential amplifier; the input voltage source generating the first input voltage and the second input voltage according to the measurement result of the input offset voltage by the offset measuring device; and the voltage control unit applying a voltage between the source and drain of the first MOS transistor or the second MOS transistor so as to reduce the input offset voltage.

[0009] Any combination of the above components and conversion of the expression of the present disclosure between methods, devices, systems, etc. are also valid aspects of the present disclosure. [Brief explanation of the drawings]

[0010] [Figure 1] FIG. 1 is a block diagram showing an offset adjustment system for a differential amplifier according to the first embodiment. [Figure 2] FIG. 2 is a circuit diagram of the differential amplifier according to the first embodiment. [Figure 3] FIG. 3 is a circuit diagram of an SRAM according to the reference technique. [Figure 4] FIG. 4 is a diagram showing a voltage curve in an SRAM according to the reference technology. [Figure 5] FIG. 5 is a flowchart showing an example of a method for adjusting the input offset voltage of a differential amplifier using the offset adjusting device according to the first embodiment. [Figure 6] FIG. 6 is a diagram for explaining a method for adjusting an input offset voltage according to the first comparative technique. [Figure 7] FIG. 7 is a diagram for explaining a method for adjusting an input offset voltage according to the second comparative technique. [Figure 8] FIG. 8 is a circuit diagram of a differential amplifier according to the second embodiment.

[0011] [Detailed explanation] (overview) A summary of some exemplary embodiments of the present disclosure is provided. This summary is intended to provide a simplified overview of some concepts of one or more embodiments in order to provide a basic understanding of the embodiments as a prelude to the more detailed description that follows. It is not intended to limit the scope of the invention or disclosure. This summary is not an exhaustive overview of all possible embodiments, and is not intended to identify key elements of all embodiments or to delineate the scope of some or all aspects. For convenience, the term "one embodiment" may refer to one embodiment (example or variant) or multiple embodiments (examples or variants) disclosed herein.

[0012] A differential amplifier according to one embodiment includes a non-inverting input terminal receiving a first input voltage, an inverting input terminal receiving a second input voltage, and an input stage including an input differential pair having a first MOS transistor having a base connected to the non-inverting input terminal and a second MOS transistor having a base connected to the inverting input terminal. The input stage is configured such that, when the non-inverting input terminal and the inverting input terminal receive the first input voltage and the second input voltage corresponding to a measurement result of an input offset voltage of the differential amplifier, respectively, a voltage is applied between the source and drain of the first MOS transistor or the second MOS transistor so as to reduce the input offset voltage of the differential amplifier.

[0013] According to this configuration, the input offset voltage of the differential amplifier can be reduced with a simpler configuration.

[0014] In one embodiment, the differential amplifier may further include a power supply terminal receiving a power supply voltage and a ground terminal. The first MOS transistor and the second MOS transistor may be disposed between the power supply terminal and the ground terminal, respectively. A voltage corresponding to the power supply voltage may be applied between the source and drain of the first MOS transistor or the second MOS transistor.

[0015] In one embodiment, the power supply voltage may be higher than the rated voltage of the differential amplifier.

[0016] In one embodiment, the differential amplifier may further include an active load connectable to the drains of the input differential pair, and an output stage connected to the active load and generating an output voltage by amplifying a difference between the first input voltage and the second input voltage. The input stage may further include a switching circuit configured to switch a connection destination of the drains of the input differential pair between the ground terminal and the active load. A voltage may be applied between the source and drain of the first MOS transistor or the second MOS transistor so as to reduce the input offset voltage while the drains of the input differential pair are connected to the ground terminal via the switching circuit.

[0017] In one embodiment, the input stage may further include a tail current source that supplies a tail current to the input differential pair, and a switching circuit configured to switch a connection destination of the sources of the input differential pair between the power supply terminal and the tail current source. A voltage may be applied between the source and drain of the first MOS transistor or the second MOS transistor so as to reduce the input offset voltage when the sources of the input differential pair are connected to the power supply terminal via the switching circuit.

[0018] In one embodiment, the first input voltage and the second input voltage may be generated such that when a voltage is applied between the source and drain of the first MOS transistor or the second MOS transistor so as to reduce the input offset voltage, both the first MOS transistor and the second MOS transistor are turned on, and a difference between the first input voltage and the second input voltage corresponds to a measurement result of the input offset voltage.

[0019] In one embodiment, a voltage may be applied between the source and drain of the first MOS transistor or the second MOS transistor for a time period according to a measurement result of the input offset voltage, so that the input offset voltage becomes smaller.

[0020] In one embodiment, the first MOS transistor and the second MOS transistor may be heated by a heater when a voltage is applied between a source and a drain of the first MOS transistor or the second MOS transistor so that the input offset voltage is reduced.

[0021] An offset adjustment device according to one embodiment adjusts the input offset voltage of a differential amplifier, and includes an input voltage source that generates the first input voltage and the second input voltage, an offset measuring device that measures the input offset voltage of the differential amplifier, and a voltage control unit that controls the source-drain voltages of the first MOS transistor and the second MOS transistor. The input voltage source generates the first input voltage and the second input voltage according to a measurement result of the input offset voltage by the offset measuring device. The voltage control unit controls the source-drain voltage of the first MOS transistor or the second MOS transistor so as to reduce the input offset voltage of the differential amplifier when the non-inverting input terminal and the inverting input terminal receive the first input voltage and the second input voltage according to the measurement result of the input offset voltage of the differential amplifier, respectively.

[0022] According to this configuration, the input offset voltage of the differential amplifier can be reduced with a simpler configuration.

[0023] In one embodiment, when a voltage is applied between the source and drain of the first MOS transistor or the second MOS transistor so that the input offset voltage becomes small, the input voltage source may turn both the first MOS transistor and the second MOS transistor on, and generate the first input voltage and the second input voltage having a difference according to a measurement result of the input offset voltage.

[0024] In one embodiment, the voltage control unit may apply a voltage between the source and drain of the first MOS transistor or the second MOS transistor for a time period according to a measurement result of the input offset voltage, so as to reduce the input offset voltage.

[0025] In one embodiment, the offset adjustment device may further include a heater that heats the first MOS transistor and the second MOS transistor.

[0026] A method for adjusting the input offset voltage of a differential amplifier using an offset adjustment device according to one embodiment includes: the offset measuring device measuring the input offset voltage of the differential amplifier; the input voltage source generating the first input voltage and the second input voltage according to a measurement result of the input offset voltage by the offset measuring device; and the voltage control unit applying a voltage between the source and drain of the first MOS transistor or the second MOS transistor so as to reduce the input offset voltage.

[0027] According to this configuration, the input offset voltage of the differential amplifier can be reduced with a simpler configuration.

[0028] (Embodiment) Preferred embodiments will be described below with reference to the drawings. The same or equivalent components, parts, and processes shown in each drawing will be given the same reference numerals, and redundant explanations will be omitted as appropriate. Furthermore, the embodiments are examples and do not limit the disclosure and invention, and all features and combinations thereof described in the embodiments are not necessarily essential to the disclosure and invention.

[0029] In this specification, "a state in which component A is connected to component B" includes not only a case in which component A and component B are directly physically connected to each other, but also a case in which component A and component B are indirectly connected to each other via other components that do not substantially affect the electrical connection between them or that do not impair the function or effect achieved by their connection.

[0030] Similarly, "a state in which component C is connected (provided) between component A and component B" includes not only a case in which component A and component C, or component B and component C, are directly connected, but also a case in which they are indirectly connected via other components that do not substantially affect the electrical connection state between them or that do not impair the function or effect achieved by their combination.

[0031] (First embodiment) 1 is a block diagram showing an offset adjustment system 1 for a differential amplifier 10 according to the first embodiment. The offset adjustment system 1 includes the differential amplifier 10, a control device 20, a power supply 30, and a heater 40. The control device 20, the power supply 30, and the heater 40 constitute an offset adjustment device 2 for adjusting the offset voltage Vofs (input offset voltage) of the differential amplifier 10.

[0032] The differential amplifier 10 amplifies the difference between the two input voltages Vin_p and Vin_n to generate an output voltage Vout. The configuration of the differential amplifier 10 will be described in detail later.

[0033] The control device 20 controls the operation of the differential amplifier 10. Specifically, the control device 20 measures the offset voltage Vofs of the differential amplifier 10, generates input voltages Vin_p and Vin_n according to the measurement result, and controls the differential amplifier 10 to adjust the offset voltage Vofs. The offset voltage Vofs is the voltage difference between the non-inverting input terminal and the inverting input terminal when the output voltage Vout of the differential amplifier 10 becomes 0 V.

[0034] The control device 20 according to this embodiment includes an offset measuring device 22, an input voltage source 24, a voltage control unit 26, and a storage unit 28. The control device 20 may also include a CPU (Central Processing Unit), RAM (Random Access Memory), ROM (Read Only Memory), and the like, as needed.

[0035] The offset measuring device 22 measures the offset voltage Vofs of the differential amplifier 10. The offset voltage Vofs may be measured using any of various known methods. The measurement result D1 of the offset voltage Vofs is stored in the storage unit .

[0036] The input voltage source 24 generates input voltages Vin_p and Vin_n to be supplied to the differential amplifier 10. When adjusting the offset voltage Vofs of the differential amplifier 10, the input voltage source 24 generates the input voltages Vin_p and Vin_n according to the measurement result D1 of the offset voltage Vofs by the offset measuring instrument 22. This makes it possible to reduce the offset voltage Vofs of the differential amplifier 10.

[0037] When adjusting the offset voltage Vofs of the differential amplifier 10, the voltage control unit 26 controls the source-drain voltage of the MOS transistor that constitutes the input differential pair (described in detail below) of the differential amplifier 10. By controlling this source-drain voltage, it is possible to adjust changes in the offset voltage Vofs. In this embodiment, the voltage control unit 26 controls the source-drain voltage of the MOS transistor by transmitting a control signal S1 to the differential amplifier 10. This control signal S1 is a signal for switching a switch that controls the source-drain voltage of the MOS transistor, as described below.

[0038] The storage unit 28 stores various types of information. For example, the storage unit 28 may store a measurement result D1 of the offset voltage Vofs measured by the offset measuring instrument 22. The storage unit 28 may also store a table that associates the measurement result of the offset voltage Vofs with the input voltages Vin_p, Vin_n or the conditions of the voltages applied between the source and drain of the MOS transistors of the input differential pair.

[0039] For example, the storage unit 28 may store a table D2 in which the input voltage to be input to the differential amplifier 10 corresponds to the measurement result of the offset voltage Vofs. For example, the table D2 may correspond to the measurement result x1 (x1 is an arbitrary value) of the offset voltage Vofs and the input voltages y1 and y2. The input voltage source 24 can generate the input voltages Vin_p and Vin_n in accordance with the measurement result of the offset voltage Vofs by referring to this table D2.

[0040] The storage unit 28 may store a table D3 that associates the magnitude of the voltage to be applied between the source and drain of the MOS transistor of the input differential pair and the application time for each value of the offset voltage Vofs. For example, table D3 may associate the magnitude z1 of the voltage to be applied between the source and drain or the time t1 for which the voltage is applied with a measurement result x2 (x2 is an arbitrary value) of the offset voltage Vofs. By referring to this table D3, the voltage control unit 26 can control the magnitude of the voltage to be applied between the source and drain of the MOS transistor of the input differential pair or the application time for the voltage.

[0041] The power supply 30 supplies the power supply voltage Vdd to the differential amplifier 10. When adjusting the offset voltage Vofs of the differential amplifier 10, the power supply 30 may supply a voltage (overvoltage) higher than the rated voltage as the power supply voltage Vdd. For example, if the rated voltage of the differential amplifier 10 is 7 V, the power supply 30 may supply a voltage of about 7.5 V when adjusting the offset voltage Vofs of the differential amplifier 10.

[0042] The heater 40 is configured to be able to heat the differential amplifier 10. The heater 40 may be any of various known heating devices. In this embodiment, the heater 40 heats the MOS transistors that constitute the input differential pair of the differential amplifier 10 when adjusting the offset voltage Vofs of the differential amplifier 10. This makes it possible to adjust the offset voltage Vofs more quickly. The temperature to which the MOS transistors are heated is preferably, for example, 125°C to 150°C, and may be, for example, approximately 150°C. Furthermore, the temperature to which the MOS transistors are heated is preferably, for example, 175°C or less than 200°C. This prevents other elements that constitute the differential amplifier 10 from being affected by the heating.

[0043] 2 is a circuit diagram of a differential amplifier 10 according to the first embodiment. The differential amplifier 10 according to the present embodiment mainly includes an input stage 100, current mirror circuits 110 and 112, a load circuit 114, an output stage 120, a non-inverting input terminal INP, an inverting input terminal INN, a power supply terminal VDD, a ground terminal GND, a switching signal terminal SEL1, and an output terminal OUT. The circuit configuration of the differential amplifier 10 is not limited to the example shown in FIG. 2, and various modifications are possible for the circuit configuration of stages subsequent to the input stage 100, such as the output stage 120.

[0044] The non-inverting input terminal INP receives an input voltage Vin_p (first input voltage), and the inverting input terminal INN receives an input voltage Vin_n (second input voltage). Furthermore, the power supply terminal VDD receives a power supply voltage Vdd from the power supply 30, and the switching signal terminal SEL1 receives a control signal S1 from the control device 20. Furthermore, the output terminal OUT outputs the generated output signal Vout.

[0045] The input stage 100 is configured to receive two input voltages Vin_p and Vin_n and output currents I1 and I2 to a connected current mirror circuit 112. The input stage 100 includes an input differential pair 102 including a transistor M1 (first transistor) and a transistor M2 (second transistor), a low-side switching circuit 104, and a tail current source 108.

[0046] As will be described in detail later, the input stage 100 according to this embodiment is configured so that when the non-inverting input terminal INP and the inverting input terminal INN receive input voltages Vin_p and Vin_n, respectively, that correspond to the measurement result of the offset voltage Vofs of the differential amplifier 10, a voltage (hereinafter also referred to as a "stress voltage") is applied between the source and drain of the transistor M1 or the transistor M2 so as to reduce the offset voltage Vofs of the differential amplifier 10.

[0047] The input differential pair 102 outputs currents I1 and I2 according to input voltages Vin_p and Vin_n. The transistors M1 and M2 of the input differential pair 102 are each configured by a P-channel MOS transistor. The transistors M1 and M2 are each arranged between a power supply voltage VDD and a ground terminal GND. The gate of the transistor M1 is connected to the non-inverting input terminal INP, and the source of the transistor M1 is connected to the source of the transistor M2. The gate of the transistor M2 is connected to the inverting input terminal INN. The drains of the input differential pair 102 are connected to the low-side switching circuit 104. Specifically, the drains of the transistors M1 and M2 are connected to the low-side switching circuit 104.

[0048] A voltage corresponding to the power supply voltage Vdd is applied between the source and drain of at least one of the transistors M1 and M2. In this embodiment, a stress voltage corresponding to the connection destination is applied between the source and drain of the transistors M1 and M2 in response to switching of the connection destination in the low-side switching circuit 104.

[0049] When a stress voltage is applied to the transistors M1 and M2, the power supply voltage Vdd may be a voltage (overvoltage) higher than the rated voltage of the differential amplifier 10. This allows a stronger stress voltage to be applied to the transistors M1 and M2, enabling the offset voltage Vofs to be adjusted more quickly. Note that the power supply voltage Vdd is preferably a voltage of a magnitude that does not affect other elements of the transistors M1 and M2.

[0050] The tail current source 108 supplies a tail current to the input differential pair 102. The tail current source 108 according to this embodiment is configured with a P-channel MOS transistor. The source of the transistor is connected to the power supply terminal VDD, and the drain of the transistor is connected to the sources of the input differential pair 102 (specifically, the sources of the transistors M1 and M2).

[0051] The current mirror circuit 110 includes two transistors M4 and M5, each configured as a P-channel MOS transistor. The source of transistor M4 is connected to a power supply terminal VDD, and the gate and drain of transistor M4 are connected to each other. The source of transistor M5 is connected to the power supply terminal VDD, the source of the transistor that configures tail current source 108, and load circuit 114. The gate of transistor M5, along with the base of transistor M4 and the base of the transistor that configures tail current source 108, is connected to output stage 120. The drain of transistor M5 is connected to the drain of transistor M3, which is configured as an N-channel MOS transistor. The source of transistor M3 is connected to ground terminal GND, and the base of transistor M3, along with its drain, is connected to output stage 120.

[0052] The current mirror circuit 112 is an active load that is connectable to the drains of the input differential pair 102. Specifically, the current mirror circuit 112 is connectable to at least one of the drain of the transistor M1 and the drain of the transistor M2.

[0053] The current mirror circuit 112 is a cascode current mirror circuit capable of operating at a low voltage, and includes transistors M6 to M9, each configured as an N-channel MOS transistor. The gates of the transistors M6 and M7 are commonly connected to the output stage 120. The gates of the transistors M8 and M9 are commonly connected to the drain of the transistor M6. The sources of the transistors M8 and M9 are connected to the ground terminal GND and the output stage 120. The drain of the transistor M8 is connected to the source of the transistor M6, and the drain of the transistor M9 is connected to the source of the transistor M7.

[0054] The low-side switching circuit 104 is configured to be able to switch the connection destination of the drains of the input differential pair 102 between the ground terminal VDD and the current mirror circuit 112. In this embodiment, the low-side switching circuit 104 can switch the connection destination of the drains of the transistors M1 and M2 between the ground terminal VDD and the current mirror circuit 112 in response to a control signal S1 from the voltage control unit 26. In this embodiment, the voltage control unit 26 can control the source-drain voltages of the transistors M1 and M2 by controlling the switching of the connection destinations in the low-side switching circuit 104. The low-side switching circuit 104 includes a first switch 105 and a second switch 106.

[0055] The first switch 105 switches the connection destination of the drain of the transistor M1 between the current mirror circuit 112 (specifically, between the transistors M7 and M9) and the ground terminal GND. By connecting the drain of the transistor M1 to the ground terminal GND, a larger voltage can be applied between the source and drain of the transistor M1 than when the drain of the transistor M1 is connected to the current mirror circuit 112. As a result, the threshold voltage Vth1 of the transistor M1 can be changed more quickly.

[0056] The second switch 106 switches the connection destination of the drain of the transistor M2 between the current mirror circuit 112 (specifically, between the transistors M6 and M8) and the ground terminal GND. By connecting the drain of the transistor M2 to the ground terminal GND, a larger voltage can be applied between the source and drain of the transistor M2 than when the drain of the transistor M2 is connected to the current mirror circuit 112. As a result, the threshold voltage Vth2 of the transistor M2 can be changed more quickly.

[0057] The load circuit 114 includes transistors M10 to M13, each configured as a P-channel MOS transistor. The sources of the transistors M10 and M11 are connected to a power supply terminal VDD and the output stage 120. The gates of the transistors M10 and M11 are commonly connected to the output stage 120. The drain of the transistor M10 is connected to the source of the transistor M12. The drain of the transistor M11 is connected to the source of the transistor M13.

[0058] The drain of the transistor M12 is connected to the drain of the transistor M6 of the current mirror circuit 112. The drain of the transistor M13 is connected to the drain of the transistor M7 of the current mirror circuit 112. The gates of the transistors M12 and M13 are connected to the output stage 120 in common.

[0059] The output stage 120 is connected to the current mirror circuit 112 and generates an output voltage Vout by amplifying the difference between the input voltages Vin_p and Vin_n. The output stage 120 includes a high-side transistor M14 configured as a P-channel MOS transistor and a low-side transistor M15 configured as an N-channel MOS transistor. The output voltage Vout is output from between the high-side transistor M14 and the low-side transistor M15.

[0060] The configuration of the differential amplifier 10 according to this embodiment has been described above. A method for adjusting the offset voltage Vofs of the differential amplifier 10 according to this embodiment will now be described.

[0061] The threshold voltage of transistor M1 of the input differential pair 102 is Vth1, the threshold voltage of transistor M2 of the input differential pair 102 is Vth2, and the difference between these threshold voltages is ΔVth (=Vth1-Vth2). An offset voltage Vofs occurs when ΔVth is out of balance. If the offset voltage Vofs is 0V when ΔVth is 0V, the offset voltage Vofs occurs when ΔVth deviates from 0V. For example, if ΔVth>0, the offset voltage Vofs is negative, and if ΔVth<0, the offset voltage ofs is positive. Furthermore, the larger the magnitude of ΔVth, the larger the magnitude of the offset voltage ofs. Therefore, the magnitude of the offset voltage ofs can be reduced by reducing the magnitude of ΔVth.

[0062] In this embodiment, the threshold voltages Vth1 and Vth2 of the transistors M1 and M2 are adjusted using BTI (Bias Temperature Instability). It is well known that BTI irreversibly changes the threshold voltage of a MOS transistor. This property is sometimes used in the technical field of SRAM (Static Random Access Memory) as a method for improving the stability of SRAM by reducing the variation in threshold voltage.

[0063] Here, an example of adjusting the threshold voltage of a MOS transistor in an SRAM using BTI will be described as a reference technique with reference to Figures 3 and 4. Figure 3 is a circuit diagram of an SRAM 90 according to the reference technique.

[0064] 3, an SRAM 90 according to the reference technology has six transistors 91 to 96. Transistors 91 and 92 and transistors 93 and 94 respectively constitute a CMOS (Complementary Metal-Oxide-Semiconductor) inverter. The threshold voltage of transistor 91, which is a P-channel MOS transistor in the first CMOS inverter, is denoted as Vtha. The threshold voltage of transistor 93, which is a P-channel MOS transistor in the second CMOS inverter, is denoted as Vthb.

[0065] When Vtha>Vthb, the initial value of SRAM 90 is stable with VB (base voltage of transistor 91) high and VA (base voltage of transistor 93) low. At this time, transistor 91 is in the off state and transistor 93 is in the on state. In this state, if Vdd is made an overvoltage at high temperature, the threshold voltage Vthb of transistor 93 in the on state increases, and the difference between Vtha and Vthb decreases. When the difference between Vtha and Vthb disappears, the phase stability of SRAM 90 improves and the initial value becomes unstable (random).

[0066] FIG. 4 shows the curves of voltages VA and VB in an SRAM 90 according to the reference technology. In FIG. 4, the vertical axis represents voltage VA, and the horizontal axis represents voltage VB. In FIG. 4, curve C1 represents a curve when the difference between Vtha and Vthb is large, and curve C2 represents a curve when the difference is small (Vtha and Vthb are substantially equal). Point P1, where VA=0V and VB=Vdd, is the stable point. If the difference between the two threshold voltages Vtha and Vthb is large, the voltages VA and VB will be biased toward the stable point, making it difficult to rewrite data. On the other hand, if the two threshold voltages Vtha and Vthb are equal, the stability of the SRAM 90 will be improved, making it easier to rewrite data. As such, in the SRAM technology field, a technique for adjusting the threshold voltage of a MOS transistor using BTI is used.

[0067] In this embodiment, the threshold voltages of transistors M1 and M2 constituting the input differential pair 102 of the differential amplifier 10 are adjusted using BTI. Specifically, input voltages Vin_p and Vin_n corresponding to the measurement result D1 of the offset voltage ofs measured by the offset measuring device 22 are input to the transistors M1 and M2. In this state, a voltage is applied between the source and drain of at least one of the transistors M1 and M2. This changes at least one of the threshold voltages Vth1 and Vth2, reducing the magnitude of ΔVth and thereby reducing the magnitude of the offset voltage ofs.

[0068] The transistors M1 and M2 may be heated by the heater 40 when a voltage is applied between the source and drain of at least one of the transistors M1 and M2 so as to reduce the offset voltage Vofs. This allows the threshold voltages Vth1 and Vth2 to be changed more quickly, thereby reducing the magnitude of the offset voltage Vofs. For example, when a voltage is applied between the source and drain at room temperature, it takes approximately 1 to 10 minutes to sufficiently reduce the offset voltage. In contrast, by heating the transistors M1 and M2 (to, for example, approximately 150°C) with the heater 40, it becomes possible to sufficiently reduce the offset voltage ofs in a few seconds.

[0069] The voltage between the source and drain of transistors M1 and M2 is controlled by the operation of the lower switching circuit 104. For example, a voltage can be applied between the source and drain of transistor M1 by using the first switch 105 to switch the connection of the drain of transistor M1 from open to the ground terminal GND or the current mirror circuit 112. At this time, the amount of change in the threshold voltage Vth1 can be adjusted by adjusting the time that the voltage is applied between the source and drain. The longer the time that the voltage is applied between the source and drain, the greater the amount of change in the threshold voltage Vth1.

[0070] In this embodiment, a voltage is applied between the source and drain of transistor M1 or transistor M2 so that the offset voltage Vofs becomes small while the drain of the input differential pair 102 is connected to the ground terminal GND via the lower switching circuit 104. For example, when the connection destination of the drain of transistor M1 is the ground terminal GND, the voltage between the source and drain of transistor M1 is larger than when the connection destination of the drain of transistor M1 is the current mirror circuit 112. As a result, the threshold voltage Vth1 can be changed earlier. The threshold voltage Vth2 of transistor M2 can also be changed in the same manner as the threshold voltage Vth1 of transistor M1.

[0071] Here, an example of adjusting the threshold voltages Vth1 and Vth2 when Vth1 < Vth2 will be described. In this case, for example, a voltage is applied to transistors M1 and M2 so as to increase the threshold voltage Vth1 of transistor M1 and maintain the threshold voltage Vth2 of transistor M2. Specifically, input voltages Vin_p and Vin_n are supplied to transistors M1 and M2 so that transistor M1 is in an on state and transistor M2 is in an off state. By applying a voltage between the source and drain of transistor M1 in this state, the threshold voltage Vth1 increases.

[0072] Conversely, when Vth1 > Vth2, a voltage is applied to transistors M1 and M2 so as to increase the threshold voltage Vth2 of transistor M2 and maintain the threshold voltage Vth1 of transistor M1.

[0073] After applying a voltage between the source and drain of transistors M1 and M2 to adjust the offset voltage Vofs, the offset voltage Vofs may be measured again, and based on the measurement result, the offset voltage Vofs may be adjusted again. Thereby, the offset voltage Vofs can be adjusted more accurately.

[0074] 5 is a flowchart showing an example of a method for adjusting the offset voltage Vofs of the differential amplifier 10 using the offset adjusting device 2 according to the first embodiment. The flow of adjusting the offset voltage Vofs will be described below with reference to the flowchart shown in FIG.

[0075] First, the offset measuring device 22 measures the offset voltage Vofs of the differential amplifier 10 (S101).

[0076] Next, the heater 40 heats the transistors M1 and M2 that make up the input differential pair 102 (S103). At this time, the heating temperature may be, for example, about 150°C.

[0077] Next, the input voltage source 24 generates input voltages Vin_p and Vin_n according to the measurement result of the offset voltage Vofs in S101 (S105).

[0078] Next, the voltage control unit 26 applies a voltage between the source and drain of the transistors M1 and M2 that make up the input differential pair 102 so as to reduce the offset voltage Vofs (S107).

[0079] Specifically, the voltage control unit 26 controls the first switch 105 and the second switch 106 so that the drain of at least one of the transistors M1 and M2 is connected to the ground terminal GND. This applies a voltage between the source and drain of at least one of the transistors M1 and M2. As a result, at least one of the threshold voltages Vth1 and Vth2 changes, and the offset voltage Vofs decreases.

[0080] The voltage control unit 26 may apply a voltage between the source and drain of at least one of the transistors M1 and M2 for a time period corresponding to the measurement result of the offset voltage Vofs. Specifically, the larger the magnitude of the offset voltage Vofs, the longer the time for which the stress voltage may be applied to the transistor M1 or M2. This allows the threshold voltage to be appropriately adjusted.

[0081] FIG. 6 is a diagram illustrating a method for adjusting an input offset voltage according to Comparative Technique 1. In the method for adjusting an input offset voltage according to Comparative Technique 1, variable resistors R12 and R22 are connected to the drains of transistors M1 and M2, respectively (via wiring resistors R11 and R21). When the threshold voltages of transistors M1 and M2 are the same, input voltages are input to the inverting input terminal INP and the non-inverting input terminal INN, respectively, so that the currents I3 and I4 flowing through the wiring resistors R11 and R21 are the same. When the threshold voltages of transistors M1 and M2 are different, causing a difference in the currents I3 and I4, the resistance values ​​of the variable resistors R12 and R22 are adjusted to match the currents I3 and I4, thereby adjusting the offset voltage.

[0082] 7 is a diagram illustrating a method for adjusting an input offset voltage according to Comparative Technique 2. In this method, variable current sources 98 and 99 are connected to the drains of transistors M1 and M2, respectively, via wiring resistors R13 and R23. When the threshold voltages of transistors M1 and M2 are the same, input voltages are input to the inverting input terminal INP and the non-inverting input terminal INN, respectively, so that the currents I5 and I6 flowing through the wiring resistors R13 and R23 are the same. When the threshold voltages of transistors M1 and M2 are different, causing a difference in the currents I5 and I6, the current amounts I7 and I9 of the variable current sources 98 and 99 are adjusted to match the currents I8 and I10 flowing through the wiring resistors R14 and R24. This adjusts the input offset voltage.

[0083] As in Comparative Techniques 1 and 2, there are methods for adjusting the current difference caused by a mismatch in the threshold voltage pairing of transistors M1 and M2 using circuitry. However, to adjust the current difference, the adjustment method of Comparative Technique 1 requires a finely divided resistor array or the like as variable resistors R12 and R22. The adjustment method of Comparative Technique 2 requires the inclusion of a current DAC (Digital-to-Analog Converter) that generates the divided current as variable current sources 98 and 99. As a result, the adjustment methods of Comparative Techniques 1 and 2 require the inclusion of a considerable amount of circuitry. In addition, fuses or nonvolatile memory are required to fix the codes (such as the current DAC codes) for individually adjusting the current difference. Furthermore, when adjusting the current difference by adding resistors as in Comparative Technique 1, another method is to use linearly trimmable thin-film resistors as resistors and trim the resistors with a laser. However, this method requires a certain area for the resistors to be processed.

[0084] The differential amplifier 10 according to the above embodiment is configured such that, when the inverting input terminal INP and the non-inverting input terminal INN receive a first input voltage Vin_p and a second input voltage Vin_n, respectively, that correspond to a measurement result of the offset voltage Vofs (input offset voltage) of the differential amplifier 10, a voltage is applied between the source and drain of the transistor M1 (first MOS transistor) or the transistor M2 (second MOS transistor) so as to reduce the offset voltage Vofs of the differential amplifier 10. This configuration allows the offset voltage Vofs to be reduced by adjusting the threshold voltage of at least one of the transistors M1 and M2. This configuration does not require a circuit of a considerable scale as in Comparative Techniques 1 and 2, and therefore enables the offset voltage Vofs of the differential amplifier 10 to be reduced with a simpler configuration.

[0085] (Second embodiment) 8 is a circuit diagram of a differential amplifier 12 according to the second embodiment. The differential amplifier 12 according to the second embodiment differs from the differential amplifier 10 according to the first embodiment mainly in that it includes an upper-side switching circuit 124 instead of the lower-side switching circuit 104 included in the differential amplifier 10 according to the first embodiment. The offset adjustment device according to the second embodiment may have the same functions as the offset adjustment device 2 according to the first embodiment. The differential amplifier 12 according to the second embodiment may have the same configuration as the differential amplifier 10 according to the first embodiment, except for the lower-side switching circuit 104. In this case, the drain of the input differential pair 102 is connected to a current mirror circuit 112.

[0086] The upper switching circuit 124 is configured to be able to switch the connection destination of the sources of the input differential pair 102 (specifically, the sources of the transistors M1 and M2) between a tail current source (specifically, the drains of the transistors) and a power supply terminal VDD. The connection destination of the sources of the input differential pair 102 is controlled in response to a control signal S2 input to a switching signal terminal SEL2. This control signal S2 may be generated by the voltage control unit 26.

[0087] In this embodiment, a voltage (stress voltage) is applied between the source and drain of at least one of the transistors M1 and M2 so as to reduce the offset voltage Vofs, with the source of the input differential pair 102 connected to the power supply terminal VDD via the upper switching circuit 124. This makes it possible to apply a larger voltage between the source and drain of the transistors M1 and M2 than when the source of the input differential pair 102 is connected to the tail current source 108. As a result, it becomes possible to adjust the threshold voltages of the transistors M1 and M2 more quickly.

[0088] (First Modification) In the above embodiment, an example has been described in which the offset voltage Vofs is adjusted by applying a voltage between the source and drain of the transistors M1 and M2 while one of the transistors M1 and M2 constituting the input differential pair 102 is turned on and the other is turned off. However, the present invention is not limited to this, and the offset voltage Vofs may be adjusted by turning on both the transistors M1 and M2 and applying a voltage between the source and drain of the transistors M1 and M2 in this state.

[0089] Specifically, when a voltage is applied between the source and drain of at least one of transistors M1 and M2 so as to reduce offset voltage Vofs, both transistors M1 and M2 are turned on, and input voltages Vin_p and Vin_n are generated so as to have a difference corresponding to the measurement result of offset voltage Vofs. Note that these input voltages Vin_p and Vin_n may be generated by input voltage source 24.

[0090] Specifically, a higher input voltage may be applied to the transistor corresponding to the smaller of the threshold voltages Vth1 and Vth2 than to the other transistor. In this state, applying a voltage between the gate and source of transistors M1 and M2 causes the smaller threshold voltage to change more than the larger threshold voltage, thereby reducing the magnitude of ΔVth.

[0091] This allows for more precise adjustment of ΔVth than applying a voltage between the source and drain of transistors M1 and M2 by turning on one of the transistors M1 and M2 and turning off the other. Note that by adjusting the difference between the input voltages Vin_p and Vin_n, the difference in the amount of change between the threshold voltages Vth1 and Vth2 can be adjusted.

[0092] (Second Modification) In the above embodiment, an example has been described in which the input differential pair 102 is configured with two P-channel MOS transistors, but the input differential pair may be configured with two N-channel MOS transistors. Even when the input differential pair is configured with N-channel MOS transistors, it is possible to reduce the input offset voltage by adjusting the threshold voltage using BTI, as in the above embodiment.

[0093] (supplement) Although the embodiments of the present disclosure have been described using specific terms, this description is merely an example to facilitate understanding and does not limit the scope of the present disclosure or the claims, and the scope of the present invention is defined by the claims. Furthermore, not only the embodiments but also embodiments, examples, and modifications not described herein are included in the scope of the present invention.

[0094] It is also possible to combine the configuration of one embodiment with the configuration of another embodiment (or modified example). For example, the input stage of a differential amplifier may include the low-side switching circuit 104 according to the first embodiment and the high-side switching circuit 124 according to the second embodiment. This allows the transistors of the input differential pair to be connected to the power supply terminal VDD and the ground terminal GND, allowing a larger voltage to be applied between the source and drain of the transistor.

[0095] (Addendum) One aspect of the technology disclosed in this specification can be understood as follows.

[0096] (Item 1) A differential amplifier, a non-inverting input terminal receiving a first input voltage; an inverting input terminal for receiving a second input voltage; an input stage including an input differential pair having a first MOS transistor having a base connected to the non-inverting input terminal and a second MOS transistor having a base connected to the inverting input terminal; the input stage is configured such that, when the non-inverting input terminal and the inverting input terminal receive the first input voltage and the second input voltage corresponding to a measurement result of an input offset voltage of the differential amplifier, a voltage is applied between the source and drain of the first MOS transistor or the second MOS transistor so as to reduce the input offset voltage of the differential amplifier. Differential amplifier.

[0097] (Item 2) a power supply terminal for receiving a power supply voltage; a ground terminal; the first MOS transistor and the second MOS transistor are each disposed between the power supply terminal and the ground terminal; a voltage corresponding to the power supply voltage is applied between the source and drain of the first MOS transistor or the second MOS transistor; The differential amplifier described in item 1.

[0098] (Item 3) the power supply voltage is higher than the rated voltage of the differential amplifier; The differential amplifier described in item 2.

[0099] (Item 4) an active load provided so as to be connectable to the drains of the input differential pair; an output stage connected to the active load and configured to generate an output voltage obtained by amplifying a difference between the first input voltage and the second input voltage; the input stage further includes a switching circuit configured to be able to switch a connection destination of the drains of the input differential pair between the ground terminal and the active load, a voltage is applied between the source and drain of the first MOS transistor or the second MOS transistor so as to reduce the input offset voltage, with the drains of the input differential pair connected to the ground terminal via the switching circuit; A differential amplifier as described in item 2 or 3.

[0100] (Item 5) the input stage further includes a tail current source that supplies a tail current to the input differential pair, and a switching circuit configured to be able to switch a connection destination of the sources of the input differential pair between the power supply terminal and the tail current source, a voltage is applied between the source and drain of the first MOS transistor or the second MOS transistor so as to reduce the input offset voltage, with the sources of the input differential pair connected to the power supply terminals via the switching circuit; 5. The differential amplifier according to any one of items 2 to 4.

[0101] (Item 6) the first input voltage and the second input voltage are generated so as to have a difference corresponding to a measurement result of the input offset voltage when a voltage is applied between the source and drain of the first MOS transistor or the second MOS transistor so as to reduce the input offset voltage, and both the first MOS transistor and the second MOS transistor are turned on. 6. The differential amplifier according to any one of items 1 to 5.

[0102] (Item 7) a voltage is applied between the source and drain of the first MOS transistor or the second MOS transistor for a time period corresponding to a measurement result of the input offset voltage so as to reduce the input offset voltage; 7. The differential amplifier according to any one of items 1 to 6.

[0103] (Item 8) the first MOS transistor and the second MOS transistor are heated by a heater when a voltage is applied between a source and a drain of the first MOS transistor or the second MOS transistor so that the input offset voltage is reduced; 8. The differential amplifier according to any one of items 1 to 7.

[0104] (Item 9) An offset adjustment device for adjusting an input offset voltage of a differential amplifier according to any one of items 1 to 8, an input voltage source that generates the first input voltage and the second input voltage; an offset measuring device for measuring an input offset voltage of the differential amplifier; a voltage control unit that controls a voltage between the source and the drain of the first MOS transistor and the second MOS transistor, the input voltage source generates the first input voltage and the second input voltage according to a measurement result of the input offset voltage by the offset measuring device; the voltage control unit controls the voltage between the source and drain of the first MOS transistor or the second MOS transistor so as to reduce the input offset voltage of the differential amplifier when the non-inverting input terminal and the inverting input terminal receive the first input voltage and the second input voltage, respectively, according to a measurement result of the input offset voltage of the differential amplifier. Offset adjustment device.

[0105] (Item 10) When a voltage is applied between the source and drain of the first MOS transistor or the second MOS transistor so that the input offset voltage becomes small, the first MOS transistor and the second MOS transistor are both turned on, and the input voltage source generates the first input voltage and the second input voltage having a difference corresponding to a measurement result of the input offset voltage. Item 9. The offset adjustment device according to item 9.

[0106] (Item 11) the voltage control unit applies a voltage between the source and drain of the first MOS transistor or the second MOS transistor for a time period corresponding to a measurement result of the input offset voltage so as to reduce the input offset voltage; Item 11. The offset adjustment device according to item 9 or 10.

[0107] (Item 12) further comprising a heater for heating the first MOS transistor and the second MOS transistor; 12. The offset adjusting device according to any one of items 9 to 11.

[0108] (Item 13) A method for adjusting the input offset voltage of the differential amplifier using the offset adjustment device according to any one of items 9 to 12, the offset measuring device measuring the input offset voltage of the differential amplifier; the input voltage source generates the first input voltage and the second input voltage according to a measurement result of the input offset voltage by the offset measuring device; the voltage control unit applying a voltage between the source and drain of the first MOS transistor or the second MOS transistor so as to reduce the input offset voltage. A method for adjusting the input offset voltage of a differential amplifier using an offset adjustment device. [Explanation of symbols]

[0109] 1 offset adjustment system, 2 offset adjustment device, 10, 12 differential amplifier, 20 control device, 22 offset measuring device, 24 input voltage source, 26 voltage control section, 28 memory section, 30 power supply, 40 heater, 100 input stage, 102 input differential pair, 104 lower switching circuit, 105 first switch, 106 second switch, 108 tail current source, 11, 112 current mirror circuit, 114 load circuit, 120 output stage, 124 upper switching circuit, M1 to M15 transistors, INP non-inverting input terminal, INN inverting input terminal, VDD power supply terminal, GND ground terminal.

Claims

1. A differential amplifier, a non-inverting input terminal receiving a first input voltage; an inverting input terminal for receiving a second input voltage; an input stage including an input differential pair having a first MOS transistor having a base connected to the non-inverting input terminal and a second MOS transistor having a base connected to the inverting input terminal; the input stage is configured such that, when the non-inverting input terminal and the inverting input terminal receive the first input voltage and the second input voltage corresponding to a measurement result of an input offset voltage of the differential amplifier, a voltage is applied between the source and drain of the first MOS transistor or the second MOS transistor so as to reduce the input offset voltage of the differential amplifier. Differential amplifier.

2. a power supply terminal for receiving a power supply voltage; a ground terminal; the first MOS transistor and the second MOS transistor are each disposed between the power supply terminal and the ground terminal; a voltage corresponding to the power supply voltage is applied between the source and drain of the first MOS transistor or the second MOS transistor; 2. The differential amplifier according to claim 1.

3. the power supply voltage is higher than the rated voltage of the differential amplifier; 3. The differential amplifier according to claim 2.

4. an active load provided so as to be connectable to the drains of the input differential pair; an output stage connected to the active load and configured to generate an output voltage obtained by amplifying a difference between the first input voltage and the second input voltage; the input stage further includes a switching circuit configured to be able to switch a connection destination of the drains of the input differential pair between the ground terminal and the active load, a voltage is applied between the source and drain of the first MOS transistor or the second MOS transistor so as to reduce the input offset voltage, with the drain of the input differential pair being connected to the ground terminal via the switching circuit; 3. The differential amplifier according to claim 2.

5. the input stage further includes a tail current source that supplies a tail current to the input differential pair, and a switching circuit configured to be able to switch a connection destination of the sources of the input differential pair between the power supply terminal and the tail current source, a voltage is applied between the source and drain of the first MOS transistor or the second MOS transistor so as to reduce the input offset voltage, with the sources of the input differential pair connected to the power supply terminals via the switching circuit; 3. The differential amplifier according to claim 2.

6. the first input voltage and the second input voltage are generated so as to have a difference corresponding to a measurement result of the input offset voltage when a voltage is applied between the source and drain of the first MOS transistor or the second MOS transistor so as to reduce the input offset voltage, and both the first MOS transistor and the second MOS transistor are turned on.

2. The differential amplifier according to claim 1.

7. a voltage is applied between the source and drain of the first MOS transistor or the second MOS transistor for a time period corresponding to a measurement result of the input offset voltage so as to reduce the input offset voltage; 2. The differential amplifier according to claim 1.

8. the first MOS transistor and the second MOS transistor are heated by a heater when a voltage is applied between a source and a drain of the first MOS transistor or the second MOS transistor so that the input offset voltage is reduced; 2. The differential amplifier according to claim 1.

9. 9. An offset adjustment device for adjusting an input offset voltage of a differential amplifier according to claim 1, an input voltage source that generates the first input voltage and the second input voltage; an offset measuring device for measuring an input offset voltage of the differential amplifier; a voltage control unit that controls a voltage between the source and the drain of the first MOS transistor and the second MOS transistor, the input voltage source generates the first input voltage and the second input voltage according to a measurement result of the input offset voltage by the offset measuring device; the voltage control unit controls the voltage between the source and drain of the first MOS transistor or the second MOS transistor so as to reduce the input offset voltage of the differential amplifier when the non-inverting input terminal and the inverting input terminal receive the first input voltage and the second input voltage, respectively, according to a measurement result of the input offset voltage of the differential amplifier. Offset adjustment device.

10. When a voltage is applied between the source and drain of the first MOS transistor or the second MOS transistor so as to reduce the input offset voltage, the input voltage source turns both the first MOS transistor and the second MOS transistor on, and generates the first input voltage and the second input voltage having a difference corresponding to a measurement result of the input offset voltage.

10. The offset adjusting device according to claim 9.

11. the voltage control unit applies a voltage between the source and drain of the first MOS transistor or the second MOS transistor for a time period corresponding to a measurement result of the input offset voltage so as to reduce the input offset voltage; 10. The offset adjusting device according to claim 9.

12. further comprising a heater for heating the first MOS transistor and the second MOS transistor; 10. The offset adjusting device according to claim 9.

13. 10. A method for adjusting an input offset voltage of the differential amplifier using the offset adjustment device according to claim 9, comprising: the offset measuring device measuring the input offset voltage of the differential amplifier; the input voltage source generates the first input voltage and the second input voltage according to a measurement result of the input offset voltage by the offset measuring device; the voltage control unit applies a voltage between the source and drain of the first MOS transistor or the second MOS transistor so as to reduce the input offset voltage. A method for adjusting the input offset voltage of a differential amplifier using an offset adjustment device.

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