Semiconductor device

Abstract

To provide a semiconductor device capable of being improved in withstand voltage.SOLUTION: A semiconductor device includes: an annular first trench TR1 surrounding an element region in plan view; an annular second trench TR2 extending from a surface of an epitaxial semiconductor layer 14 to a depth penetrating a substrate epitaxial semiconductor layer 12 and surrounding the first trench TR1 in the plan view; and a third trench TR3 extending from the surface of the epitaxial semiconductor layer 14 to the depth penetrating the substrate epitaxial semiconductor layer 12 and connecting the first trench TR1 and the second trench TR2 in the plan view. In the plan view, the third trench TR3 includes a first region R1 located on the first trench TR1 side and a second region R2 located on the second trench TR2 side. The first region R1 of the third trench TR3 is electrically insulated from a substrate 11, and a conductive region CR3 electrically connected to the substrate 11 is embedded within the second region R2 of the third trench TR3.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present disclosure relates to semiconductor devices. [Background technology]

[0002] Patent Document 1 discloses a semiconductor device including a deep trench isolation (DTI) structure. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] International Publication No. 2022 / 153693

[0004] [overview] The present disclosure provides a semiconductor device capable of improving the breakdown voltage.

[0005] The semiconductor device of the present disclosure includes: an underlying epitaxial semiconductor layer formed on a substrate; an epitaxial semiconductor layer formed on the underlying epitaxial semiconductor layer via a buried semiconductor layer; a first annular trench extending from a surface of the epitaxial semiconductor layer to a depth penetrating the underlying epitaxial semiconductor layer and surrounding an element region in a planar view; a second annular trench extending from the surface of the epitaxial semiconductor layer to a depth penetrating the underlying epitaxial semiconductor layer and surrounding the first trench in a planar view; and a third trench that extends from the surface of the epitaxial semiconductor layer to a depth penetrating the underlying epitaxial semiconductor layer and connects the first trench and the second trench in a planar view, the third trench having a first region located on the first trench side and a second region located on the second trench side in a planar view, the first region of the third trench being electrically insulated from the substrate, and a conductive region electrically connected to the substrate being embedded in the second region of the third trench. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is a plan view of a semiconductor chip. [Figure 2] FIG. 2 is a plan view of the device region of the first embodiment. [Figure 3] FIG. 3 is a diagram showing a vertical cross-sectional configuration of the device region taken along the line AA of the arrow shown in FIG. [Figure 4] FIG. 4 is a diagram showing a vertical cross-sectional configuration of the device region taken along the arrow line BB shown in FIG. [Figure 5] FIG. 5 is a plan view of the device region of the second embodiment. [Figure 6] FIG. 6 is a diagram showing a vertical cross-sectional configuration of the device region taken along the line AA of the arrow shown in FIG. [Figure 7] FIG. 7 is a diagram showing a vertical cross-sectional configuration of the device region taken along the arrow line BB shown in FIG. [Figure 8] FIG. 8 is a plan view of the device region of the third embodiment. [Figure 9] FIG. 9 is a diagram showing a vertical cross-sectional configuration of the device region taken along the line AA of the arrow shown in FIG. [Figure 10] FIG. 10 is a diagram showing a vertical cross-sectional configuration of the device region taken along the arrow line BB shown in FIG. [Figure 11] FIG. 11 is a plan view of a device region in the fourth embodiment. [Figure 12] FIG. 12 is a diagram showing a vertical cross-sectional configuration of the device region taken along the arrow line BB shown in FIG. [Figure 13] FIG. 13 is a diagram showing a longitudinal cross-sectional structure of an example of the device.

[0007] [Detailed explanation] Various exemplary embodiments will be described in detail below with reference to the drawings. Note that the same or equivalent parts in the drawings will be denoted by the same reference numerals, and redundant explanations will be omitted.

[0008] FIG. 1 is a plan view of a semiconductor chip 100. As shown in FIG.

[0009] The semiconductor chip 100 (semiconductor device) has a rectangular parallelepiped shape. The semiconductor chip 100 has a first main surface 3 on one side and a second main surface 4 on the other side (see FIG. 3). The semiconductor chip 100 has a first side surface 5A, a second side surface 5B, a third side surface 5C, and a fourth side surface 5D that connect the first main surface 3 and the second main surface 4. The thickness direction of the semiconductor chip 100 is defined as the Z-axis direction, the direction perpendicular to the Z-axis is defined as the X-axis direction, and the direction perpendicular to both the Z-axis and the X-axis is defined as the Y-axis direction. The depth direction of the semiconductor chip 100 (the depth direction of the trenches formed in the substrate) is defined as the positive direction of the Z-axis, and the negative direction of the Z-axis indicates the direction from the second main surface 4 (back surface) of the semiconductor substrate toward the first main surface 3 (top surface).

[0010] The first main surface 3 and the second main surface 4 are each perpendicular to the Z axis. The planar shape (shape in plan view) of the first main surface 3 when viewed from the normal direction (Z axis direction) of the first main surface 3 is a rectangle (quadrilateral). The shape of the second main surface 4 is also a rectangle (quadrilateral). The first side surface 5A and the second side surface 5B, which constitute two opposing sides of the rectangle in plan view, each extend along the X axis direction. The third side surface 5C and the fourth side surface 5D, which constitute the other two opposing sides of the rectangle in plan view, each extend along the Y axis direction. These adjacent side surfaces are perpendicular to each other in plan view, but can also intersect at an angle other than perpendicular.

[0011] The semiconductor chip 100 includes a plurality of device regions 10 provided on the first main surface 3. There is a gap between each device region 10 and each side surface (first side surface 5A to fourth side surface 5D) of the semiconductor chip 100. The number, arrangement, and shape of the device regions 10 are arbitrary and are not limited to a specific number, arrangement, or shape.

[0012] Various devices are formed within each device region 10. At least one device region 10 includes a deep trench isolation structure surrounding the device 50.

[0013] An example of the device 50 is a field-effect transistor. An example of a field-effect transistor is a metal insulator semiconductor field effect transistor (MISFET). A metal-oxide-semiconductor field-effect transistor (MOSFET) can be used as the MISFET. A double-diffused MOSFET (DMOS) can be used as the power MOSFET, and a lateral LDMOS can also be used. MISFETs with drain-source voltages of high voltage (HV: for example, 100 V or more and 1000 V or less), medium voltage (MV: for example, 30 V or more and 100 V or less), and low voltage (LV: for example, 1 V or more and 30 V or less) are also known.

[0014] FIG. 2 is a plan view of the device region 10 of the first embodiment.

[0015] The device region 10 includes a double deep trench isolation structure including a first trench TR1 surrounding the device 50 and a second trench TR2 surrounding the first trench TR1. The isolation structure further includes a plurality of third trenches TR3 connecting the first trench TR1 and the second trench TR2.

[0016] Although four third trenches TR3 are shown in the drawing, the number of third trenches TR3 may be any number, for example, five or more, as long as it is plural. Furthermore, the shapes and dimensions of the individual third trenches TR3 are the same.

[0017] In a plan view, the width direction of the first trench TR1 is a direction perpendicular to the circumferential direction of the annular trench. In a plan view, the width direction of the second trench TR2 is a direction perpendicular to the circumferential direction of the annular trench. The first width W1 of the first trench TR1 may be, for example, 0.5 μm or more and 10 μm or less. The second width W2 of the second trench TR2 may be, for example, 0.5 μm or more and 10 μm or less. In this example, the first width W1 is set to 2 μm, and the second width W2 is also set to 2 μm.

[0018] The third trench TR3 includes a first region R1 located on the first trench TR1 side and a second region R2 located on the second trench TR2 side. In a plan view, the width direction of the third trench TR3 is a direction perpendicular to the direction from the first trench TR1 to the second trench TR2. The third trench TR3 has a plurality of widths. The first width (Y1) (the width of the first region R1) of the third trench TR3 on the first trench TR1 side is, for example, 1 μm. The second width (Y2) (the width of the second region R2) of the third trench TR3 on the second trench TR2 side is, for example, 3 μm. That is, Y1 < Y2 is satisfied. Since a third conductive region is embedded in the third trench TR3, Y2 is larger than Y1. Also, the width of the trench in this example satisfies Y1 < W1 < Y2. In other words, in a plan view, the first width Y1 perpendicular to the longitudinal direction of the first region R1 and the second width Y2 perpendicular to the longitudinal direction of the second region R2 satisfy the relationship Y1 < Y2. The first width W1 and the second width W2 are set to be equal, but they may be different. Note that the longitudinal dimension of the first region R1 in a plan view can be set, for example, to 2 μm to 7 μm, and the longitudinal dimension of the second region R2 can be set, for example, to 6 μm to 15 μm.

[0019] A first conductive region CR1 is embedded in the first trench TR1. A second conductive region CR2 is embedded in the second trench TR2. A third conductive region CR3 is embedded in the third trench TR3.

[0020] FIG. 3 is a diagram showing a longitudinal cross-sectional configuration along the A-A arrow line of the device region shown in FIG. 2.

[0021] In this example, each semiconductor region constituting the device region 10 of the semiconductor device has a first conductivity type of P-type and a second conductivity type of N-type, but these conductivity types are interchangeable. An exemplary P-type impurity (trivalent element) is boron (B). An exemplary N-type impurity (pentavalent element) is phosphorus (P) or arsenic (As).

[0022] The element region where the device 50 is formed is a region where active elements such as field-effect transistors are formed. An example of a FET that constitutes the device 50 is a DMOS-FET. The semiconductor device includes a semiconductor substrate 1. The semiconductor substrate 1 is made of silicon (Si) and includes an underlying substrate 11, an underlying epitaxial semiconductor layer 12, a buried semiconductor layer 13, and an epitaxial semiconductor layer 14. The underlying substrate 11 is a P-type semiconductor substrate. The underlying epitaxial semiconductor layer 12 has P-type conductivity and is formed on the substrate 11. The buried semiconductor layer 13 has N-type conductivity and is formed on the underlying epitaxial semiconductor layer 12. The epitaxial semiconductor layer 14 has N-type conductivity and is formed on the buried semiconductor layer 13. In other words, the epitaxial semiconductor layer 14 is formed on the substrate via the buried semiconductor layer 13. An insulating region 18 is formed on the surface of the semiconductor substrate 1.

[0023] The inner first trench TR1 extends from the surface of the epitaxial semiconductor layer 14 to a depth penetrating the buried semiconductor layer 13, is annular in plan view, and surrounds the element region (device 50). The outer second trench TR2 extends from the surface of the epitaxial semiconductor layer 14 to a depth penetrating the buried semiconductor layer 13 and further to a depth penetrating the underlying epitaxial semiconductor layer 12, reaching the inside of the substrate 11. This makes it possible to suppress the occurrence of punch-through between adjacent N-type semiconductor regions and to suppress the operation of a parasitic NPN bipolar transistor. The second trench TR2 is annular in plan view and surrounds the first trench TR1.

[0024] The depth of the first trench TR1 can be set to, for example, 10 μm to 30 μm. The deep trench isolation structure includes a first insulating layer I1 covering the inner surface of the first trench TR1 and a first conductive region CR1 (conductive material) provided within the first trench TR1 via the first insulating layer I1. The first conductive region CR1 is polysilicon doped with impurities. A P-type additive such as boron (B) can be used as the impurity to be doped into the polysilicon. The first conductive region CR1 extends from the surface of the semiconductor substrate 1 toward the depth thereof and has a tapered shape. The tip of the first conductive region CR1 is located within the first insulating layer I1 (insulating region) and does not reach the trench bottom.

[0025] The deep trench isolation structure may include an N-type first impurity-doped layer S1 located outside the first insulating layer I1. The first impurity-doped layer S1 extends along the outer surface of the first insulating layer I1, contacts the buried semiconductor layer 13, and further extends into the underlying epitaxial semiconductor layer 12, but does not reach the substrate 11. The first impurity-doped layer S1 is connected to the N-type buried semiconductor layer 13 provided inside the semiconductor substrate. When the first impurity-doped layer S1 is N-type, the buried semiconductor layer 13 and the first impurity-doped layer S1 are electrically connected. On the device side to which a high voltage is applied, electric field concentration is likely to occur near this connection, and the withstand voltage of the first trench alone tends to decrease. The first terminal E1 may be electrically connected to the first conductive region CR1.

[0026] Similarly, the depth of the second trench TR2 can be set to, for example, 10 μm to 30 μm. The deep trench isolation structure includes a second insulating layer I2 covering the inner surface of the second trench TR2 and a second conductive region CR2 (conductive material) provided within the second trench TR2 via the second insulating layer I2. The second conductive region CR2 is polysilicon doped with impurities. A P-type additive such as boron (B) can be used as the impurity to be doped into the polysilicon. The second conductive region CR2 extends from the surface of the semiconductor substrate 1 toward the depth thereof and has a tapered shape. The tip of the second conductive region CR2 is located within the second insulating layer I2 (insulating region) and does not reach the trench bottom.

[0027] The deep trench isolation structure may include an N-type second impurity doped layer S2 located outside the second insulating layer I2. The second impurity doped layer S2 extends along the outer surface of the second insulating layer I2, contacts the buried semiconductor layer 13, and further extends deep into the substrate. The second impurity doped layer S2 is connected to the N-type buried semiconductor layer 13 provided inside the semiconductor substrate. When the second impurity doped layer S2 is N-type, the buried semiconductor layer 13 and the second impurity doped layer S2 are electrically connected. A second terminal E2 may be electrically connected to the second conductive region CR2.

[0028] FIG. 4 is a diagram showing a vertical cross-sectional configuration of the device region taken along the arrow line BB shown in FIG.

[0029] The third trench TR3 penetrates the buried semiconductor layer 13 from the surface of the epitaxial semiconductor layer 14, and further extends deep enough to penetrate the underlying epitaxial semiconductor layer 12 and reach the inside of the substrate 11. This prevents punch-through between adjacent N-type semiconductor regions and suppresses the operation of a parasitic NPN bipolar transistor. The third trench TR3 connects the first trench TR1 and the second trench TR2 in a plan view. In a plan view, the third trench TR3 includes a first region R1 located on the first trench TR1 side and a second region R2 located on the second trench TR2 side. The first region R1 of the third trench TR3 is electrically insulated from the substrate. A third conductive region CR3 electrically connected to the substrate 11 (the underlying semiconductor substrate) is buried in the second region R2 of the third trench TR3. The device 50 side of the third trench TR3 is continuous with the first trench TR1.

[0030] The deep trench isolation structure may include an N-type third impurity doped layer S3 located outside the third insulating layer I3. The third impurity doped layer S3 extends along the outer surface of the third insulating layer I3, contacts the buried semiconductor layer 13, and further extends into the underlying epitaxial semiconductor layer 12, but does not reach the substrate 11. The third impurity doped layer S3 is connected to the N-type buried semiconductor layer 13 provided inside the semiconductor substrate. When the third impurity doped layer S3 is N-type, the buried semiconductor layer 13 and the third impurity doped layer S3 are electrically connected. A third terminal E3 may be electrically connected to the third conductive region CR3.

[0031] Referring to FIG. 2, a third conductive region CR3 is embedded in the second region R2, and the trench width (Y2) of the second region R2 is wider than the trench width (Y1) of the first region R1. The trench width is determined based on the interface between the epitaxial semiconductor layer 14 and the third insulating layer I3 covering the inner surface of the trench. In the left and right third trenches TR3 in FIG. 2, the third insulating layer I3 is located on both sides of the third conductive region CR3 in the YZ plane. Similarly, in the upper and lower third trenches TR3 in FIG. 2, the third insulating layer I3 is located on both sides of the third conductive region CR3 in the XZ plane. The third conductive region CR3 extends deep from the surface of the semiconductor substrate 1, penetrating the third insulating layer I3 located at the bottom of the trench to reach the interior of the substrate 11.

[0032] The first terminal E1, the second terminal E2, and the third terminal E3 are provided as needed, and a configuration in which they are not provided is also possible. A bias potential may be applied to each of the first terminal E1, the second terminal E2, and the third terminal E3.

[0033] For example, no potential is applied to the first terminal E1 (see FIG. 3) on the high potential side located close to the device 50, and the potential of the first conductive region CR1 is set to a floating potential. In other words, if the first conductive region CR1 is set to a floating potential, the first terminal E1 does not need to be provided. It is also possible to adopt a configuration in which an appropriate potential is applied to the first conductive region CR1 via the first terminal E1, thereby reducing the potential difference with the potential on the device 50 side and alleviating electric field concentration due to the potential difference.

[0034] For example, the ground potential is applied to the second terminal E2 (see FIG. 3) on the low potential side located away from the device 50, and the potential of the second conductive region CR2 is set to the ground potential.

[0035] A ground potential is applied to the third terminal E3 (see FIG. 4) on the low-potential side, located away from the device 50, and the potential of the third conductive region CR3 is set to the ground potential. Since the third conductive region CR3 is electrically connected to the substrate 11, the potential of the third conductive region CR3 can also be set to the ground potential by setting the potential of the substrate 11 to the ground potential. In this case, the third terminal E3 is not necessary. Furthermore, if the second conductive region CR2 and the third conductive region CR3 are physically and electrically connected, the potential of the other conductive region can be controlled by applying a specific potential to only one conductive region. The third conductive region CR3 provides resistance to latch-up and noise. For example, consider a semiconductor chip with a low-voltage logic area next to a large-area DMOS transistor area. In this chip, even if an unexpected surge voltage or surge current is input into the DMOS transistor area, generating excessive current, this current can be absorbed by the through-type DTI including the third conductive region CR3. This makes it possible to suppress the introduction of excessive current into the logic area and prevent damage to the logic area.

[0036] FIG. 5 is a plan view of the device region 10 of the second embodiment.

[0037] The device region 10 of the second type has a structure in which the outer second trenches TR2 are removed, as compared with the device region of the first type. The number of third trenches TR3 in this example is greater than that in the first type. The remaining structure is the same as that of the semiconductor device having the device region of the first type. While 24 third trenches TR3 are shown in the figure as an example, the number may be 23 or less, or 25 or more.

[0038] This semiconductor device includes a first trench TR1 and a plurality of third trenches TR3 (the second trench in the order focused only on this example). The first trench TR1 penetrates the embedded semiconductor layer 13 from the surface of the above-described epitaxial semiconductor layer 14 (see FIG. 6), and further extends to a depth that penetrates the underlying epitaxial semiconductor layer 12 and reaches the inside of the substrate 11. Thereby, the occurrence of punch-through between adjacent N-type semiconductor regions can be suppressed, and the operation of the parasitic NPN bipolar transistor can be suppressed. The first trench TR1 is annular in plan view and surrounds the element region (device 50). A higher voltage is applied to the inner region of the annular first trench TR1 than to the outer region. Each of the plurality of third trenches TR3 penetrates the embedded semiconductor layer 13 from the surface of the above-described epitaxial semiconductor layer 14 (see FIG. 7), and further extends to a depth that penetrates the underlying epitaxial semiconductor layer 12 and reaches the inside of the substrate 11. Each of the plurality of third trenches TR3 extends outward from the first trench TR1 in plan view.

[0039] Similar to the structure of the above-described semiconductor device, in plan view, each third trench TR3 includes a first region R1 located on the first trench TR1 side and a second region R2 located on the opposite side of the first region R1. Also, similar to the device region of the first embodiment, in plan view, a first width Y1 perpendicular to the longitudinal direction of the first region R1 and a second width Y2 perpendicular to the longitudinal direction of the second region R2 satisfy the relationship Y1 < Y2.

[0040] FIG. 6 is a diagram showing a longitudinal cross-sectional configuration along the A-A arrow line of the device region shown in FIG. 5.

[0041] The longitudinal cross-sectional configuration of the device region 10 of the second embodiment has a structure in which the outer second trench (TR2) is removed as compared with the longitudinal cross-sectional configuration of the device region of the first embodiment (see FIG. 3). Other structures are the same as the structures shown in FIG. 3.

[0042] FIG. 7 is a diagram showing a longitudinal cross-sectional configuration along the B-B arrow line of the device region shown in FIG. 5.

[0043] In the device region of the second embodiment, similar to the first embodiment, the first region R1 of the third trench TR3 is electrically insulated from the substrate 11 (underlying semiconductor substrate), and a third conductive region CR3 electrically connected to the substrate 11 is embedded in the second region R2 of the third trench TR3. A ground potential is applied to the low-potential-side third terminal E3 located at a position away from the device 50, and the potential of the third conductive region CR3 is set to the ground potential. Since the third conductive region CR3 is electrically connected to the substrate 11, the potential of the third conductive region CR3 can also be set to the ground potential by setting the potential of the substrate 11 to the ground potential. In this case, the third terminal E3 may not be provided. By providing the third conductive region CR3, as described above, excess current or the like caused by a surge voltage or a surge current is sucked up by the through-type DTI provided with the third conductive region CR3, making it stronger against latch-up and noise. The device region of the second embodiment has the same structure as that of the first embodiment, except that it does not include the outer second trench.

[0044] FIG. 8 is a plan view of the device region of the third embodiment.

[0045] The device region 10 of the third embodiment has a structure in which the first conductive region CR1 located inside the first trench TR1 is removed as compared with the device region of the second embodiment. Other structures are the same as those of the semiconductor device provided with the device region of the second embodiment. Similar to the structure of the semiconductor device described above, in a plan view, each third trench TR3 includes a first region R1 located on the first trench TR1 side and a second region R2 located on the side opposite to the first region R1. Also, similar to the device regions of the first and second embodiments, in a plan view, a first width Y1 perpendicular to the longitudinal direction of the first region R1 and a second width Y2 perpendicular to the longitudinal direction of the second region R2 satisfy the relationship Y1 < Y2.

[0046] FIG. 9 is a diagram showing a longitudinal cross-sectional configuration along the line A-A of the device region shown in FIG. 8.

[0047] The vertical cross-sectional configuration of the device region 10 of the third embodiment is different from the vertical cross-sectional configuration of the device region of the second embodiment (see FIG. 6) in that the first conductive region CR1 is removed. The other structure is the same as the structure shown in FIG.

[0048] FIG. 10 is a diagram showing a vertical cross-sectional configuration of the device region taken along the arrow line BB shown in FIG.

[0049] In the device region of the third form, similarly to the second form, the first region R1 of the third trench TR3 is electrically insulated from the substrate 11 (the underlying semiconductor substrate), and a third conductive region CR3 electrically connected to the substrate 11 is embedded in the second region R2 of the third trench TR3. The longitudinal cross-sectional configuration of the device region 10 of the third form has a structure in which the first conductive region CR1 is removed, as compared with the longitudinal cross-sectional configuration of the device region of the second form (see FIG. 7). The other structure is the same as the structure shown in FIG. 7.

[0050] FIG. 11 is a plan view of a device region in the fourth embodiment.

[0051] The device region 10 of the fourth embodiment has a structure in which the first region R1 of the third trench TR3 is removed, as compared with the device region of the third embodiment. The remaining structure is the same as that of the semiconductor device having the device region of the third embodiment. In plan view, each third trench TR3 has the second region R2 described above. The second width Y2 perpendicular to the longitudinal direction of the second region R2 is, for example, 0.3 μm.

[0052] Fig. 12 is a diagram showing a vertical cross-sectional configuration of the device region taken along the line BB of the arrow shown in Fig. 11. The vertical cross-sectional configuration of the device region taken along the line AA of the device region shown in Fig. 11 is the same as the configuration shown in Fig. 9.

[0053] The device region 10 of the fourth embodiment has a structure in which the first region R1 in the third trench TR3 shown in Fig. 8 has been removed. The other configurations are the same as those shown in Fig. 8.

[0054] A semiconductor device having a device region of the fourth type includes an epitaxial semiconductor layer 14 formed on a substrate 11 via a buried semiconductor layer 13, and a first trench TR1. The first trench TR1 extends from the surface of the epitaxial semiconductor layer 14 through the buried semiconductor layer 13 and further extends to a depth that penetrates the underlying epitaxial semiconductor layer 12 and reaches the inside of the substrate 11. This makes it possible to suppress the occurrence of punch-through between adjacent N-type semiconductor regions and to suppress the operation of a parasitic NPN bipolar transistor. The first trench TR1 has an annular shape surrounding the element region (device 50) in a plan view.

[0055] The semiconductor device includes a plurality of third trenches TR3 (the order is the second trench when focusing only on the fourth form). Each third trench TR3 penetrates the buried semiconductor layer 13 from the surface of the epitaxial semiconductor layer 14, and further extends to a depth that penetrates the underlying epitaxial semiconductor layer 12 and reaches the inside of the substrate 11. This makes it possible to suppress the occurrence of punch-through between adjacent N-type semiconductor regions and suppress the operation of a parasitic NPN bipolar transistor. The plurality of third trenches TR3 are arranged at intervals so as to surround the first trench TR1 in a plan view.

[0056] In plan view, the intervals between the plurality of (five in this example) third trenches TR3 (third conductive regions CR3) aligned along one side in the X-axis direction of the first trench TR1 are equal. Note that the third trenches TR3 (third conductive regions CR3) aligned along one side (X-axis direction) do not include the third trenches TR3 located at the corners of the first trench TR1 in plan view. Similarly, the intervals between the plurality of (five in this example) third trenches TR3 (third conductive regions CR3) aligned along one side in the Y-axis direction of the first trench TR1 are equal. Note that the third trenches TR3 (third conductive regions CR3) aligned along one side (Y-axis direction) do not include the third trenches TR3 located at the corners of the first trench TR1 in plan view. In this way, the first trench TR1 has one side that extends linearly along one direction (X-axis direction or Y-axis direction) in a planar view, and the multiple third conductive regions CR3 embedded respectively in the multiple third trenches TR3 are aligned and equally spaced along the above-mentioned one side (X-axis direction or Y-axis direction) in a planar view.

[0057] The interval between the third conductive regions CR3 aligned along the direction of one side is the distance between the centers of gravity of the adjacent third conductive regions CR3 in plan view (=D X This distance (D X ) average value (D X(AVE) The above meaning of equal intervals is the intervals (D X ) average value (D X(AVE) ) deviation (D X -D X(AVE) ) is the average value (D X(AVE) ) within ±5% (D X(AVE) ×(-5%)≦(D X -D X(AVE) )≦D X(AVE) × 5%). Note that the number of third trenches TR3 (third conductive regions CR3) along one side is not limited to five as illustrated, and may be less than five or may be five or more.

[0058] In plan view, the third trench TR3 is filled with a third conductive region CR3 electrically connected to the substrate 11. By removing the first region R1 of the third trench TR3 shown in FIG. 10, the first trench TR1 and the third trench TR3 are completely separated from each other.

[0059] FIG. 13 is a diagram showing a longitudinal cross-sectional configuration of an example of the device 50. As shown in FIG.

[0060] The FET constituting the device 50 is made of silicon (Si) and includes an N-type well region 51, a P-type well region 52, a source region SR, a drain region DR, a gate insulating film GX, and a gate electrode G1. The N-type well region 51 is made of an N-type semiconductor, and the P-type well region 52 is made of a P-type semiconductor. The source region SR and the drain region DR are made of N-type semiconductors. The gate insulating film GX is made of SiO2. The gate electrode G1 can be made of polysilicon, but may also contain metals such as copper (Cu) or aluminum (Al), alloys containing one or more metals, or compounds of metal and silicon (silicides). The FET may also include a second transistor Q2 having a symmetrical structure to the transistor structure consisting of these elements. The FET may also be a DMOS-FET. A P-type contact region may also be provided adjacent to the source region SR.

[0061] To manufacture the above-described structure, the underlying epitaxial semiconductor layer 12, the buried semiconductor layer 13, and the epitaxial semiconductor layer 14 are sequentially formed on the substrate 11, and then the trenches are formed by mask patterning and etching. The buried semiconductor layer 13 can be formed by ion implantation. If necessary, impurities are added to the inner surface of the trench by ion implantation to form impurity-doped layers (first impurity-doped layer S1, second impurity-doped layer S2, and third impurity-doped layer S3). Thermal oxidation of the inner surface of the trench can form insulating layers (first insulating layer I1, second insulating layer I2, and third insulating layer I3) made of silicon dioxide or the like that cover the inner surface of the trench. Each insulating layer can include multiple insulating layers. Alternatively, the silicon dioxide layer can be formed by chemical vapor deposition (CVD) using TEOS (Si(OC2H5)4).

[0062] After etching the insulating layer inside the trench as needed, a conductive material such as impurity-doped polysilicon is embedded inside the trench by sputtering or the like to form each conductive region (first conductive region CR1, second conductive region CR2, third conductive region CR3). After the conductive regions are formed, the semiconductor substrate surface can be subjected to chemical mechanical polishing (CMP) as needed. An insulating region 18 can be formed on the exposed surface of the semiconductor substrate. Methods for forming the insulating region 18 include thermal oxidation of the exposed surface or etching the exposed surface followed by embedding silicon dioxide by CVD. After the isolation structure is formed, a device 50 such as a transistor can be formed within the region surrounded by the isolation structure. Note that a CVD method using silane (SiH4) can also be used as a method for forming a conductive region containing an epitaxial layer or polysilicon.

[0063] Next, the materials and impurity concentrations of the above-mentioned semiconductor regions will be described.

[0064] The semiconductor material constituting the semiconductor chip 100 described above is silicon (Si). Compound semiconductors can also be used as the semiconductor material constituting the semiconductor chip 100. Compound semiconductors include III-V compound semiconductors, IV-IV compound semiconductors, and alloy semiconductors using these semiconductors. Ga-containing semiconductors such as GaAs and GaN can be used as III-V compound semiconductors. Si-containing semiconductors such as SiC and SiGe can be used as IV-IV compound semiconductors.

[0065] More specifically, the material of the substrate 11 is silicon (Si). The material of the substrate 11 can also be made of a compound semiconductor such as silicon carbide (SiC) or gallium nitride (GaN). The conductivity type of the substrate 11 is P-type (first conductivity type), and the impurity concentration (C 11 ) is, for example, 1×10 14 cm -3 ~5×10 18 cm -3 The thickness of the substrate 11 is, for example, 250 μm to 800 μm.

[0066] The material of the underlying epitaxial semiconductor layer 12 can be the same as the semiconductor material of the substrate 11. The conductivity type of the underlying epitaxial semiconductor layer 12 is P-type (first conductivity type). 12 ) is, for example, 1×10 13 cm -3 ~5×10 16 cm -3 can be set to.

[0067] The material of the buried semiconductor layer 13 can be the same as the semiconductor material of the substrate 11. The conductivity type of the buried semiconductor layer 13 is N-type (second conductivity type), and the impurity concentration (C 13 ) is, for example, 1×10 17 cm -3 ~1×10 19 cm -3 The thickness of the buried semiconductor layer 13 can be set to, for example, 1 μm to 5 μm.

[0068] The material of the epitaxial semiconductor layer 14 can be the same as the semiconductor material of the substrate 11. The conductivity type of the epitaxial semiconductor layer 14 is N-type (second conductivity type), and the impurity concentration (C 14 ) is, for example, 5×10 14 cm -3 ~1×10 17 cm -3 The thickness of the epitaxial semiconductor layer 14 can be set to, for example, 3 μm to 20 μm. In this example, the impurity concentration is 14 <C 11 <C 13 The conductivity type of the epitaxial semiconductor layer 14 can be P-type depending on the purpose of reducing the drain capacitance of an N-channel DMOS transistor or the like.

[0069] The material of the N-type well region 51 can be the same as the semiconductor material of the substrate 11. The conductivity type of the N-type well region 51 is N-type (second conductivity type), and the impurity concentration (C 51 ) is, for example, 1×10 16 cm -3 ~1×10 18 cm -3 The thickness of the N-type well region 51 can be set to, for example, 0.5 μm to 4 μm.

[0070] The material of the P-type well region 52 can be the same as the semiconductor material of the substrate 11. The conductivity type of the P-type well region 52 is P type (first conductivity type), and the impurity concentration (C 52 ) is, for example, 1×10 16 cm -3 ~1×10 18 cm -3 The thickness of the P-type well region 52 can be set to, for example, 0.5 μm to 4 μm.

[0071] The material of the source region SR and the drain region DR can be the same as the semiconductor material of the substrate 11. The conductivity type of the source region SR and the drain region DR is N-type (second conductivity type), and the impurity concentrations (C SR , C DR ) is, for example, 1×1019 cm -3 ~5×10 21 cm -3 The thickness of the source region SR and the drain region DR can be set to, for example, 0.2 μm to 1 μm, but a structure in which the depth is made shallower or deeper is also possible.

[0072] The impurity concentrations of the first impurity doped layer S1, the second impurity doped layer S2, and the third impurity doped layer S3 can be set to, for example, the same as the concentration of the buried semiconductor layer 13. Furthermore, the first conductive region CR1, the second conductive region CR2, and the third conductive region CR3 can be doped with high concentrations of impurities. A high concentration of impurities may also be doped into a region of the substrate 11 located below the third conductive region CR3. The impurity concentrations of the first to third conductive regions are, for example, 1×10 18 cm -3 More than 1×10 22 cm -3 As the material for these conductive regions, tungsten, copper, or other materials may be used instead of polysilicon.

[0073] (Supplementary Note) As described above, various embodiments of the present disclosure can be defined as the following supplementary notes.

[0074] [A1] A semiconductor device comprising: a base epitaxial semiconductor layer 12 formed on a substrate 11; an epitaxial semiconductor layer 14 formed on the base epitaxial semiconductor layer 12 via an embedded semiconductor layer 13; a first trench TR1 that extends from the surface of the epitaxial semiconductor layer 14 to a depth penetrating the base epitaxial semiconductor layer 12 and surrounds an element region (device 50) in a plan view; a second trench TR2 that extends from the surface of the epitaxial semiconductor layer 14 to a depth penetrating the base epitaxial semiconductor layer 12 and surrounds the first trench TR1 in a plan view; and a third trench TR3 that extends from the surface of the epitaxial semiconductor layer 14 to a depth penetrating the base epitaxial semiconductor layer 12 and connects the first trench TR1 and the second trench TR2 in a plan view. In the plan view, the third trench TR3 includes a first region R1 located on the first trench TR1 side and a second region R2 located on the second trench TR2 side. The first region R1 of the third trench TR3 is electrically insulated from the substrate 11, and a conductive region (third conductive region CR3) electrically connected to the substrate 11 is embedded in the second region R2 of the third trench TR.

[0075] [A2] The semiconductor device according to [A1], wherein in a plan view, a first width Y1 perpendicular to the longitudinal direction of the first region R1 and a second width Y2 perpendicular to the longitudinal direction of the second region R2 satisfy the relationship Y1 < Y2.

[0076] [A3] The semiconductor device according to [A1] or [A2], comprising a first conductive region CR1 embedded in the first trench TR1.

[0077] [A4] The semiconductor device according to any one of [A1] to [A3], comprising a second conductive region CR2 embedded in the second trench TR2.

[0078] [A5] The semiconductor device according to [A4], wherein the conductive region (third conductive region CR3) embedded in the third trench TR3 is physically and electrically connected to the second conductive region CR2.

[0079] [A6] A base epitaxial semiconductor layer 12 formed on a substrate 11, an epitaxial semiconductor layer 14 formed on the base epitaxial semiconductor layer 12 via an embedded semiconductor layer 13, a first trench TR1 that extends from the surface of the epitaxial semiconductor layer 14 to a depth penetrating the base epitaxial semiconductor layer 12 and that surrounds an element region (device 50) in a plan view, and a plurality of second trenches (third trenches TR3) that extend from the surface of the epitaxial semiconductor layer 14 to a depth penetrating the base epitaxial semiconductor layer 12 and that extend outward from the first trench TR1 in a plan view. In the plan view, the second trench (third trench TR3) includes a first region R1 located on the first trench TR1 side and a second region R2 located on the side opposite to the first region R1. The first region R1 of the second trench (third trench TR3) is electrically insulated from the substrate 11, and a conductive region (third conductive region CR3) electrically connected to the substrate 11 is embedded in the second region R2 of the second trench (third trench TR3). A semiconductor device.

[0080] [A7] In a plan view, a first width Y1 perpendicular to the longitudinal direction of the first region R1 and a second width Y2 perpendicular to the longitudinal direction of the second region R2 satisfy the relationship Y1 < Y2. The semiconductor device according to [A6].

[0081] [A8] The semiconductor device according to [A6] or [A7], comprising a first conductive region CR1 embedded in the first trench TR1.

[0082] [A9] A semiconductor device comprising: an underlying epitaxial semiconductor layer 12 formed on a substrate 11; an epitaxial semiconductor layer 14 formed on the underlying epitaxial semiconductor layer 12 with a buried semiconductor layer 13 interposed therebetween; an annular first trench TR1 extending from a surface of the epitaxial semiconductor layer 14 to a depth penetrating the underlying epitaxial semiconductor layer 12 and surrounding an element region (device 50) in a planar view; and a plurality of second trenches (third trenches TR3) extending from the surface of the epitaxial semiconductor layer 14 to a depth penetrating the underlying epitaxial semiconductor layer 12 and arranged at a distance from each other so as to surround the first trench in a planar view, wherein a conductive region (third conductive region CR3) electrically connected to the substrate 11 is buried in the second trench TR2 in a planar view.

[0083] [A10] A semiconductor device according to [A9], wherein the first trench TR1 has one side extending linearly along one direction in a planar view, and the second conductive regions (third conductive regions CR3) embedded in the second trenches (third trenches TR3) are aligned and equally spaced along the one side in a planar view.

[0084] Although various exemplary embodiments have been described above, various omissions, substitutions, and modifications may be made without being limited to the above-described exemplary embodiments. Furthermore, elements from different embodiments may be combined to form other embodiments. It will be understood from the above description that various embodiments of the present disclosure have been described herein for illustrative purposes, and that various modifications may be made without departing from the scope and spirit of the present disclosure. Accordingly, the various embodiments disclosed herein are not intended to be limiting, with the true scope and spirit being indicated by the appended claims. [Explanation of symbols]

[0085] 100...semiconductor chip, 3...first main surface, 4...second main surface, 5A...first side surface, 5B...second side surface, 5C...third side surface, 5D...fourth side surface, 10...device region, 50...device, TR1...first trench, TR2...second trench, TR3...third trench, CR1...first conductive region, CR2...second conductive region, CR3...third conductive region, E1...first terminal, E2...second terminal, E3...third terminal, 1...semiconductor substrate, 11...substrate, 12...underlying epitaxial layer a buried semiconductor layer, 13...buried semiconductor layer, 14...epitaxial semiconductor layer, 18...insulating region, I1...first insulating layer, I2...second insulating layer, I3...third insulating layer, S1...first impurity doped layer, S2...second impurity doped layer, S3...third impurity doped layer, R1...first region, R2...second region, 51...N-type well region, 52...P-type well region, SR...source region, DR...drain region, GX...gate insulating film, G1...gate electrode, Q2...second transistor.

Claims

1. an underlying epitaxial semiconductor layer formed on a substrate; an epitaxial semiconductor layer formed on the underlying epitaxial semiconductor layer via a buried semiconductor layer; a first trench having an annular shape in a plan view, the first trench extending from a surface of the epitaxial semiconductor layer to a depth penetrating the underlying epitaxial semiconductor layer and surrounding an element region; a second trench having an annular shape in a plan view, the second trench extending from a surface of the epitaxial semiconductor layer to a depth penetrating the underlying epitaxial semiconductor layer and surrounding the first trench; a third trench extending from a surface of the epitaxial semiconductor layer to a depth penetrating the underlying epitaxial semiconductor layer and connecting the first trench and the second trench in a plan view; Equipped with In a plan view, the third trench has a first region located on the first trench side; a second region located on the second trench side; Equipped with the first region of the third trench is electrically isolated from the substrate; a conductive region electrically connected to the substrate is embedded in the second region of the third trench; Semiconductor device.

2. In plan view, a first width Y1 perpendicular to the longitudinal direction of the first region; The second width Y2 perpendicular to the longitudinal direction of the second region is Y1<Y2, The relationship between The semiconductor device according to claim 1 .

3. a first conductive region embedded in the first trench; The semiconductor device according to claim 1 .

4. a second conductive region embedded in the second trench; The semiconductor device according to claim 1 .

5. the conductive region embedded in the third trench is physically and electrically connected to the second conductive region; The semiconductor device according to claim 4 .

6. an underlying epitaxial semiconductor layer formed on a substrate; an epitaxial semiconductor layer formed on the underlying epitaxial semiconductor layer via a buried semiconductor layer; a first trench having an annular shape in a plan view, the first trench extending from a surface of the epitaxial semiconductor layer to a depth penetrating the underlying epitaxial semiconductor layer and surrounding an element region; a plurality of second trenches extending from a surface of the epitaxial semiconductor layer to a depth penetrating the underlying epitaxial semiconductor layer and extending outward from the first trenches in a plan view; Equipped with In a plan view, the second trench has a first region located on the first trench side; a second region located on the opposite side to the first region; Equipped with the first region of the second trench is electrically isolated from the substrate; a conductive region electrically connected to the substrate is embedded in the second region of the second trench; Semiconductor device.

7. In plan view, a first width Y1 perpendicular to the longitudinal direction of the first region; The second width Y2 perpendicular to the longitudinal direction of the second region is Y1<Y2, The relationship between The semiconductor device according to claim 6.

8. a first conductive region embedded in the first trench; The semiconductor device according to claim 6.

9. an underlying epitaxial semiconductor layer formed on a substrate; an epitaxial semiconductor layer formed on the underlying epitaxial semiconductor layer via a buried semiconductor layer; a first trench having an annular shape in a plan view, the first trench extending from a surface of the epitaxial semiconductor layer to a depth penetrating the underlying epitaxial semiconductor layer and surrounding an element region; a plurality of second trenches extending from a surface of the epitaxial semiconductor layer to a depth penetrating the underlying epitaxial semiconductor layer and arranged at a distance from the first trench in a plan view so as to surround the first trench; Equipped with a conductive region electrically connected to the substrate is embedded in the second trench in a plan view; Semiconductor device.

10. the first trench has one side extending linearly along one direction in a plan view, the conductive regions embedded in the second trenches are aligned along the one side and arranged at equal intervals in a plan view; The semiconductor device according to claim 9 .

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