Driving circuit board and manufacturing method for driving circuit board

Abstract

To provide a driving circuit board that efficiently uses a polycrystalline silicon layer and an oxide semiconductor layer.SOLUTION: A driving circuit board (1) includes a unit driving circuit (DRU) including: a first semiconductor layer (3) corresponding to a polycrystalline silicon layer including a first channel region (CHR1), a first source region (SR1), and a first drain region (DR1); a first insulating layer (4) provided on the first semiconductor layer (3); a second counter electrode (G-CE2) also serving as a first gate electrode provided on the first insulating layer (4) so as to overlap with a part of the first channel region (CHR1) and the first source region (SR1), which is a first counter electrode (CE1) in a plan view and containing conductive impurities and an oxide semiconductor; and a first transistor (T1) including a first drain electrode (D) electrically connected to the first drain region (DR1), a first source electrode (S) electrically connected to the first source region (SR1), and a holding capacitor (Cs) including the first counter electrode (CE1) and the second counter electrode (G-CE2).SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present disclosure relates to a drive circuit board and a method for manufacturing the drive circuit board. [Background technology]

[0002] In recent years, drive circuit boards equipped with a plurality of unit drive circuits each including a transistor have been frequently used in the field of display devices as pixel circuits that display in the display area of ​​the display device, or as drivers that are provided in the non-display area of ​​the display device and drive the pixel circuits. Because these boards can also be applied to a variety of fields other than display devices, such as 3D printers and fingerprint sensors, research and development into these boards is being actively conducted. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] U.S. Patent Publication US2015 / 0055051 [Patent Document 2] U.S. Patent Publication US2015 / 0053935 Summary of the Invention [Problem to be solved by the invention]

[0004] Patent Documents 1 and 2 describe a drive circuit substrate including a plurality of unit drive circuits, each including a drive transistor and a selection transistor, that is used as a pixel circuit for displaying in the display area of ​​a display device. However, one of the drive transistors and the selection transistors included in the unit drive circuits described in Patent Documents 1 and 2 includes only a polycrystalline silicon layer as a semiconductor layer, while the other of the drive transistors and the selection transistor includes only an oxide semiconductor layer as a semiconductor layer. Therefore, the unit drive circuits described in Patent Documents 1 and 2 do not efficiently utilize the polycrystalline silicon layer and the oxide semiconductor layer.

[0005] An object of one aspect of the present disclosure is to provide a drive circuit board that efficiently utilizes a polycrystalline silicon layer and an oxide semiconductor layer, and a method for manufacturing the drive circuit board. [Means for solving the problem]

[0006] In order to solve the above problems, the drive circuit board of the present disclosure has: a first semiconductor layer including a first channel region that is a part of a polycrystalline silicon layer, and a first source region and a first drain region that are formed in a region of the polycrystalline silicon layer different from the first channel region and that contain impurities; a first insulating layer provided on the first semiconductor layer; a first gate electrode and second counter electrode, which is provided on the first insulating layer so as to overlap with the first channel region and a part of the first source region, which is a first counter electrode, in a plan view, and which contains a conductive impurity and an oxide semiconductor; a first drain electrode electrically connected to the first drain region; a first source electrode electrically connected to the first source region; a unit driver circuit including a first transistor having a holding capacitor including the first opposing electrode and the second opposing electrode.

[0007] In order to solve the above-mentioned problems, the manufacturing method of the drive circuit board of the present disclosure includes: a first step of forming a polycrystalline silicon layer; a second step of forming a first insulating layer on the polycrystalline silicon layer; a third step of forming a resist film of a predetermined shape on the first insulating layer, and implanting impurities into a part of the polycrystalline silicon layer using the resist film as a mask, thereby forming a first channel region, a first source region containing the impurity, and a first drain region containing the impurity; a fourth step of forming a first gate electrode and second counter electrode containing a first oxide semiconductor layer and a conductive impurity on the first insulating layer so as to overlap, in a plan view, the first channel region and a part of the first source region which is a first counter electrode, after removing the resist film; a fifth step of forming a first drain electrode electrically connected to the first drain region and a first source electrode electrically connected to the first source region; A unit driver circuit is formed that includes a first transistor having a storage capacitor that includes the first opposing electrode and the second opposing electrode. [Effects of the Invention]

[0008] According to one aspect of the present disclosure, it is possible to provide a drive circuit board that efficiently utilizes a polycrystalline silicon layer and an oxide semiconductor layer, and a method for manufacturing the drive circuit board. [Brief explanation of the drawings]

[0009] [Figure 1] FIG. 3 is a circuit diagram of a unit driver circuit provided on a driver circuit board according to the first embodiment. [Figure 2] 3 is a cross-sectional view showing a schematic configuration of a first transistor provided on the drive circuit board of the first embodiment. FIG. [Figure 3] FIG. 1 is a plan view of a drive circuit board according to a first embodiment, showing a schematic configuration of the drive circuit board. [Figure 4] 1 is a cross-sectional view showing a schematic configuration of a drive circuit board according to a first embodiment. [Figure 5] 10 is a diagram comparing the on / off characteristics of the first transistor and the second transistor provided in the drive circuit board of the first embodiment with the on / off characteristics of a transistor provided with an amorphous silicon semiconductor layer. FIG. [Figure 6] 10 is a diagram showing the IV characteristics of a second channel region in a second semiconductor layer of a second transistor provided in the drive circuit board of the first embodiment. FIG. [Figure 7] FIG. 10 is a diagram showing the IV characteristics of the first gate electrode and second opposing electrode of the first transistor provided in the drive circuit board of embodiment 1, and the IV characteristics of the second source region and the second drain region in the second semiconductor layer of the second transistor. [Figure 8] 3A to 3C are diagrams illustrating some steps in a method for manufacturing a drive circuit board according to the first embodiment. [Figure 9] 5A to 5C are diagrams illustrating other steps in the method for manufacturing the drive circuit board according to the first embodiment. [Figure 10] 5A to 5C are diagrams showing still other steps in the method for manufacturing the drive circuit board according to the first embodiment. [Figure 11] 10A and 10B are diagrams illustrating some steps in a method for manufacturing a drive circuit board according to Comparative Example 1. [Figure 12] FIG. 10 is a cross-sectional view showing a schematic configuration of a drive circuit board according to a second embodiment. [Figure 13] FIG. 10 is a plan view showing a schematic configuration of a drive circuit board of Comparative Example 1. [Figure 14] 1 is a cross-sectional view showing a schematic configuration of a drive circuit board of Comparative Example 1. FIG. DETAILED DESCRIPTION OF THE INVENTION

[0010] The following describes embodiments of the present disclosure with reference to Figures 1 to 14. For the sake of convenience, components having the same functions as those described in specific embodiments will be denoted by the same reference numerals, and their description may be omitted.

[0011] [Embodiment 1] FIG. 1 is a circuit diagram of a unit driver circuit DRU provided on a driver circuit board 1 of embodiment 1. FIG. 2 is a cross-sectional view showing a schematic configuration of a first transistor T1 provided on the driver circuit board 1 of embodiment 1. FIG. 3 is a plan view of the driver circuit board 1 of embodiment 1, showing a schematic configuration of the driver circuit board 1. Note that FIG. 3 does not show a barrier layer 2, a first insulating layer 4, a second insulating layer 6, an interlayer insulating film 7, or a passivation film 8. FIG. 4 is a cross-sectional view showing a schematic configuration of the driver circuit board 1 of embodiment 1 taken along lines X1-X2 and Y1-Y2 shown in FIG. 3, respectively.

[0012] In this embodiment, as shown in FIG. 1, a case where a light-emitting element is provided as a functional unit FEL electrically connected to each unit driver circuit DRU is described as an example. However, this is not limited to this. The functional unit FEL electrically connected to the unit driver circuit DRU may be provided, for example, with a fingerprint sensor unit or an anode electrode for a 3D printer. Furthermore, for example, the unit driver circuit DRU shown in FIG. 1 may be a driver provided in a non-display area of ​​a display device. In this case, the functional unit FEL electrically connected to the unit driver circuit DRU may be a pixel circuit provided in a display area of ​​the display device. Note that in this embodiment, a case where the light-emitting element serving as the functional unit FEL is an OLED (organic light-emitting diode) is described as an example. However, this is not limited to this. The light-emitting element may be, for example, a QLED (quantum dot light-emitting diode) or a microLED.

[0013] In the unit driver circuit DRU and functional section FEL shown in FIG. 1, as shown in FIGS. 1, 2, and 4, the source electrode S of the first transistor T1, which is a drive transistor, is electrically connected to one electrode of the light-emitting element, which is the functional section FEL, for example, an anode electrode (not shown), and a first counter electrode CE1 of the storage capacitor Cs. As shown in FIGS. 1, 2, and 4, a first gate electrode / second counter electrode G-CE2 (shown in FIGS. 2 and 4) which is a common electrode is provided as the gate electrode of the first transistor T1 and the second counter electrode of the storage capacitor Cs. As shown in FIG. 3, the first gate electrode / second counter electrode G-CE2 is electrically connected to the second drain region DR2 of the second transistor T2, which is a selection transistor. As shown in FIG. 1, the drain electrode D of the first transistor T1 is connected to a high-potential power supply voltage line V to which a high-potential power supply voltage is supplied. DD1 and 4, the source electrode S' of the second transistor T2, which is a selection transistor, is electrically connected to a data signal line V to which a data signal is supplied. DATA The gate electrode G′ of the second transistor T2 is electrically connected to the scanning signal line V SEL 1, each unit driver circuit DRU includes a current-driven light-emitting element as a functional unit FEL electrically connected to the unit driver circuit DRU. Therefore, it is preferable that the first transistor T1, which is a drive transistor provided in each of the plurality of unit driver circuits DRU of the drive circuit substrate 1, has high current driving capability. On the other hand, the second transistor T2, which is a selection transistor, supplies a voltage corresponding to a data signal to the first transistor T1 in accordance with the timing of the scan signal and changes the voltage of the first transistor T1. Therefore, it is preferable that the second transistor T2 has transistor characteristics with low leakage current. Therefore, in this embodiment, as shown in FIGS. 2 and 4, the first transistor T1, which is a drive transistor, includes a first semiconductor layer 3 including a first channel region CHR1 that is a polycrystalline silicon layer, and the second transistor T2, which is a selection transistor, includes a second semiconductor layer 5b including a second channel region CHR2 that is an oxide semiconductor layer.

[0014] As shown in Figures 2 and 4, the drive circuit substrate 1 is equipped with a unit drive circuit DRU including a first transistor T1 having: a first channel region CHR1 that is a part of a polycrystalline silicon layer; a first semiconductor layer 3 that is formed in a region of the polycrystalline silicon layer different from the first channel region CHR1 and includes a first source region SR1 and a first drain region DR1 that contain impurities; a first insulating layer 4 that is provided on the first semiconductor layer 3; a first gate electrode and second counter electrode G-CE2 that is provided on the first insulating layer 4 so as to overlap, in a plan view, with the first channel region CHR1 and a part of the first source region SR1 that is the first counter electrode CE1, and that contains a conductive impurity and an oxide semiconductor; a first drain electrode D electrically connected to the first drain region DR1; a first source electrode S electrically connected to the first source region SR1; and a storage capacitor Cs that includes the first counter electrode CE1 and the second counter electrode G-CE2. In this embodiment, the case where the drive circuit board 1 includes a unit drive circuit DRU including a first transistor T1 and a second transistor T2 will be described as an example, but the present invention is not limited to this, and the drive circuit board 1 may include any unit drive circuit DRU including the first transistor T1. The first transistor T1 included in the drive circuit board 1 includes a first semiconductor layer 3 that is a polycrystalline silicon layer, and a first gate electrode and second counter electrode G-CE2 that is an oxide semiconductor layer containing conductive impurities, and therefore a drive circuit board 1 that efficiently utilizes the polycrystalline silicon layer and oxide semiconductor layer can be realized.

[0015] 2 and 4, the first gate electrode / second counter electrode G-CE2 provided on the drive circuit substrate 1 preferably further overlaps with a portion of the first drain region DR1 on the first channel region CHR1 side in a plan view. This configuration achieves an electric field relaxation effect, i.e., a reduction in the off current Ioff generated when the first transistor T1 is off. Therefore, in the first transistor T1, it is not necessary to provide a separate lightly doped drain (LDD) region between the first channel region CHR1 and the first drain region DR1 to achieve the above-mentioned electric field relaxation effect. Therefore, the unit drive circuit DRU including the first transistor T1 can be made smaller, and the unit drive circuit DRU including the first transistor T1 can be made higher-definition in the drive circuit substrate 1.

[0016] 3 and 4, the unit driver circuit DRU provided on the driver circuit substrate 1 includes a second transistor T2 in addition to the above-mentioned first transistor T1. As shown in Fig. 4, the second transistor T2 includes a second semiconductor layer 5b including a second channel region CHR2, a second source region SR2, and a second drain region DR2, a second insulating layer 6 provided on the second channel region CHR2 so as to overlap only with the second channel region CHR2 in a planar view, a second gate electrode G' provided on the second insulating layer 6 so as to overlap with the second channel region CHR2 in a planar view, and a second source electrode S' electrically connected to the second source region SR2. The second channel region CHR2 is formed in the same layer as the first gate electrode and second counter electrode G-CE2 and is made of the same material as the oxide semiconductor (in this embodiment, an In-Ga-Zn-O-based semiconductor) contained in the first gate electrode and second counter electrode G-CE2. The second source region SR2 and the second drain region DR2 are each formed in the same layer as the first gate electrode and second counter electrode G-CE2 and are made of the same material as the first gate electrode and second counter electrode G-CE2 (in this embodiment, an In-Ga-Zn-O-based semiconductor and conductive impurities). That is, as shown in FIG. 3, the drive circuit substrate 1 includes a second semiconductor layer 5 including an oxide semiconductor. As shown in FIG. 4, the second semiconductor layer 5 includes a second semiconductor layer 5a included in the first transistor T1 and a second semiconductor layer 5b included in the second transistor T2. The second semiconductor layer 5a included in the first transistor T1 includes conductive impurities and an oxide semiconductor and functions as the first gate electrode and second counter electrode G-CE2. The second source region SR2 and the second drain region DR2 in the second semiconductor layer 5b provided in the second transistor T2 each contain a conductive impurity and an oxide semiconductor, similar to the second semiconductor layer 5a provided in the first transistor T1, and the second channel region CHR2 in the second semiconductor layer 5b provided in the second transistor T2 is formed of the same material as the oxide semiconductor (in this embodiment, an In-Ga-Zn-O based semiconductor) included in the first gate electrode / second counter electrode G-CE2.

[0017] As described above, the second transistor T2 included in the unit driver circuit DRU provided on the driver circuit board 1 includes a second channel region CHR2 formed from the same material as the oxide semiconductor (in this embodiment, an In-Ga-Zn-O based semiconductor) included in the first gate electrode / second counter electrode G-CE2. As a result, as will be described later, an electric field relaxation effect can be achieved, that is, a reduction in the off current Ioff that occurs when the second transistor T2 is off. Since there is no need to provide a separate low concentration region LDD (Lightly Doped Drain), the unit driver circuit DRU including the first transistor T1 and the second transistor T2 can be made smaller, and in the driver circuit board 1, the unit driver circuit DRU including the first transistor T1 and the second transistor T2 can be made higher definition.

[0018] FIG. 5 is a diagram comparing the on / off characteristics of the first transistor T1 and the second transistor T2 provided on the drive circuit board 1 of the first embodiment with the on / off characteristics of a transistor including an amorphous silicon semiconductor layer.

[0019] In this embodiment, the first channel region CHR1, which is a polycrystalline silicon layer included in the first transistor T1, which is a drive transistor, is made of polysilicon formed at a low temperature, and the second channel region CHR2, which is an oxide semiconductor layer included in the second transistor T2, which is a select transistor, is made of an In-Ga-Zn-O based semiconductor, as an example, but this is not limiting. The first channel region CHR1, which is a polycrystalline silicon layer included in the first transistor T1, which is a drive transistor, may be made of polysilicon formed at a high temperature, for example, and the second channel region CHR2, which is an oxide semiconductor layer included in the second transistor T2, which is a select transistor, may be made of an oxide semiconductor other than In-Ga-Zn-O, for example.

[0020] As shown in FIG. 5, the mobility of the first transistor T1, which is a driving transistor and has a first channel region CHR1 that is a polycrystalline silicon layer, when the TFT is on, i.e., the value of the current Idd when the TFT is on, is greater than the mobility of the second transistor T2, which is a selection transistor and has a second channel region CHR2 that is an oxide semiconductor layer, and the comparative example transistor which has a channel region that is an amorphous silicon semiconductor layer, when the TFT is on, i.e., the value of the current Idd when the TFT is on, and the first transistor T1, which is a driving transistor, has high current driving capability.

[0021] 5, the mobility of the second transistor T2, which is a selection transistor and has a second channel region CHR2 that is an oxide semiconductor layer, when the TFT is on, i.e., the value of the current Idd when the TFT is on, is approximately 20 to 50 times higher than that of the comparative transistor having a channel region that is an amorphous silicon semiconductor layer. Also, the mobility of the second transistor T2, which is a selection transistor and has a second channel region CHR2 that is an oxide semiconductor layer, when the TFT is off, i.e., the value of the off current Idd when the TFT is off, is approximately 1 / 100 times lower than that of the comparative transistor having a channel region that is an amorphous silicon semiconductor layer, and is approximately 1 / 1000 times lower than that of the first transistor T1, which is a drive transistor and has a first channel region CHR1 that is a polycrystalline silicon layer. That is, the resistance value in the off state of the second transistor T2, which is a selection transistor having the second channel region CHR2 that is an oxide semiconductor layer, is about 100 times that of the comparative example transistor having a channel region that is an amorphous silicon semiconductor layer, and is about 1000 times that of the first transistor T1, which is a drive transistor having the first channel region CHR1 that is a polycrystalline silicon layer. As described above, the Ion / Ioff of the second transistor T2, which is a selection transistor having the second channel region CHR2 that is an oxide semiconductor layer, i.e., the ratio of the amount of current when the TFT is on to the amount of current when the TFT is off, is 10 9As a result, the Ion / Ioff of the first transistor T1, which is a driving transistor and includes the first channel region CHR1, which is a polycrystalline silicon layer, is 10 7 and the Ion / Ioff of the comparative transistor having a channel region that is an amorphous silicon semiconductor layer is 10 6 Therefore, the second transistor T2, which is a selection transistor and includes the second channel region CHR2 that is an oxide semiconductor layer, has transistor characteristics with a small leakage current.

[0022] 2 and 4, the first semiconductor layer 3 is provided on a barrier layer 2. The barrier layer 2 is a layer that prevents foreign substances such as water and oxygen from entering the first transistor T1 and the second transistor T2, and can be composed of, for example, a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a laminate film of these, formed by a CVD method. The thickness of the barrier layer 2 is not particularly limited as long as it can prevent foreign substances such as water and oxygen from entering the first transistor T1 and the second transistor T2.

[0023] 3, it is preferable that the second drain region DR2 of the second transistor T2 provided on the drive circuit board 1 and the first gate electrode / second counter electrode G-CE2 of the first transistor T1 are connected. With this configuration, there is no need for a contact hole for electrically connecting the second drain region DR2 provided on the second transistor T2 and the first gate electrode / second counter electrode G-CE2 provided on the first transistor T1, so the unit driver circuit DRU including the first transistor T1 and the second transistor T2 can be made smaller, and in the drive circuit board 1, the unit driver circuit DRU including the first transistor T1 and the second transistor T2 can be made higher-definition.

[0024] 4 contains, for example, hydrogen as a conductive impurity. When the interlayer insulating film 7 containing, for example, hydrogen as a conductive impurity is formed, the conductive impurity, for example, hydrogen in the interlayer insulating film 7 diffuses into the second semiconductor layer 5a of the first transistor T1 including an oxide semiconductor, which is in direct contact with the interlayer insulating film 7, and into the second source region SR2 and the second drain region DR2 of the second semiconductor layer 5b of the second transistor T2, respectively, and thereby the second source region SR2 and the second drain region DR2 of the second semiconductor layer 5b of the second transistor T2 and the first gate electrode / second counter electrode G-CE2, which is the second semiconductor layer 5a of the first transistor T1, become conductive. 4, in the drive circuit substrate 1, the interlayer insulating film 7 containing conductive impurities, for example, hydrogen, is provided on the second source region SR2, the second drain region DR2, and the first gate electrode and second counter electrode G-CE2, and is in contact with the second source region SR2, the second drain region DR2, and the first gate electrode and second counter electrode G-CE2, while the interlayer insulating film 7 containing conductive impurities, for example, hydrogen, is not in contact with the second channel region CHR2. As described above, in the drive circuit substrate 1, an interlayer insulating film containing conductive impurities, for example, hydrogen, is used as the interlayer insulating film 7, and the interlayer insulating film 7 is provided so as to be in direct contact with the portion of the oxide semiconductor layer that needs to be made conductive, thereby realizing the conductive nature of the oxide semiconductor layer, and therefore eliminating the need for an additional process of adding conductive impurities to the oxide semiconductor layer.

[0025] Fig. 6 is a diagram showing the IV characteristics of the second channel region CHR2 in the second semiconductor layer 5b of the second transistor T2 provided in the drive circuit board 1 of Embodiment 1. Fig. 7 is a diagram showing the IV characteristics of the first gate electrode / second counter electrode G-CE2 of the first transistor T1 provided in the drive circuit board 1 of Embodiment 1, and the IV characteristics of the second source region SR2 and the second drain region DR2 in the second semiconductor layer 5b of the second transistor T2.

[0026] The second insulating layer 6 shown in FIG. 4 is a silicon oxide film, and the interlayer insulating film 7 shown in FIG. 4 containing the conductive impurity, for example, hydrogen, is preferably a single layer film made of silicon nitride or a laminated film including a silicon nitride film as the bottom layer.

[0027] As shown in FIG. 4, in the second semiconductor layer 5b of the second transistor T2, the second channel region CHR2 including an oxide semiconductor is in contact with the second insulating layer 6 which is a silicon oxide film, and the second channel region CHR2 including an oxide semiconductor is oxidized by the second insulating layer 6 which is a silicon oxide film. As a result, the second channel region CHR2 including an oxide semiconductor is in a high-resistance state as shown in FIG. 6, compared with the second source region SR2, the second drain region DR2, and the first gate electrode / second counter electrode G-CE2 which include the conductive oxide semiconductor.

[0028] In this embodiment, a stacked film having a silicon nitride film as a lower layer and a silicon oxide film as an upper layer is used as the interlayer insulating film 7 containing a conductive impurity, e.g., hydrogen, as shown in FIG. 4. By using a stacked film containing a silicon nitride film containing a conductive impurity, e.g., hydrogen, as the bottom layer as in this embodiment, the silicon nitride film containing the conductive impurity, e.g., hydrogen, reduces the oxide semiconductor contained in the second source region SR2, the second drain region DR2, and the first gate electrode / second counter electrode G-CE2, converting them into conductors. The second source region SR2, the second drain region DR2, and the first gate electrode / second counter electrode G-CE2 containing the conductive oxide semiconductor are each in a low-resistance state compared to the second channel region CHR2 containing the oxide semiconductor, as shown in FIG. 7.

[0029] In this embodiment, a laminated film including a silicon nitride film is used as the bottom layer, but a film other than a silicon nitride film may be used as long as it contains a certain amount of hydrogen or more and can supply hydrogen to the oxide semiconductor, i.e., can reduce the oxide semiconductor. Therefore, the interlayer insulating film 7 containing the conductive impurity, for example, hydrogen, shown in Figure 4 may be a single layer film made of any of silicon nitride, silicon nitride oxide, and silicon oxide, or a laminated film containing two or more of a silicon nitride film, a silicon nitride oxide film, and a silicon oxide film.

[0030] Fig. 13 is a plan view showing a schematic configuration of a drive circuit board 100 of Comparative Example 1. Note that the barrier layer 2, the first insulating layer 4, the interlayer insulating film 15, and the passivation film 8 are not shown in Fig. 13. Fig. 14 is a cross-sectional view showing a schematic configuration of the drive circuit board 100 of Comparative Example 1 taken along the X3-X4 line and the Y3-Y4 line shown in Fig. 13, respectively.

[0031] 13 and 14, the drive circuit substrate 100 of Comparative Example 1 includes a unit drive circuit DRU including a first transistor T1r having a storage capacitor Csr including a first opposing electrode CE1 and a second opposing electrode CE2, and a second transistor T2r having a second gate electrode G' with a double-gate structure. The first transistor T1r includes a first channel region CHR1 that is a part of a polycrystalline silicon layer, and a first semiconductor layer 93 that is formed in a region of the polycrystalline silicon layer different from the first channel region CHR1 and includes a first source region SR1 and a first drain region DR1 that contain impurities. The second transistor T2r also includes second channel regions CHR2 and CHR2' that are part of the polycrystalline silicon layer, and a second semiconductor layer 93' that is formed in a region of the polycrystalline silicon layer different from the second channel regions CHR2 and CHR2' and includes a second source region SR2, a second drain region DR2, and a high-concentration region HDR that contain impurities. The first transistor T1r includes a first drain electrode D electrically connected to the first drain region DR1 via contact hole CON14 and a first source electrode S electrically connected to the first source region SR1 via contact hole CON15, and the second transistor T2r includes a second source electrode S' electrically connected to the second source region SR2 via contact hole CON12 and a second drain electrode D' electrically connected to the second drain region DR2 via contact hole CON13.

[0032] As shown in FIGS. 13 and 14 , in the case of the first transistor T1r included in the drive circuit board 100 of Comparative Example 1, the first gate electrode G and the second opposing electrode CE2 are provided as different layers. Therefore, in the drive circuit board 100 of Comparative Example 1, contact holes CON18 and CON19 for electrically connecting the first gate electrode G and the second opposing electrode CE2 must be provided in the interlayer insulating film 15. As described above, the formation area of ​​the first transistor T1r included in the drive circuit board 100 of Comparative Example 1, which is provided with contact holes CON18 and CON19 that were unnecessary in the drive circuit board 1 of Embodiment 1, is larger than the formation area of ​​the first transistor T1 included in the drive circuit board 1 of Embodiment 1. Therefore, in the drive circuit board 100 of Comparative Example 1, it is more difficult to achieve high-definition unit drive circuits DRU compared to the drive circuit board 1 of Embodiment 1.

[0033] 13 and 14, the first transistor T1r and the second transistor T2r included in the drive circuit substrate 100 of Comparative Example 1 each include a first channel region CHR1 and a second channel region CHR2 / CHR2', which are polycrystalline silicon layers. Therefore, in the first transistor T1r, a low-concentration region LDR1 must be provided between the first channel region CHR1 and the first drain region DR1 to achieve an electric field relaxation effect. Similarly, in the second transistor T2r, a low-concentration region LDR6 must be provided between the second channel region CHR2' and the second drain region DR2, and between the second channel region CHR2 and the high-concentration region HDR to achieve an electric field relaxation effect. As described above, the formation area of ​​the first transistor T1r and the second transistor T2r provided in the drive circuit board 100 of Comparative Example 1, which is provided with the lightly doped drain (LDD) regions that were unnecessary in the drive circuit board 1 of Embodiment 1, is larger than the formation area of ​​the first transistor T1 and the second transistor T2 provided in the drive circuit board 1 of Embodiment 1. Therefore, it is difficult to achieve high-definition unit drive circuits DRU in the drive circuit board 100 of Comparative Example 1 compared to the drive circuit board 1 of Embodiment 1. Note that the first transistor T1r provided in the drive circuit board 100 of Comparative Example 1 has a lightly doped drain region LDR1 on the drain side and a lightly doped source region LDR2 on the source side. Furthermore, the second transistor T2r provided in the drive circuit board 100 of Comparative Example 1 has lightly doped drain regions LDR4 and LDR6 on the drain side and lightly doped source regions LDR3 and LDR5 on the source side.

[0034] Fig. 8 is a diagram showing some steps in the method for manufacturing the drive circuit board 1 of embodiment 1. Fig. 9 is a diagram showing other steps in the method for manufacturing the drive circuit board 1 of embodiment 1. Fig. 10 is a diagram showing still other steps in the method for manufacturing the drive circuit board 1 of embodiment 1. Fig. 11 is a diagram showing some steps in the method for manufacturing the drive circuit board 100 of comparative example 1.

[0035] 8, the manufacturing method of the drive circuit board 1 of the first embodiment includes a first step S1 of forming a polycrystalline silicon layer PS' on the barrier layer 2, a second step S2 of forming a first insulating layer 4 on the polycrystalline silicon layer PS', and a third step S3 of forming a resist film RM of a predetermined shape on the first insulating layer 4 and implanting impurities into parts of the polycrystalline silicon layer PS' using the resist film RM as a mask to form a first semiconductor layer 3 including a first channel region CHR1, a first source region SR1 containing the impurity, and a first drain region DR1 containing the impurity. The first step S1 shown in FIG. 8 includes a step S1a of forming an amorphous silicon layer on the barrier layer 2, followed by annealing (heat treatment) for dehydrogenation at, for example, 450°C, and then processing with an excimer laser at a relatively low temperature to obtain a polysilicon film PS formed at low temperature, and a step S1b of etching the polysilicon film PS using the resist film to form island-shaped polycrystalline silicon layers PS' on the barrier layer 2. In this embodiment, the island-shaped polycrystalline silicon layer PS' is formed to a thickness of, for example, 40 nm, but is not limited thereto. In the second step S2 shown in FIG. 8, for example, a silicon oxide film is formed and then annealed (heat treated) to obtain a first insulating layer 4 with a thickness of 85 nm. In the second step S2 shown in FIG. 8, the first insulating layer 4 is formed in addition to the island-shaped polycrystalline silicon layer PS'. In the third step S3 shown in FIG. 8, a resist film RM is used as a mask to perform high-concentration impurity implantation (HDP), thereby forming a first channel region CHR1 that is protected by the resist film RM and does not contain impurities, and a first source region SR1 and a first drain region DR11 that contain high-concentration impurities and have higher impurity concentrations than the first channel region CHR1. In this embodiment, the first channel region CHR1 is made of, for example, polysilicon, which is a semiconductor that does not contain impurities, and the first source region SR1 and first drain region DR1 that contain impurities are each formed by implanting impurities into polysilicon, which is a semiconductor that does not contain impurities.In this embodiment, the first source region SR1 and the first drain region DR1 containing impurities are formed by implanting P (phosphorus ions), which is an N-type impurity, as the impurity. However, the present invention is not limited to this, and for example, the first source region SR1 and the first drain region DR1 may be formed by implanting As (arsenic ions), which is an N-type impurity, or B (boron ions), which is a P-type impurity.

[0036] As shown in Fig. 9, the manufacturing method of the drive circuit substrate 1 of Embodiment 1 further includes a fourth step S4 of forming a first gate electrode / second counter electrode G-CE2 containing a first oxide semiconductor layer OX and a conductive impurity on the first insulating layer 4 after removing the resist film RM, so as to overlap, in a plan view, the first channel region CHR1 and a portion of the first source region SR1, which is the first counter electrode CE1. Then, as shown in Fig. 10, the manufacturing method of the drive circuit substrate 1 of Embodiment 1 further includes a fifth step S5 of forming a first drain electrode D electrically connected to the first drain region DR1 and a first source electrode S electrically connected to the first source region SR1, thereby forming a unit drive circuit DRU including a first transistor T1 with a storage capacitor Cs including the first counter electrode CE1 and the second counter electrode G-CE2. Note that, as shown in Fig. 10, the manufacturing method of the drive circuit substrate 1 of Embodiment 1 may further include a sixth step S6 of forming a passivation film 8 after the fifth step S5. The fourth step S4 shown in FIG. 9 includes an oxide semiconductor layer formation step S4a of forming, on the first insulating layer 4, the first oxide semiconductor layer OX included in the first transistor T1 and the second oxide semiconductor layer OX included in the second transistor T2 as the same layer and made of the same material; a step S4b of forming the second insulating layer 6 and the second gate electrode G′ on the second insulating layer 6; and a step S4c of forming the interlayer insulating film 7 containing conductive impurities. Step S4b of forming the second insulating layer 6 and the second gate electrode G' on the second insulating layer 6 includes: step S4b1 of forming an inorganic film 6P, a part of which will become the second insulating layer 6, over the entire surface of the first insulating layer 4, the first oxide semiconductor layer OX, and the second oxide semiconductor layer OX, and then forming a metal film GP, a part of which will become the second gate electrode G', over the entire surface; a second insulating layer forming step of forming the second insulating layer 6 so that it overlaps only a part of the second oxide semiconductor layer OX included in the second transistor T2, which is the second channel region CHR2, in a planar view; and a second gate electrode forming step of forming the second gate electrode G' on the second insulating layer 6 so that it overlaps with the second channel region CHR2 in a planar view.In this embodiment, the second insulating layer forming step of forming the second insulating layer 6 and the second gate electrode forming step are performed as a single step S4b2. However, this is not limiting. The second insulating layer forming step of forming the second insulating layer 6 and the second gate electrode forming step may be performed as separate steps. In this embodiment, the first oxide semiconductor layer OX included in the first transistor T1 and the second oxide semiconductor layer OX included in the second transistor T2 are formed using an In-Ga-Zn-O-based semiconductor material with a thickness of, for example, 30 nm, but this is not limiting. In this embodiment, the second insulating layer 6 is formed using a silicon oxide film with a thickness of, for example, 100 nm, but this is not limiting. In this embodiment, the second gate electrode G′ is formed using MoW with a thickness of, for example, 300 nm, but this is not limiting. 9, the interlayer insulating film 7 containing conductive impurities is formed so as to be in contact with the first oxide semiconductor layer OX included in the first transistor T1 and the second oxide semiconductor layer OX included in the second transistor T2 other than the second channel region CHR2, thereby forming the second source region SR2 containing the conductive impurities, the second drain region DR2 containing the conductive impurities, and the first gate electrode / second counter electrode G-CE2 containing the conductive impurities. In this embodiment, the interlayer insulating film 7 containing conductive impurities is formed using a stacked film having a lower layer which is, for example, a silicon nitride film with a thickness of 160 nm and an upper layer which is, for example, a silicon oxide film with a thickness of 680 nm, but the present invention is not limited to this.

[0037] 10 includes a contact hole forming step S5a of forming a contact hole CON1 exposing the second source region SR2 of the second transistor T2, a contact hole CON2 exposing the first drain region DR1 of the first transistor T1, and a contact hole CON3 exposing the first source region SR1 of the first transistor T1. Note that the contact hole CON1 is a contact hole formed in the interlayer insulating film 7, and the contact holes CON2 and CON3 are contact holes formed in both the first insulating layer 4 and the interlayer insulating film 7. The fifth step S5 shown in FIG. 10 further includes a step S5b of forming a first drain electrode D electrically connected to the first drain region DR1, a first source electrode S electrically connected to the first source region SR1, and a second source electrode S' electrically connected to the second source region SR2. In this embodiment, the first drain electrode D, the first source electrode S, and the second source electrode S′ are each formed using a stacked film of, for example, a 30 nm thick Ti film, a 300 nm thick Al film, and a 20 nm thick Ti film, but the present invention is not limited to this.

[0038] In the sixth step S6 of forming the passivation film 8 shown in FIG. 10, the passivation film 8 is formed using, for example, a silicon nitride film with a thickness of 300 nm, but is not limited to this.

[0039] 9, it is preferable to form the first gate electrode / second counter electrode G-CE2 so that it further overlaps with a portion of the first drain region DR1 on the first channel region CHR1 side in plan view. This can achieve an electric field relaxation effect, i.e., a reduction in the off current Ioff generated when the first transistor T1 is off. Therefore, it is not necessary to provide a separate lightly doped drain (LDD) region between the first channel region CHR1 and the first drain region DR1 in the first transistor T1 to achieve the above-described electric field relaxation effect. Therefore, the unit driver circuit DRU including the first transistor T1 can be made smaller, and the unit driver circuit DRU including the first transistor T1 can be made higher-definition in the driver circuit substrate 1.

[0040] 9, it is preferable to form a connection between the second drain region DR2 and the first gate electrode / second counter electrode G-CE2, and to form a second source electrode S' electrically connected to the second source region SR2 in a fifth step S5 shown in Fig. 10. In this way, a contact hole for electrically connecting the second drain region DR2 of the second transistor T2 and the first gate electrode / second counter electrode G-CE2 of the first transistor T1 is not required, so that the unit driver circuit DRU including the first transistor T1 and the second transistor T2 can be made smaller, and the unit driver circuit DRU including the first transistor T1 and the second transistor T2 can be made higher-definition in the drive circuit substrate 1.

[0041] In step S4c of forming the interlayer insulating film 7 containing conductive impurities shown in FIG. 9, the interlayer insulating film 7 may be a single layer film made of any of silicon nitride, silicon nitride oxide, and silicon oxide, or a laminated film including two or more of a silicon nitride film, a silicon nitride oxide film, and a silicon oxide film.

[0042] In addition, the second insulating layer 6 formed in the fourth step S4 shown in FIG. 9 may be formed of a silicon oxide film, and in step S4c of forming the interlayer insulating film 7 containing conductive impurities shown in FIG. 9, the interlayer insulating film 7 may be formed of a single layer film made of silicon nitride or a stacked film whose bottom layer is a silicon nitride film.

[0043] 11, in the manufacturing method of the drive circuit substrate 100 of Comparative Example 1 shown in FIGS. 13 and 14, the first semiconductor layer 93 and the second semiconductor layer 93′ shown in FIG. 14 can be formed by performing step S101 of forming the first gate electrode G of the first transistor T1r and the second gate electrode G′ of the second transistor T2r, step S102 of implanting a low concentration of impurities (LDP) using the first gate electrode G and the second gate electrode G′ as a mask, and step S103 of implanting a high concentration of impurities (HDP) using a resist film RM′ as a mask. On the other hand, in the manufacturing method of the drive circuit substrate 1 of the present embodiment, the first semiconductor layer 3 of the first transistor T1 and the second semiconductor layer 5b of the second transistor T2 can be formed by performing step S3 shown in FIG. 8, step S4a of forming an oxide semiconductor layer shown in FIG. 9, step S4b of forming the second insulating layer 6 and the second gate electrode G′ on the second insulating layer 6 shown in FIG. 9, and step S4c of forming an interlayer insulating film 7 containing conductive impurities shown in FIG. Note that the step S4c of forming the interlayer insulating film 7 containing conductive impurities corresponds to the step of forming the interlayer insulating film 15 in the manufacturing method of the drive circuit board 100 of Comparative Example 1. Therefore, in the manufacturing method of the drive circuit board 1 of this embodiment, the first semiconductor layer 3 of the first transistor T1 and the second semiconductor layer 5b of the second transistor T2 can be formed without any increase or decrease in the number of steps compared to the manufacturing method of the drive circuit board 100 of Comparative Example 1.

[0044] [Embodiment 2] FIG. 12 is a cross-sectional view showing a schematic configuration of a drive circuit board 1a of the second embodiment.

[0045] As shown in FIG. 12, the first gate electrode and second opposing electrode G-CE2′ of the first transistor T1′ provided on the drive circuit board 1a differs from the first transistor T1 provided on the drive circuit board 1 of the above-described first embodiment in that, in a planar view, it does not overlap with a part of the first drain region DR1 on the first channel region CHR1 side.

[0046] The first transistor T1' provided in the drive circuit board 1a comprises a first semiconductor layer 3 which is a polycrystalline silicon layer, and a first gate electrode and second opposing electrode G-CE2' which is an oxide semiconductor layer containing conductive impurities, thereby realizing a drive circuit board 1a which efficiently utilizes the polycrystalline silicon layer and the oxide semiconductor layer. [Industrial Applicability]

[0047] The present disclosure can be used for a drive circuit board and a method for manufacturing a drive circuit board. [Explanation of symbols]

[0048] 1, 1a Drive circuit board 2. Barrier layer 3 First semiconductor layer 4 First insulating layer 5 Second semiconductor layer 5a: second semiconductor layer of first transistor 5b Second semiconductor layer of second transistor 6 Second insulating layer 7 Interlayer insulating film 8 Passivation film OX First oxide semiconductor layer, second oxide semiconductor layer SR1 First source region DR1 First drain region CHR1 First channel region SR2 Second source region DR2 Second drain region CHR2 Second channel region CE1 First counter electrode G-CE2, G-CE2': first gate electrode and second counter electrode, second counter electrode S First source electrode D First drain electrode S' Second source electrode G' Second gate electrode T1, T1' First transistor T2 Second transistor Cs holding capacitor DRU unit driver circuit CON1~CON5 contact holes RM resist film

Claims

1. a first semiconductor layer including a first channel region that is a part of a polycrystalline silicon layer, and a first source region and a first drain region that are formed in a region of the polycrystalline silicon layer different from the first channel region and that contain impurities; a first insulating layer provided on the first semiconductor layer; a first gate electrode and second counter electrode, which is provided on the first insulating layer so as to overlap with the first channel region and a part of the first source region, which is a first counter electrode, in a plan view, and which contains a conductive impurity and an oxide semiconductor; a first drain electrode electrically connected to the first drain region; a first source electrode electrically connected to the first source region; a storage capacitor including the first opposing electrode and the second opposing electrode;

2. 2 . The drive circuit board according to claim 1 , wherein the first gate electrode / second counter electrode overlaps a part of the first drain region on the first channel region side in a plan view.

3. the unit driver circuit includes a second transistor, The second transistor is a second semiconductor layer including a second channel region, a second source region, and a second drain region; a second insulating layer provided on the second channel region so as to overlap only with the second channel region in a plan view; a second gate electrode provided on the second insulating layer so as to overlap the second channel region in a plan view; a second source electrode electrically connected to the second source region; the second channel region is formed in the same layer as the first gate electrode and second counter electrode and is made of the same material as the oxide semiconductor; 3. The drive circuit board according to claim 1, wherein the second source region and the second drain region are formed in the same layer as the first gate electrode and second opposing electrode and are made of the same material as the first gate electrode and second opposing electrode.

4. 4. The drive circuit board according to claim 3, wherein the second drain region and the first gate electrode / second counter electrode are connected to each other.

5. an interlayer insulating film containing the conductive impurities, the interlayer insulating film is provided on the second source region, the second drain region, and the first gate electrode / second opposing electrode, and the second source region, the second drain region, and the first gate electrode / second opposing electrode are in contact with each other; 5. The drive circuit board according to claim 4, wherein the interlayer insulating film is not in contact with the second channel region.

6. 6. The drive circuit board according to claim 5, wherein the interlayer insulating film is a single layer film made of any of silicon nitride, silicon nitride oxide, and silicon oxide, or a laminated film including two or more of a silicon nitride film, a silicon nitride oxide film, and a silicon oxide film.

7. the second insulating layer is a silicon oxide film, 6. The drive circuit board according to claim 5, wherein the interlayer insulating film is a single layer film made of silicon nitride or a multilayer film including a silicon nitride film as a bottom layer.

8. a first step of forming a polycrystalline silicon layer; a second step of forming a first insulating layer on the polycrystalline silicon layer; a third step of forming a resist film having a predetermined shape on the first insulating layer, and implanting impurities into a portion of the polycrystalline silicon layer using the resist film as a mask to form a first channel region, a first source region containing the impurity, and a first drain region containing the impurity; a fourth step of forming a first gate electrode and second counter electrode, which includes a first oxide semiconductor layer and a conductive impurity, on the first insulating layer so as to overlap, in a plan view, the first channel region and a part of the first source region, which is a first counter electrode, after removing the resist film; a fifth step of forming a first drain electrode electrically connected to the first drain region and a first source electrode electrically connected to the first source region; A method for manufacturing a drive circuit substrate, comprising forming a unit drive circuit including a first transistor having a storage capacitor including the first opposing electrode and the second opposing electrode.

9. 9. The method for manufacturing a drive circuit substrate according to claim 8, wherein in the fourth step, the first gate electrode and second opposing electrode is formed so as to overlap, in plan view, with a part of the first drain region on the side of the first channel region.

10. In the second step, the first insulating layer is formed on other surfaces than the polycrystalline silicon layer, The fourth step is an oxide semiconductor layer forming step of forming the first oxide semiconductor layer included in the first transistor and the second oxide semiconductor layer included in the second transistor as the same layer and made of the same material on the first insulating layer; a second insulating layer forming step of forming a second insulating layer so as to overlap only a portion of the second oxide semiconductor layer included in the second transistor, which is a second channel region, in a plan view; a second gate electrode forming step of forming a second gate electrode on the second insulating layer so as to overlap the second channel region in a plan view; 10. The method for manufacturing a drive circuit substrate according to claim 8, further comprising: forming an interlayer insulating film containing the conductive impurities so as to be in contact with the first oxide semiconductor layer included in the first transistor and the second oxide semiconductor layer included in the second transistor other than the second channel region, and forming a second source region containing the conductive impurities, a second drain region containing the conductive impurities, and the first gate electrode / second opposing electrode containing the conductive impurities.

11. In the fourth step, the second drain region and the first gate electrode / second counter electrode are formed in a connected manner, 11. The method for manufacturing a drive circuit board according to claim 10, wherein in the fifth step, a second source electrode electrically connected to the second source region is formed.

12. 12. The method for manufacturing a drive circuit board according to claim 11, wherein in the interlayer insulating film formation step, a single layer film made of any of silicon nitride, silicon nitride oxide, and silicon oxide, or a laminated film including two or more of a silicon nitride film, a silicon nitride oxide film, and a silicon oxide film, is formed as the interlayer insulating film.

13. In the second insulating layer forming step, a silicon oxide film is formed as the second insulating layer, 12. The method for manufacturing a drive circuit board according to claim 11, wherein in the interlayer insulating film forming step, a single layer film made of silicon nitride or a multilayer film having a silicon nitride film as a bottom layer is formed as the interlayer insulating film.

Images