Driving circuit board and manufacturing method for driving circuit board

Abstract

To provide a driving circuit board that secures high definition and high reliability of a unit driving circuit by efficiently using a polycrystalline silicon layer and an oxide semiconductor layer, and a manufacturing method for the driving circuit board.SOLUTION: A driving circuit board 1 includes a unit driving circuit including: a first semiconductor layer 3 provided on a barrier layer 2 and including a first channel region CHR1, and a first source region SR1 and a first drain region DR1 containing P-type impurities; a first insulating layer 4 provided on the first semiconductor layer; a first gate electrode G-CE1 also serving as a first counter electrode provided on the first insulating layer so as to overlap with the first channel region in a plan view and containing an oxide semiconductor and conductive impurities; a first interlayer insulating film 7 provided on the first gate electrode also serving as the first counter electrode; a second counter electrode CE2 provided on the first interlayer insulating film so as to overlap with the first gate electrode also serving as the first counter electrode in the plan view; and a first transistor T1 including a first drain electrode D, a first source electrode S, and a holding capacitor Cs.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present disclosure relates to a drive circuit board and a method for manufacturing the drive circuit board. [Background technology]

[0002] In recent years, drive circuit boards equipped with a plurality of unit drive circuits each including a transistor have been frequently used in the field of display devices as pixel circuits that display in the display area of ​​the display device, or as drivers that are provided in the non-display area of ​​the display device and drive the pixel circuits. Because these boards can also be applied to a variety of fields other than display devices, such as 3D printers and fingerprint sensors, research and development into these boards is being actively conducted. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] U.S. Patent Publication US2015 / 0055051 [Patent Document 2] U.S. Patent Publication US2015 / 0053935 Summary of the Invention [Problem to be solved by the invention]

[0004] Patent Documents 1 and 2 describe a drive circuit substrate including a plurality of unit drive circuits, each including a drive transistor and a selection transistor, that is used as a pixel circuit for displaying in the display area of ​​a display device. However, one of the drive transistors and the selection transistors included in the unit drive circuits described in Patent Documents 1 and 2 includes only a polycrystalline silicon layer as a semiconductor layer, while the other of the drive transistors and the selection transistor includes only an oxide semiconductor layer as a semiconductor layer. Therefore, the unit drive circuits described in Patent Documents 1 and 2 do not efficiently utilize the polycrystalline silicon layer and the oxide semiconductor layer.

[0005] Furthermore, Patent Documents 1 and 2 do not incorporate any measures to reduce the area required to form the unit driver circuits and to improve their reliability, making it difficult to ensure high definition and high reliability of the unit driver circuits.

[0006] One aspect of the present disclosure aims to provide a drive circuit board and a method for manufacturing a drive circuit board that can efficiently utilize a polycrystalline silicon layer and an oxide semiconductor layer while ensuring high definition and high reliability of unit drive circuits. [Means for solving the problem]

[0007] In order to solve the above problems, the drive circuit board of the present disclosure has: a first semiconductor layer including a first channel region that is a part of a polycrystalline silicon layer, and a first source region and a first drain region that are formed in a region of the polycrystalline silicon layer different from the first channel region and that contain a P-type impurity; a first insulating layer provided on the first semiconductor layer; a first counter electrode / first gate electrode that is provided on the first insulating layer so as to overlap the first channel region in a plan view, the first counter electrode / first gate electrode including an oxide semiconductor and a conductive impurity; a first interlayer insulating film provided on the first counter electrode and first gate electrode; a second counter electrode provided on the first interlayer insulating film so as to overlap the first counter electrode and first gate electrode in a plan view; a first drain electrode electrically connected to the first drain region; a first source electrode electrically connected to the first source region and the second counter electrode; a unit driver circuit including a first transistor having a holding capacitor including the first opposing electrode and the second opposing electrode.

[0008] In order to solve the above-mentioned problems, the manufacturing method of the drive circuit board of the present disclosure includes: a first step of forming a polycrystalline silicon layer; a second step of forming a first insulating layer on the polycrystalline silicon layer; a third step of forming a resist film of a predetermined shape on the first insulating layer, and implanting a P-type impurity into a part of the polycrystalline silicon layer using the resist film as a mask, thereby forming a first channel region, a first source region containing the P-type impurity, and a first drain region containing the P-type impurity; a fourth step of forming a first counter electrode and first gate electrode, the fourth step including: an oxide semiconductor layer forming step of forming a first oxide semiconductor layer on the first insulating layer so as to overlap the first channel region in a plan view after removing the resist film; and a first interlayer insulating film forming step of forming a first interlayer insulating film containing a conductive impurity on the first insulating layer and the first oxide semiconductor layer; a fifth step of forming a second counter electrode on the first interlayer insulating film so as to overlap the first counter electrode and first gate electrode in a plan view; a sixth step of forming a first drain electrode electrically connected to the first drain region and a first source electrode electrically connected to the first source region and the second opposing electrode; A unit driver circuit is formed that includes a first transistor having a storage capacitor that includes the first opposing electrode and the second opposing electrode.

[0009] In order to solve the above-mentioned problems, the manufacturing method of the drive circuit board of the present disclosure includes: a first step of forming a polycrystalline silicon layer; a second step of forming a first insulating layer on the polycrystalline silicon layer; a third step including: an oxide semiconductor layer forming step of forming a first oxide semiconductor layer on the first insulating layer so as to overlap a portion of the polycrystalline silicon layer in a plan view; and a step of forming a resist film on the first oxide semiconductor layer and implanting a P-type impurity into the polycrystalline silicon layer other than the portion using the resist film as a mask, thereby forming a first channel region, a first source region containing the P-type impurity, and a first drain region containing the P-type impurity; a fourth step of forming a first counter electrode and a first gate electrode, the fourth step including a first interlayer insulating film formation step of forming a first interlayer insulating film containing a conductive impurity on the first insulating layer and the first oxide semiconductor layer after removing the resist film; a fifth step of forming a second counter electrode on the first interlayer insulating film so as to overlap the first counter electrode and first gate electrode in a plan view; a sixth step of forming a first drain electrode electrically connected to the first drain region and a first source electrode electrically connected to the first source region and the second opposing electrode; A unit driver circuit is formed that includes a first transistor having a storage capacitor that includes the first opposing electrode and the second opposing electrode. [Effects of the Invention]

[0010] According to one aspect of the present disclosure, it is possible to provide a drive circuit board and a method for manufacturing a drive circuit board that can efficiently utilize a polycrystalline silicon layer and an oxide semiconductor layer while ensuring high definition and high reliability of unit drive circuits. [Brief explanation of the drawings]

[0011] [Figure 1] FIG. 3 is a circuit diagram of a unit driver circuit provided on a driver circuit board according to the first embodiment. [Figure 2] 3 is a cross-sectional view showing a schematic configuration of a first transistor provided on the drive circuit board of the first embodiment. FIG. [Figure 3] FIG. 1 is a plan view of a drive circuit board according to a first embodiment, showing a schematic configuration of the drive circuit board. [Figure 4] 1 is a cross-sectional view showing a schematic configuration of a drive circuit board according to a first embodiment. [Figure 5] 10 is a diagram comparing the on / off characteristics of the first transistor and the second transistor provided in the drive circuit board of the first embodiment with the on / off characteristics of a transistor provided with an amorphous silicon semiconductor layer. FIG. [Figure 6]10 is a diagram showing the IV characteristics of a second channel region in a second semiconductor layer of a second transistor provided in the drive circuit board of the first embodiment. FIG. [Figure 7] FIG. 10 is a diagram showing the IV characteristics of the first opposing electrode and first gate electrode of the first transistor provided in the drive circuit board of embodiment 1, and the IV characteristics of the second source region and the second drain region in the second semiconductor layer of the second transistor. [Figure 8] 10 is a diagram comparing the reliability of the first transistor, which is a P-type transistor provided in the drive circuit board of the first embodiment, with the reliability of an N-type transistor, which is a comparative example. [Figure 9] 3A to 3C are diagrams illustrating some steps in a method for manufacturing a drive circuit board according to the first embodiment. [Figure 10] 5A to 5C are diagrams illustrating other steps in the method for manufacturing the drive circuit board according to the first embodiment. [Figure 11] 5A to 5C are diagrams showing still other steps in the method for manufacturing the drive circuit board according to the first embodiment. [Figure 12] 5A to 5C are diagrams illustrating some remaining steps in the method for manufacturing the drive circuit board according to the first embodiment. [Figure 13] 10A and 10B are diagrams illustrating some steps in a method for manufacturing a drive circuit board according to Comparative Example 1. [Figure 14] 10A to 10C are diagrams illustrating some steps in a method for manufacturing a drive circuit board according to a second embodiment. [Figure 15] 10A to 10C are diagrams showing other steps in the method for manufacturing a drive circuit board according to the second embodiment. [Figure 16] FIG. 10 is a plan view showing a schematic configuration of a drive circuit board of Comparative Example 1. [Figure 17] 1 is a cross-sectional view showing a schematic configuration of a drive circuit board of Comparative Example 1. FIG. DETAILED DESCRIPTION OF THE INVENTION

[0012] The following describes embodiments of the present disclosure with reference to Figures 1 to 17. For the sake of convenience, components having the same functions as those described in specific embodiments will be denoted by the same reference numerals, and their description may be omitted.

[0013] [Embodiment 1] FIG. 1 is a circuit diagram of a unit driver circuit DRU provided in a driver circuit board 1 of Embodiment 1. FIG. 2 is a cross-sectional view showing a schematic configuration of a first transistor T1 provided in the driver circuit board 1 of Embodiment 1. FIG. 3 is a plan view of the driver circuit board 1 of Embodiment 1, showing a schematic configuration of the driver circuit board 1. Note that FIG. 3 does not show a barrier layer 2, a first insulating layer 4, a second insulating layer 6, a first interlayer insulating film 7, a second interlayer insulating film 8, and a passivation film 9. FIG. 4 is a cross-sectional view showing a schematic configuration of the driver circuit board 1 of Embodiment 1 taken along lines X1-X2 and Y1-Y2 shown in FIG. 3, respectively.

[0014] In this embodiment, as shown in FIG. 1, a case where a light-emitting element is provided as a functional unit FEL electrically connected to each unit driver circuit DRU is described as an example. However, this is not limited to this. The functional unit FEL electrically connected to the unit driver circuit DRU may be provided, for example, with a fingerprint sensor unit or an anode electrode for a 3D printer. Furthermore, for example, the unit driver circuit DRU shown in FIG. 1 may be a driver provided in a non-display area of ​​a display device. In this case, the functional unit FEL electrically connected to the unit driver circuit DRU may be a pixel circuit provided in a display area of ​​the display device. Note that in this embodiment, a case where the light-emitting element serving as the functional unit FEL is an OLED (organic light-emitting diode) is described as an example. However, this is not limited to this. The light-emitting element may be, for example, a QLED (quantum dot light-emitting diode) or a microLED.

[0015] In the unit driver circuit DRU and functional section FEL shown in FIG. 1, as shown in FIGS. 1, 2, and 4, the drain electrode D of the first transistor T1, which is a drive transistor, is electrically connected to one electrode of the light-emitting element, which is the functional section FEL, for example, an anode electrode (not shown). Also, as shown in FIGS. 1, 2, and 4, the source electrode S of the first transistor T1, which is a drive transistor, is electrically connected to a second counter electrode CE2 of the storage capacitor Cs. Also, as shown in FIGS. 1, 2, and 4, a first counter electrode / first gate electrode G-CE1 (shown in FIGS. 2 and 4) which is a common electrode is provided as the gate electrode of the first transistor T1 and the first counter electrode of the storage capacitor Cs. Also, as shown in FIG. 3, the first counter electrode / first gate electrode G-CE1 is electrically connected to the second drain region DR2 of the second transistor T2, which is a selection transistor. And, as shown in FIG. 1, the source electrode S of the first transistor T1 is electrically connected to a high-potential power supply voltage line V to which a high-potential power supply voltage is supplied. DD 1 and 4, the source electrode S' of the second transistor T2, which is a selection transistor, is electrically connected to a data signal line V to which a data signal is supplied. DATA The gate electrode G′ of the second transistor T2 is electrically connected to the scanning signal line V SEL1, each unit driver circuit DRU includes a current-driven light-emitting element as a functional unit FEL electrically connected to the unit driver circuit DRU. Therefore, it is preferable that the first transistor T1, which is a drive transistor provided in each of the plurality of unit driver circuits DRU of the drive circuit substrate 1, has high current driving capability. On the other hand, the second transistor T2, which is a selection transistor, supplies a voltage corresponding to a data signal to the first transistor T1 in accordance with the timing of the scan signal and changes the voltage of the first transistor T1. Therefore, it is preferable that the second transistor T2 has transistor characteristics with low leakage current. Therefore, in this embodiment, as shown in FIGS. 2 and 4, the first transistor T1, which is a drive transistor, includes a first semiconductor layer 3 including a first channel region CHR1 that is a polycrystalline silicon layer, and the second transistor T2, which is a selection transistor, includes a second semiconductor layer 5b including a second channel region CHR2 that is an oxide semiconductor layer. Furthermore, in this embodiment, the first transistor T1 is a P-type transistor including a first semiconductor layer 3 including a first channel region CHR1 that is a polycrystalline silicon layer, and a first source region SR1 and a first drain region DR1 in which P-type impurities are contained in the polycrystalline silicon layer, so that characteristic changes (hot carrier degradation) due to electric field concentration at the end of the drain electrode D on the first drain region DR1 side and at the first drain region DR1 are reduced. Therefore, in the first transistor T1, characteristic changes (hot carrier degradation) due to electric field concentration can be suppressed without providing a separate lightly doped drain region LDD (Lightly Doped Drain) between the first channel region CHR1 and the first drain region DR1, so that the first transistor T1 can be miniaturized and a drive circuit substrate 1 can be realized in which the unit drive circuit DRU including the first transistor T1 can be made higher definition.2 and 4, in the first transistor T1, the second counter electrode CE2 of the storage capacitor Cs is arranged to overlap, in plan view, with the first counter electrode / first gate electrode G-CE1, which is arranged to overlap with the first channel region CHR1, and the electrical connection between the second counter electrode CE2 and the first source electrode S is realized using a contact hole for electrically connecting the first source electrode S and the first source region SR1. This allows the first transistor T1 to be further miniaturized, thereby realizing a drive circuit substrate 1 that can further increase the resolution of the unit driver circuit DRU including the first transistor T1. Furthermore, as will be described later, since the reliability of P-type transistors is higher than that of N-type transistors, in this embodiment, by using a P-type transistor as the first transistor T1, a drive circuit substrate 1 that can ensure high reliability of the unit driver circuit can be realized.

[0016] As described above, when a P-type transistor is used as the first transistor T1 included in the unit driver circuit DRU, the input signal input to the first transistor T1 from the outside must also be changed to a signal for a P-type transistor, and the configuration of the IC chip that outputs the input signal input to the first transistor T1 must also be changed. Therefore, in the unit driver circuit DRU provided in the driver circuit board 1 of this embodiment, the input signal from the outside, for example, the data signal line V DATA Data signals and scanning signal lines V SEL The scanning signal from the unit driver circuit DRU is input only to the second transistor T2, which is an N-type transistor including the second semiconductor layer 5b, which includes a second channel region CHR2 that is an oxide semiconductor layer, and a second source region SR2 and a second drain region DR2 that contain conductive impurities. Therefore, the unit driver circuit DRU provided on the driver circuit board 1 does not require changing the configuration of the input signal input to the unit driver circuit DRU from outside and the IC chip that outputs the input signal to the unit driver circuit DRU for use with P-type transistors.

[0017] As shown in FIGS. 2 and 4 , the first transistor T1 included in the unit driver circuit DRU of the driver circuit substrate 1 includes: a first channel region CHR1 that is a part of a polycrystalline silicon layer; a first semiconductor layer 3 that is formed in a region of the polycrystalline silicon layer different from the first channel region CHR1 and that includes a first source region SR1 and a first drain region DR1 containing P-type impurities; a first insulating layer 4 that is provided on the first semiconductor layer 3; and an oxide semiconductor (In—Ga—Zn—O-based semiconductor in this embodiment) that is provided on the first insulating layer 4 so as to overlap with the first channel region CHR1 in plan view. ) and a second semiconductor layer 5a containing conductive impurities, a first interlayer insulating film 7 provided on the first opposing electrode and first gate electrode G-CE1, a second opposing electrode CE2 provided on the first interlayer insulating film 7 so as to overlap with the first opposing electrode and first gate electrode G-CE1 in a plan view, a first drain electrode D electrically connected to the first drain region DR1, a first source electrode S electrically connected to the first source region SR1 and the second opposing electrode CE2, and a storage capacitor Cs including the first opposing electrode G-CE1 and the second opposing electrode CE2. In this embodiment, a case will be described as an example in which the drive circuit board 1 includes a unit driver circuit DRU including a first transistor T1 and a second transistor T2, but the present invention is not limited to this, and the drive circuit board 1 may include any unit driver circuit DRU including the first transistor T1. The first transistor T1 provided in the drive circuit board 1 includes a first semiconductor layer 3 that is a polycrystalline silicon layer and a first counter electrode / first gate electrode G-CE1 that is an oxide semiconductor layer containing conductive impurities, thereby realizing a drive circuit board 1 that efficiently utilizes the polycrystalline silicon layer and the oxide semiconductor layer. Furthermore, the first transistor T1 provided in the drive circuit board 1 is a P-type transistor that includes a first semiconductor layer 3 that includes a first channel region CHR1 that is a polycrystalline silicon layer and a first source region SR1 and a first drain region DR1 in which the polycrystalline silicon layer contains P-type impurities. Therefore, as described above, the drive circuit board 1 can be miniaturized and ensure high reliability. This makes it possible to realize a drive circuit board 1 that can ensure high definition and high reliability of the unit drive circuit DRU.

[0018] 3 and 4, the unit driver circuit DRU included in the driver circuit substrate 1 includes a first transistor T1, which is a P-type transistor, and a second transistor T2, which is an N-type transistor. As shown in Fig. 4, the second transistor T2 includes a second semiconductor layer 5b including a second channel region CHR2, a second source region SR2, and a second drain region DR2; a second insulating layer 6 provided on the second channel region CHR2 so as to overlap only with the second channel region CHR2 in a planar view; a second gate electrode G' provided on the second insulating layer 6 so as to overlap with the second channel region CHR2 in a planar view; and a second source electrode S' electrically connected to the second source region SR2. The second channel region CHR2 is formed in the same layer as the first counter electrode / first gate electrode G-CE1 and is made of the same material as the oxide semiconductor (in this embodiment, an In-Ga-Zn-O-based semiconductor) included in the first counter electrode / first gate electrode G-CE1. The second source region SR2 and the second drain region DR2 are each formed in the same layer as the first counter electrode and first gate electrode G-CE1 and from the same material as the first counter electrode and first gate electrode G-CE1 (in this embodiment, an In-Ga-Zn-O-based semiconductor and conductive impurities). That is, as shown in FIG. 3, the drive circuit substrate 1 includes a second semiconductor layer 5 including an oxide semiconductor, and as shown in FIG. 4, the second semiconductor layer 5 includes a second semiconductor layer 5a included in the first transistor T1 and a second semiconductor layer 5b included in the second transistor T2. The second semiconductor layer 5a included in the first transistor T1 includes conductive impurities and an oxide semiconductor, and functions as the first counter electrode and first gate electrode G-CE1. The second source region SR2 and the second drain region DR2 in the second semiconductor layer 5b provided in the second transistor T2 each contain a conductive impurity and an oxide semiconductor, similar to the second semiconductor layer 5a provided in the first transistor T1, and the second channel region CHR2 in the second semiconductor layer 5b provided in the second transistor T2 is formed of the same material as the oxide semiconductor (in this embodiment, an In-Ga-Zn-O based semiconductor) included in the first counter electrode / first gate electrode G-CE1.

[0019] As described above, the second transistor T2 included in the unit driver circuit DRU provided on the driver circuit board 1 includes a second channel region CHR2 formed from the same material as the oxide semiconductor (in this embodiment, an In-Ga-Zn-O based semiconductor) included in the first opposing electrode / first gate electrode G-CE1. As a result, as will be described later, an electric field relaxation effect can be achieved, that is, a reduction in the off current Ioff that occurs when the second transistor T2 is off. Since there is no need to provide a separate low concentration region LDD (Lightly Doped Drain), the unit driver circuit DRU including the first transistor T1 and the second transistor T2 can be made smaller, and in the driver circuit board 1, the unit driver circuit DRU including the first transistor T1 and the second transistor T2 can be made higher definition.

[0020] As described above, the first transistor T1, which is a drive transistor included in the unit drive circuit DRU provided on the drive circuit substrate 1, has a first semiconductor layer 3 including a first channel region CHR1 which is a polycrystalline silicon layer, and the second transistor T2, which is a selection transistor, has a second semiconductor layer 5b including a second channel region CHR2 which is an oxide semiconductor layer.Therefore, as will be described later, the first transistor T1 has high current driving capability, and the second transistor T2 has transistor characteristics with low leakage current.

[0021] As described above, the unit driver circuit DRU provided on the driver circuit board 1 includes the second transistor T2, which is an N-type transistor. Therefore, by inputting the external input signal only to the second transistor T2, which is an N-type transistor, there is no need to change the configuration of the input signal input to the unit driver circuit DRU from the outside and the IC chip that outputs the input signal input to the unit driver circuit DRU to use P-type transistors.

[0022] FIG. 5 is a diagram comparing the on / off characteristics of the first transistor T1 and the second transistor T2 provided on the drive circuit board 1 of the first embodiment with the on / off characteristics of a transistor including an amorphous silicon semiconductor layer.

[0023] In this embodiment, the first channel region CHR1, which is a polycrystalline silicon layer included in the first transistor T1, which is a drive transistor, is made of polysilicon formed at a low temperature, and the second channel region CHR2, which is an oxide semiconductor layer included in the second transistor T2, which is a select transistor, is made of an In-Ga-Zn-O based semiconductor, as an example, but this is not limiting. The first channel region CHR1, which is a polycrystalline silicon layer included in the first transistor T1, which is a drive transistor, may be made of polysilicon formed at a high temperature, for example, and the second channel region CHR2, which is an oxide semiconductor layer included in the second transistor T2, which is a select transistor, may be made of an oxide semiconductor other than In-Ga-Zn-O, for example.

[0024] As shown in FIG. 5, the mobility of the first transistor T1, which is a driving transistor and has a first channel region CHR1 that is a polycrystalline silicon layer, when the TFT is on, i.e., the value of the current Idd when the TFT is on, is greater than the mobility of the second transistor T2, which is a selection transistor and has a second channel region CHR2 that is an oxide semiconductor layer, and the comparative example transistor which has a channel region that is an amorphous silicon semiconductor layer, when the TFT is on, i.e., the value of the current Idd when the TFT is on, and the first transistor T1, which is a driving transistor, has high current driving capability.

[0025] 5, the mobility of the second transistor T2, which is a selection transistor and has a second channel region CHR2 that is an oxide semiconductor layer, when the TFT is on, i.e., the value of the current Idd when the TFT is on, is approximately 20 to 50 times higher than that of the comparative transistor having a channel region that is an amorphous silicon semiconductor layer. Also, the mobility of the second transistor T2, which is a selection transistor and has a second channel region CHR2 that is an oxide semiconductor layer, when the TFT is off, i.e., the value of the off current Idd when the TFT is off, is approximately 1 / 100 times lower than that of the comparative transistor having a channel region that is an amorphous silicon semiconductor layer, and is approximately 1 / 1000 times lower than that of the first transistor T1, which is a drive transistor and has a first channel region CHR1 that is a polycrystalline silicon layer. That is, the resistance value in the off state of the second transistor T2, which is a selection transistor having the second channel region CHR2 that is an oxide semiconductor layer, is about 100 times that of the comparative example transistor having a channel region that is an amorphous silicon semiconductor layer, and is about 1000 times that of the first transistor T1, which is a drive transistor having the first channel region CHR1 that is a polycrystalline silicon layer. As described above, the Ion / Ioff of the second transistor T2, which is a selection transistor having the second channel region CHR2 that is an oxide semiconductor layer, i.e., the ratio of the amount of current when the TFT is on to the amount of current when the TFT is off, is 10 9 As a result, the Ion / Ioff of the first transistor T1, which is a driving transistor and includes the first channel region CHR1, which is a polycrystalline silicon layer, is 10 7 and the Ion / Ioff of the comparative transistor having a channel region that is an amorphous silicon semiconductor layer is 10 6 Therefore, the second transistor T2, which is a selection transistor and includes the second channel region CHR2 that is an oxide semiconductor layer, has transistor characteristics with a small leakage current.

[0026] 2 and 4, the first semiconductor layer 3 is provided on a barrier layer 2. The barrier layer 2 is a layer that prevents foreign substances such as water and oxygen from entering the first transistor T1 and the second transistor T2, and can be composed of, for example, a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a laminate film of these, formed by a CVD method. The thickness of the barrier layer 2 is not particularly limited as long as it can prevent foreign substances such as water and oxygen from entering the first transistor T1 and the second transistor T2.

[0027] 3, the second drain region DR2 of the second transistor T2 provided on the drive circuit board 1 and the first counter electrode / first gate electrode G-CE1 of the first transistor T1 are preferably connected. With this configuration, there is no need for a contact hole for electrically connecting the second drain region DR2 of the second transistor T2 and the first counter electrode / first gate electrode G-CE1 of the first transistor T1, so the unit driver circuit DRU including the first transistor T1 and the second transistor T2 can be made smaller, and the unit driver circuit DRU including the first transistor T1 and the second transistor T2 can be made higher-definition on the drive circuit board 1.

[0028] 4 contains, for example, hydrogen as a conductive impurity. When the first interlayer insulating film 7 containing, for example, hydrogen as a conductive impurity is formed, the conductive impurity, for example, hydrogen in the first interlayer insulating film 7 diffuses into the second semiconductor layer 5a of the first transistor T1 including an oxide semiconductor that is in direct contact with the first interlayer insulating film 7, and into the second source region SR2 and the second drain region DR2 of the second semiconductor layer 5b of the second transistor T2, respectively, and thereby the second source region SR2 and the second drain region DR2 of the second semiconductor layer 5b of the second transistor T2 and the first counter electrode / first gate electrode G-CE1 that is the second semiconductor layer 5a of the first transistor T1 are made conductive. 4, in the drive circuit substrate 1, the first interlayer insulating film 7 containing conductive impurities, for example, hydrogen, is provided on each of the second source region SR2, the second drain region DR2, and the first counter electrode / first gate electrode G-CE1, and is in contact with the second source region SR2, the second drain region DR2, and the first counter electrode / first gate electrode G-CE1, while the first interlayer insulating film 7 containing conductive impurities, for example, hydrogen, is not in contact with the second channel region CHR2. As described above, in the drive circuit substrate 1, an interlayer insulating film containing conductive impurities, for example, hydrogen, is used as the first interlayer insulating film 7, and the first interlayer insulating film 7 is provided so as to be in direct contact with the portion of the oxide semiconductor layer that needs to be made conductive, thereby realizing the conductive nature of the oxide semiconductor layer, and therefore eliminating the need for an additional process of adding conductive impurities to the oxide semiconductor layer.

[0029] Fig. 6 is a diagram showing the IV characteristics of the second channel region CHR2 in the second semiconductor layer 5b of the second transistor T2 provided in the drive circuit board 1 of Embodiment 1. Fig. 7 is a diagram showing the IV characteristics of the first counter electrode / first gate electrode G-CE1 of the first transistor T1 provided in the drive circuit board 1 of Embodiment 1, and the IV characteristics of the second source region SR2 and the second drain region DR2 in the second semiconductor layer 5b of the second transistor T2.

[0030] The second insulating layer 6 shown in FIG. 4 is a silicon oxide film, and the first interlayer insulating film 7 shown in FIG. 4 containing conductive impurities, for example, hydrogen, is preferably a single layer film made of silicon nitride or a laminated film including a silicon nitride film as the bottom layer.

[0031] As shown in FIG. 4, in the second semiconductor layer 5b of the second transistor T2, the second channel region CHR2 including an oxide semiconductor is in contact with the second insulating layer 6 which is a silicon oxide film, and the second channel region CHR2 including an oxide semiconductor is oxidized by the second insulating layer 6 which is a silicon oxide film. As a result, the second channel region CHR2 including an oxide semiconductor is in a high-resistance state as shown in FIG. 6, compared with the second source region SR2, the second drain region DR2, and the first opposing electrode / first gate electrode G-CE1 which include the oxide semiconductor made conductive.

[0032] In this embodiment, a stacked film having a silicon nitride film as a lower layer and a silicon oxide film as an upper layer is used as the first interlayer insulating film 7 containing a conductive impurity, for example, hydrogen, as shown in FIG. In this embodiment, by using a stacked film containing a silicon nitride film containing a conductive impurity, for example, hydrogen, as the bottom layer, the silicon nitride film containing the conductive impurity, for example, hydrogen, reduces the oxide semiconductor contained in the second source region SR2, the second drain region DR2, and the first counter electrode / first gate electrode G-CE1, converting them into conductors. The second source region SR2, the second drain region DR2, and the first counter electrode / first gate electrode G-CE1 containing the conductive oxide semiconductor are each in a low-resistance state compared to the second channel region CHR2 containing the oxide semiconductor, as shown in FIG. 7.

[0033] In this embodiment, a laminated film including a silicon nitride film is used as the bottom layer, but a film other than a silicon nitride film may be used as long as it contains a certain amount of hydrogen or more and can supply hydrogen to the oxide semiconductor, i.e., can reduce the oxide semiconductor. Therefore, the first interlayer insulating film 7 containing the conductive impurity, for example, hydrogen, shown in Figure 4 may be a single layer film made of any of silicon nitride, silicon nitride oxide, and silicon oxide, or a laminated film containing two or more of a silicon nitride film, a silicon nitride oxide film, and a silicon oxide film.

[0034] FIG. 8 is a diagram comparing the reliability of the first transistor, which is a P-type transistor provided in the drive circuit board 1 of the first embodiment, with the reliability of an N-type transistor, which is a comparative example.

[0035] As shown in Figure 8, two different predetermined voltages were applied to the first transistor, which is a P-type transistor provided in the drive circuit board of embodiment 1, and an N-type transistor as a comparative example, and two different current stresses were applied to evaluate the degree of degradation of each. As shown in Figure 8, it was confirmed that for both types of current stress, the first transistor, which is a P-type transistor provided in the drive circuit board of embodiment 1, showed a smaller degree of degradation, i.e., a smaller change in the amount of current over the time the stress current was applied (e.g., 10 hours or more), than the N-type transistor as a comparative example. This is thought to be largely due to the difference in carriers (electrons / holes) between P-type transistors and N-type transistors. Furthermore, the amount of heat generated by P-type transistors is also smaller than that generated by N-type transistors.

[0036] As described above, P-type transistors are more advantageous than N-type transistors in terms of miniaturization and reliability, and therefore the first transistor provided in the drive circuit board 1 of this embodiment is a P-type transistor.

[0037] Fig. 16 is a plan view showing a schematic configuration of a drive circuit board 100 of Comparative Example 1. Note that the barrier layer 2, the first insulating layer 4, the interlayer insulating film 15, and the passivation film 9 are not shown in Fig. 16. Fig. 17 is a cross-sectional view showing a schematic configuration of the drive circuit board 100 of Comparative Example 1 taken along the X3-X4 line and the Y3-Y4 line shown in Fig. 16, respectively.

[0038] 16 and 17, the drive circuit substrate 100 of Comparative Example 1 includes a unit drive circuit DRU including a first transistor T1r having a storage capacitor Csr including a first opposing electrode CE1 and a second opposing electrode CE2, and a second transistor T2r having a second gate electrode G' with a double-gate structure. The first transistor T1r includes a first channel region CHR1 that is a part of a polycrystalline silicon layer, and a first semiconductor layer 93 that is formed in a region of the polycrystalline silicon layer different from the first channel region CHR1 and includes a first source region SR1 and a first drain region DR1 that contain impurities. The second transistor T2r also includes second channel regions CHR2 and CHR2' that are part of the polycrystalline silicon layer, and a second semiconductor layer 93' that is formed in a region of the polycrystalline silicon layer different from the second channel regions CHR2 and CHR2' and includes a second source region SR2, a second drain region DR2, and a high-concentration region HDR that contain impurities. The first transistor T1r includes a first drain electrode D electrically connected to the first drain region DR1 via contact hole CON14 and a first source electrode S electrically connected to the first source region SR1 via contact hole CON15, and the second transistor T2r includes a second source electrode S' electrically connected to the second source region SR2 via contact hole CON12 and a second drain electrode D' electrically connected to the second drain region DR2 via contact hole CON13.

[0039] As shown in FIGS. 16 and 17 , in the case of the first transistor T1r included in the drive circuit board 100 of Comparative Example 1, the first gate electrode G and the second opposing electrode CE2 are provided as different layers. Therefore, in the drive circuit board 100 of Comparative Example 1, contact holes CON18 and CON19 for electrically connecting the first gate electrode G and the second opposing electrode CE2 must be provided in the interlayer insulating film 15. As described above, the formation area of ​​the first transistor T1r included in the drive circuit board 100 of Comparative Example 1, which is provided with contact holes CON18 and CON19 that were unnecessary in the drive circuit board 1 of Embodiment 1, is larger than the formation area of ​​the first transistor T1 included in the drive circuit board 1 of Embodiment 1. Therefore, in the drive circuit board 100 of Comparative Example 1, it is more difficult to achieve high-definition unit drive circuits DRU compared to the drive circuit board 1 of Embodiment 1.

[0040] 16 and 17, the first transistor T1r included in the drive circuit substrate 100 of Comparative Example 1 includes a first channel region CHR1, which is a polycrystalline silicon layer, and a first drain region DR1 and a first source region SR1, which are polycrystalline silicon layers containing N-type impurities. The second transistor T2r includes second channel regions CHR2 and CHR2', which are polycrystalline silicon layers, and a second drain region DR2 and a second source region SR2, which are polycrystalline silicon layers containing N-type impurities. Therefore, in the first transistor T1r, a low-concentration region LDR1 must be provided between the first channel region CHR1 and the first drain region DR1 to achieve an electric field relaxation effect. Similarly, in the second transistor T2r, a low-concentration region LDR6 must be provided between the second channel region CHR2' and the second drain region DR2, and between the second channel region CHR2 and the high-concentration region HDR to achieve an electric field relaxation effect. As described above, the formation area of ​​the first transistor T1r and the second transistor T2r provided in the drive circuit board 100 of Comparative Example 1, which is provided with the lightly doped drain (LDD) regions that were unnecessary in the drive circuit board 1 of Embodiment 1, is larger than the formation area of ​​the first transistor T1 and the second transistor T2 provided in the drive circuit board 1 of Embodiment 1. Therefore, it is difficult to achieve high-definition unit drive circuits DRU in the drive circuit board 100 of Comparative Example 1 compared to the drive circuit board 1 of Embodiment 1. Note that the first transistor T1r provided in the drive circuit board 100 of Comparative Example 1 has a lightly doped drain region LDR1 on the drain side and a lightly doped source region LDR2 on the source side. Furthermore, the second transistor T2r provided in the drive circuit board 100 of Comparative Example 1 has lightly doped drain regions LDR4 and LDR6 on the drain side and lightly doped source regions LDR3 and LDR5 on the source side.

[0041] Fig. 9 is a diagram showing some steps in the method for manufacturing the drive circuit board 1 of embodiment 1. Fig. 10 is a diagram showing other steps in the method for manufacturing the drive circuit board 1 of embodiment 1. Fig. 11 is a diagram showing still other steps in the method for manufacturing the drive circuit board 1 of embodiment 1. Fig. 12 is a diagram showing the remaining steps in the method for manufacturing the drive circuit board 1 of embodiment 1. Fig. 13 is a diagram showing some steps in the method for manufacturing the drive circuit board 100 of comparative example 1.

[0042] 9, the manufacturing method of the drive circuit board 1 of the first embodiment includes a first step S1 of forming a polycrystalline silicon layer PS' on the barrier layer 2, a second step S2 of forming a first insulating layer 4 on the polycrystalline silicon layer PS', and a third step S3 of forming a resist film RM of a predetermined shape on the first insulating layer 4 and implanting P-type impurities into parts of the polycrystalline silicon layer PS' using the resist film RM as a mask to form a first semiconductor layer 3 including a first channel region CHR1, a first source region SR1 containing the P-type impurity, and a first drain region DR1 containing the P-type impurity. The first step S1 shown in FIG. 9 includes a step S1a of forming an amorphous silicon layer on the barrier layer 2, followed by annealing (heat treatment) for dehydrogenation at, for example, 450°C, and then processing with an excimer laser at a relatively low temperature to obtain a polysilicon film PS formed at low temperature, and a step S1b of etching the polysilicon film PS using the resist film to form island-shaped polycrystalline silicon layers PS' on the barrier layer 2. In this embodiment, the island-shaped polycrystalline silicon layer PS' is formed to a thickness of, for example, 40 nm, but is not limited to this. In the second step S2 shown in FIG. 9, for example, a silicon oxide film is formed and then annealed (heat treated) to obtain a first insulating layer 4 to a thickness of 85 nm. Note that in the second step S2 shown in FIG. 9, the first insulating layer 4 is formed in addition to the island-shaped polycrystalline silicon layer PS'. In the third step S3 shown in FIG. 9, a high-concentration P-type impurity implantation (HDP) is performed using the resist film RM as a mask to form a first channel region CHR1 that is protected by the resist film RM and does not contain P-type impurities, and a first source region SR1 and a first drain region DR11 that have a higher P-type impurity concentration than the first channel region CHR1 and contain high-concentration P-type impurities. In this embodiment, the first channel region CHR1 is made of, for example, polysilicon, which is a semiconductor that does not contain P-type impurities, and the first source region SR1 and the first drain region DR1 that contain P-type impurities are each formed by injecting P-type impurities into polysilicon, which is a semiconductor that does not contain P-type impurities.In this embodiment, the first source region SR1 and the first drain region DR1 containing P-type impurities are formed by implanting, for example, B (boron ions) as the P-type impurity, but the P-type impurity is not limited to this as long as it is a P-type impurity.

[0043] As shown in FIG. 10 , after removing the resist film RM, the manufacturing method of the drive circuit board 1 of embodiment 1 further includes a fourth step S4 of forming a first opposing electrode and first gate electrode G-CE1, which includes an oxide semiconductor layer forming step S4a of forming a first oxide semiconductor layer OX on the first insulating layer 4 so as to overlap the first channel region CHR1 in a planar view, and a first interlayer insulating film forming step S4c of forming a first interlayer insulating film 7 containing conductive impurities on the first insulating layer 4 and the first oxide semiconductor layer OX. 11, the method for manufacturing the drive circuit substrate 1 of Embodiment 1 includes a fifth step S5 of forming a second opposing electrode CE2 on the first interlayer insulating film 7 so as to overlap the first opposing electrode / first gate electrode G-CE1 in a plan view, and a sixth step S6 of forming a first drain electrode D electrically connected to the first drain region DR1 and a first source electrode S electrically connected to the first source region SR1 and the second opposing electrode CE2, thereby forming a unit drive circuit DRU including a first transistor T1 with a storage capacitor Cs including the first opposing electrode G-CE1 and the second opposing electrode CE2. Note that, as shown in FIG. 12, the method for manufacturing the drive circuit substrate 1 of Embodiment 1 may further include a seventh step S7 of forming a passivation film 9 after the sixth step S6.

[0044] 10, the first oxide semiconductor layer OX included in the first transistor T1 and the second oxide semiconductor layer OX included in the second transistor T2 were formed as the same layer and made of the same material on the first insulating layer 4. Then, between the oxide semiconductor layer forming step S4a and the first interlayer insulating film forming step S4c, a step S4b of forming the second insulating layer 6 and the second gate electrode G' on the second insulating layer 6 was performed. Step S4b of forming the second insulating layer 6 and the second gate electrode G' on the second insulating layer 6 includes: step S4b1 of forming an inorganic film 6P, a portion of which will become the second insulating layer 6, over the entire surfaces of the first insulating layer 4, the first oxide semiconductor layer OX, and the second oxide semiconductor layer OX, and then forming a metal film GP, a portion of which will become the second gate electrode G', over the entire surfaces of the first insulating layer 4, the first oxide semiconductor layer OX, and the second oxide semiconductor layer OX; a second insulating layer forming step of forming the second insulating layer 6 so as to overlap only a portion of the second oxide semiconductor layer OX included in the second transistor T2, which is the second channel region CHR2, in plan view; and a second gate electrode forming step of forming the second gate electrode G' on the second insulating layer 6 so as to overlap the second channel region CHR2 in plan view. Note that in this embodiment, the second insulating layer forming step of forming the second insulating layer 6 and the second gate electrode forming step are performed as one step S4b2 as an example, but the present invention is not limited to this; the second insulating layer forming step of forming the second insulating layer 6 and the second gate electrode forming step may be performed as separate steps. In this embodiment, the first oxide semiconductor layer OX included in the first transistor T1 and the second oxide semiconductor layer OX included in the second transistor T2 are formed using an In-Ga-Zn-O-based semiconductor material to a thickness of, for example, 30 nm, but are not limited to this. In this embodiment, the second insulating layer 6 is formed using a silicon oxide film to a thickness of, for example, 100 nm, but are not limited to this. In this embodiment, the second gate electrode G′ is formed using MoW to a thickness of, for example, 300 nm, but are not limited to this.

[0045] In step S4c of forming the first interlayer insulating film 7 containing conductive impurities shown in FIG. 10 , the first interlayer insulating film 7 containing conductive impurities is formed so as to contact the first counter electrode / first gate electrode G-CE1 and the second channel region CHR2 of the second oxide semiconductor layer OX included in the second transistor T2, thereby forming the first counter electrode / first gate electrode G-CE1 containing conductive impurities and the second source region SR2 and second drain region DR2 containing conductive impurities. In this embodiment, the first interlayer insulating film 7 containing conductive impurities is formed using a silicon nitride film with a thickness of, for example, 160 nm, but is not limited thereto. Also, in this embodiment, the second counter electrode CE2 is formed using MoW with a thickness of, for example, 100 nm, but is not limited thereto.

[0046] 11, the second interlayer insulating film 8 is formed to cover the second opposing electrode CE2 and the first interlayer insulating film 7, but the present invention is not limited to this, and the second interlayer insulating film 8 does not have to be formed. In particular, when a stacked film is used as the first interlayer insulating film 7, the second interlayer insulating film 8 does not have to be provided. In the present embodiment, the second interlayer insulating film 8 is formed using a silicon oxide film with a thickness of 680 nm, for example, but the present invention is not limited to this.

[0047] 11 includes a contact hole forming step S6a of forming a contact hole CON1 exposing the second source region SR2 of the second transistor T2, a contact hole CON2 exposing the first source region SR1 of the first transistor T1, and a contact hole CON3 exposing the first drain region DR1 of the first transistor T1. Note that the contact hole CON1 is a contact hole formed in the first interlayer insulating film 7 and the second interlayer insulating film 8, and the contact holes CON2 and CON3 are contact holes formed in the first insulating layer 4, the first interlayer insulating film 7, and the second interlayer insulating film 8. The sixth step S6 shown in FIG. 11 further includes a step S6b of forming a first drain electrode D electrically connected to the first drain region DR1, a first source electrode S electrically connected to the first source region SR1, and a second source electrode S' electrically connected to the second source region SR2. 11, the electrical connection between the second opposing electrode CE2 and the first source electrode S is realized by using a contact hole for electrically connecting the first source electrode S and the first source region SR1. This makes it possible to further reduce the size of the first transistor T1 and realize a drive circuit substrate 1 capable of further increasing the definition of the unit drive circuit DRU including the first transistor T1. Note that in this embodiment, the first drain electrode D, the first source electrode S, and the second source electrode S' are each formed using a stacked film of, for example, a 30-nm-thick Ti film, a 300-nm-thick Al film, and a 20-nm-thick Ti film, but the present invention is not limited to this.

[0048] In the seventh step S7 of forming the passivation film 9 shown in FIG. 12, the passivation film 9 is formed using, for example, a silicon nitride film with a thickness of 300 nm, but is not limited to this.

[0049] 10 , i.e., the oxide semiconductor layer forming step S4a and the first interlayer insulating film forming step S4c, it is preferable to form the second drain region DR2 and the first counter electrode / first gate electrode G-CE1 so that they are connected to each other. This eliminates the need for a contact hole for electrically connecting the second drain region DR2 of the second transistor T2 to the first counter electrode / first gate electrode G-CE1 of the first transistor T1, so that the unit driver circuit DRU including the first transistor T1 and the second transistor T2 can be made smaller, and the unit driver circuit DRU including the first transistor T1 and the second transistor T2 can be made higher-definition in the drive circuit substrate 1.

[0050] In step S4c of forming the first interlayer insulating film 7 containing conductive impurities as shown in FIG. 10, the first interlayer insulating film 7 may be a single layer film made of any of silicon nitride, silicon nitride oxide, and silicon oxide, or a laminated film including two or more of a silicon nitride film, a silicon nitride oxide film, and a silicon oxide film.

[0051] In addition, the second insulating layer 6 formed in the fourth step S4 shown in Figure 10 may be formed of a silicon oxide film, and in step S4c of forming the first interlayer insulating film 7 containing conductive impurities shown in Figure 10, the first interlayer insulating film 7 may be formed of a single layer film made of silicon nitride or a stacked film whose bottom layer is a silicon nitride film.

[0052] 13, in the manufacturing method of the drive circuit substrate 100 of Comparative Example 1 shown in FIGS. 16 and 17, the first semiconductor layer 93 and the second semiconductor layer 93′ shown in FIG. 17 can be formed by performing step S101 of forming the first gate electrode G of the first transistor T1r and the second gate electrode G′ of the second transistor T2r, step S102 of implanting a low concentration of impurities (LDP) using the first gate electrode G and the second gate electrode G′ as a mask, and step S103 of implanting a high concentration of impurities (HDP) using a resist film RM′ as a mask. On the other hand, in the manufacturing method of the drive circuit substrate 1 of the present embodiment, the first semiconductor layer 3 of the first transistor T1 and the second semiconductor layer 5b of the second transistor T2 can be formed by performing step S3 shown in FIG. 9, step S4a of forming an oxide semiconductor layer shown in FIG. 10, step S4b of forming the second insulating layer 6 and the second gate electrode G′ on the second insulating layer 6 shown in FIG. 10, and step S4c of forming the first interlayer insulating film 7 containing conductive impurities shown in FIG. Note that the step S4c of forming the first interlayer insulating film 7 containing conductive impurities corresponds to the step of forming the interlayer insulating film 15 in the manufacturing method of the drive circuit board 100 of Comparative Example 1. Therefore, in the manufacturing method of the drive circuit board 1 of this embodiment, the first semiconductor layer 3 of the first transistor T1 and the second semiconductor layer 5b of the second transistor T2 can be formed without any increase or decrease in the number of steps compared to the manufacturing method of the drive circuit board 100 of Comparative Example 1.

[0053] In the case of an N-type transistor having a first channel region CHR1 that is a polycrystalline silicon layer, a first drain region DR1 that is a polycrystalline silicon layer containing N-type impurities, and a first source region SR1 that is a polycrystalline silicon layer containing P-type impurities, degradation is greater than that of a P-type transistor having a first channel region CHR1 that is a polycrystalline silicon layer, and a first drain region DR1 that is a polycrystalline silicon layer containing P-type impurities. To suppress this degradation, the channel length must be increased, resulting in a disadvantage of a larger fabrication area. On the other hand, in the case of the P-type transistor described above, degradation is smaller, so the channel length can be shortened, resulting in a smaller fabrication area. Therefore, in this embodiment, a P-type transistor with a storage capacitor Cs is used as the first transistor T1 included in the unit driver circuit DRU of the driver circuit board 1, thereby realizing a driver circuit board 1 that can ensure high definition and high reliability of the unit driver circuit DRU.

[0054] Furthermore, the unit driver circuit DRU of the drive circuit substrate 1 preferably includes a first transistor T1, which is a P-type transistor with a storage capacitor Cs, and a second transistor T2, which is an N-type transistor with an oxide semiconductor layer. This configuration allows a CMOS structure to be realized within the unit driver circuit DRU of the drive circuit substrate 1, combining the first transistor T1, which is a P-type transistor with a polycrystalline silicon layer, and the second transistor T2, which is an N-type transistor with an oxide semiconductor layer. When a plurality of unit driver circuits DRU including such a CMOS structure are provided, for example, in the non-display area of ​​a display device and used as a driver for driving pixel circuits, this configuration makes it easier to generate an inverted signal waveform compared to a single-sided channel circuit composed of only a P-type transistor and an N-type transistor. This reduces the number of transistors required in the entire peripheral circuit of the display device, enabling a narrower frame in the non-display area, i.e., the peripheral area of ​​the display device.

[0055] Furthermore, a demultiplexer (DEMUX) may be realized within the unit driver circuit DRU of the driver circuit substrate 1 by combining a first transistor T1, which is a P-type transistor with a polycrystalline silicon layer, and a second transistor T2, which is an N-type transistor with an oxide semiconductor layer. This configuration allows the drive voltage of the demultiplexer to be lowered, resulting in lower power consumption. For example, if the demultiplexer (DEMUX) is configured solely with the second transistor T2, which is an N-type transistor with an oxide semiconductor layer, it must be driven at VDL / VDH = 0V / 10V when the video voltage range is, for example, 0V to 5V. However, if the demultiplexer (DEMUX) is configured by combining the first transistor T1, which is a P-type transistor with a polycrystalline silicon layer, and the second transistor T2, which is an N-type transistor with an oxide semiconductor layer, it can be driven at VDL / VDH = 0V / 5V when the video voltage range is, for example, 0V to 5V.

[0056] [Embodiment 2] Fig. 14 is a diagram showing some steps in the method for manufacturing a drive circuit board according to Embodiment 2. Fig. 15 is a diagram showing other steps in the method for manufacturing a drive circuit board according to Embodiment 2.

[0057] Note that the first step S1 of forming a polycrystalline silicon layer PS', the second step of forming a first insulating layer 4 on the polycrystalline silicon layer PS', the fifth step S5 of forming a second opposing electrode CE2 on the first interlayer insulating film 4 so as to overlap the first opposing electrode / first gate electrode G-CE1 in a planar view, and the sixth step S6 of forming a first drain electrode S electrically connected to the first drain region DR1 and a first source electrode S electrically connected to the first source region SR1 and the second opposing electrode CE2 are the same as those in the above-mentioned first embodiment, and therefore their description will be omitted here.

[0058] In this embodiment, instead of the third step S3 and the fourth step S4 described above in the first embodiment, a third step S3' shown in FIG. 14 and a fourth step S4' shown in FIG. 15, which will be described later, were performed.

[0059] 14 includes an oxide semiconductor layer forming step of forming a first oxide semiconductor layer OX on the first insulating layer 4 so as to overlap a portion of the polycrystalline silicon layer in a plan view, and a step S3b' of forming a resist film RM on the first oxide semiconductor layer OX and implanting P-type impurities into the portion of the polycrystalline silicon layer other than the portion using the resist film RM as a mask to form a first channel region CHR1, a first source region SR1 containing P-type impurities, and a first drain region DR1 containing P-type impurities. The oxide semiconductor layer forming step also includes a step S3a of forming an oxide semiconductor layer OXP on the entire surface of the first insulating layer 4, and a step of etching the oxide semiconductor layer OXP formed on the entire surface of the first insulating layer 4 using the resist film RM to obtain the first oxide semiconductor layer OX.

[0060] 15 is a step of forming a first counter electrode and first gate electrode G-CE1, which includes a first interlayer insulating film formation step of forming a first interlayer insulating film 7 containing conductive impurities on the first insulating layer 4 and the first oxide semiconductor layer OX after removing the resist film RM. Note that step S4a', which includes steps S4a1' and S4a2' shown in FIG. 15, is the same as step S4b, which includes steps S4b1 and S4b2 shown in FIG. 10, and therefore its description will be omitted here. Also, step S4b' shown in FIG. 15 is the same as step S4c shown in FIG. 10, and therefore its description will be omitted here. [Industrial Applicability]

[0061] The present disclosure can be used for a drive circuit board and a method for manufacturing a drive circuit board. [Explanation of symbols]

[0062] 1 Drive circuit board 2. Barrier layer 3 First semiconductor layer 4 First insulating layer 5 Second semiconductor layer 5a: second semiconductor layer of first transistor 5b Second semiconductor layer of second transistor 6 Second insulating layer 7 First interlayer insulating film 8 Second interlayer insulating film 9 Passivation film OX First oxide semiconductor layer, second oxide semiconductor layer SR1 First source region DR1 First drain region CHR1 First channel region SR2 Second source region DR2 Second drain region CHR2 Second channel region G-CE1: First counter electrode and first gate electrode, first counter electrode CE2 Second counter electrode S First source electrode D First drain electrode S' Second source electrode G' Second gate electrode T1 First transistor T2 Second transistor Cs holding capacitor DRU unit driver circuit CON1~CON5 contact holes RM resist film

Claims

1. a first semiconductor layer including a first channel region that is a part of a polycrystalline silicon layer, and a first source region and a first drain region that are formed in a region of the polycrystalline silicon layer different from the first channel region and that contain a P-type impurity; a first insulating layer provided on the first semiconductor layer; a first counter electrode and first gate electrode that is provided on the first insulating layer so as to overlap the first channel region in a plan view, the first counter electrode and first gate electrode including an oxide semiconductor and a conductive impurity; a first interlayer insulating film provided on the first counter electrode and first gate electrode; a second counter electrode provided on the first interlayer insulating film so as to overlap the first counter electrode and first gate electrode in a plan view; a first drain electrode electrically connected to the first drain region; a first source electrode electrically connected to the first source region and the second counter electrode; a storage capacitor including the first opposing electrode and the second opposing electrode;

2. the unit driver circuit includes a second transistor, The second transistor is a second semiconductor layer including a second channel region, a second source region, and a second drain region; a second insulating layer provided on the second channel region so as to overlap only with the second channel region in a plan view; a second gate electrode provided on the second insulating layer so as to overlap the second channel region in a plan view; a second source electrode electrically connected to the second source region; the second channel region is formed in the same layer as the first counter electrode and first gate electrode and is made of the same material as the oxide semiconductor; 2. The drive circuit board according to claim 1, wherein the second source region and the second drain region are formed in the same layer as the first opposing electrode and first gate electrode and are made of the same material as the first opposing electrode and first gate electrode.

3. the first interlayer insulating film contains the conductive impurity, the first interlayer insulating film is provided on the second source region, the second drain region, and the first opposing electrode / first gate electrode, and the second source region, the second drain region, and the first opposing electrode / first gate electrode are in contact with each other; 3. The drive circuit board according to claim 2, wherein the first interlayer insulating film is not in contact with the second channel region.

4. 4. The drive circuit board according to claim 3, wherein the first interlayer insulating film is a single layer film made of any of silicon nitride, silicon nitride oxide, and silicon oxide, or a laminated film including two or more of a silicon nitride film, a silicon nitride oxide film, and a silicon oxide film.

5. the second insulating layer is a silicon oxide film, 4. The drive circuit board according to claim 3, wherein the first interlayer insulating film is a single layer film made of silicon nitride or a multilayer film including a silicon nitride film as a bottom layer.

6. 6. The drive circuit board according to claim 2, wherein the second drain region and the first counter electrode / first gate electrode are connected to each other.

7. a first step of forming a polycrystalline silicon layer; a second step of forming a first insulating layer on the polycrystalline silicon layer; a third step of forming a resist film of a predetermined shape on the first insulating layer, and implanting a P-type impurity into a part of the polycrystalline silicon layer using the resist film as a mask, thereby forming a first channel region, a first source region containing the P-type impurity, and a first drain region containing the P-type impurity; a fourth step of forming a first opposing electrode and a first gate electrode, the fourth step including: after removing the resist film, forming a first oxide semiconductor layer on the first insulating layer so as to overlap the first channel region in a plan view; and forming a first interlayer insulating film containing a conductive impurity on the first insulating layer and the first oxide semiconductor layer. a fifth step of forming a second counter electrode on the first interlayer insulating film so as to overlap the first counter electrode / first gate electrode in a plan view; a sixth step of forming a first drain electrode electrically connected to the first drain region and a first source electrode electrically connected to the first source region and the second opposing electrode; A method for manufacturing a drive circuit substrate, comprising forming a unit drive circuit including a first transistor having a storage capacitor including the first opposing electrode and the second opposing electrode.

8. a first step of forming a polycrystalline silicon layer; a second step of forming a first insulating layer on the polycrystalline silicon layer; a third step including: an oxide semiconductor layer forming step of forming a first oxide semiconductor layer on the first insulating layer so as to overlap a portion of the polycrystalline silicon layer in a plan view; and a step of forming a resist film on the first oxide semiconductor layer and implanting a P-type impurity into a portion of the polycrystalline silicon layer other than the portion using the resist film as a mask, thereby forming a first channel region, a first source region containing the P-type impurity, and a first drain region containing the P-type impurity; a fourth step of forming a first opposing electrode and a first gate electrode, the fourth step including a first interlayer insulating film forming step of forming a first interlayer insulating film containing a conductive impurity on the first insulating layer and the first oxide semiconductor layer after removing the resist film; a fifth step of forming a second counter electrode on the first interlayer insulating film so as to overlap the first counter electrode / first gate electrode in a plan view; a sixth step of forming a first drain electrode electrically connected to the first drain region and a first source electrode electrically connected to the first source region and the second opposing electrode; A method for manufacturing a drive circuit substrate, comprising forming a unit drive circuit including a first transistor having a storage capacitor including the first opposing electrode and the second opposing electrode.

9. In the second step, the first insulating layer is formed on other surfaces than the polycrystalline silicon layer, In the oxide semiconductor layer forming step, the first oxide semiconductor layer included in the first transistor and the second oxide semiconductor layer included in the second transistor are formed as the same layer and made of the same material on the first insulating layer; a second insulating layer forming step of forming a second insulating layer so as to overlap, in plan view, only a part of the second oxide semiconductor layer included in the second transistor, which is a second channel region; and a second gate electrode forming step of forming a second gate electrode on the second insulating layer so as to overlap, in plan view, the second channel region, 9. The method for manufacturing a drive circuit substrate according to claim 7, wherein in the first interlayer insulating film forming step, the first interlayer insulating film is formed so as to be in contact with a region other than the second channel region of the second oxide semiconductor layer included in the second transistor and with the first opposing electrode and first gate electrode, and the first opposing electrode and first gate electrode containing the conductive impurities and the second source region and second drain region containing the conductive impurities are formed.

10. 10. The method for manufacturing a drive circuit substrate according to claim 9, wherein in the oxide semiconductor layer forming step and the first interlayer insulating film forming step, the second drain region and the first opposing electrode / first gate electrode are formed so as to be connected to each other.

11. 11. The method for manufacturing a drive circuit board according to claim 10, wherein in the first interlayer insulating film formation step, a single layer film made of any of silicon nitride, silicon nitride oxide, and silicon oxide, or a laminated film including two or more of a silicon nitride film, a silicon nitride oxide film, and a silicon oxide film, is formed as the first interlayer insulating film.

12. In the second insulating layer forming step, a silicon oxide film is formed as the second insulating layer, 11. The method for manufacturing a drive circuit board according to claim 10, wherein in the first interlayer insulating film forming step, a single layer film made of silicon nitride or a multilayer film having a silicon nitride film as a bottom layer is formed as the first interlayer insulating film.

Images