Bonded substrate, and method of producing the same

Abstract

To provide a bonded substrate, in which poor solder bonding to a semiconductor element or the like is prevented from occurring.SOLUTION: There is provided, according to one aspect of the present invention, a bonded substrate comprising a first plating layer, a metal circuit layer, a ceramic plate, a metal layer and a second plating layer. The first plating layer includes a gold-containing first layer and a nickel / phosphorus-containing second layer in this order from the opposite surface with respect to the metal circuit layer, the second plating layer includes a gold-containing third layer and a nickel / phosphorus-containing fourth layer in this order from the opposite surface with respect to the metal layer, and the amount of desorbed gas having a mass number of 2 detected from 25 to 200°C is 13.00×10-3 ml / g or less based on the total mass of the metal circuit layer, the first plating layer, the metal layer and the second plating layer, when the bonded substrate is measured according to a thermal desorption gas analysis method by carrying out the heating at a heating rate of 100°C / hour from 25 to 400°C.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to a bonded substrate and a method for manufacturing the same. [Background technology]

[0002] Patent Documents 1 to 3 disclose circuit boards and the like that include a ceramic plate and a metal plate formed on the upper surface of the ceramic plate. In order to improve solder wettability and oxidation resistance, such circuit boards are usually used by providing a plating layer on the metal plate and then soldering it to semiconductor elements and external wiring (for example, Patent Document 4). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2002-232090 [Patent Document 2] International Publication No. 2017 / 056360 [Patent Document 3] International Publication No. 2018 / 154692 [Patent Document 4] Japanese Patent Application Laid-Open No. 2014-167983 Summary of the Invention [Problem to be solved by the invention]

[0004] However, depending on the plating layer, poor solder joints may occur between the circuit board and the semiconductor element, etc., and there is room for improvement.

[0005] An object of the present disclosure is to provide a bonded substrate that suppresses the occurrence of solder joint defects with semiconductor elements and the like, and a method for manufacturing the same. [Means for solving the problem]

[0006] The inventors have conducted research and found that poor solder joints with semiconductor elements and the like are caused by voids in the joint layer, and that the voids are formed by desorbed gases (e.g., hydrogen gas) generated from a plating layer (e.g., a plating layer having a gold plating layer on a nickel-phosphorus plating layer). The inventors have also found that the desorbed gases generated from the plating layer are generated when the plating layer is heated during solder jointing, and that the total amount of desorbed gases generated during solder jointing can be reduced by previously performing a heat treatment on the vicinity of the plating layer. The present disclosure is based on the above findings.

[0007] This disclosure provides the following [1].

[0008] [1] A bonded substrate comprising: a ceramic plate; a metal circuit layer provided on a main surface of the ceramic plate; a first plating layer provided on the metal circuit layer; a metal layer provided on a main surface of the ceramic plate opposite to the metal circuit layer; and a second plating layer provided on the metal layer, the first plating layer includes, from a surface opposite to the metal circuit layer, a first layer containing gold, and a second layer containing nickel and phosphorus provided so as to be in contact with the surface of the first layer facing the metal circuit layer, the second plating layer includes, from a surface opposite to the metal layer, a third layer containing gold, and a fourth layer containing nickel and phosphorus provided so as to be in contact with the surface of the third layer facing the metal layer, When the bonded substrate is measured based on thermal desorption spectroscopy by heating from 25°C to 400°C at a temperature increase rate of 100°C / hour, the amount of desorbed gas detected from 25°C to 200°C, the mass number of which is 2, is 13.00 x 10 based on the total mass of the metal circuit layer, the first plating layer, the metal layer, and the second plating layer. -3 mL / g or less of the bonded substrate.

[0009] In the above-mentioned bonded substrate, the amount of desorbed gas with a mass number of 2 detected by thermal desorption gas analysis at temperatures between 25°C and 200°C is below a predetermined value. Even when such a bonded substrate has the above-mentioned predetermined plating layer, the amount of desorbed gas derived from the plating layer is sufficiently reduced even when heated during solder bonding, and the occurrence of defective solder bonding with semiconductor elements, etc. can be suppressed.

[0010] This disclosure also provides the following [2].

[0011] [2] A bonded substrate comprising: a ceramic plate; a metal circuit layer provided on a main surface of the ceramic plate; a first plating layer provided on the metal circuit layer; a metal layer provided on a main surface of the ceramic plate opposite to the metal circuit layer; and a second plating layer provided on the metal layer, the first plating layer includes, from a surface opposite to the metal circuit layer, a first layer containing gold, and a second layer containing nickel and phosphorus provided so as to be in contact with the surface of the first layer facing the metal circuit layer, the second plating layer includes, from a surface opposite to the metal layer, a third layer containing gold, and a fourth layer containing nickel and phosphorus provided so as to be in contact with the surface of the third layer facing the metal layer, The bonded substrate has a liquid film containing dodecacyclohexasiloxane applied to a surface of the bonded substrate on the side where the metal circuit layer is provided, the liquid film being 0.9 to 1.2 mm thick, the bonded substrate having the liquid film applied thereto being placed on a hot plate with the second plating layer in contact with the hot plate, and the bonded substrate being heated to 255°C for 30 seconds to harden the liquid film and form a silicone gel layer, the total area of ​​voids observed in the region where the first plating layer is provided when viewed from above from the main surface of the bonded substrate on the side where the metal circuit layer is provided is 22.0 area % or less of the area of ​​the region.

[0012] When the bonding substrate has a silicone gel layer formed thereon, the total area of ​​voids trapped in the silicone gel layer is equal to or less than a predetermined value. Even when such a bonding substrate has the above-mentioned predetermined plating layer, the amount of gas desorbed from the plating layer is sufficiently reduced even when heated during solder bonding, thereby preventing poor solder bonding with semiconductor elements, etc.

[0013] The present disclosure also provides the following [3] to [7].

[0014] [3] The bonded substrate according to claim 1 or 2, wherein the first layer has a thickness of 0.040 to 0.050 μm. [4] The bonded substrate according to any one of claims 1 to 3, wherein the first layer is a layer made of gold. [5] The bonded substrate according to any one of claims 1 to 4, wherein the second layer has a thickness of 1 to 8 µm. [6] The bonded substrate according to any one of claims 1 to 5, wherein the second layer is a layer made of nickel and phosphorus. [7] When the bonded substrate is measured by thermal desorption spectroscopy in which the substrate is heated from 25°C to 400°C at a heating rate of 100°C / hour, the amount of desorbed gas detected from 25°C to 300°C, the mass number of which is 2, is 26.00 x 10 based on the total mass of the metal circuit layer, the first plating layer, the metal layer, and the second plating layer. -3 The bonded substrate according to claim 1, wherein the viscosity is mL / g or less.

[0015] One aspect of the present disclosure also provides the following [8].

[0016] [8] A method for manufacturing a ceramic circuit board, the method comprising: heating a ceramic circuit board including a ceramic plate, a metal circuit layer provided on a main surface of the ceramic plate, a first plating layer provided on the metal circuit layer, a metal layer provided on a main surface of the ceramic plate opposite to the metal circuit layer, and a second plating layer provided on the metal layer at 164°C or higher for 5 minutes or longer; the first plating layer includes, from a surface opposite to the metal circuit layer, a first layer containing gold, and a second layer containing nickel and phosphorus provided so as to be in contact with the surface of the first layer facing the metal circuit layer, the second plating layer includes, from a surface opposite to the metal layer, a third layer containing gold, and a fourth layer containing nickel and phosphorus provided so as to be in contact with the surface of the third layer facing the metal layer.

[0017] The above manufacturing method heat-treats a ceramic circuit board having a predetermined plating layer at a predetermined temperature or higher for 5 minutes or longer, thereby making it possible to manufacture a bonded substrate in which the amount of gas released from the plating layer due to heating during soldering is sufficiently reduced, even when the substrate has the predetermined plating layer described above. The bonded substrate thus obtained can suppress the occurrence of solder joint defects with semiconductor elements, etc. [Effects of the Invention]

[0018] According to the present disclosure, it is possible to provide a bonded substrate in which the occurrence of solder joint defects with semiconductor elements or the like is suppressed, and a method for manufacturing the same. [Brief explanation of the drawings]

[0019] [Figure 1] FIG. 1 is a cross-sectional view schematically showing an example of a bonded substrate. [Figure 2] FIG. 2 is a cross-sectional view that schematically shows a cross section of the first plating layer of the bonding substrate. [Figure 3] FIG. 3 is a schematic diagram of a bonded substrate on which a silicone gel layer is formed, when the main surface on which a metal circuit layer is provided is viewed from above. [Figure 4] FIG. 4 is a mass chromatogram showing the results of the thermal desorption gas analysis of Example 1. [Figure 5] FIG. 5 is a mass chromatogram showing the results of the thermal desorption gas analysis of Example 2. [Figure 6] FIG. 6 is a mass chromatogram showing the results of thermal desorption gas analysis of Comparative Example 1. [Figure 7]FIG. 7 is a mass chromatogram showing the results of thermal desorption gas analysis of Comparative Example 2. [Figure 8] FIG. 8 is a mass chromatogram showing the results of thermal desorption gas analysis of Reference Example 1. [Figure 9] FIG. 9 is a photograph of the bonded substrate and ceramic circuit substrate on which the silicone gel layer is formed, viewed from above at the main surface on which the metal circuit layer is provided. DETAILED DESCRIPTION OF THE INVENTION

[0020] An embodiment of the present disclosure will be described below, with reference to the drawings where appropriate. However, the following embodiment is an example for explaining the present disclosure and is not intended to limit the present disclosure to the following content. In the description, the same elements or elements having the same functions will be designated by the same reference numerals, and redundant explanations will be omitted where appropriate. Furthermore, unless otherwise specified, positional relationships such as up, down, left, and right will be based on the positional relationships shown in the drawings. Furthermore, the dimensional ratios of each element are not limited to those shown in the drawings.

[0021] (bonded substrate) One embodiment of the bonded substrate includes a first plating layer, a metal circuit layer, a ceramic plate, a metal layer, and a second plating layer. The components may be arranged as follows: a ceramic plate, a metal circuit layer provided on a main surface of the ceramic plate, a first plating layer provided on the metal circuit layer, a metal layer provided on the main surface of the ceramic plate opposite the main surface on which the metal circuit layer is provided, and a second plating layer provided on the metal layer. The metal circuit layer and the metal layer may each be bonded to the ceramic plate via a brazing material layer.

[0022] The first plating layer includes a first layer containing gold on the surface opposite the metal circuit layer, and a second layer containing nickel and phosphorus provided in contact with the surface of the first layer facing the metal circuit layer, while the second plating layer includes a third layer containing gold on the surface opposite the metal layer, and a fourth layer containing nickel and phosphorus provided in contact with the surface of the third layer facing the metal layer.

[0023] FIG. 1 is a schematic cross-sectional view showing an example of a bonded substrate, showing a cross section of the bonded substrate cut along the lamination direction. The bonded substrate 100 includes a ceramic plate 10, a metal circuit layer 30, and a metal layer 32. The metal circuit layer 30 is bonded to the ceramic plate 10 via a brazing filler metal layer 20. The metal layer 32 is bonded to the ceramic plate 10 via a brazing filler metal layer 22. FIG. 1 shows an example in which two metal circuit layers 30 are provided on the ceramic plate 10 and one metal layer 32 is provided on the surface of the ceramic plate 10 opposite the metal circuit layer 30. However, this is not limited to this example. There may be one or more metal circuit layers 30 and metal layers 32, and the number of each may be one or more, and may be changed as appropriate depending on the intended use of the bonded substrate 100. The metal circuit layer 30 may function as a circuit board. The metal layer 32 may function, for example, as a heat sink.

[0024] The ceramic plate 10 may be, for example, a sintered nitride plate or the like, and from the viewpoint of excellent thermal conductivity and insulating properties, may be an aluminum nitride plate, a silicon nitride plate or the like.

[0025] The thickness of the ceramic plate 10 may be, for example, 0.2 to 1.5 mm, 0.25 to 1.0 mm, 0.5 to 1.0 mm, or 0.5 to 0.8 mm.

[0026] The thickness of the plate or layer in this specification refers to the arithmetic mean value of the thickness measured with a micrometer at any 10 points on the plate or layer to be measured.

[0027] The brazing filler metal layers 20 and 22 are layers obtained by heat-treating a brazing filler metal. The brazing filler metal contains a metal such as aluminum as a main component and an active metal as a secondary component. In addition to aluminum, the metal components of the brazing filler metal may include, for example, silver, copper, and tin. The active metal may include, for example, magnesium and titanium. The brazing filler metal may contain other components, such as an organic solvent and an organic binder.

[0028] The brazing filler metal layers 20 and 22 may have the same or different thicknesses, for example, 3 to 30 μm, 5 to 25 μm, or 10 to 20 μm. When the thicknesses of the brazing filler metal layers 20 and 22 are within the above ranges, the bonding strength between the ceramic plate 10 and the metal circuit layer 30 and the metal layer 32 can be made more sufficient.

[0029] The metal circuit layer 30 may contain, for example, at least one selected from the group consisting of aluminum, an aluminum alloy, copper, and a copper alloy, and from the viewpoint of further improving heat cycle resistance, may contain aluminum or an aluminum alloy, or may be made of aluminum.

[0030] The thickness of the metal circuit layer 30 may be 0.10 to 1.00 mm, 0.15 to 0.50 mm, or 0.20 to 0.40 mm.

[0031] The metal circuit layer 30 has a first plating layer 40. The first plating layer 40 has a portion that contacts the ceramic plate 10, but it may be provided so as not to contact the ceramic plate 10. In FIG. 1 , two metal circuit layers 30 are provided, but when two or more metal circuit layers 30 are provided, it is preferable that the first plating layers 40 provided on the metal circuit layers 30 are provided so as not to contact each other.

[0032] The first plating layer 40 is provided on the metal circuit layer 30 so that the second layer 42 containing nickel and phosphorus and the first layer 41 containing gold are in contact with each other. The first plating layer 40 may be composed of the first layer 41 and the second layer 42, or may have other plating layers. However, the other plating layers are arranged so that the first layer 41 and the second layer 42 are the outermost layers. In other words, the other plating layers are provided between the second layer 42 and the metal circuit layer 30.

[0033] The second plating layer 50 is provided on the metal layer 32 such that a fourth layer 52 containing nickel and phosphorus and a third layer 51 containing gold are in contact with each other. The second plating layer 50 may be composed of the third layer 51 and the fourth layer 52, or may include other plating layers. However, the other plating layers are arranged so that the third layer 51 and the fourth layer 52 are the outermost layers. In other words, the other plating layers are provided between the fourth layer 52 and the metal layer 32.

[0034] The first plating layer 40 and the second plating layer 50 may have the same layer structure or may be different from each other. The constituent materials of the first layer 41 and the second layer 42 included in the first plating layer 40 may be the same as or different from the constituent materials of the third layer 51 and the fourth layer 52 included in the second plating layer 50, respectively. Since this makes it easier to manufacture the bonded substrate, it is preferable that the first plating layer 40 and the second plating layer 50 have the same layer structure, and it is also preferable that the first layer 41 and the third layer 51, and the second layer 42 and the fourth layer 52 are each formed from the same constituent material.

[0035] The first plating layer 40 has, in this order from the surface opposite the metal circuit layer 30, a first layer 41 containing gold and a second layer 42 containing nickel and phosphorus. The second layer 42 is in contact with the surface of the first layer 41 facing the metal circuit layer 30.

[0036] The first plating layer 40 may be provided so as to cover a portion of the surface of the metal circuit layer 30, or may be provided so as to cover the entire surface including the side surfaces of the metal circuit layer 3. The first plating layer 40 may be provided so as to cover a portion of the brazing material layer 20. When the first plating layer 40 is provided so as to cover the entire surface of the metal circuit layer 30, the solder wettability and oxidation resistance of the bonding substrate can be further improved.

[0037] The first layer 41 contains gold, but may contain other components as long as the gist of the present disclosure is not impaired. The first layer 41 may be a layer made of gold. The first layer 41 may be gold plating, immersion gold plating, or electroless immersion gold plating.

[0038] The lower limit of the thickness of the first layer 41 may be, for example, 0.010 μm or more, 0.020 μm or more, 0.030 μm or more, or 0.040 μm or more. When the lower limit of the thickness of the first layer 41 is within the above range, good solder wettability can be obtained. The upper limit of the thickness of the first layer 41 may be, for example, 0.100 μm or less, 0.080 μm or less, 0.060 μm or less, 0.050 μm or less, or 0.040 μm or less. When the upper limit of the thickness of the first layer 41 is within the above range, the time required to form the plating layer can be shortened, resulting in efficient production. The thickness of the first layer 41 may be adjusted within the above range, for example, 0.010 to 0.100 μm, 0.020 to 0.080 μm, 0.030 to 0.060 μm, or 0.040 to 0.050 μm.

[0039] The second layer 42 contains nickel and phosphorus, but may contain other components as long as the gist of the present disclosure is not impaired. The second layer 42 may be made of nickel-phosphorus plating or may be electroless nickel-phosphorus plating.

[0040] The lower limit of the thickness of the second layer 42 may be, for example, 1.0 μm or more, 1.5 μm or more, or 2.0 μm or more. When the lower limit of the thickness of the second layer 42 is within the above range, solder wettability can be further improved. The upper limit of the thickness of the second layer 42 may be, for example, 8.0 μm or less, 7.0 μm or less, or 6.0 μm or less. When the upper limit of the thickness of the second layer 42 is within the above range, the time required to form the plating layer can be shortened, and bonded substrates can be produced efficiently. The thickness of the second layer 42 may be adjusted within the above range, and may be, for example, 1.0 to 8.0 μm, 1.5 to 7.0 μm, or 2.0 to 6.0 μm.

[0041] In the first plating layer 40, for example, the first layer 41 may be an immersion gold plating layer and the second layer 42 may be an electroless nickel-phosphorus layer. When the first layer 41 is an immersion gold plating layer, voids (also called spikes) may be formed near the interface between the first layer 41 and the second layer 42 in a cross section along the stacking direction of the first layer 41 and the second layer 42, extending toward the inside of the second layer 42. The voids in the second layer 42 are formed when nickel ions contained in the second layer 42 are eluted into the solution when the first layer 41 is formed by immersion gold plating using a gold-containing solution.

[0042] FIG. 2 shows an example of a cross section of the first plating layer 40 taken along the lamination direction of the bonding substrate. In this cross section, voids 4 are formed in the second layer 42 from near the interface with the first layer 41 toward the metal circuit layer 30. While the reason for this is unclear, the inventors have confirmed that, in general, when a first plating layer 40 is formed that forms voids 4, the total amount of desorbed gas generated during bonding to a semiconductor element or the like tends to increase. On the other hand, the bonding substrate according to the present disclosure reduces the amount of desorbed gas generated, and therefore, even when the above-described voids 4 are formed, it is possible to sufficiently suppress bonding failures during bonding to a semiconductor element or the like. In other words, the effects of the present disclosure are more pronounced in a bonding substrate formed with a plating layer that forms the above-described voids 4.

[0043] The maximum depth of the voids 4 may be, for example, 5.0 μm or less, 4.0 μm or less, or 3.0 μm or less.

[0044] The metal layer 32 may contain, for example, at least one selected from the group consisting of aluminum, an aluminum alloy, copper, and a copper alloy, and from the viewpoint of further improving heat cycle resistance, may contain aluminum or an aluminum alloy, or may be made of aluminum.

[0045] The thickness of the metal layer 32 may be 0.10 to 1.00 mm, 0.15 to 0.50 mm, or 0.20 to 0.40 mm.

[0046] The second plating layer 50 has, in this order from the surface opposite the metal layer 32, a third layer 51 containing gold and a fourth layer 52 containing nickel and phosphorus. The fourth layer 52 is in contact with the surface of the third layer 51 facing the metal layer 32.

[0047] The second plating layer 50 may have the same configuration as or a different configuration from the first plating layer 40. The descriptions of the first plating layer 40, the first layer 41, and the second layer 42 can be applied to the second plating layer 50, the third layer 51, and the fourth layer 52, respectively.

[0048] In the second plating layer 50, the third layer 51 may be a displacement gold plating layer and the fourth layer 52 may be an electroless nickel-phosphorus layer.

[0049] In one embodiment of the bonded substrate, when measurements are performed based on thermal desorption spectroscopy (TDS analysis) in which the substrate is heated from 25°C to 400°C at a temperature increase rate of 100°C / hour, the amount of desorbed gas having a mass number of 2 detected from 25°C to 200°C is 13.00 x 10 based on the total mass of the metal circuit layer, the first plating layer, the metal layer, and the second plating layer. -3 It may be mL / g or less. A mass number of 2 means that the total number of protons and neutrons that make up the molecule or ion is 2. A molecule or ion with a mass number of 2 is a hydrogen molecule.

[0050] In the above-mentioned bonded substrate, the amount of desorbed gas with a mass number of 2 is below a predetermined value in the above-mentioned measurement, so that the amount of hydrogen gas generated during soldering with a semiconductor element or the like is suppressed, thereby suppressing solder joint defects.

[0051] The amount of desorbed gas having a mass number of 2 detected between 25°C and 200°C is, for example, 11.00 x 10 based on the total mass of the metal circuit layer, the first plating layer, the metal layer, and the second plating layer. -3 mL / g or less, 9.00×10 -3 mL / g or less, 6.00×10 -3 mL / g or less, 5.00×10-3 mL / g or less, 4.50×10 -3 mL / g or less, or 4.00 x 10 -3 The upper limit of the amount of desorbed gas within the above range can further suppress solder joint defects. The amount of desorbed gas having a mass number of 2 detected between 25°C and 200°C may be zero (i.e., no desorbed gas having a mass number of 2 is generated) based on the total mass of the metal circuit layer, the first plating layer, the metal layer, and the second plating layer, but may be, for example, 0.50 x 10 -3 mL / g or more, 1.00×10 -3 mL / g or more, 3.00×10 -3 mL / g or more, or 3.50 x 10 -3 It may be greater than or equal to mL / g.

[0052] The amount of desorbed gas mentioned above is the total amount up to 200°C, but it is preferable that the amount of desorbed gas generated at higher temperatures is also kept low, allowing for a wider range of temperature adjustment for solder bonding with semiconductor elements, etc. When the above-mentioned bonded substrate is measured based on the above-mentioned desorbed gas analysis method (TDS analysis method), it is desirable that the amount of desorbed gas detected between 25°C and 300°C is kept low, with the mass number being 2.

[0053] The amount of desorbed gas having a mass number of 2 detected at temperatures between 25°C and 300°C is, for example, 26.00 x 10 based on the total mass of the metal circuit layer, the first plating layer, the metal layer, and the second plating layer. -3 mL / g or less, 25.00×10 -3 mL / g or less, 23.00×10 -3 mL / g or less, 22.00×10 -3 mL / g or less, or 21.00 x 10 -3The upper limit of the amount of desorbed gas within the above range can further suppress solder joint defects. The amount of desorbed gas having a mass number of 2 detected between 25°C and 300°C may be zero (i.e., no desorbed gas having a mass number of 2 is generated) based on the total mass of the metal circuit layer, the first plating layer, the metal layer, and the second plating layer, but may be, for example, 5.00 x 10 -3 mL / g or more, 10.00×10 -3 mL / g or more, 13.00×10 -3 mL / g or more, 15.00×10 -3 mL / g or more, 18.00×10 -3 mL / g or more, or 20.00 x 10 -3 It may be greater than or equal to mL / g.

[0054] The thermal desorption analysis described in this specification is carried out based on the following procedure: A measurement sample is placed in a vacuum heated gas extraction device, and the device is evacuated for 2 hours. -6 Heating is performed in a resistance heating furnace attached to the measurement device under conditions of 0.1 Pa or less, and mass analysis of the desorbed gas and measurement of the amount of generated gas are performed. Examples of mass analysis devices that can be used include a mass spectrometer manufactured by ANELVA (product name: TE-360S) and a quadrupole mass spectrometer (transducer type, product name: M201QA-TDM) manufactured by Canon ANELVA Corporation. The bonded substrate to be measured is stored in a desiccator for 24 hours or more and removed from the desiccator immediately before measurement. The desorbed gas with a mass number of 2 is detected by detecting components contained in the desorbed gas with an m / z value of 2 using a quadrupole mass spectrometer.

[0055] The amount of desorbed gas with a mass number of 2 is calculated based on the sum of the masses of the metal circuit layer, first plating layer, metal layer, and second plating layer (total mass). The sum of the masses of the metal circuit layer, first plating layer, metal layer, and second plating layer is approximated by subtracting the mass of the ceramic plate from the mass of the bonding substrate.

[0056] In one embodiment of the bonded substrate, a liquid film containing dodecacyclohexasiloxane is applied to the bonded substrate on the side where the metal circuit layer is provided, to a thickness of 0.9 to 1.2 mm. The bonded substrate with the liquid film is placed so that the second plating layer is in contact with a hot plate, and heated on a hot plate heated to 255°C for 30 seconds to harden the liquid film and form a silicone gel layer. When the liquid film is cured and a silicone gel layer is formed, the total area of ​​voids observed in the region where the first plating layer is provided when viewed from above from the main surface on the side where the metal circuit layer is provided of the bonded substrate may be 22.0 area% or less of the area of ​​said region. Examples of dodecacyclohexasiloxane that can be used include DOWSIL SE 1880 (trade name) manufactured by Dow Chemical Japan, Ltd.

[0057] As described above, as the silicone gel layer is formed on the bonded substrate, gas generated from the plating layer is captured in the silicone gel layer and observed as voids in the silicone gel layer. The bonded substrate is manufactured so that the amount of observed voids is below a predetermined value as described above. Since the amount of hydrogen gas generated during soldering with a semiconductor element or the like is suppressed, solder joint defects are suppressed. The silicone gel layer simulates the bonding layer formed during soldering with a semiconductor element or the like. Therefore, fewer voids formed in the silicone gel layer means fewer voids will be formed in the bonding layer during future soldering with a semiconductor element or the like.

[0058] The total void area will be specifically explained using FIG. 3. FIG. 3 is a schematic diagram of a bonding substrate having a silicone gel layer formed thereon, viewed from above on the main surface on which the metal circuit layer is provided. FIG. 3 illustrates an example of a bonding substrate 102 having two metal circuit layers on one main surface of a ceramic plate 10, with a first plating layer 40 covering the entire surface. The bonding substrate 102 also has a metal layer on the surface opposite the metal circuit layers, with a second plating layer covering the entire surface. In FIG. 3, two first layers 41 are provided, resulting in two regions where the first plating layer is provided. For evaluation, the sum of the areas of these two regions is used as the basis, and the ratio of the total area of ​​voids 71 ​​observed within these two regions among the voids trapped in the silicone gel layer 60 to this total is calculated. In some cases, voids 72 are observed outside the region of the first plating layer 40, but these voids 72 do not contribute to the bonding surface with a semiconductor element or the like, and therefore their areas are not considered. When the first plating layer is provided in multiple locations as described above, the area ratio of the voids is calculated as [(total area of ​​voids observed within the first plating layer region) / (total area of ​​the first plating layer region)]×100.

[0059] The total area of ​​voids observed in the region where the first plating layer is provided when viewed from above from the main surface of the bonding substrate on which the metal circuit layer is provided may be, for example, 20.0 area% or less, 18.0 area% or less, 17.5 area% or less, 10.0 area% or less, 8.0 area% or less, 5.0 area% or less, or 3.0 area% or less, based on the area of ​​the region. When the total area of ​​the voids is within the above range, the resulting bonding substrate can further reduce the occurrence of solder joint defects with semiconductor elements, etc. The total area of ​​the voids may be 0 area% (i.e., no voids are observed) based on the area of ​​the region, but may also be, for example, 0.5 area% or more, or 1.0 area% or more.

[0060] The void area ratio in this specification refers to a value determined by the method described below. First, a bonded substrate with a silicone gel layer formed thereon is used as a measurement sample, and an image of the main surface on which the metal circuit layer is provided is obtained as viewed from above. Next, of the entire area of ​​the acquired image, only the area where the silicone gel layer is provided on the metal circuit layer (hereinafter also referred to as the target area) is imported into image analysis software. Areas in the target area that can be determined to be bubbles (hereinafter also referred to as the desorbed gas area) are visually determined, and the desorbed gas area is filled in white. The color image is then grayscaled, and the brightness threshold is confirmed using 255 levels. A binarization process is performed using a threshold value of 192 levels from black to white, thereby creating a binarized image. White areas in the obtained binarized image are considered voids, and the ratio of the total area of ​​the voids is determined using the image analysis software. For example, "GIMP" (product name) manufactured by GNU General Public License, etc. can be used as the image analysis software.

[0061] The silicone gel layer is formed on the metal circuit layer side. This corresponds to bonding to a semiconductor element or the like to the metal circuit layer. The lower limit of the silicone gel layer thickness may be, for example, 0.8 mm or more, 0.9 mm or more, or 1.0 mm or more. If the lower limit of the silicone gel layer thickness is within the above range, it is possible to sufficiently capture desorbed gas generated from the plating layer within the silicone gel layer, enabling more accurate evaluation. The upper limit of the silicone gel layer thickness may be 1.5 mm or less, 1.4 mm or less, 1.3 mm or less, or 1.2 mm or less. If the upper limit of the silicone gel layer thickness is within the above range, it is possible to prevent the liquid film containing dodecacyclohexane from leaking out of the ceramic circuit board when the silicone gel layer is formed. In this specification, the thickness of the silicone gel layer is the thickness between the top surface of the plating layer and the top surface of the liquid film, and the arithmetic average of measurements taken at any three locations is used.

[0062] (Method of manufacturing bonded substrate) One embodiment of a method for manufacturing a bonded substrate includes a step of heating a ceramic circuit substrate, the ceramic circuit substrate including: a ceramic plate; a metal circuit layer provided on a major surface of the ceramic plate; a first plating layer provided on the metal circuit layer; a metal layer provided on a major surface of the ceramic plate opposite the metal circuit layer; and a second plating layer provided on the metal layer, at 164°C or higher for 5 minutes or longer (hereinafter also referred to as a heat treatment step). The first plating layer includes, from the surface opposite the metal circuit layer, a first layer containing gold and a second layer containing nickel and phosphorus provided so as to contact the surface of the first layer facing the metal circuit layer. The second plating layer includes, from the surface opposite the metal layer, a third layer containing gold and a fourth layer containing nickel and phosphorus provided so as to contact the surface of the third layer facing the metal layer.

[0063] Heat treatment of a ceramic circuit board prior to bonding to a semiconductor element or the like is not normally performed due to concerns about product deterioration, reduced reliability, etc. In the above-described manufacturing method, a bonded substrate can be manufactured that suppresses the occurrence of bonding defects in solder bonding to a semiconductor element or the like by intentionally subjecting the ceramic circuit board to a pre-heat treatment, thereby reducing the potential desorbed gas contained in the plating layer.

[0064] The lower limit of the temperature (heating temperature) to which the ceramic circuit substrate is heated in the heat treatment step may be, for example, 165°C or higher, 170°C or higher, 175°C or higher, 180°C or higher, 185°C or higher, 190°C or higher, 195°C or higher, 200°C or higher, 210°C or higher, 220°C or higher, or 230°C or higher. When the lower limit of the heating temperature is within the above range, potentially desorbed gas contained in the plating layer can be more sufficiently removed. The upper limit of the heating temperature in the heat treatment step may be, for example, 350°C or lower, 320°C or lower, 300°C or lower, 280°C or lower, 270°C or lower, 260°C or lower, or 250°C or lower. When the upper limit of the heating temperature is within the above range, oxidation of the plating layer surface can be suppressed, and solder wettability can be ensured.

[0065] The lower limit of the time (heating time) for heating the ceramic circuit substrate in the heat treatment step may be, for example, 6 minutes or more, 10 minutes or more, 12 minutes or more, 15 minutes or more, 18 minutes or more, 20 minutes or more, 23 minutes or more, 25 minutes or more, 30 minutes or more, 35 minutes or more, 40 minutes or more, 45 minutes or more, 50 minutes or more, or 55 minutes or more. The upper limit of the heating time in the heat treatment step may be, for example, 120 minutes or less, 80 minutes or less, or 60 minutes or less. In this specification, the heating time refers to the time (retention time) for which the ceramic circuit substrate is maintained at a predetermined temperature after reaching that temperature.

[0066] The heat treatment step may be performed under reduced pressure to facilitate the removal of desorbed gases. The upper limit of the atmospheric pressure in the heat treatment step is 1×10 -2 MPa or less, 1×10 -3 MPa or less, or 1×10 -4 The lower limit of the pressure of the atmosphere in the heat treatment step may be 1×10 MPa or less. -7 MPa or more, 1×10 -6 MPa or more, or 1×10 -5 The pressure in this specification means gauge pressure.

[0067] The manufacturing method may further include a step other than the heat treatment step.

[0068] Although several embodiments have been described above, the present disclosure is not limited to the above embodiments. Furthermore, the descriptions of the above embodiments can be mutually applied. [Example]

[0069] The present disclosure will be described in more detail with reference to examples and comparative examples, but the present disclosure is not limited to the following examples.

[0070] Example 1 [Ceramic circuit board fabrication] A 0.635 mm thick aluminum nitride plate (thermal conductivity: 180 W / mK) was prepared as the ceramic plate, a 0.3 mm thick aluminum plate (Al purity: 99.99 mass%) was prepared as the metal plate for the metal circuit layer, and a 0.2 mm thick aluminum plate (Al purity: 99.99 mass%) was prepared as the metal plate for the metal layer, and two sheets of alloy foil made of an aluminum alloy (thickness: 0.020 mm, alloy composition: Al-Mg-Cu) were prepared as the brazing material.

[0071] A laminate was prepared by laminating an aluminum plate for the metal circuit, a brazing filler metal, an aluminum nitride plate, another brazing filler metal, and an aluminum plate for the metal layer in this order. The laminate was sandwiched between spacers made of carbon-spray-coated aluminum plates, and subjected to a heating and pressurizing treatment in a hot press apparatus at 615°C in a nitrogen atmosphere for 19 minutes (holding time) while applying a uniform pressure of 6.30 MPa in the direction perpendicular to the main surfaces of the ceramic plates, under conditions such that the maximum temperature of the laminate was 640°C or less, thereby bonding the aluminum nitride plate to the aluminum plate for the metal circuit and the aluminum plate for the metal layer, and obtaining a bonded assembly.

[0072] Next, the bonded body was subjected to electroless plating treatment at 80.0°C using a Ni-P plating solution (phosphorus concentration: 8.5 mass%) to form electroless plated layers (nickel-phosphorus plated layers) having a thickness of 3.8 μm on each of the aluminum plates.

[0073] Furthermore, the bonded body on which the nickel-phosphorus plating layer was formed was subjected to electroless displacement plating using a gold solution at 80.0°C to form an electroless gold plating layer (displacement gold plating layer) having a thickness of 0.045 µm on each of the nickel-phosphorus plating layers, thereby forming a plating layer consisting of the nickel-phosphorus plating layer and the displacement gold plating layer. A ceramic circuit substrate was obtained as the bonded body having the plating layer thus obtained.

[0074] [Fabrication of bonded substrate] The obtained ceramic circuit board was placed in a metal container and heated to 164°C using a constant temperature incubator (Yamato Scientific Co., Ltd., model: DNF910) and maintained at 164°C for 30 minutes (holding time) in the atmosphere, thereby obtaining a bonded substrate.

[0075] Example 2 A ceramic circuit substrate and a bonded substrate were produced in the same manner as in Example 1, except that the holding time during the heat treatment of the ceramic circuit substrate was changed from 30 minutes to 60 minutes.

[0076] (Comparative Examples 1 and 2) The ceramic circuit substrates produced in Examples 1 and 2 (before the heat treatment for obtaining the bonded substrate) were used as ceramic circuit substrates of Comparative Examples 1 and 2, respectively.

[0077] (Reference example 1) A ceramic circuit substrate was produced in the same manner as in Example 1, and a bonded body was produced on which an electroless nickel-phosphorus plating layer was formed under the same conditions as in Example 1.

[0078] <Thermal desorption analysis> Thermal desorption gas analysis was performed on the bonded substrates of Examples 1 and 2, the ceramic circuit substrates of Comparative Examples 1 and 2, and the bonded body of Reference Example 1. Specifically, the bonded substrate, ceramic circuit substrate, or bonded body was first heated in a vacuum to 25 to 400°C at a temperature increase rate of 100°C / hour, and the desorbed gas generated during this time was introduced into a mass spectrometer (quadrupole mass spectrometer "M201QA-TDM" (trade name) manufactured by Canon Anelva Corporation) and mass analyzed. The measurement conditions for the mass spectrometer were as follows:

[0079] [Mass spectrometer measurement conditions] Ionization energy: 70 eV - Applied voltage of secondary ion electron multiplier: -1400 eV Measurement mass range (m / z): 1 to 200 Measurement temperature range: 25 to 400°C Heating rate: 100°C / hour Initial pressure at the start of measurement: 1 x 10 -6 Pa

[0080] [Qualitative analysis of components contained in desorbed gas] The desorbed gas generated was analyzed by thermal desorption spectrometry. Among the components contained in the desorbed gas with m / z values ​​of 1 to 200, those with particularly high mass spectrum intensities are shown in Table 1 below. Among the m / z values ​​listed in Table 1, the chemical species with a mass number of 2 is limited to hydrogen (H2) and the chemical species with a mass number of 18 is limited to water (HO). Therefore, the desorbed gas with an m / z of 2 was determined to be hydrogen gas, and the desorbed gas with an m / z of 18 was determined to be water (water vapor).

[0081] [Table 1]

[0082] For reference, Figures 4 to 8 show mass chromatograms showing the relationship between temperature and mass spectrum intensity of each m / z in TDS analysis. Comparing Figures 6 and 4, and Figures 7 and 5, it can be seen that hydrogen gas generation was observed in the temperature range of 100 to 200°C for the ceramic circuit board of the comparative example, but no hydrogen gas generation was observed in the corresponding temperature range for the bonded substrate of the example. From this, it can be confirmed that the amount of hydrogen gas generated in the bonded substrate of the example is suppressed, even from a qualitative perspective. Furthermore, from these results, it can be said that solder joint defects during bonding to semiconductor elements, etc., can be suppressed compared to the ceramic circuit board of the comparative example, which is equivalent to a conventional product.

[0083] 8, the bonded body of Reference Example 1, which was not subjected to immersion gold plating, generated less hydrogen gas than the ceramic circuit boards of Comparative Examples 1 and 2, which were subjected to immersion gold plating. This confirmed that immersion gold plating, which was thought to improve solder wettability and bondability, actually tends to form voids in the bonding layer when bonding to a semiconductor element or the like, and can degrade solder bondability.

[0084] [Quantitative analysis of components contained in desorbed gas] Next, the amount of each desorbed gas generated was calculated and evaluated according to the following procedure from the integrated intensity and conversion coefficient of the components contained in the desorbed gas in the bonded substrates of Examples 1 and 2, the ceramic circuit substrates of Comparative Examples 1 and 2, and the bonded body of Reference Example 1.

[0085] First, a conversion factor was determined. Using a control sample for hydrogen analysis (Japan Iron and Steel Federation, JSS GS-7a (hydrogen content: 6.0 ppm)) as a standard, the integrated mass spectrum intensity was calculated when the sample was heated from 25°C to 900°C at a heating rate of 100°C / hour. From the calculated integrated mass spectrum intensity of hydrogen gas from the standard, a conversion factor was determined to convert the integrated mass spectrum intensity into the volume of hydrogen gas at 0°C and 1 atmosphere.

[0086] Next, from the results of the TDS analysis, the integrated mass spectrum intensity at 25 to 200°C and 25 to 300°C was calculated for each m / z. The calculated integrated mass spectrum intensity was used to calculate the volume of each desorbed gas generated using the conversion coefficients described above. Subsequently, the total mass of each of the bonded substrates of Examples 1 and 2, the ceramic circuit substrates of Comparative Examples 1 and 2, and the bonded body of Reference Example 1 was measured, and the mass of the ceramic plate was subtracted from the total mass to calculate the total mass (total mass) of the metal circuit layer, first plating layer, metal layer, and second plating layer provided on each substrate. The amount of hydrogen gas generated per total mass of the metal circuit layer, first plating layer, metal layer, and second plating layer provided on each substrate (×10 -3 The calculated values ​​(mL / g) are shown in Table 2 below.

[0087] [Table 2]

[0088] As shown in Table 2, the bonded substrates of Examples 1 and 2 generated less hydrogen gas per total mass of the metal circuit layer, first plating layer, metal layer, and second plating layer than the ceramic circuit boards of Comparative Examples 1 and 2. This result also indicates that solder joint defects during bonding with semiconductor elements and the like can be suppressed compared to the ceramic circuit boards of Comparative Examples, which are equivalent to conventional products.

[0089] Example 3 [Ceramic circuit board fabrication] In the same manner as in Example 1, an aluminum nitride plate, an aluminum plate for metal circuits, and an aluminum plate for metal layer were joined together to obtain a joined body.

[0090] Next, a resist pattern having a predetermined shape was formed on the aluminum plate for the metal circuit layer using an exposure device, and then etching was performed using an aqueous iron chloride solution to remove the portions not covered by the resist pattern. Thereafter, the resist pattern was removed using an alkaline stripping solution.

[0091] After removing the resist pattern, the bonded body was subjected to electroless plating treatment at 80°C using a Ni-P plating solution (phosphorus concentration: 8.5 mass%) to form electroless plated films (nickel-phosphorus plated films) with a thickness of 3.8 μm on each of the aluminum plates.

[0092] Furthermore, the bonded body on which the electroless plating film was formed was subjected to electroless displacement plating using a gold solution at 80°C, and an electroless gold plating film (displacement gold plating film) having a thickness of 0.045 µm was formed on each of the electroless plating films, thereby forming a plating layer consisting of a nickel-phosphorus plating film and a displacement gold plating film. A ceramic circuit substrate was obtained as the bonded body having the plating layer thus obtained.

[0093] [Fabrication of bonded substrate] The ceramic circuit substrate was subjected to a heat treatment in the same manner as in Example 1 to obtain a bonded substrate.

[0094] Example 4 A bonded substrate was produced in the same manner as in Example 3, except that the holding time during the heat treatment of the ceramic circuit substrate was changed from 30 minutes to 28 minutes.

[0095] Example 5 A ceramic circuit substrate and a bonded substrate were produced in the same manner as in Example 3, except that the holding time during the heat treatment of the ceramic circuit substrate was changed from 30 minutes to 18 minutes.

[0096] Example 6 A ceramic circuit substrate and a bonded substrate were produced in the same manner as in Example 3, except that the holding time during the heat treatment of the ceramic circuit substrate was changed from 30 minutes to 15 minutes.

[0097] Example 7 A ceramic circuit substrate and a bonded substrate were produced in the same manner as in Example 3, except that the holding time during the heat treatment of the ceramic circuit substrate was changed from 30 minutes to 7 minutes.

[0098] (Comparative Example 3) A ceramic circuit substrate (before the heat treatment for obtaining a bonded substrate) obtained in the same manner as in Example 3 was used as the ceramic circuit substrate of Comparative Example 3.

[0099] <Evaluation of void area> Three bonded substrates of Examples 3 to 7 and three ceramic circuit substrates of Comparative Example 3 were prepared as measurement samples, and a silicone gel layer was formed on each of them according to the method described below. The area of ​​voids formed in the silicone gel layer was determined and evaluated.

[0100] [Preparation of measurement sample with silicone gel layer] First, 10 cc of dodecacyclohexane (manufactured by Dow Chemical Japan, product name: DOWSIL SE 1880) was dropped onto only the side of each measurement sample on which the metal circuit layer was provided, and a liquid film was formed by spreading it over the entire surface.

[0101] The measurement sample with the liquid film formed thereon was placed on a hot plate preheated to 255°C so that the second plating layer was in contact with the plate and heated for 30 seconds. After heating for 30 seconds, the measurement sample was removed from the hot plate and allowed to cool to room temperature. The heating caused the dodecacyclohexane to harden, forming a silicone gel layer.

[0102] The thickness of the silicone gel layer was measured for the bonded substrates with silicone gel layers and the ceramic circuit substrates with silicone gel layers obtained as described above. The thickness of the silicone gel layer was measured at three locations on the silicone gel layer located on the displacement gold plating layer (first layer), for a total of nine locations on the three substrates. The thickness of the silicone gel layer was 0.92 to 1.16 mm.

[0103] [Measurement of the area of ​​voids in the silicone gel layer] Images of the measurement samples equipped with the silicone gel layer prepared as described above were taken, with the main surface on which the metal circuit layer was provided viewed from above. For reference, images of one of three measurement samples equipped with the silicone gel layer prepared in each Example and Comparative Example are shown in Figure 9. (A) to (E) of Figure 9 correspond to the examples using the bonded substrates of Examples 3 to 7, and (F) of Figure 9 shows the results corresponding to the example using the ceramic circuit substrate of Comparative Example 3.

[0104] The captured images were then imported into image analysis software (manufactured by GNU General Public License, product name: GIMP) and binarized to identify voids within the area where the displacement plating layer (first layer) was visible (i.e., the area where the first plating layer was visible). The total area of ​​the voids was determined, and the ratio based on the area of ​​the first plating layer was calculated. The results are shown in Table 3.

[0105] [Table 3]

[0106] As shown in Table 3, it was confirmed that the void area ratio was 22 area % or less in all of the bonded substrates of Examples 3 to 7, and that the void area ratio was significantly greater than 22 area % in the ceramic circuit substrate of Comparative Example 3. If the void area ratio is similar to that of Example 7, the ratio of voids generated in the bonding layer during bonding to a semiconductor element or the like is small, and a solder bonding sufficient for practical use can be achieved. Examples 3 to 6 can exhibit more desirable performance. [Explanation of symbols]

[0107] 4...gap, 10...ceramic plate, 20, 22...solder layer, 30...metal circuit layer, 32...metal layer, 40...first plating layer, 41...first layer, 42...second layer, 50...second plating layer, 51...third layer, 52...fourth layer, 60...silicone gel layer, 71, 72...void, 100...bonded substrate, 102...bonded substrate.

Claims

1. A bonding substrate comprising: a ceramic plate; a metal circuit layer provided on a main surface of the ceramic plate; a first plating layer provided on the metal circuit layer; a metal layer provided on a main surface of the ceramic plate opposite to the metal circuit layer; and a second plating layer provided on the metal layer, the first plating layer includes, from a surface opposite to the metal circuit layer, a first layer containing gold, and a second layer containing nickel and phosphorus provided so as to be in contact with the surface of the first layer facing the metal circuit layer, the second plating layer includes, from a surface opposite to the metal layer, a third layer containing gold, and a fourth layer containing nickel and phosphorus provided so as to be in contact with the surface of the third layer facing the metal layer, When the bonded substrate is measured based on thermal desorption spectroscopy by heating from 25°C to 400°C at a temperature increase rate of 100°C / hour, the amount of desorbed gas detected from 25°C to 200°C, the mass number of which is 2, is 13.00 x 10 based on the total mass of the metal circuit layer, the first plating layer, the metal layer, and the second plating layer. －３ mL / g or less.

2. A bonding substrate comprising: a ceramic plate; a metal circuit layer provided on a main surface of the ceramic plate; a first plating layer provided on the metal circuit layer; a metal layer provided on a main surface of the ceramic plate opposite to the metal circuit layer; and a second plating layer provided on the metal layer, the first plating layer includes, from a surface opposite to the metal circuit layer, a first layer containing gold, and a second layer containing nickel and phosphorus provided so as to be in contact with the surface of the first layer facing the metal circuit layer, the second plating layer includes, from a surface opposite to the metal layer, a third layer containing gold, and a fourth layer containing nickel and phosphorus provided so as to be in contact with the surface of the third layer facing the metal layer, The bonding substrate has a liquid film containing dodecacyclohexasiloxane formed on the side of the bonding substrate on which the metal circuit layer is formed, the liquid film having a thickness of 0.9 to 1.2 mm, the bonding substrate having the liquid film formed thereon is arranged so that the second plating layer is in contact with a hot plate, and the bonding substrate is heated on the hot plate heated to 255°C for 30 seconds to harden the liquid film and form a silicone gel layer, the total area of ​​voids observed in the region on which the first plating layer is formed when viewed from above from the main surface on the side on which the metal circuit layer is formed of the bonding substrate is 22.0 area % or less of the area of ​​the region.

3. 3. The bonded substrate according to claim 1, wherein the first layer has a thickness of 0.040 to 0.050 μm.

4. 3. The bonded substrate according to claim 1, wherein the first layer is a layer made of gold.

5. 3. The bonded substrate according to claim 1, wherein the second layer has a thickness of 1.0 to 8.0 μm.

6. 3. The bonded substrate according to claim 1, wherein the second layer is a layer made of nickel and phosphorus.

7. When the bonded substrate is measured based on thermal desorption spectroscopy by heating from 25°C to 400°C at a temperature increase rate of 100°C / hour, the amount of desorbed gas having a mass number of 2 detected from 25°C to 300°C is 26.00 x 10 based on the total mass of the metal circuit layer, the first plating layer, the metal layer, and the second plating layer. －３ The bonded substrate according to claim 1 , wherein the viscosity is mL / g or less.

8. a step of heating a ceramic circuit board comprising: a ceramic plate; a metal circuit layer provided on a main surface of the ceramic plate; a first plating layer provided on the metal circuit layer; a metal layer provided on a main surface of the ceramic plate opposite to the metal circuit layer; and a second plating layer provided on the metal layer at 164°C or higher for 5 minutes or longer; the first plating layer includes, from a surface opposite to the metal circuit layer, a first layer containing gold, and a second layer containing nickel and phosphorus provided so as to be in contact with the surface of the first layer facing the metal circuit layer, the second plating layer includes, from a surface opposite to the metal layer, a third layer containing gold, and a fourth layer containing nickel and phosphorus provided so as to be in contact with the surface of the third layer facing the metal layer.

Images