Method of manufacturing field effect transistor

Abstract

To suppress variations of breakdown voltage characteristics in a field effect transistor including a first p-type region and a second p-type region.SOLUTION: A method of manufacturing a field effect transistor includes steps of: forming a plurality of trenches penetrating a body layer on a top face of a semiconductor wafer by etching so as to expose a drift layer on a bottom face of each of the trenches; measuring a depth of a measurement target trench that is at least one of the plurality of trenches; and injecting a p-type impurity to the bottom face of each of the trenches, thereby forming a second p-type region in a lower part of each of the trenches and in a depth range overlapping each of first p-type regions. In the step of forming the second p-type region, an injection depth of the p-type impurity is adjusted in such a manner that the shallower the depth of the measurement target trench becomes, the deeper the injection depth of the p-type impurity becomes.SELECTED DRAWING: Figure 8

Description

[Technical Field]

[0001] The technology disclosed in this specification relates to a method for manufacturing a field effect transistor.

[0002] Patent Document 1 discloses a method for manufacturing a field-effect transistor, in which the dimensions of the gate electrode are measured and additional ion implantation is performed according to the measured dimensions, thereby adjusting the gate threshold value. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2006-108498 Summary of the Invention [Problem to be solved by the invention]

[0004] In a field-effect transistor, providing a first p-type region and a second p-type region below the body layer can improve the breakdown voltage characteristics. The second p-type region is provided in the lower part of a trench, and at least a portion of the first p-type region is provided at a position other than the lower part of the trench. The first p-type region and the second p-type region are provided in depth ranges where they overlap. In a manufacturing method for this type of field-effect transistor, the second p-type region is formed by implanting p-type impurities into the bottom surface of the trench. However, with this manufacturing method, there is a large manufacturing variation in the depth of the trench, making it difficult to accurately form the second p-type region in the depth direction. As a result, there is a large variation in the relative positions of the first p-type region and the second p-type region in the depth direction, which leads to a large variation in the breakdown voltage characteristics of the field-effect transistor. This specification proposes a manufacturing method for a field-effect transistor having a first p-type region and a second p-type region, which can suppress variation in the breakdown voltage characteristics. [Means for solving the problem]

[0005] The present specification discloses a method for manufacturing a field-effect transistor, which includes a trench forming step, a trench depth measuring step, and a second p-type region forming step. In the trench forming step, a semiconductor wafer having an n-type drift layer, a plurality of first p-type regions disposed within the depth range of the drift layer and laterally spaced apart, and a p-type body layer disposed above the drift layer is etched to form a plurality of trenches penetrating the body layer such that the drift layer is exposed at the bottom of each trench. In the trench depth measuring step, the depth of a measurement target trench, which is at least one of the plurality of trenches, is measured. In the second p-type region forming step, a p-type impurity is implanted into the bottom of each trench to form a second p-type region below each trench in a depth range overlapping with each first p-type region. In the second p-type region forming step, the implantation depth of the p-type impurity is adjusted so that the implantation depth of the p-type impurity is deeper as the depth of the measurement target trench is shallower.

[0006] The "lateral direction" mentioned above means a direction parallel to the upper surface of the semiconductor substrate, i.e., a direction perpendicular to the thickness direction of the semiconductor substrate.

[0007] In this manufacturing method, in the step of forming the second p-type region, the implantation depth of the p-type impurity is adjusted so that the shallower the depth of the trench to be measured, the deeper the implantation depth of the p-type impurity. Therefore, even if there is a large variation in the trench depth, the second p-type region can be formed with high precision in the depth direction. Therefore, this manufacturing method can suppress variation in the breakdown voltage characteristics. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a perspective view of a field effect transistor 10. [Figure 2] FIG. 3 is a plan view showing the arrangement of the first p-type region 41 and the second p-type region 42 when viewed from above. [Figure 3] FIG. 1 is a plan view of a semiconductor wafer 12. [Figure 4]FIG. 2 is an explanatory diagram of the manufacturing method of the first embodiment. [Figure 5] FIG. 2 is an explanatory diagram of the manufacturing method of the first embodiment. [Figure 6] FIG. 2 is an explanatory diagram of the manufacturing method of the first embodiment. [Figure 7] FIG. 2 is an explanatory diagram of the manufacturing method of the first embodiment. [Figure 8] FIG. 2 is an explanatory diagram of the manufacturing method of the first embodiment. [Figure 9] FIG. 2 is an explanatory diagram of the manufacturing method of the first embodiment. [Figure 10] FIG. 2 is an explanatory diagram of the manufacturing method of the first embodiment. [Figure 11] FIG. 10 is a perspective view of a field effect transistor according to a modified example. [Figure 12] FIG. 10 is a perspective view of a field effect transistor according to a modified example. [Figure 13] FIG. 10 is a perspective view of a field effect transistor according to a modified example. [Figure 14] FIG. 10 is a perspective view of a field-effect transistor 100 according to a third embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0009] In one example manufacturing method disclosed in the present specification, in the step of forming the second p-type regions, the implantation depth of the p-type impurities is adjusted so that the lower end of each of the second p-type regions is positioned higher than the lower end of each of the first p-type regions.

[0010] This configuration can suppress the electric field at the bottom end of the trench.

[0011] The exemplary manufacturing method disclosed herein may further include, prior to the step of forming the trenches, a step of forming a mask having an opening on the top surface of the semiconductor wafer. The step of forming the trenches may include etching the top surface of the semiconductor wafer through the mask to form the trenches. The step of measuring the depth of the measurement target trench may include a step of measuring the distance from the top surface of the mask to the bottom surface of the measurement target trench in the thickness direction of the semiconductor wafer, a step of measuring the thickness of the mask, and a step of calculating the depth of the measurement target trench by subtracting the thickness of the mask from the distance. The step of forming the second p-type region may include implanting p-type impurities into the bottom surface of each trench through the mask.

[0012] This configuration allows the trench formation step and the second p-type region formation step to be performed using a common mask, and also allows the trench depth to be measured in the presence of the mask.

[0013] In one example of the manufacturing method disclosed herein, the step of measuring the depth of the measurement target trench may measure the depths of a plurality of the measurement target trenches. The step of forming the second p-type region may include implanting the p-type impurity deeper in shallower positions of the measurement target trench than in deeper positions of the measurement target trench.

[0014] This configuration can suppress variations in the position of the second p-type region in the depth direction within the semiconductor wafer.

[0015] In the example manufacturing method disclosed herein, the step of forming the trench may form the trench inside and outside the element region of the semiconductor wafer, and the measurement target trench may be the trench outside the element region.

[0016] According to this configuration, the depth of the trench can be accurately measured using the trench outside the element region.

[0017] An example manufacturing method disclosed in this specification may further include, after the step of forming the second p-type region, a step of forming, in each trench, a gate insulating film covering the inner surface of the trench and a gate electrode insulated from the semiconductor wafer by the gate insulating film.

[0018] An example manufacturing method disclosed in this specification may further include, after the step of forming the second p-type region, a step of forming an electrode in contact with the second p-type region in each of the trenches. [Example]

[0019] FIG. 1 shows a field-effect transistor 10 manufactured by the manufacturing method of Example 1. The field-effect transistor 10 has a semiconductor substrate 12. Hereinafter, the thickness direction of the semiconductor substrate 12 is referred to as the z-direction, a direction parallel to the upper surface 12a of the semiconductor substrate 12 (a direction perpendicular to the z-direction) is referred to as the x-direction, and a direction perpendicular to the x-direction and z-direction is referred to as the y-direction. The semiconductor substrate 12 is made of silicon carbide (i.e., SiC). The semiconductor substrate 12 may also be made of other compound semiconductors such as gallium nitride and gallium oxide. A plurality of trenches 14 are provided in the upper surface 12a of the semiconductor substrate 12. The plurality of trenches 14 extend elongately along the y-direction on the upper surface 12a. The plurality of trenches 14 are arranged at intervals in the x-direction.

[0020] The inner surface (i.e., the side and bottom surfaces) of each trench 14 is covered with a gate insulating film 16. A gate electrode 18 is disposed in each trench 14. Each gate electrode 18 is insulated from the semiconductor substrate 12 by the gate insulating film 16. The upper surface of each gate electrode 18 is covered with an interlayer insulating film 20. A source electrode 22 is provided on the upper part of the semiconductor substrate 12. The source electrode 22 covers each interlayer insulating film 20. The source electrode 22 is insulated from the gate electrode 18 by the interlayer insulating film 20. The source electrode 22 is in contact with the upper surface 12a of the semiconductor substrate 12 at a position where the interlayer insulating film 20 is not present. A drain electrode 24 is disposed on the lower part of the semiconductor substrate 12. The drain electrode 24 is in contact with the entire lower surface 12b of the semiconductor substrate 12.

[0021] The semiconductor substrate 12 has a source layer 30, a plurality of contact layers 32, a body layer 34, a plurality of first p-type regions 41, a plurality of second p-type regions 42, a first drift layer 36, a second drift layer 37, and a drain layer 38.

[0022] The source layer 30 is an n-type layer having a high concentration of n-type impurities. The source layer 30 is disposed in an area including the upper surface 12a of the semiconductor substrate 12. The source layer 30 is in ohmic contact with the source electrode 22. The source layer 30 is in contact with the gate insulating film 16 at the top of the side surface of each trench 14. The source layer 30 faces the gate electrode 18 with the gate insulating film 16 interposed therebetween.

[0023] Each contact layer 32 is a p-type layer having a high concentration of p-type impurities. Each contact layer 32 is disposed in an area including the upper surface 12a of the semiconductor substrate 12. Each contact layer 32 is in ohmic contact with the source electrode 22.

[0024] The body layer 34 is a p-type layer having a lower p-type impurity concentration than the contact layer 32. The body layer 34 is disposed below the source layer 30 and the contact layer 32. The body layer 34 contacts the source layer 30 and the contact layer 32 from below. The body layer 34 contacts the gate insulating film 16 on the side surface of the trench 14 located below the source layer 30. The body layer 34 faces the gate electrode 18 with the gate insulating film 16 interposed therebetween.

[0025] The first drift layer 36 is an n-type layer having a lower n-type impurity concentration than the source layer 30. The first drift layer 36 is disposed below the body layer 34 and contacts the body layer 34 from below. The first drift layer 36 contacts the gate insulating film 16 on the side surface of the trench 14 located below the body layer 34. The first drift layer 36 is distributed across the lower portions of the multiple trenches 14.

[0026] The second drift layer 37 is an n-type layer having an n-type impurity concentration higher than that of the first drift layer 36 and lower than that of the source layer 30. The second drift layer 37 contacts the first drift layer 36 from below.

[0027] The drain layer 38 is an n-type layer having a higher n-type impurity concentration than the second drift layer 37. The drain layer 38 is in contact with the second drift layer 37 from below. The drain layer 38 is disposed in an area including the lower surface 12b of the semiconductor substrate 12. The drain layer 38 is in ohmic contact with the drain electrode 24.

[0028] Each first p-type region 41 is disposed below the body layer 34. Each first p-type region 41 is disposed within the depth range of the first drift layer 36 (i.e., within the range in the z direction in which the first drift layer 36 exists). Each first p-type region 41 contacts the body layer 34 from below. As shown in FIG. 2, each first p-type region 41 extends elongatedly in the x direction. The multiple first p-type regions 41 are disposed at intervals in the y direction.

[0029] As shown in FIG. 1, each second p-type region 42 is disposed at the bottom of the corresponding trench 14. Each second p-type region 42 contacts the gate insulating film 16 at the bottom of the corresponding trench 14. Each second p-type region 42 is disposed within a depth range overlapping with each first p-type region 41 (i.e., within the range in the z direction in which the first p-type region 41 exists). The lower end of each second p-type region 42 is located slightly above the lower end of each first p-type region 41. As shown in FIG. 2, each second p-type region 42 extends elongatedly in the y direction along the corresponding trench 14. The multiple second p-type regions 42 are disposed at intervals in the x direction. That is, the first p-type regions 41 and the second p-type regions 42 are distributed in a lattice pattern.

[0030] The field-effect transistor 10 is used with a higher potential applied to the drain electrode 24 than to the source electrode 22. When a potential equal to or greater than a threshold is applied to the gate electrode 18, a channel is formed in the body layer 34. As a result, electrons flow from the source layer 30 to the drain layer 38 via the channel, the first drift layer 36, and the second drift layer 37. When the potential of the gate electrode 18 is reduced to a value equal to or less than the threshold, the channel disappears and the flow of electrons stops. In other words, the field-effect transistor 10 is turned off. This causes a depletion layer to extend from the body layer 34, the first p-type region 41, and the second p-type region 42 into the first drift layer 36. The extending depletion layer depletes the first drift layer 36 and the second drift layer 37. The depleted drift layers 36 and 37 hold a voltage.

[0031] As described above, the lower end of the first p-type region 41 is located slightly lower than the lower end of the second p-type region 42. This suppresses electric field concentration in the semiconductor substrate 12 when the field-effect transistor 10 is in an off state. This allows the field-effect transistor 10 to achieve high breakdown voltage characteristics. On the other hand, if the position of the lower end of the second p-type region 42 varies in the z-direction due to manufacturing variations, the breakdown voltage characteristics of the field-effect transistor 10 will vary. For example, if the lower end of the second p-type region 42 is located higher than in FIG. 1, the lower end of the first p-type region 41 will protrude significantly lower than the lower end of the second p-type region 42. In this case, the electric field will likely concentrate around the lower end of the first p-type region 41, thereby reducing the breakdown voltage characteristics of the field-effect transistor 10. Furthermore, if the lower end of the second p-type region 42 is located lower than in FIG. 1, the lower end of the second p-type region 42 will protrude lower than the lower end of the first p-type region 41. In this case, the electric field tends to concentrate around the lower end of the second p-type region 42 and around the lower end of each trench 14 (particularly in the gate insulating film 16), reducing the breakdown voltage characteristics of the field-effect transistor 10. In the manufacturing method of the embodiment described below, the second p-type region 42 can be formed with high precision in the z direction, and variations in the breakdown voltage characteristics can be suppressed.

[0032] In the manufacturing method of the embodiment, a field effect transistor 10 is manufactured from a semiconductor wafer 12 (i.e., a semiconductor substrate 12 before dicing) shown in Fig. 3. The semiconductor wafer 12 shown in Fig. 3 has a plurality of element regions 90. In each process described below, a field effect transistor 10 is formed in each element region 90.

[0033] First, as shown in FIG. 4 , a drain layer 38, a second drift layer 37, a first drift layer 36, a body layer 34, a source layer 30, a first p-type region 41, and a contact layer 32 are formed in a semiconductor wafer 12. The stacked structure including the second drift layer 37, the first drift layer 36, the body layer 34, and the source layer 30 may be formed by epitaxial growth or ion implantation. The contact layer 32 is formed above the body layer 34 (i.e., within the depth range of the source layer 30). The contact layers 32 are formed spaced apart in the y direction. Therefore, the source layer 30 and the contact layer 32 are exposed on the upper surface 12a of the semiconductor wafer 12. The first p-type region 41 is formed below the body layer 34 (i.e., within the depth range of the first drift layer 36). The first p-type regions 41 are formed spaced apart in the y direction. The contact layer 32 and the first p-type region 41 may be formed by epitaxial growth or by ion implantation.

[0034] 5, a mask 50 having a plurality of openings 50a is formed on the upper surface 12a of the semiconductor wafer 12. The openings 50a are spaced apart in the x direction and extend longitudinally along the y direction.

[0035] Next, as shown in FIG. 6, the upper surface 12a of the semiconductor wafer 12 is etched using a mask 50 to form a plurality of trenches 14 in the upper surface 12a. Here, each trench 14 is formed so as to penetrate the source layer 30, the contact layer 32, and the body layer 34. Therefore, the first drift layer 36 is exposed at the bottom surface of each trench 14. Note that, as shown in FIG. 1, the bottom surface of each trench 14 is located above the lower end of the first p-type region 41. Therefore, the first p-type region 41 is also exposed at the bottom surface of each trench 14.

[0036] Next, the depth D1 of the trench 14 is measured. Here, the depth D1 (i.e., the distance in the z direction from the upper surface 12a to the bottom surface of the trench 14) is measured for at least one of the multiple trenches 14. The trench 14 for which the depth D1 is to be measured may be referred to as the measurement target trench. In this embodiment, the distance D2 in the z direction from the upper surface of the mask 50 to the bottom surface of the trench 14 and the thickness D3 of the mask 50 are measured, and the depth D1 is calculated by subtracting the thickness D3 from the distance D2. The distance D2 may be measured using a non-contact depth measuring device (e.g., an interferometer, a laser displacement meter, etc.) or a contact depth measuring device. The thickness D3 may be measured using a non-contact film thickness measuring device (e.g., an interferometer, etc.) or a contact film thickness measuring device.

[0037] It should be noted that if the intervals between the trenches 14 are small, it may not be possible to accurately measure the depth D1 of the trenches 14. Furthermore, if a contact-type measuring device is used, measuring the depth D1 of the trenches 14 within the element region 90 may affect the characteristics of the field-effect transistor 10. Therefore, in the step of forming the trenches 14, dummy trenches may be formed outside the element region 90 (for example, within a dicing line or on the outer periphery of the semiconductor wafer 12) at the same time as forming the trenches 14 within the element region 90, and the depth D1 of the dummy trenches may be measured.

[0038] Next, as shown in FIG. 7, a protective film 52 (e.g., a silicon oxide film) is formed to cover the side surfaces of the trenches 14. Next, as shown in FIG. 8, p-type impurities are implanted into the semiconductor wafer 12 from above through a mask 50. The mask 50 prevents the p-type impurities from being implanted into the upper surface 12a. The protective film 52 also prevents the p-type impurities from being implanted into the side surfaces of the trenches 14. Therefore, the p-type impurities are implanted into the bottom surfaces of the trenches 14. As a result, a second p-type region 42 is formed in an area exposed at the bottom surface of the trenches 14. Here, as shown in FIG. 1, the second p-type region 42 is formed in a depth range that overlaps with the first p-type region 41. Here, the second p-type region 42 is formed so that the lower end of the second p-type region 42 is located slightly above the lower end of the first p-type region 41.

[0039] In the p-type impurity implantation step, the implantation energy of the p-type impurities (i.e., the implantation depth of the p-type impurities) is adjusted according to the depth D1 of the trench 14 measured previously. More specifically, the shallower the depth D1 of the trench 14, the deeper the implantation depth of the p-type impurities. Therefore, as shown in FIG. 9, when the depth D1 of the trench 14 is shallow, the thickness of the second p-type region 42 is thick. Also, as shown in FIG. 10, when the depth D1 of the trench 14 is deep, the thickness of the second p-type region 42 is thin. Therefore, even if the depth D1 of the trench 14 varies as shown in FIGS. 8 to 10, the variation in the position of the lower end of the second p-type region 42 (i.e., the distance D4 in the z direction from the upper surface 12a to the lower end of the second p-type region 42) can be suppressed. Note that, because the trench 14 is formed by etching, the variation in the depth D1 of the trench 14 is relatively large. On the other hand, the implantation depth of the p-type impurities in the p-type impurity implantation step can be accurately controlled. Therefore, by measuring the depth D1 of the trench 14 and adjusting the implantation depth of the p-type impurity in accordance with the measured depth D1, it is possible to suppress variations in the position of the lower end of the second p-type region 42. Therefore, it is possible to accurately control the relative positions in the z direction of the lower ends of the first p-type region 41 and the second p-type region 42.

[0040] Next, a gate insulating film 16 is formed to cover the inner surface of the trench 14. Next, a gate electrode 18 is formed in the trench 14. Next, an interlayer insulating film 20 is formed on the gate electrode 18. Next, a source electrode 22 is formed on the upper part of the semiconductor wafer 12. Next, a drain electrode 24 is formed on the lower part of the semiconductor wafer 12. Thereafter, the semiconductor wafer 12 is divided into chips to complete the field effect transistor 10 shown in FIG. 1.

[0041] As described above, this manufacturing method makes it possible to accurately control the relative positions in the z direction between the lower ends of the first p-type region 41 and the second p-type region 42. Therefore, it is possible to suppress variations in the withstand voltage characteristics among field-effect transistors 10 during mass production. [Example]

[0042] In Example 2, processing is performed up to the stage shown in FIG. 6 in the same manner as in Example 1. Next, in Example 2, the depth D1 of the plurality of trenches 14 is measured. In FIG. 3, the hatched area is the central portion 92 of the semiconductor wafer 12, and the area surrounding the central portion 92 is the outer peripheral portion 94. In Example 2, the depth D1 of the trenches 14 in the central portion 92 and the depth D1 of the trenches 14 in the outer peripheral portion 94 are measured. Next, a protective film 52 is formed as shown in FIG. 8, and p-type impurities are implanted into the bottom surfaces of the trenches 14 as shown in FIG. 9 to form second p-type regions 42. In Example 2, in the step of implanting p-type impurities into the bottom surfaces of the trenches 14, the implantation depth of the p-type impurities is made different between the central portion 92 and the outer peripheral portion 94.

[0043] When the depth D1 of the trench 14 in the central portion 92 is deeper than the depth D1 of the trench 14 in the peripheral portion 94, a mask plate is placed on top of the central portion 92, and p-type impurities are implanted with no mask plate present on top of the peripheral portion 94. In the central portion 92, the p-type impurities that have penetrated the mask plate (i.e., p-type impurities with attenuated energy) are implanted into the bottom surface of the trench 14, while in the peripheral portion 94, the p-type impurities are implanted directly into the bottom surface of the trench 14. For this reason, the implantation depth of the p-type impurities is shallower in the central portion 92 than in the peripheral portion 94. As a result, the difference in the positions of the lower ends of the second p-type regions 42 between the central portion 92 and the peripheral portion 94 becomes smaller.

[0044] When the depth D1 of the trench 14 in the outer peripheral portion 94 is deeper than the depth D1 of the trench 14 in the central portion 92, a mask plate is placed on top of the outer peripheral portion 94, and p-type impurities are implanted without the mask plate being present on top of the central portion 92. In the outer peripheral portion 94, the p-type impurities that have penetrated the mask plate (i.e., p-type impurities with attenuated energy) are implanted into the bottom surface of the trench 14, while in the central portion 92, the p-type impurities are implanted directly into the bottom surface of the trench 14. For this reason, the implantation depth of the p-type impurities is shallower in the outer peripheral portion 94 than in the central portion 92. As a result, the difference in the positions of the lower ends of the second p-type regions 42 between the central portion 92 and the outer peripheral portion 94 becomes smaller.

[0045] In Example 2, after the second p-type region 42 is formed, the field-effect transistor 10 is manufactured by performing each process similar to that of Example 1. The manufacturing method of Example 2 can suppress variations in the positions of the lower ends of the second p-type regions 42 among a plurality of element regions 90 present in the surface of the semiconductor wafer 12. Therefore, this manufacturing method can more effectively suppress variations in the withstand voltage characteristics among field-effect transistors 10 during mass production.

[0046] In Example 2, the implantation depth of the p-type impurity was adjusted separately in two regions, the central region 92 and the outer peripheral region 94. However, it is also possible to set more detailed regions within the surface of the semiconductor wafer 12 and adjust the implantation depth of the p-type impurity separately in each region according to the depth of the trench 14.

[0047] Although the first p-type region 41 is in contact with the body layer in FIG. 1, the first p-type region 41 may be separated from the body layer as shown in FIG.

[0048] 1, the second p-type region 42 is in contact with the bottom surface of the trench 14, but the second p-type region 42 may be separated from the bottom surface of the trench 14 as shown in FIG.

[0049] 1 and 2, the first p-type region 41 extends long along the x direction, but the first p-type region 41 may be formed as shown in FIG. 13. In FIG. 13, each first p-type region 41 is disposed between two trenches 14 in the x direction. In FIG. 13, each first p-type region 41 extends long along the y direction. In the configuration of FIG. 13, the first p-type region 41 may be separated from the body layer 34, and the second p-type region 42 may be separated from the body layer 34. [Example]

[0050] 14 shows a field-effect transistor 100 of Example 3 having a double trench structure. In the field-effect transistor 100, trenches 14 (i.e., gate trenches) and control trenches 114 are provided on the upper surface 12a of a semiconductor substrate 12. The trenches 14 and control trenches 114 are alternately arranged in the x direction. On the upper surface 12a, the trenches 14 and control trenches 114 extend along the y direction. A control electrode 118 is provided in each control trench 114. The control electrode 118 contacts the semiconductor substrate 12 within the control trench 114. The control electrode 118 is connected to the source electrode 22 at its upper end.

[0051] The semiconductor substrate 12 has a p-type region 120 disposed below the trench 14 and a p-type region 122 disposed below the control trench 114. The p-type region 120 and the p-type region 122 are disposed in depth ranges where they overlap. The lower end of the p-type region 122 is disposed slightly below the lower end of the p-type region 120. The p-type region 122 is in ohmic contact with the control electrode 118. When the field-effect transistor 100 is turned off, depletion layers extend from the p-type regions 120 and 122 to the drift layers 36 and 37, thereby suppressing electric field concentration.

[0052] In the manufacturing process of the field effect transistor 100, the control trench 114 is formed by etching. Next, the depth of the control trench 114 is measured. Next, p-type impurities are implanted into the bottom surface of the control trench 114 to form the p-type region 122. At this time, By adjusting the implantation depth of the p-type impurity according to the measured depth of the control trench 114, the position of the bottom end of the p-type region 122 can be accurately controlled. This makes it possible to suppress variations in the withstand voltage characteristics of the field-effect transistor 100. Next, a control electrode 118 is formed in the control trench 114 so as to contact the p-type region 122. Thereafter, other necessary regions, electrodes, insulating films, etc. are formed, thereby completing the field-effect transistor 100 of FIG. 14. In this manufacturing method, the p-type region 122 is an example of a second p-type region, and the p-type region 120 is an example of a first p-type region.

[0053] The configurations of the techniques disclosed in this specification are listed below. (Configuration 1) A method for manufacturing a field effect transistor, comprising: a step of forming, on a top surface of a semiconductor wafer having an n-type drift layer, a plurality of first p-type regions disposed within a depth range of the drift layer and laterally spaced apart, and a p-type body layer disposed on top of the drift layer, a plurality of trenches penetrating the body layer by etching such that the drift layer is exposed at the bottom of each trench; measuring the depth of a measurement target trench, which is at least one of the plurality of trenches; forming second p-type regions in a depth range below each of the trenches and overlapping with each of the first p-type regions by implanting p-type impurities into the bottom surface of each of the trenches; and In the step of forming the second p-type region, the implantation depth of the p-type impurity is adjusted so that the implantation depth of the p-type impurity becomes deeper as the depth of the measurement target trench becomes shallower. Manufacturing method. (Configuration 2) The manufacturing method according to configuration 1, wherein in the step of forming the second p-type regions, the implantation depth of the p-type impurity is adjusted so that the lower end of each of the second p-type regions is positioned higher than the lower end of each of the first p-type regions. (Configuration 3) The method further includes a step of forming a mask having an opening on the top surface of the semiconductor wafer before the step of forming the trench, In the step of forming the trench, the trench is formed by etching the top surface of the semiconductor wafer through the mask; The step of measuring the depth of the measurement target trench includes: measuring a distance from an upper surface of the mask to the bottom surface of the measurement target trench in a thickness direction of the semiconductor wafer; measuring the thickness of the mask; calculating the depth of the measurement target trench by subtracting the thickness of the mask from the distance; and In the step of forming the second p-type region, p-type impurities are implanted into the bottom surface of each of the trenches through the mask. The method for producing the method according to configuration 1 or 2. (Configuration 4) In the step of measuring the depth of the measurement target trench, the depths of the measurement target trenches are measured; In the step of forming the second p-type region, the p-type impurity is implanted deeper at a shallower position of the measurement target trench than at a deeper position of the measurement target trench. The method for producing according to any one of aspects 1 to 3. (Configuration 5) In the step of forming the trench, the trench is formed inside and outside the element region of the semiconductor wafer; the measurement target trench is the trench outside the element region; The method for producing according to any one of aspects 1 to 4. (Configuration 6) 6. The manufacturing method according to any one of configurations 1 to 5, further comprising, after the step of forming the second p-type region, a step of forming, in each of the trenches, a gate insulating film covering the inner surface of the trench, and a gate electrode insulated from the semiconductor wafer by the gate insulating film. (Configuration 7) The manufacturing method according to any one of configurations 1 to 5, further comprising, after the step of forming the second p-type region, a step of forming an electrode in contact with the second p-type region in each of the trenches.

[0054] Although the embodiments have been described in detail above, these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and variations of the specific examples exemplified above. The technical elements described in this specification or drawings exhibit technical utility alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. Furthermore, the technology exemplified in this specification or drawings simultaneously achieves multiple objectives, and achieving one of these objectives itself has technical utility. [Explanation of symbols]

[0055] 12: semiconductor wafer, 14: trench, 18: gate electrode, 30: source layer, 32: contact layer, 34: body layer, 36: first drift layer, 41: first p-type region, 42: second p-type region

Claims

1. A method for manufacturing a field effect transistor, comprising: a step of forming, on a top surface of a semiconductor wafer having an n-type drift layer, a plurality of first p-type regions disposed within a depth range of the drift layer and laterally spaced apart, and a p-type body layer disposed on top of the drift layer, a plurality of trenches penetrating the body layer by etching such that the drift layer is exposed at a bottom surface of each trench; measuring the depth of a measurement target trench, which is at least one of the plurality of trenches; forming second p-type regions in a depth range that overlaps with each of the first p-type regions at a lower portion of each of the trenches by implanting p-type impurities into the bottom surface of each of the trenches; and In the step of forming the second p-type region, the implantation depth of the p-type impurity is adjusted so that the implantation depth of the p-type impurity becomes deeper as the depth of the measurement target trench becomes shallower. Manufacturing method.

2. 2. The manufacturing method according to claim 1, wherein in the step of forming the second p-type regions, the implantation depth of the p-type impurity is adjusted so that a lower end of each of the second p-type regions is positioned higher than a lower end of each of the first p-type regions.

3. The method further includes a step of forming a mask having an opening on the top surface of the semiconductor wafer before the step of forming the trench, In the step of forming the trench, the trench is formed by etching the top surface of the semiconductor wafer through the mask; The step of measuring the depth of the measurement target trench includes: measuring a distance from an upper surface of the mask to the bottom surface of the measurement target trench in a thickness direction of the semiconductor wafer; measuring the thickness of the mask; calculating the depth of the measurement target trench by subtracting the thickness of the mask from the distance; and In the step of forming the second p-type region, p-type impurities are implanted into the bottom surface of each of the trenches through the mask. The method according to claim 1 or 2.

4. In the step of measuring the depth of the measurement target trench, the depths of the measurement target trenches are measured; In the step of forming the second p-type region, the p-type impurity is implanted deeper at a shallower position of the measurement target trench than at a deeper position of the measurement target trench. The method according to claim 1 or 2.

5. In the step of forming the trench, the trench is formed inside and outside the element region of the semiconductor wafer; the measurement target trench is the trench outside the element region; The method according to claim 1 or 2.

6. 3. The manufacturing method according to claim 1, further comprising, after the step of forming the second p-type region, a step of forming, in each of the trenches, a gate insulating film covering the inner surface of the trench, and a gate electrode insulated from the semiconductor wafer by the gate insulating film.

7. The manufacturing method according to claim 1 , further comprising the step of forming an electrode in contact with the second p-type region in each of the trenches after the step of forming the second p-type region.

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