Multi-die bridge assembly and method of three-dimensional implementation

Abstract

To provide a multi-die bridge assembly and a method for a three-dimensional implementation.SOLUTION: In an architecture, a bridge member having two or more integrated circuit dies is assembled to form a multi-die (MD) bridge assembly. Means for attaching the bridge member to the die may be a hybrid bonding, a solder bumps, a thermocompression bonding, or a combination thereof. The formed MD bridge assembly is subjected to a performance testing prior to attachment to a substrate. A step of attaching the MD bridge assembly to the substrate may include a step of fitting the bridge member part to a cavity in the substrate; and a step of attaching the bridge member to a cavity floor using another plurality of attachment options.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a multi-die bridge assembly and a method for three-dimensional packaging. [Background technology]

[0002] Efforts are underway to improve bump density, power efficiency, speed, and bandwidth in semiconductor packaging. Summary of the Invention [Problem to be solved by the invention]

[0003] However, available methods and architectures that support 3D packaging present manufacturing challenges and are costly. Therefore, there is a need for improved architectures and methods for three-dimensional (3D) semiconductor packaging. [Means for solving the problem]

[0004] The present invention provides a semiconductor assembly comprising: a bridge member comprising a first insulating material and defined by a first surface and a second surface; a bridge member, the first surface having a plurality of first metal contacts, the plurality of first metal contacts being organized into a first region and a second region; a first die having a first top surface with a second insulating material and a plurality of second metal contacts; a second die having a second top surface with a third insulating material and a plurality of third metal contacts; and the bridge member provides at least one electrical path between a first first metal contact in the first region and a second first metal contact in the second region; the first top surface is on the first region of the first surface, the first insulating material is directly bonded to the second insulating material, and portions of the first metal contacts are directly bonded to respective second metal contacts; A semiconductor assembly is provided in which the second top surface is on the second region of the first surface, the first insulating material is directly bonded to the third insulating material, and other first metal contacts are directly bonded to respective third metal contacts. [Brief explanation of the drawings]

[0005] [Figure 1] FIG. 1 is a simplified cross-sectional view of a multi-die bridge assembly including a bridge member and two integrated circuit dies, according to various embodiments. [Figure 2A] FIG. 2 illustrates the structure of FIG. 1 with a bridge member hybrid bonded to two integrated circuit dies, according to various embodiments. [Figure 2B] FIG. 2 illustrates the structure of FIG. 1 with a bridge component soldered to two integrated circuit dies, in accordance with various embodiments. [Figure 3A] FIG. 2 illustrates the structure of FIG. 1 with another bridge member hybrid bonded to two integrated circuit dies, according to various embodiments. [Figure 3B] FIG. 2 illustrates the structure of FIG. 1 with another bridge member soldered to two integrated circuit dies, according to various embodiments. [Figure 4A] 10A-10C illustrate a mold encapsulation on the bottom / backside of an integrated circuit member in a hybrid bond bridge embodiment, according to various embodiments. [Figure 4B] 10A-10C illustrate a mold encapsulation on the bottom / backside of an integrated circuit member in a solder bond bridge embodiment, according to various embodiments. [Figure 5A] 1 illustrates a multi-die bridge assembly with ball pitch solder pads according to various embodiments. [Figure 5B]1 illustrates a multi-die bridge assembly configured for hybrid bonding within a cavity and having ball pitch solder pads for two integrated circuit dies, according to various embodiments. [Figure 6A] 1 illustrates a multi-die bridge assembly including a glass frame, according to various embodiments. [Figure 6B] 1 illustrates an inverted multi-die bridge assembly, according to various embodiments, with the bridge member on top and the bottom or backside of the two integrated circuit dies prepared for soldering. [Figure 7] 1A-1C illustrate a substrate having cavities for bonding to a multi-die bridge assembly, according to various embodiments. [Figure 8] 8 illustrates the substrate of FIG. 7 with an embodiment of a multi-die bridge assembly soldered within the cavity, according to various embodiments. [Figure 9] 8 illustrates the substrate of FIG. 7 having an embodiment of a hybrid-bonded multi-die bridge assembly within a cavity, according to various embodiments. [Figure 10] FIG. 1 illustrates a cavity-free substrate with a multi-die bridge assembly inverted and solder bonded to the top surface, according to various embodiments. [Figure 11] FIG. 1 illustrates an exemplary method for multi-die bridge assembly, according to various embodiments. [Figure 12] FIG. 1 is a top view of a die and wafer that may be included in a microelectronic assembly according to any embodiment disclosed herein. [Figure 13] 1 is a simplified cross-sectional side view illustrating an implementation of an integrated circuit on a die that may be included in various embodiments, according to any embodiment disclosed herein. [Figure 14] 1 is a cross-sectional side view of a microelectronic assembly including any of the embodiments disclosed herein. [Figure 15] FIG. 1 is a block diagram of an exemplary electrical device including any embodiment disclosed herein. DETAILED DESCRIPTION OF THE INVENTION

[0006] Attention is focused on three-dimensional (3D) semiconductor packaging architectures and methods that offer significant improvements in bump density, power efficiency, speed, and bandwidth. Many proposed solutions rely on die-to-die (D2D) and / or die-to-wafer (D2W) bonding methods and architectures. However, many available D2D and D2W methods and architectures face manufacturing challenges and high costs.

[0007] For example, D2D or D2W assembly may require the integration of multiple different dies with various pitch dimensions and joint types (such as solder joints and hybrid joints). One of the technical challenges of D2D and D2W joining is the complexity and high cost of the required copper-to-copper joining technology.

[0008] Another technical challenge is the implementation and characteristics of bridge members. Bridge members are used to operatively connect separate integrated circuit dies and often incorporate multiple pitch and bonding applications. Passive bridge members only provide electrical or signal routing between dies on one surface. Passive bridge members are easy to manufacture and low cost, but they have difficulty achieving the maximum current (Imax) required for many applications. Active bridge members often have through-silicon vias (TSVs) to route power and ground between surfaces, which improves Imax. However, technical challenges such as drilling, alignment, cavity filling, and soldering remain. Therefore, continuous improvement in 3D semiconductor packaging methods and architectures is desirable.

[0009] The embodiments described herein provide technical solutions to these technical challenges in the form of multi-die bridge assemblies and 3D packaging methods. Some embodiments employ hybrid bonding (HB), also referred to as hybrid bond interconnect (HBI) or direct bond interconnect (DBI). HBI is a packaging technology that generally involves bonding the surfaces of two semiconductor devices together under applied pressure and / or elevated temperatures as an alternative to die stacking, resulting in dielectric-to-dielectric and metal-to-metal bonds. HBI significantly achieves "small" pitches (defined here as pitches less than 10 microns ±10%, and in some cases, pitches less than 1 micron ±10%). However, for various reasons, many substrates remain solder-attached, including solder-based interconnects for electrical connection to IC dies. Therefore, in some embodiments of the multi-die bridge members described below, hybrid bond interconnect (HBI) members are integrated with soldered members. These concepts are described in more detail below.

[0010] An example embodiment will now be described in conjunction with the following drawings, in which like reference numerals represent like elements. Unless otherwise specified, the drawings are not necessarily drawn to scale, and spatial orientation and relative placement of features may be based on the figures. It will be understood that certain terms such as "ceiling" and "floor," as well as "upper," "top," "lower," "top," "below," "bottom," and "top" refer to directions as viewed in the referenced drawings. Furthermore, terms such as "front," "back," "rear," "side," "vertical," and "horizontal" may refer to the orientation and / or placement of portions of a component within any frame of reference that is consistent but becomes apparent by reference to the text describing the component under discussion and the associated drawings. Such terms may include previously specifically mentioned terms, derivatives thereof, and terms of similar import.

[0011] As used herein, the term "adjacent" refers to layers or members that are in direct physical contact with one another, with no layers or members between them. For example, layer X adjacent to layer Y refers to a layer that is in direct physical contact with layer Y. On the other hand, as used herein, the phrase "disposed over" (alternatively, in the context of a first layer or member that is disposed on a second layer or member, "disposed below," "disposed above," or "disposed next to") includes (i) configurations in which a first layer or member is directly physically attached to (i.e., adjacent to) a second layer, and (ii) members and configurations in which a first layer or member is attached to (e.g., coupled to) a second layer or member via one or more intervening layers or members.

[0012] The following detailed description is not intended to limit the application and uses of the disclosed technology. It is apparent that novel embodiments may be practiced without every detail described herein. For simplicity, well-known structures and devices may be shown in block diagram form to facilitate description thereof.

[0013] 1-6B provide various non-limiting examples of embodiments of multi-die bridge assemblies for 3D implementation. Many of the objects in the images are repeated, and similar objects, whether labeled or not, are intended to perform the same function or be the same feature across the images.

[0014] FIG. 1 is a simplified cross-sectional view of a multi-die bridge assembly 100 having a bridge member 102 and two integrated circuit dies, die 106 (IC1) and die 110 (IC2). Dies 106 and 110 may be unpackaged integrated circuit dies or may be referred to as chips, chiplets, chip composites, or chiplet composites. While the terms die, chip, and chiplet may be used interchangeably, the term chiplet is sometimes used to refer to an integrated circuit die that implements a subset of the functionality of a larger integrated circuit member. While the figures show chiplets with uniform dimensions, in reality, chiplet dimensions (lateral dimensions and thickness) and shapes may vary among chiplets. Chiplets may also differ by type / function (e.g., computation, memory, I / O, power management (controlling the supply of power and / or providing power to members)). Furthermore, multi-die bridge assembly 100 can have any shape, such as a generally square, rectangular, or circular shape.

[0015] Die 106 and die 110 are stabilized within an encapsulant 124. The encapsulant 124 may include a molding compound, a dielectric material, a metal, a ceramic, a plastic, or a combination thereof. For ease of description of features, the encapsulant has been omitted from the illustrations of Figures 2, 3, and 4, although in practice these embodiments have an encapsulant.

[0016] The multi-die bridge assembly 100 has a bottom surface 105 / 205 / 305 / 405 (as shown) and a top surface 107. The die 106 / 206 / 306 / 406 / 506 / 606 / has an area of ​​input / output contacts 120-1 (I / O 120-1) (and I / O 220-1 / 320-1 / 420-1 / 520-1 / 620-1) that interface with the substrate and are typically arranged at a bump pitch larger than the hybrid bond interconnect (HBI) bump pitch. In a non-limiting example, the bump pitch may be 110-86 microns BP for the first IC and 110-95 microns BP for the second IC. In another example, the solder bumps are 25 microns or greater and the HBI bump pitch is less than 25 microns. In some embodiments, the HBI bumps may be 10 microns, and in other embodiments, the HBI bumps may be 2 microns. Die 110 / 210 / 310 / 410 / 510 / 610 similarly has an area of ​​input / output contacts 120-2 (I / O 120-2) (and I / O 220-2 / 320-2 / 420-2 / 520-2 / 620-2) that interface with the substrate and are typically arranged at a bump pitch. In some embodiments, I / O 120-1 and I / O 120-2 include solder bumps attached thereto.

[0017] The bridge members 102 / 202 / 302 / 402 / 502 / 602 provide one or more electronic paths between the die 106 and the die 110, as indicated by the curved arrows. The bridge members 102 / 202 / 302 / 402 / 502 / 602 may be implemented as conventional silicon bridges, organic bridges, glass bridges, or some combination thereof. As used herein, a passive bridge member is limited to an electronic path between the die 106 and the die 110, while an active bridge member may include transistors, logic, and / or memory in addition to the electronic path. The electronic connection between the die 106 and the die 110 is facilitated through these electronic paths in the bridge members 102 / 202 / 302 / 402 / 502 / 602 by the attachment means 125. As described in more detail below, the attachment means may be solder bumps containing a solder material, hybrid bonds (HB), first level interconnect thermocompression bonded (TCB) microballs, or plating.

[0018] Die 106 has I / O structures 108 on a first portion of its top surface for connecting to die 110 via bridge member 102, and die 110 has similar I / O structures 112 on a first portion of its top surface for connecting to die 106 via bridge member 102. The collective I / O structures supporting die-to-die (or wafer-to-wafer) communication are referred to as attachment means 125. The attachment means on the top surface of bridge member 102 is separated into a first portion for attaching first die 106 and a second portion for attaching second die 110. As can be appreciated, if the attachment means are solder bumps, then I / O structures 108 and 112 and the top surface of bridge member 102 are configured for solder bumps; if the attachment means are hybrid bonding (HB), then the I / O structures and the top surface of bridge member 102 are configured for HB, and so on. For bridge members, when the attachment means 125 are solder bumps or microbump fields 225-2 / 325-2 / 425-2, the solder bump pitch (BP) may range from 45 microns ±10% to 55 microns ±10%. In other embodiments, the solder bump pitch may be in the range of 25-35 microns. When the attachment means 125 are HBIs, the HBI pitch on the bridge member 102 is even smaller, in the range of 1-10 microns.

[0019] Optional arrow 123 represents an electronic path between first surface 103 of bridge member 102 and second surface 105 of bridge member 102. Optional arrow 123 represents a through silicon via (TSV) or through glass via (TGV) having conductive material therein, typically for power and ground routing. In various embodiments, although not always, if optional arrow 123 is omitted, bridge member 102 is a "passive bridge member." Similarly, in various embodiments, although not always, if bridge member 102 includes optional arrow 123, bridge member 102 is an "active bridge member." In practice, optional arrow 123 is often used to allow power to be supplied to bridge member 102 from a power source located at the bottom of a cavity in the substrate. The electrical path or route indicated by optional arrow 123 can reduce the number of substrate routing layers and improve product yield.

[0020] Multi-die bridge assembly 200 in Figure 2A shows bridge member 202 hybrid-bonded to two integrated circuit dies, while multi-die bridge assembly 230 in Figure 2B shows bridge member 202 solder-bonded to two integrated circuit dies. The side toward the top of the page is the bottom surface (corresponding to top surface 107 in Figure 1) of dies IC1 and IC2 because they are flipped during fabrication. Die 106 / 206 / 306 / 406 has top surface 209 / 309 / 409 and bottom surface 211 / 311 / 411, and die 110 / 210 / 310 / 410 has top surface 213 / 313 / 413 / 513 and bottom surface 215 / 315 / 415 / 515.

[0021] 2A, when attachment means 125 is implemented as hybrid bonding interface (HBI) 225-1, die 106 and die 110 each include an HB surface. As mentioned above, dies 206 / 306 / 406 / 506 / 606 and 208 / 308 / 408 / 508 / 608 are inverted, so that the HB surface is recognized as the underside of the die in a multi-die bridge assembly.

[0022] The HB surface of die 206 / 306 / 406 is defined by hybrid bond contacts 208 / 308 / 408 surrounded by insulating material (often a dielectric material). The HB surface of die 210 / 310 / 410 is defined by hybrid bond contacts 212 / 312 / 412 surrounded by insulating material (which need not be the same dielectric material as used in die 206 / 306 / 406). Similarly, bridge member 202 / 302 / 402 includes insulating material and is defined by a first surface 203 and a second surface 205.

[0023] The insulating material in bridge members IC1 and / or IC2 may be any dielectric material, such as silicon dioxide (SiO), a suitable nitride or oxide such as carbon-doped silicon dioxide (C-doped SiO, a material containing silicon, oxygen, and carbon, also known as CDO or organosilicate glass), fluorine-doped silicon dioxide (F-doped SiO, a material containing fluorine, silicon, and oxygen, also known as fluorosilicate glass), or hydrogen-doped silicon dioxide (H-doped SiO, a material containing silicon, oxygen, and hydrogen). In some embodiments, the dielectric layer comprises a photoimageable dielectric (PID). In some embodiments, the dielectric layer comprises an Ajinomoto build-up film (often referred to as ABF), which is a material comprising an organic resin matrix containing different types of fillers (e.g., silica fillers of different sizes, or hollow fillers of different sizes) to control the coefficient of thermal expansion (CTE) and / or electrical properties (e.g., dielectric constant (Dk), and / or dissipation factor (insertion loss) (Df)).

[0024] In some embodiments, it is advantageous for the dielectric layer in the bridge member to have a CTE that matches the CTE of the integrated circuit die (IC1 and IC2) (e.g., matches the CTE of silicon) or matches the substrate or PCB. In some embodiments, the dielectric material may have a CTE that is close to (e.g., within 10%) the CTE of silicon. In other embodiments, the dielectric material may be any type of epoxy molding compound.

[0025] Returning to the description of the HB interface 225-1, the first die 106 / 206 / 306 has a top surface 209 / 309 / 409 having an insulating material and a plurality of HB contacts, and the second die 210 / 310 / 410 has another insulating material having another plurality of HB contacts 212 / 312 / 412. At the surface 209 / 309 / 409 and the surface 213 / 313 / 413, the HB contacts are exposed and the dielectric is exposed. In other words, at the HB surface, there is dielectric material adjacent to the metal / Cu hybrid junction contacts. The HB contacts 208 / 308 / 408 and the HB contacts 212 / 312 / 412 may be metal or may include copper. In various embodiments, at least one hybrid junction contact 208 / 308 / 408 and at least one hybrid junction contact 212 / 312 / 412 are exposed at the HB interface 225-1.

[0026] When the attachment means 125 is HB, such as HB interface 225-1, the first surface 203 has a plurality of HB contacts (first metal contacts 204 / 304 / 404), which are arranged in a first area (first metal contacts 204-1 / 304-1 / 404-1) and a second area (second first metal contacts 204-2 / 304-2 / 404-2). As shown by the arrows in FIG. 1 , the bridge member provides at least one electrical path 240 / 340 / 440 / 540 / 640 between the first first metal contact 204-1 in the first region and the second first metal contact 204-2 in the second region. The second surface 205 may be configured to be attached to a substrate.

[0027] In multi-die bridge assembly 200, die 206 is hybrid bonded to bridge member 202, and die 210 is hybrid bonded to bridge member 202, as shown. Thus, at HB interface 225-1, the insulator or dielectric material of die 106 and the insulator or dielectric material of die 110 are bonded to the insulator or dielectric material of bridge member 202 (e.g., in SEM images, the dielectric material SiO x From SiO x , SiO x N y From SiO x N y HB contact 208 is bonded to HB contact 204-1, and HB contact 212 is bonded to HB contact 204-2. No solder material is present at this HB interface 225-1.

[0028] Figure 2B has all the same components and objects as Figure 2A, except for the embodiment of attachment means 125. In Figure 2B, the attachment means are solder bumps or microbump fields 225-2 / 325-2 / 425-2. The first die 206 / 306 / 406 is soldered to the bridge member 202 / 302 / 402 using solder bumps 232 / 332 / 432, and the second die 210 / 310 / 410 is soldered to the bridge member 202 / 302 / 402 using solder bumps 234 / 334 / 434.

[0029] The multi-die bridge assembly 300 of Figure 3A shows a bridge member hybrid-bonded to two integrated circuit dies. Figure 3A has the same components and objects as Figure 2A, but adds at least one contact 320-3 / 420-3 on the second surface 305 / 405 to provide an electrical path to the first surface 303 / 403 (arrow 123 in the embodiment of Figure 1). When assembled into a package with a substrate, power and ground may be routed from the second surface 305 to the integrated circuits on die 106 and die 110, respectively, via these electrical paths.

[0030] Figure 3B shows a multi-die bridge assembly 330 solder-bonded to two integrated circuit dies, according to various embodiments. Figure 3B has the same components and objects as Figure 2B, but adds at least one contact 320-3 on the second surface 305 to provide an electrical path to the first surface 303.

[0031] Multi-die bridge assembly 400 in FIG. 4A illustrates multi-die bridge assembly 300 with mold encapsulation 424 over the bottom / backside of die 406 and die 410. Similar to FIGS. 2A and 3A, bridge member 402 is hybrid-bonded to die 406 and die 410. Multi-die bridge assembly 430 in FIG. 4B illustrates multi-die bridge assembly 330 with mold encapsulation 424 over the bottom / backside of die 406 and die 410 in an embodiment with solder-bonded bridge member 402, and further illustrates underfill 436 between the bridge member and top surfaces 409 and 413. The underfill surrounds solder bumps 432 and 434. Various underfill materials can be used, and they are typically non-conductive (electrically) and reduce thermomechanical stress. The underfill material may take the form of a liquid prepolymer containing fillers such as silica, alumina, or boron nitride. The underfill is allowed to cure and solidify.

[0032] 5A and 5B provide two non-limiting examples of multi-die bridge assemblies 500 and 530 prepared for assembly onto a substrate. The illustrated bridge member 502 is a bridge member with TSVs or TGVs. The multi-die bridge assembly 500 has ball pitch solder pads 520-1 on a first die 506, ball pitch solder pads 520-2 on a second die 510, and ball pitch solder pads 526 on a second surface (the "bottom" in the drawings, the portion that can fit into a cavity in a substrate) of the bridge member 502. FIG. 5B shows a multi-die bridge assembly 530 configured for hybrid bonding within a cavity (HB contacts 536), with ball pitch solder pads 520-1 and 520-2 configured for soldering the two integrated circuit dies to a substrate.

[0033] 6A, embodiment 600 shows embodiment 500 with the addition of glass frame 628. In plan view, glass frame 628 may appear as a glass ladder or glass door with a pair of open windows or cavities running through it. The glass frame (also referred to herein as the glass structure) provides structural stability to die 606 and die 610. The individual dies are placed within the cavities of the glass structure, and the dies are surrounded by encapsulant 624.

[0034] The embodiment of multi-die bridge assembly 630 in FIG. 6B illustrates that in some applications, multi-die bridge assembly 630 may be flipped upside down so that the underside or backside of die 106 and die 110 (solder bumps 650-2 on die 610 and solder bumps 650-1 on die 606) can be attached to a substrate.

[0035] The above is not an exhaustive list of permissible combinations for a multi-die bridge member. It will be apparent to one skilled in the art that additional multi-die bridge assembly embodiments not shown are supported based on the figures and descriptions contained herein. See, for example, Table 1. In addition to the variations provided in Table 1, embodiments may include a glass frame. Also, as part of the thermal management solution, a thermally conductive interface material (TIM) (not shown) may be disposed over the encapsulant and / or over the dies 106 / 206 / 306 / 406 / 506 / 606 and 110 / 210 / 310 / 410 / 510 / 610. The TIM may be any suitable material, such as a silver particle-filled thermal compound, thermal grease, a phase change material, an indium foil, or a graphite sheet. The thermal management solution may be a conformal solution that accommodates the height differences of the integrated circuit dies to which it provides cooling. For example, the thermal management solution may include a substantially planar cooling member with TIM of varying thicknesses between the cooling member and the integrated circuit dies. In another example, the cooling component may be non-planar, and the profile of the cooling member may vary depending on the thickness of the integrated circuit die to which it provides cooling. In such an embodiment, the TIM may be of substantially uniform thickness between the cooling member and integrated circuit dies of various thicknesses. The thermal management solution may also have an integrated heat spreader.

[0036] [Table 1] The multi-die (MD) assembly can be attached to a substrate, as described with reference to Figures 7, 8, 9, and 10. Figure 7 shows a substrate 700 / 870 / 970 / 1070 that includes one or more dielectric layers 724 patterned with redistribution layer (RDL) conductive traces 728. Various embodiments of the substrate may also have a layer of glass 702 / 802 / 902 / 1002 or glass core and a dielectric layer 730 / 830 / 930 / 1030 disposed on the underside of the glass core 702 / 802 / 902 / 1002 with RDL conductive traces and vias 726 / 728, 826 / 828, 926 / 928, and 1026 / 1028 patterned therein.

[0037] The dielectric layers 724 and 730 may be any suitable dielectric, as described above. The conductive materials used for the conductive contacts, HB contacts (e.g., 208, 212, 204), and RDL traces and vias 728 / 728 may include metals (e.g., copper, aluminum, nickel, cobalt, iron, tin, gold, silver, or combinations thereof) or another suitable conductive material.

[0038] The substrate 700 shows a layer of glass 702 / 802 / 902 / 1002 or glass core patterned with through holes or a plurality of through-glass vias (TGVs) 704 / 804 / 904 / 1004. The glass layer 702 / 830 / 930 / 1030 may comprise glass (as used herein, glass may be an alkali-free alkaline earth boro-aluminosilicate glass, such as a glass containing aluminum, oxygen, boron, silicon, and alkaline earth metals (e.g., glasses containing beryllium, magnesium, calcium, strontium, barium, radium, e.g., SiO2, Al2O3, BO3, and MgO), or a photosensitive glass (photomachinable or photostructurable glass)). In some embodiments, the photosensitive glass may be a glass belonging to the lithium silicate family of glasses (e.g., glasses containing lithium, silicon, and oxygen) containing metal particles such as gold, silver, or other suitable metal particles. The glass layer 702 or glass core may include multiple glass sheets bonded together with adhesive layers. In various embodiments, for example, in a substrate 700 having a Z height (as shown) ranging from approximately 10 millimeters (mm) to 500 mm, the layer of glass 702 may have a thickness (Z height) ranging from approximately 20 micrometers to approximately 1.5 millimeters ±10%. The TGVs 704 are volumes from which glass has been removed, in which a conductive material is disposed in a volume sufficient to allow electrical communication from the top surface 703 to the bottom surface. As shown in the embodiment of the substrate 700, the TGVs 704 are substantially perpendicular to the top surface 703 of the glass layer 702. In embodiments where a panel is fabricated at one time, the X length and corresponding Y length (defining an area in a top or plan view) may be within a first length (e.g., X) ranging from 10 millimeters to 500 millimeters, and a second length (e.g., Y) ranging from 10 millimeters to 500 millimeters, where the first length may be perpendicular to the second length.

[0039] In embodiments of substrates 700, 870, and 970, a cavity 701 is formed in the top surface 703 of the substrate. As will be understood, the cavity portion of the substrate comprises a smaller width, area, or volume of the overall substrate under consideration. The figures reflect a cross-sectional view, and portions of the dielectric cavity are shown as widths, whereas in a top view, portions of the dielectric cavity appear as areas. The dielectric cavity is formed in the substrate by removing dielectric material to a predetermined depth. A laser drilling or ablation process may be used to remove the dielectric material and form the dielectric cavity. The cavity walls are substantially straight (i.e., 90 degrees ± 20 degrees from perpendicular to the top surface of the glass layer 702, although in other embodiments, the cavity walls may be 90 degrees ± 10 degrees) and may have an internal taper that reflects the drilling or ablation process used to open the cavity. Another manufacturing method may include laser drilling holes on the bottom surface 705 / 805 / 905 / 1005, via / solder bump plating, followed by SR lamination, SRO opening, and solder ball attach.

[0040] FIG. 8 illustrates a semiconductor package 800 with a multi-die bridge member attached. The reader can see IC1, IC2, and encapsulant 824 / 924, as well as attachment means 825 / 925. IC1 and IC2 are soldered to the top surface of a substrate 870 / 970 with solder bumps 882 / 982. The multi-die bridge member includes bridge members 872 / 972 with TSVs or TGVs, soldered to the cavity floor as shown. Underfill material 860 / 960 extends across the entire top surface of the substrate 870 and is guided into the cavity around the bridge members 872 / 972. To identify this embodiment in an SEM or TEM image, look for this underflow and ensure it contains the same material throughout. The bottom surface 805 may have openings formed for the solder bumps.

[0041] Figure 9 shows most of the same objects and components as Figure 8. In embodiment 900, the multi-die bridge assembly is attached to a substrate 970 using hybrid bonds within the cavity (for the bridge) and solder bonds outside the cavity (for die 1 and die 2 to the substrate). In other embodiments, the multi-die bridge member may have passive bridge members and be attached to the cavity floor using an adhesive material. The bottom surface 905 may have openings formed for solder bumps.

[0042] 10 illustrates an inverted embodiment of multi-die bridge assembly 630 with solder attached to top surface 1003 of substrate 1070 (see solder attachments 1020-1 and 1020-2). Underfill (not shown) may be added prior to further fabrication steps. Bottom surface 1005 may have openings formed for solder bumps.

[0043] In the above embodiments, functionality traditionally associated with a monolithic system-on-chip (SoC) may be provided in a multi-die package assembly, and further, overmolding processes and thermal solutions (not shown) may be added.

[0044] 11 illustrates a method of multi-die bridge assembly for 3D semiconductor packaging. Method 1100 includes assembling (at 1102) a first integrated circuit (IC) die and a second IC die on a carrier using an adhesive or bonding film. At 1104, a layer of encapsulant or molding material is overlaid on the first IC and the second IC. In some embodiments, a layer of dielectric material is sandwiched between the first IC, the second IC, and the layer of encapsulant.

[0045] At 1106, the carrier is removed from the assembly. At 1108, a bridge member is attached to the first portion of the first IC and the first portion of the second IC, thereby forming a multi-die bridge assembly. At 1110, the multi-die bridge assembly is subjected to testing to determine whether it passes performance metrics.

[0046] At 1112, after the multi-die bridge assembly passes performance metrics, a substrate is attached to the multi-die bridge assembly. At 1112, the substrate has a cavity, and the multi-die bridge assembly is attached to the substrate such that the bridge member is disposed within the cavity. As previously described, there are various methods for attaching the bridge member within the cavity, such as hybrid bonding, solder bump bonding, adhesive or bonding film, thermocompression bonding, etc. In some embodiments, the substrate does not have a cavity, and the multi-die bridge assembly is attached to the substrate as described with respect to FIG. 10 . Upon completion of 1112, the component is referred to as a package assembly.

[0047] At 1114, any additional assembly may be performed to form a system package, which may have one or more package assemblies from 1112 and / or other integrated circuit components and / or active or passive electronic components.

[0048] Thus, various non-limiting embodiments of multi-die assembly and 3D packaging methods are described. The embodiments exhibit distinct features in SEM images, including but not limited to consistent underfill across the MD bridge members and between the bridge members and the substrate, and / or a combination of HB and solder joints. The following description provides additional details and context for various die and package assemblies and device configurations that may be formed based on or using the provided embodiments.

[0049] 12 is a top view of a wafer 1200 and dies 1202 that may be included in any embodiment disclosed herein. Wafer 1200 may be composed of a semiconductor material and may include one or more dies 1202 formed on its surface. After fabrication of integrated circuit components on wafer 1200 is complete, wafer 1200 is subjected to a singulation process in which dies 1202 are separated from one another to provide individual “chips” or packaged integrated circuit components. Individual dies 1202 with integrated circuit components may include one or more transistors (e.g., part of transistor 1340 in FIG. 13 described below), support circuitry for routing electrical signals to the transistors, passive components (e.g., signal traces, resistors, capacitors, or inductors), and / or any other integrated circuit components. In some embodiments, wafer 1200 or die 1202 may include memory devices (e.g., random access memory (RAM) devices such as static RAM (SRAM) devices, magnetic RAM (MRAM) devices, resistive RAM (RRAM) devices, conductive bridging RAM (CBRAM) devices, etc.), logic devices (e.g., AND, OR, NAND, or NOR gates), or any other suitable circuit elements. Multiple devices may also be combined on a single die 1202. For example, a memory array formed by multiple memory devices may be formed on the same die 1202 as a processor unit (e.g., processor unit 1502 of FIG. 15 ) or other logic configured to store information in the memory devices or execute instructions stored in the memory array. In some embodiments, die 1202 may be attached to wafer 1200 including other dies, and wafer 1200 is then singulated. This manufacturing procedure is referred to as die-to-wafer assembly technology.

[0050] 13 is a cross-sectional side view of integrated circuits 1300 that may be included in any embodiment disclosed herein. One or more of the integrated circuits 1300 may be included in one or more dies 1202 (FIG. 12). The integrated circuits 1300 may be formed on a die substrate 1302 (e.g., wafer 1200 of FIG. 12) or may be included in a die (e.g., die 1202 of FIG. 12).

[0051] The die substrate 1302 may be a semiconductor substrate composed of a semiconductor material system, including, for example, an n-type or p-type material system (or a combination of both). The die substrate 1302 may have a crystalline substrate formed, for example, using bulk silicon or a silicon-on-insulator (SOI) substructure. In some embodiments, the die substrate 1302 may be formed using alternative materials, which may or may not be combined with silicon, including, but not limited to, germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. Other materials classified as II-VI, III-V, or IV may also be used to form the die substrate 1302. While some examples of materials from which the die substrate 1302 can be formed are described herein, any material capable of serving as the basis for the integrated circuit 1300 may be used. Die substrate 1302 may be part of a singulated die (eg, die 1202 in FIG. 12) or a wafer (eg, wafer 1200 in FIG. 12).

[0052] The integrated circuit 1300 may have one or more device layers 1304 disposed on a die substrate 1302. The device layer 1304 may include features of one or more transistors 1340 (e.g., metal oxide semiconductor field effect transistors (MOSFETs)) formed on the die substrate 1302. The transistor 1340 may have, for example, one or more source and / or drain (S / D) regions 1320, a gate 1322 that controls the flow of current between the S / D regions 1320, and one or more S / D contacts 1324 that conduct electrical signals to / from the S / D regions 1320.

[0053] The gate 1322 may be formed of at least two layers: a gate dielectric and a gate electrode. The gate dielectric may have one layer or a stack of layers. One or more layers may include silicon oxide, silicon dioxide, silicon carbide, and / or a high-k dielectric material. The high-k dielectric material may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high-k materials that may be used for the gate dielectric include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. In some embodiments, when high-k materials are used, an annealing process may be performed on the gate dielectric to improve its quality.

[0054] A gate electrode is formed on the gate dielectric and may have at least one p-type work function metal or n-type work function metal, depending on whether the transistor 1340 is a p-type metal oxide semiconductor (PMOS) transistor or an n-type metal oxide semiconductor (NMOS) transistor. In some implementations, the gate electrode has a stack of two or more metal layers, where one or more metal layers are work function metal layers and at least one metal layer is a fill metal layer. Additional metal layers, such as barrier layers, may be included for other purposes.

[0055] For PMOS transistors, metals that may be used for the gate electrode may include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, conductive metal oxides (e.g., ruthenium oxide), and any of the metals described below with respect to NMOS transistors (e.g., for work function adjustment). For NMOS transistors, metals that may be used for the gate electrode may include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide), and any of the aforementioned metals (e.g., for work function adjustment) listed with respect to PMOS transistors.

[0056] In some embodiments, when viewed as a cross-section of the transistor 1340 along the source-channel-drain direction, the gate electrode may have a U-shaped structure with a bottom substantially parallel to the surface of the die substrate 1302 and two sidewalls substantially perpendicular to the top surface of the die substrate 1302. In other embodiments, at least one of the metal layers forming the gate electrode may simply be a flat layer, with sidewalls substantially parallel to the top surface of the die substrate 1302 and no sidewalls substantially perpendicular to the top surface of the die substrate 1302. In other embodiments, the gate electrode may include a combination of a U-shaped structure and a flat, non-U-shaped structure. For example, the gate electrode may have one or more U-shaped metal layers formed on one or more flat, non-U-shaped layers.

[0057] In some embodiments, a set of sidewall spacers may be formed on opposing sides of the gate stack to surround the gate stack. The sidewall spacers may be formed from materials such as silicon nitride, silicon oxide, silicon carbide, carbon-doped silicon nitride, and silicon oxynitride. Processes for forming sidewall spacers are well known and include deposition and etching processes. In some embodiments, multiple sets of spacers may be used, for example, two, three, or four sets of sidewall spacers may be formed on opposing sides of the gate stack.

[0058] The S / D regions 1320 may be formed in the die substrate 1302 adjacent to the gates 1322 of the individual transistors 1340. The S / D regions 1320 may be formed using, for example, an implantation / diffusion process or an etching / deposition process. In the former process, dopants such as boron, aluminum, antimony, phosphorus, or arsenic may be ion-implanted into the die substrate 1302 to form the S / D regions 1320. An annealing process may be performed following the ion-implantation process to activate the dopants and further diffuse them into the die substrate 1302. In the latter process, the die substrate 1302 may first be etched to form recesses at the locations of the S / D regions 1320. An epitaxial deposition process may then be performed to fill the recesses with the material used to fabricate the S / D regions 1320. In some embodiments, the S / D regions 1320 may be fabricated using silicon alloys such as silicon germanium or silicon carbide. In some embodiments, the epitaxially deposited silicon alloy may be n-situ doped with dopants such as boron, arsenic, or phosphorus. In some embodiments, the S / D regions 1320 may be formed using one or more alternative semiconductor materials, such as germanium or a III-V material or alloy. In other embodiments, the S / D regions 1320 may be formed using one or more layers of metal and / or metal alloy.

[0059] Electrical signals, such as power signals and / or input / output (I / O) signals, may be routed to and / or from devices (e.g., transistor 1340) in device layer 1304 through one or more interconnect layers (shown in FIG. 13 as interconnect layers 1306-1310) disposed in device layer 1304. For example, conductive features (e.g., gate 1322 and S / D contacts 1324) in device layer 1304 may be electrically coupled with interconnect structures 1328 in interconnect layers 1306-1310. One or more interconnect layers 1306-1310 may form a metallization stack (also referred to as an "ILD stack") 1319 of integrated circuit 1300.

[0060] Interconnect structures 1328 may be disposed within interconnect layers 1306-1310 and route electrical signals according to a wide variety of designs, and notably, this arrangement is not limited to the particular configuration of interconnect structures 1328 shown in Figure 13. While Figure 13 shows a particular number of interconnect layers 1306-1310, embodiments of the present disclosure have integrated circuits that include more or fewer interconnect layers than shown.

[0061] In some embodiments, the interconnect structures 1328 may include lines 1328a and / or vias 1328b filled with a conductive material, such as metal. The lines 1328a may be arranged to route electrical signals in a plane substantially parallel to the surface of the die substrate 1302 on which the device layer 1304 is formed. For example, the lines 1328a may route electrical signals in a direction into and out of the page and / or across the page. The vias 1328b may be arranged to route electrical signals in a plane substantially perpendicular to the surface of the die substrate 1302 on which the device layer 1304 is formed. In some embodiments, the vias 1328b may electrically couple the lines 1328a of different interconnect layers 1306-1310 to one another.

[0062] The interconnect layers 1306-1310 may have a dielectric material 1326 disposed between interconnect structures 1328, as shown in FIG. 13 . In some embodiments, the dielectric material 1326 disposed between the interconnect structures 1328 in different ones of the interconnect layers 1306-1310 may have different compositions. In other embodiments, the composition of the dielectric material 1326 between different interconnect layers 1306-1310 may be the same. Similarly, the device layer 1304 may have a dielectric material 1326 disposed between the transistor 1340 and the bottom layer of the metallization stack. The dielectric material 1326 included in the device layer 1304 may have a different composition than the dielectric material 1326 included in the interconnect layers 1306-1310, and in other embodiments, the composition of the dielectric material 1326 in the device layer 1304 may be the same as the dielectric material 1326 included in any one of the interconnect layers 1306-1310.

[0063] A first interconnect layer 1306 (referred to as metal 1 or "M1") may be formed directly on the device layer 1304. In some embodiments, the first interconnect layer 1306 may have lines 1328a and / or vias 1328b, as shown. The lines 1306a of the first interconnect layer 1328 may be coupled to contacts (e.g., S / D contacts 1324) of the device layer 1304. The vias 1306b of the first interconnect layer 1328 may be coupled to lines 1308a of the second interconnect layer 1328.

[0064] A second interconnect layer 1308 (referred to as metal 2 or "M2") may be formed directly on the first interconnect layer 1306. In some embodiments, the second interconnect layer 1308 may include vias 1328b, coupling lines of interconnect structures 1328 of the second interconnect layer 1308 to lines 1328a of the third interconnect layer 1310. Although the lines 1328a and vias 1328b are structurally depicted as lines within individual interconnect layers for clarity, in some embodiments, the lines 1328a and vias 1328b may be structurally and / or materially continuous (e.g., filled simultaneously during a dual damascene process).

[0065] The third interconnect layer 1310 (referred to as metal 3 or "M3") (and additional interconnect layers, if desired) may be formed successively on the second interconnect layer 1308 according to similar techniques and configurations described with respect to the second interconnect layer 1308 or the first interconnect layer 1306. In some embodiments, the "higher" (i.e., further from the device layer 1304) interconnect layers of the metallization stack 1319 in the integrated circuit 1300 may be thicker than the lower interconnect layers in the metallization stack 1319, and the lines 1328a and vias 1328b in the higher interconnect layers may be thicker than the lines and vias in the lower interconnect layers.

[0066] The integrated circuit 1300 may have a solder resist material 1334 (e.g., polyimide or a similar material) and one or more conductive contacts 1336 formed on the interconnect layers 1306-1310. In FIG. 13, the conductive contacts 1336 are shown to take the form of bond pads. The conductive contacts 1336 may be electrically coupled to the interconnect structure 1328 and configured to route electrical signals from the transistor 1340 to an external device. For example, solder bonds may be formed on one or more of the conductive contacts 1336 to mechanically and / or electrically couple an integrated circuit die including the integrated circuit 1300 to another component (e.g., a printed circuit board). The integrated circuit 1300 may have additional or different structures for routing electrical signals from the interconnect layers 1306-1310; for example, the conductive contacts 1336 may have other similar features (e.g., posts) for routing electrical signals to an external component.

[0067] In some embodiments in which integrated circuit 1300 is a double-sided die, integrated circuit 1300 may have another metallization stack (not shown) on the opposite side of device layer 1304. This metallization stack may have multiple interconnect layers, as described above with reference to interconnect layers 1306-1310, to provide conductive paths (e.g., including conductive lines and vias) between device layer 1304 and additional conductive contacts (not shown) on the opposite side of integrated circuit 1300 from conductive contact 1336.

[0068] In other embodiments in which integrated circuit 1300 is a double-sided die, integrated circuit 1300 may have one or more through-silicon vias (TSVs) that extend through die substrate 1302. These TSVs may be in contact with device layer 1304 and provide conductive paths between device layer 1304 and additional conductive contacts (not shown) on the opposite side of integrated circuit 1300 from conductive contacts 1336. In some embodiments, TSVs extending through the substrate are used to route power and ground signals from the conductive contacts on the opposite side of integrated circuit 1300, from conductive contacts 1336 to transistor 1340 and any other components integrated on the integrated circuit 1300 die, and metallization stack 1319 may be used to route I / O signals from conductive contacts 1336 to transistor 1340 and any other components integrated on the integrated circuit 1300 die.

[0069] Multiple integrated circuits 1300 may be stacked with one or more TSVs in each stacked device to provide a connection between one of the devices and any of the other devices in the stack. For example, one or more high-bandwidth memory (HBM) integrated circuit dies may be stacked on top of a base integrated circuit die, and TSVs in the HBM die may provide a connection between the individual HBM and the base integrated circuit die. Conductive contacts may provide additional connections between adjacent integrated circuit dies in the stack. In some embodiments, the conductive contacts may be fine-pitch solder bumps (microbumps).

[0070] 14 is a cross-sectional side view of a microelectronic assembly 1400 that may have any of the embodiments disclosed herein. The microelectronic assembly 1400 includes a plurality of integrated circuit components disposed on a circuit board 1402 (which may be a motherboard, system board, mainboard, etc.). The microelectronic assembly 1400 may have components disposed on a first side 1440 of the circuit board 1402 and an opposing second side 1442 of the circuit board 1402. Typically, components may be disposed on one or both of the sides 1440 and 1442.

[0071] In some embodiments, the circuit board 1402 may be a printed circuit board (PCB) that includes multiple metal (or interconnect) layers separated from each other by layers of dielectric material and interconnected by conductive vias. Individual metal layers include conductive traces. Any one or more of the metal layers may be formed in a desired circuit pattern to route electrical signals (with other metal layers, if necessary) between components coupled to the circuit board 1402. In other embodiments, the circuit board 1402 may be a non-PCB substrate. The miniaturized electronic assembly 1400 shown in FIG. 14 includes a package-on-interposer structure 1436 that is coupled to a first surface 1440 of the circuit board 1402 by a coupling member 1416. The bonding members 1416 electrically and mechanically bond the package-on-interposer structure 1436 to the circuit board 1402 and may include solder balls (as shown in FIG. 14), pins (e.g., as part of a pin grid array (PGA)), contacts (e.g., as part of a land grid array (LGA)), male and female portions of a socket, adhesive, underfill material, and / or any other suitable electrical and / or mechanical bonding structure.

[0072] The package-on-interposer structure 1436 may have an integrated circuit member 1420 coupled to the interposer 1404 by a coupling member 1418. The coupling member 1418 may take any form suitable for the application, such as those forms described above with reference to the coupling member 1416. While a single integrated circuit member 1420 is shown in FIG. 14, multiple integrated circuit members may be coupled to the interposer 1404, and in fact additional interposers may be coupled to the interposer 1404. The interposer 1404 may provide an intervening substrate used to bridge the circuit board 1402 and the integrated circuit member 1420.

[0073] Integrated circuit member 1420 may be a packaged or unpackaged integrated circuit member including one or more integrated circuit dies (e.g., die 1202 of FIG. 12, integrated circuit 1300 of FIG. 13) and / or one or more other suitable members.

[0074] The unpopulated integrated circuit member 1420 has solder bumps attached to contacts on the die. The solder bumps allow the die to be directly attached to the interposer 1404. In embodiments in which the integrated circuit member 1420 includes multiple integrated circuit dies, the dies may be of the same type (a homogeneous multi-die integrated circuit member) or two or more different types (a heterogeneous multi-die integrated circuit member). In addition to including one or more processor units, the integrated circuit member 1420 may include additional components, such as embedded DRAM, stacked high-bandwidth memory (HBM), shared cache memory, input / output (I / O) controllers, or memory controllers. Any of these additional components may be located on the same integrated circuit die as the processor unit or on one or more integrated circuit dies separate from the integrated circuit die with the processor unit. These separate integrated circuit dies may be referred to as "chiplets." In embodiments in which the integrated circuit member includes multiple integrated circuit dies, interconnections between the dies may be provided by a package substrate, one or more silicon interposers, one or more silicon bridges embedded in the package substrate, or a combination thereof. A packaged multi-die integrated circuit component may be referred to as a multi-chip package (MCP) or a multi-chip module (MCM).

[0075] The interposer 1404 may spread connections to a wider pitch or reroute connections to different connections. For example, the interposer 1404 may couple the integrated circuit member 1420 to a set of ball grid array (BGA) conductive contacts of the coupling member 1416 for coupling to the circuit board 1402. In the embodiment shown in FIG. 14 , the integrated circuit member 1420 and the circuit board 1402 are attached to opposite sides of the interposer 1404. In other embodiments, the integrated circuit member 1420 and the circuit board 1402 may be attached to the same side of the interposer 1404. In some embodiments, more than two members may be interconnected by the interposer 1404.

[0076] In some embodiments, the interposer 1404 may be formed as a PCB, having multiple metal layers separated from each other by layers of dielectric material and interconnected by conductive vias. In some embodiments, the interposer 1404 may be formed from a polymeric material such as epoxy, glass-reinforced epoxy, epoxy with inorganic filler, ceramic material, or polyimide. In some embodiments, the interposer 1404 may be formed from another rigid or flexible material, which may include materials such as those previously used in semiconductor substrates, such as silicon, germanium, and other III-V and IV materials. The interposer 1404 has metal interconnects 1408 and vias 1410, which may include, but are not limited to, through-hole vias 1410-1 (extending from the first surface 1450 of the interposer 1404 to the second surface 1454 of the interposer 1404), blind vias 1410-2 (extending from the first surface 1450 or the second surface 1454 of the interposer 1404 to an internal metal layer), and buried vias 1410-3 (connecting the internal metal layers).

[0077] In some embodiments, the interposer 1404 can include a silicon interposer. Through-silicon vias (TSVs) extending through the silicon interposer can connect connections on a first side of the silicon interposer to an opposing second side of the silicon interposer. In some embodiments, the interposer 1404 including the silicon interposer further includes one or more routing layers, where connections on the first side of the interposer 1404 are routed to the opposing second side of the interposer 1404.

[0078] The interposer 1404 may further include embedded devices 1414, including both passive and active devices. Such devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices. More complex devices, such as radio frequency devices, power amplifiers, power management devices, antennas, arrays, sensors, and small electromechanical systems (MEMS) devices, may also be formed on the interposer 1404. The package-on-interposer structure 1436 may take the form of any conventionally known package-on-interposer structure.

[0079] Integrated circuit assembly 1400 may have an integrated circuit member 1424 coupled to a first surface 1440 of circuit board 1402 by a coupling member 1422. Coupling member 1422 may take the form of any of the embodiments described above with reference to coupling member 1416, and integrated circuit member 1424 may take the form of any of the embodiments described above with reference to integrated circuit member 1420.

[0080] 14 includes a package-on-package structure 1434 coupled to a second surface 1442 of a circuit board 1402 by a bonding member 1428. The package-on-package structure 1434 may have an integrated circuit member 1426 and an integrated circuit member 1432 coupled to one another by a bonding member 1430, with the integrated circuit member 1426 disposed between the circuit board 1402 and the integrated circuit member 1432. The bonding members 1428 and 1430 may take the form of any of the previously described embodiments of the bonding member 1416, and the integrated circuit members 1426 and 1432 may take the form of any of the previously described embodiments of the integrated circuit member 1420. The package-on-package structure 1434 may be configured according to any conventionally known package-on-package structure.

[0081] FIG. 15 is a block diagram of an example electrical device 1500 that may include one or more of the embodiments disclosed herein. For example, any suitable component of electrical device 1500 may include a miniature electronic assembly 1400, an integrated circuit component 1420, an integrated circuit 1300, an integrated circuit die 1202, or one or more of the structures disclosed herein. While FIG. 15 illustrates many components included in electrical device 1500, any one or more of these components may be omitted or duplicated to suit the application. In some embodiments, some or all of the components included in electrical device 1500 may be mounted on one or more motherboards, mainboards, printed circuit boards, or system boards. In some embodiments, one or more of these components are fabricated on a single system-on-chip (SoC) die. In various embodiments, electrical device 1500 is enclosed in or integrated with a housing.

[0082] 15, but the electrical device 1500 may have interface circuitry for coupling to one or more of the components. For example, the electrical device 1500 may not have a display device 1506, but may have display device interface circuitry (e.g., connectors and driver circuitry) to which the display device 1506 may be coupled. In another set of examples, the electrical device 1500 may not have an audio input device 1524 or an audio output device 1508, but may have audio input or output device interface circuitry (e.g., connectors and support circuitry) to which the audio input device 1524 or the audio output device 1508 may be coupled.

[0083] The electrical device 1500 may have one or more processor units 1502 (e.g., one or more processor units). As used herein, the terms “processor unit,” “processing unit,” or “processor” may refer to any device or portion of a device that processes electronic data from registers and / or memory and converts the electronic data into other electronic data that can be stored in registers and / or memory. The processor unit 1502 may include one or more digital signal processors (DSPs), application-specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPUs), general-purpose GPUs (GPGPUs), accelerated processing units (APUs), field-programmable gate arrays (FPGAs), neural network processing units (NPUs), data processor units (DPUs), accelerators (e.g., graphics accelerators, compression accelerators, artificial intelligence accelerators), controller cryptoprocessors (dedicated processors that execute cryptographic algorithms in hardware), server processors, controllers, or any other suitable type of processor unit. Accordingly, the processor unit may be referred to as an XPU (or xPU).

[0084] The electrical device 1500 may include memory 1504, which itself may include one or more memory devices, such as volatile memory (e.g., dynamic random access memory (DRAM), static random access memory (SRAM)), non-volatile memory (e.g., read-only memory (ROM), flash memory, chalcogenide-based phase-change non-voltage memory), semiconductor memory, and / or a hard drive. In some embodiments, the memory 1504 may include memory located on the same integrated circuit die as the processor unit 1502. This memory may be used as cache memory (e.g., level 1 (L1), level 2 (L2), level 3 (L3), level 4 (L4), last level cache (LLC)) and may include embedded dynamic random access memory (eDRAM) or spin-transfer torque magnetization (or spin-transfer magnetization reversal) random access memory (STT-MRAM).

[0085] In some embodiments, the electrical device 1500 has one or more processor units 1502, which may be heterogeneous or asymmetric with respect to other processor units 1502 in the electrical device 1500. There may be various differences between the processor units 1502 in the system with respect to a spectrum of metrics of merit, including architectural characteristics, microarchitectural characteristics, thermal characteristics, power consumption characteristics, etc. These differences may effectively manifest as asymmetries and heterogeneity between the processor units 1502 in the electrical device 1500.

[0086] In some embodiments, the electrical device 1500 may have a communications member 1512 (e.g., one or more communications members). For example, the communications member 1512 may manage wireless communications for the transfer of data to and from the electrical device 1500. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc. that can communicate data using modulated electromagnetic radiation over a non-solid medium. The term "wireless" does not imply that the associated device does not include any wiring, although in some embodiments it may not.

[0087] The communications member 1512 may use any number of wireless standards or protocols, including, but not limited to, Wi-Fi (IEEE 802.11 family), the IEEE 802.16 standard (e.g., the IEEE 802.16-2005 amendment), Institute of Electrical and Electronics Engineers (IEEE) standards including the Long Term Evolution (LTE) project, and any amendments, updates, and / or revisions (e.g., the Advanced LTE project, the Ultra Mobile Broadband (UMB) project (also known as "3GPP2®"), etc.). IEEE 802.16-compatible broadband wireless access (BWA) networks are commonly referred to as WiMAX networks, which is an acronym that stands for Worldwide Interoperability for Microwave Access and is a certification mark for products that have passed IEEE 802.16 standard compliance and interoperability testing. The communications member 1512 may operate in accordance with a Global System for Mobile Communications (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed ​​Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network. The communications member 1512 may operate in accordance with Enhanced Data Rates for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communications member 1512 may operate in accordance with Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution Data Optimized (EV-DO), and their derivatives, as well as any other wireless protocols designated as 3G, 4G, 5G, and beyond. In other embodiments, the communications member 1512 may operate in accordance with other wireless protocols. Electrical device 1500 may have an antenna 1522 to facilitate wireless communication and / or receive other wireless communications (such as AM or FM radio transmissions).

[0088] In some embodiments, the communication member 1512 may manage wired communications, such as electrical, optical, or any other suitable communications protocol (e.g., the IEEE 802.3 Ethernet standard). As previously mentioned, the communication member 1512 may include multiple communication members. For example, a first communication member 1512 may be dedicated to short-range wireless communications, such as Wi-Fi or Bluetooth, and a second communication member 1512 may be dedicated to Global Positioning System (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, or other long-range wireless communications. In some embodiments, the first communication member 1512 may be dedicated to wireless communications and the second communication member 1512 may be dedicated to wired communications.

[0089] Electrical device 1500 may have battery / power circuitry 1514. Battery / power circuitry 1514 may include one or more energy storage devices (e.g., batteries or capacitors) and / or circuitry that couples components of electrical device 1500 to an energy source separate from electrical device 1500 (e.g., AC line power).

[0090] Electrical device 1500 may include a display device 1506 (or corresponding interface circuitry as described above), which may include one or more embedded or wired or wirelessly connected external visual indicators, such as a heads-up display, a computer monitor, a projector, a touchscreen display, a liquid crystal display (LCD), a light-emitting diode display, or a flat panel display.

[0091] The electrical device 1500 may include an audio output device 1508 (or corresponding interface circuitry as described above), which may include any built-in device that generates an audible indicator, such as a speaker, headset, or earphones, or a wired or wirelessly connected external device.

[0092] The electrical device 1500 may have an audio input device 1524 (or corresponding interface circuitry as described above). The audio input device 1524 may include any built-in device, or wired or wirelessly connected device, that generates signals representing sound, such as a microphone, a microphone array, or a digital instrument (e.g., an instrument with a Musical Instrument Digital Interface (MIDI) output). The electrical device 1500 may have a global navigation satellite system (GNSS) device 1518 (or corresponding interface circuitry as described above), such as a global positioning system (GPS) device. The GNSS device 1518 may communicate with a satellite-based system and may determine the geolocation of the electrical device 1500 based on information received from one or more GNSS satellites, as is known in the art.

[0093] The electrical device 1500 may also have other output devices 1510 (or corresponding interface circuitry as described above). Examples of other output devices 1510 include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or additional storage devices.

[0094] The electrical device 1500 may have other input devices 1520 (or corresponding interface circuitry as described above). Examples of other input devices 1520 may include an accelerometer, a gyroscope, a compass, an image capture device (e.g., a monoscopic or stereoscopic camera), a trackball, a trackpad, a touchpad, a keyboard, a cursor control device such as a mouse, a stylus, a touchscreen, a proximity sensor, a microphone, a barcode reader, a quick response (QR) code reader, an electrocardiogram (ECG) sensor, a PPG (photoplethysmogram) sensor, a galvanic skin response sensor, any other sensor, or a radio frequency identification (RFID) reader.

[0095] Electrical device 1500 may have any desired form factor, such as a handheld or mobile electrical device (e.g., a cell phone, a smartphone, a mobile Internet device, a music player, a tablet computer, a laptop computer, a 2-in-1 convertible computer, a portable all-in-one computer, a netbook computer, an ultrabook computer, a personal digital assistant (PDA), an ultra-mobile personal computer, a portable game console, etc.), a desktop electrical device, a server, a rack-level computing solution (e.g., a blade, tray, or sled computing system), a workstation or other networked computing component, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a stationary gaming console, a smart television, a vehicle control unit, a digital camera, a digital video recorder, a wearable electrical device, or an embedded computing system (e.g., a computing system that is part of a vehicle, a smart appliance, a consumer electronic product or device, or manufacturing equipment). In some embodiments, electrical device 1500 may be any other electronic device that processes data. In some embodiments, electrical device 1500 may have multiple separate physical components. Given the range of devices that electrical device 1500 may refer to in various embodiments, in some embodiments electrical device 1500 may be referred to as a computing device or a computing system.

[0096] While at least one embodiment has been presented in the foregoing detailed description, it should be understood that numerous variations exist. It should also be understood that the disclosed embodiment is merely exemplary and is in no way intended to limit the scope, applicability, or configuration of the present disclosure. Rather, the foregoing detailed description is intended to provide those skilled in the art with a convenient road map for implementing the disclosed embodiments. Various changes can be made in the function and arrangement of elements without departing from the scope of the present disclosure, as set forth in the appended claims and their legal equivalents.

[0097] As used herein, the term "electronic component" may refer to active electronic circuits (eg, processing units, memories, storage devices, FETs) or passive electronic circuits (eg, resistors, inductors, capacitors).

[0098] As used herein, the term "integrated circuit component" may refer to an electronic component configured on semiconductor material to perform a function. An integrated circuit (IC) component may include one or more of any computing system components described and referenced herein, or any other computing system component, such as a processor unit (e.g., a system-on-chip (SoC), a processor core, a graphics processor unit (GPU), an accelerator, a chipset processor), an I / O controller, a memory, or a network interface controller, and may include one or more additional active or passive devices, such as capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices.

[0099] A non-limiting example of an unmounted integrated circuit component includes a single monolithic integrated circuit die, which may have solder bumps attached to contacts on the die. If present on the die, the solder bumps or other conductive contacts allow the die to be directly attached to a printed circuit board (PCB) or other substrate.

[0100] A non-limiting example of a packaged integrated circuit component includes one or more integrated circuit dies mounted on a mounting substrate, with the integrated circuit dies and mounting substrate encapsulated in a casing material such as metal, plastic, glass, or ceramic. The casing often includes an integrated heat spreader (IHS), and the packaged integrated circuit component often has bumps, leads, or pins attached to the mounting substrate (either directly or by wires attaching the bumps, leads, or pins to the mounting substrate), with the packaged integrated circuit component being mounted to a printed circuit board (or motherboard or baseboard) or another component.

[0101] As used herein, phrases such as "embodiments," "various embodiments," and "some embodiments" indicate that some embodiments may have some, all, or none of the features described for other embodiments. Terms such as "first," "second," and "third" describe a common subject and indicate different instances of the same subject being referred to. Unless otherwise specified, they do not imply a given order in time or space, in rank, or in any other manner. In patent application terminology, "connected" refers to elements in direct physical or electrical contact with each other, and "coupled" refers to elements that cooperate or interact with each other; coupled elements may or may not be in direct physical or electrical contact. Furthermore, terms such as "comprising," "including," and "having" are used interchangeably to indicate a non-exclusive inclusion.

[0102] As used in the specification and claims, the term "at least one" or a list of items joined by the term "one or more" can refer to any combination of the listed terms. For example, the phrase "at least one of A, B, or C" can mean A; B; C; A and B; A and C; B and C; or A, B, and C. Similarly, the phrase "one or more of A, B, and C" can mean A; B; C; A and B; A and C; B and C; or A, B, and C.

[0103] As used in the specification and claims, the phrase "individual" or "respective" followed by a list of items enumerated or described as having a property, characteristic, etc. means that every item in the list has the described or listed property, characteristic, etc. For example, the phrase "individual of A, B, or C has a sidewall" or "each of A, B, or C has a sidewall" means that A has a sidewall, B has a sidewall, and C has a sidewall.

[0104] Any theories of operation, scientific principles, or other theoretical descriptions presented with respect to the devices or methods of the present disclosure are provided for better understanding and are not intended to limit the scope, and the devices and methods in the appended claims are not limited to devices and methods that function in a manner described by such theories of operation.

[0105] The following examples relate to additional embodiments of the techniques disclosed herein.

[0106] (Example) Example 1 is a semiconductor assembly, a bridge member comprising a first insulating material and defined by a first surface and a second surface; a bridge member, the first surface having a plurality of first metal contacts, the plurality of first metal contacts being organized into a first region and a second region; a first die having a first top surface with a second insulating material and a plurality of second metal contacts; a second die having a second top surface with a third insulating material and a plurality of third metal contacts; and the bridge member provides at least one electrical path between a first first metal contact in the first region and a second first metal contact in the second region; the first top surface is on the first region of the first surface, the first insulating material is directly bonded to the second insulating material, and portions of the first metal contacts are directly bonded to respective second metal contacts; The second top surface is on the second region of the first surface, the first insulating material is directly bonded to the third insulating material, and other first metal contacts are directly bonded to respective third metal contacts, which is a semiconductor assembly.

[0107] Example 2 includes the semiconductor assembly of example 1, further comprising at least one contact on the second surface to provide an electrical path to the first surface.

[0108] Example 3 includes the semiconductor assembly of example 1, wherein the first die includes a processing circuit or a graphics integrated circuit and the second die includes a memory device.

[0109] Example 4 includes the semiconductor assembly of example 1, wherein the first insulating material, the second insulating material, and the third insulating material are dielectric materials.

[0110] Example 5 includes the semiconductor assembly of example 1, wherein the plurality of first metal contacts, the plurality of second metal contacts, and the plurality of third metal contacts include copper.

[0111] Example 6 includes the semiconductor assembly of example 1, wherein the plurality of first metal contacts, the plurality of second metal contacts, and the plurality of third metal contacts are hybrid junction conductive contacts.

[0112] Example 7 includes the semiconductor assembly of example 2, further including one or more solder bumps attached to the second surface.

[0113] Example 8 is the first die further comprising a first lower surface; and the second die further comprising a second lower surface; The semiconductor assembly according to Example 1 or 2 further includes a molding member overlaid on the first lower surface and the second lower surface.

[0114] Example 9 includes the semiconductor assembly of example 8, further including a layer of dielectric material between the molding member and the first lower surface and between the molding member and the second lower surface.

[0115] Example 10 includes the semiconductor assembly of example 8, further including an underfill between the first surface and the first top surface, and an underfill between the first surface and the second top surface.

[0116] Example 11 includes the semiconductor assembly of Example 8, further including a glass structure between the first die and the second die, the glass structure contacting the first surface of the bridge member.

[0117] Example 12 further includes a substrate having one or more dielectric layers, each of the dielectric layers having a redistribution layer (RDL); the substrate includes a cavity formed in an upper surface; The semiconductor assembly is attached to the substrate by the bridge member in the cavity, and the first top surface and the second top surface extend across the upper surface.

[0118] Example 13 is a substrate having one or more dielectric layers, each having a respective redistribution layer (RDL), the substrate including a cavity formed in an upper surface; a layer of solder material within the cavity; and The semiconductor assembly is a semiconductor package having the semiconductor assembly described in Example 2, wherein the semiconductor assembly is attached to the substrate with the bridge member attached to the layer of solder in the cavity via solder bumps, and the first top surface and the second top surface extend across the upper surface.

[0119] Example 14 is a semiconductor package as described in Example 13, further having an underfill material disposed between the first top surface and the first surface, between the cavity and the bridge member, and between the second top surface and the first surface.

[0120] Example 15 further includes a substrate having one or more dielectric layers, each dielectric layer having a respective redistribution layer (RDL); the substrate includes a cavity formed in an upper surface; the cavity includes a dielectric material having a metal pad; the semiconductor assembly is attached to the substrate using the bridge member, the bridge member being attached within the cavity via direct bonding of the at least one contact to a respective metal pad, and the dielectric material being directly bonded to the first insulating material at the second surface; The first top surface and the second top surface are a semiconductor package having a semiconductor assembly according to Example 2 extending across the top surface.

[0121] Example 16 further includes a substrate having one or more dielectric layers, each dielectric layer having a respective redistribution layer (RDL); the first die has a first lower surface; the second die has a second lower surface; The semiconductor assembly on the substrate having the first lower surface and the second lower surface is attached to the upper surface of the substrate via solder bumps, which is a semiconductor package having the semiconductor assembly described in Example 1.

[0122] Example 17 is the substrate having a layer of glass having a thickness ranging from 20 microns to 1.4 millimeters; the first length is in the range of 10 millimeters to 500 millimeters, the second length is in the range of 10 millimeters to 500 millimeters, and the first length is perpendicular to the second length; 17. The semiconductor package of any one of Examples 12 to 16, wherein the glass layer has a plurality of through-glass vias.

[0123] Example 18 is a package assembly comprising: a multi-die bridge assembly comprising: a processing unit die having a first top surface and a first bottom surface; a memory die having a second top surface and a second bottom surface; and a bridge member attached on a first surface to a first portion of the first top surface and to the second top surface of the memory die, the bridge member having a plurality of paths for electrical communication between the processing unit die and the memory die; a substrate having one or more dielectric layers, each having a respective redistribution layer (RDL), the substrate including a cavity formed in an upper surface; and The multi-die bridge assembly is a package assembly that is attached to the substrate such that the bridge member is within the cavity and a second portion of the first top surface and a second portion of the second top surface extend across the top surface.

[0124] Example 19 is The package assembly of Example 18 includes the bridge member attached at the first surface to the first portion of the first top surface and the first portion of the second top surface of the memory die via a hybrid bond.

[0125] Example 20 is Example 19. The package assembly of Example 18, wherein the second portion of the first top surface and the second portion of the second top surface are hybrid-bonded to the top surface.

[0126] Example 21 is Assembling a first integrated circuit (IC) die and a second IC die on a carrier using a bonding film; disposing a layer of molding material over the first IC die and the second IC die; removing the carrier; attaching a bridge member to a first portion of the first IC die and a first portion of the second IC die, thereby forming a multi-die bridge assembly; testing the multi-die bridge assembly to determine whether it passes performance metrics; when the multi-die bridge assembly passes the performance metrics, attaching a substrate to the multi-die bridge assembly, thereby forming a package assembly; The method has the following features:

[0127] Example 22 includes the method of example 21, wherein the bridge member includes any combination of one or more of silicon, an organic material, and glass.

[0128] Example 23 is the substrate has a cavity; 23. The method of any one of Examples 21 to 22, wherein attaching the substrate to the multi-die bridge assembly comprises disposing the bridge member within the cavity.

[0129] Example 24 is 24. The method according to any one of Examples 21 to 23, wherein attaching the bridge member to the first portion of the first IC and the first portion of the second IC is accomplished by hybrid bonding.

[0130] Example 25 is 24. The method of any one of Examples 21 to 23, wherein attaching the bridge member to the first portion of the first IC and the first portion of the second IC is accomplished using solder bumps.

[0131] Example 26 further comprises: 26. The method of any one of Examples 21 to 25, comprising assembling two or more package assemblies into a system package. [Explanation of symbols]

[0132] 100 Multi-die Bridge Assembly 102 Bridge member 105 Bottom surface 106, 110 Dies 107 Upper surface 108, 112 I / O structure 120-1, 120-2 Input / Output Contacts 125 Mounting means

Claims

1. 1. A semiconductor assembly comprising: a bridge member comprising a first insulating material and defined by a first surface and a second surface; a bridge member, the first surface having a plurality of first metal contacts, the plurality of first metal contacts being organized into a first region and a second region; a first die having a first top surface with a second insulating material and a plurality of second metal contacts; a second die having a second top surface with a third insulating material and a plurality of third metal contacts; and the bridge member provides at least one electrical path between a first first metal contact in the first region and a second first metal contact in the second region; the first top surface is on the first region of the first surface, the first insulating material is directly bonded to the second insulating material, and portions of the first metal contacts are directly bonded to respective second metal contacts; the second top surface is on the second region of the first surface, the first insulating material is directly bonded to the third insulating material, and other first metal contacts are directly bonded to respective third metal contacts.

2. The semiconductor assembly of claim 1 , further comprising at least one contact on the second surface to provide an electrical path to the first surface.

3. 10. The semiconductor assembly of claim 1, wherein the first die comprises a processing circuit or a graphics integrated circuit, and the second die comprises a memory device.

4. 4. The semiconductor assembly of claim 1, wherein the first insulating material, the second insulating material, and the third insulating material are dielectric materials.

5. 4. The semiconductor assembly of claim 1, wherein the plurality of first metal contacts, the plurality of second metal contacts, and the plurality of third metal contacts comprise copper.

6. The semiconductor assembly of claim 1 , wherein the plurality of first metal contacts, the plurality of second metal contacts, and the plurality of third metal contacts are hybrid junction conductive contacts.

7. The semiconductor assembly of claim 2 , further comprising one or more solder bumps attached to the second surface.

8. the first die further has a first lower surface, and the second die further has a second lower surface; 3. The semiconductor assembly according to claim 1, further comprising a molding member overlaid on the first lower surface and the second lower surface.

9. 9. The semiconductor assembly of claim 8, further comprising a layer of dielectric material between the molding member and the first lower surface and between the molding member and the second lower surface.

10. 9. The semiconductor assembly of claim 8, further comprising an underfill between the first surface and the first top surface, and an underfill between the first surface and the second top surface.

11. 10. The semiconductor assembly of claim 8, further comprising a glass structure between the first die and the second die, the glass structure in contact with the first surface of the bridge member.

12. A semiconductor package comprising the semiconductor assembly of claim 1, Further, a substrate having one or more dielectric layers, each of the dielectric layers having a respective redistribution layer (RDL); the substrate includes a cavity formed in an upper surface; The semiconductor assembly is attached to the substrate in the cavity by the bridge member, and the first top surface and the second top surface extend across the top surface.

13. A semiconductor package comprising the semiconductor assembly of claim 2, a substrate having one or more dielectric layers, each having a respective redistribution layer (RDL), the substrate including a cavity formed in an upper surface; a layer of solder material within the cavity; and the semiconductor assembly is attached to the substrate with the bridge member attached to the layer of solder in the cavity via solder bumps, and the first top surface and the second top surface extend across the top surface.

14. 14. The semiconductor package of claim 13, further comprising an underfill material disposed between the first top surface and the first surface, between the cavity and the bridge member, and between the second top surface and the first surface.

15. A semiconductor package comprising the semiconductor assembly of claim 2, Further, a substrate having one or more dielectric layers, each having a respective redistribution layer (RDL). and the substrate includes a cavity formed in an upper surface; the cavity includes a dielectric material having a metal pad; the semiconductor assembly is attached to the substrate using the bridge member, the bridge member being attached within the cavity via direct bonding of the at least one contact to a respective metal pad, and the dielectric material being directly bonded to the first insulating material at the second surface; The first top surface and the second top surface extend across the top surface of the semiconductor package.

16. A semiconductor package comprising the semiconductor assembly of claim 1, [0023] Further, a substrate having one or more dielectric layers, each dielectric layer having a respective redistribution layer (RDL); the first die has a first lower surface; the second die has a second lower surface; The semiconductor assembly on the substrate having the first bottom surface and the second bottom surface is attached to the top surface of the substrate via solder bumps.

17. the substrate having a layer of glass having a thickness ranging from 20 microns to 1.4 millimeters; 17. The semiconductor package of claim 16, wherein the layer of glass has a plurality of through-glass vias.

18. assembling a first integrated circuit (IC) die and a second IC die on a carrier using a bonding film; disposing a layer of molding material over the first IC die and the second IC die; removing the carrier; attaching a bridge member to the first IC die and the second IC die, thereby forming a multi-die bridge assembly having an electrical path between the first IC and the second IC; testing the multi-die bridge assembly to determine whether it passes performance metrics; when the multi-die bridge assembly passes the performance metrics, attaching a substrate to the multi-die bridge assembly, thereby forming a package assembly; A method comprising:

19. the substrate has a cavity; 20. The method of claim 18, wherein attaching the substrate to the multi-die bridge assembly comprises disposing the bridge member within the cavity.

20. 20. The method of claim 18, wherein attaching the bridge member to the first IC and the second IC is accomplished by hybrid bonding.

21. 20. The method of claim 18, wherein attaching the bridge member to the first IC and the second IC is accomplished using solder bumps.

22. 20. The method of claim 18, further comprising assembling two or more package assemblies into a system package.

23. 1. A package assembly comprising: a multi-die bridge assembly comprising: a processing unit die having a first upper surface and a first lower surface; a memory die having a second upper surface and a second lower surface; and a bridge member attached to the first upper surface and the second upper surface, the bridge member having a plurality of paths for electrical communication between the processing unit die and the memory die; a substrate having one or more dielectric layers, each having a respective redistribution layer (RDL), the substrate including a cavity formed in an upper surface; and the multi-die bridge assembly is attached to the substrate such that the bridge member is within the cavity and a first portion of the first top surface and a second portion of the second top surface extend across the top surface.

24. 24. The package assembly of claim 23, wherein the bridge member is attached at the first surface to the first portion of the first top surface and the first portion of the second top surface of the memory die via a hybrid bond.

25. 24. The package assembly of claim 23, wherein the second portion of the first top surface and the second portion of the second top surface are hybrid bonded to the top surface.

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