Nitride semiconductor device and nitride semiconductor package

Abstract

To provide a nitride semiconductor device that has a small bidirectional switch circuit.SOLUTION: A nitride semiconductor device 10 includes a nitride semiconductor bidirectional switch 12 including a switch gate electrode, a first switch drain electrode, and a second switch drain electrode, a nitride semiconductor transistor type diode 14 including a diode gate electrode, a diode source electrode, and a diode drain electrode electrically connected to the diode gate electrode, a resistor element 16 including a first connection pad and a second connection pad, and a gate pad 24. The switch gate electrode is electrically connected to the first connection pad and the diode drain electrode. The gate pad 24 is electrically connected to the second connection pad and the diode source electrode. The nitride semiconductor bidirectional switch 12, the nitride semiconductor transistor type diode 14, the resistor element 16, and the gate pad 24 are formed as a single chip 30.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present disclosure relates to nitride semiconductor devices and nitride semiconductor packages. [Background technology]

[0002] Currently, high electron mobility transistors (HEMTs) using nitride semiconductors such as gallium nitride (GaN) and aluminum gallium nitride (AlGaN) are being commercialized. Patent Document 1 discloses an example of a normally-off HEMT using a nitride semiconductor.

[0003] In HEMTs, a two-dimensional electron gas (2DEG) formed near the heterojunction interface between an electron transport layer (e.g., a GaN layer) and an electron supply layer (e.g., an AlGaN layer) is used as a conductive path. In recent years, bidirectional switches using this HEMT structure have been proposed. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2017-73506

[0005] [overview] It is desirable to miniaturize a bidirectional switch circuit that includes a bidirectional switch and a plurality of circuit elements connected to the bidirectional switch.

[0006] A nitride semiconductor device according to one embodiment of the present disclosure includes: a nitride semiconductor bidirectional switch including a switch gate electrode, a first switch drain electrode, and a second switch drain electrode; a nitride semiconductor transistor-type diode including a diode gate electrode, a diode source electrode, and a diode drain electrode electrically connected to the diode gate electrode; a resistive element including a first connection pad and a second connection pad; and a gate pad. The switch gate electrode is electrically connected to the first connection pad and the diode drain electrode. The gate pad is electrically connected to the second connection pad and the diode source electrode. The nitride semiconductor bidirectional switch, the nitride semiconductor transistor-type diode, the resistive element, and the gate pad are configured as a single chip.

[0007] Other features and aspects will become apparent from the following detailed description, drawings, and claims. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a circuit diagram of an exemplary nitride semiconductor device. [Figure 2] FIG. 2 is a schematic plan view of an exemplary nitride semiconductor device. [Figure 3] FIG. 3 is a schematic plan view of an exemplary nitride semiconductor bidirectional switch. [Figure 4] FIG. 4 is a schematic plan view of an exemplary nitride semiconductor bidirectional switch. [Figure 5] FIG. 5 is an enlarged view of a portion of FIG. [Figure 6] FIG. 6 is a schematic cross-sectional view of an exemplary nitride semiconductor bidirectional switch. [Figure 7] FIG. 7 is an enlarged view of a portion of FIG. [Figure 8] FIG. 8 is a schematic cross-sectional view of an exemplary nitride semiconductor transistor diode. [Figure 9] FIG. 9 is a schematic cross-sectional view of an exemplary resistive element. [Figure 10A] FIG. 10A is a schematic cross-sectional view illustrating an exemplary manufacturing process for a nitride semiconductor bidirectional switch. [Figure 10B] FIG. 10B is a schematic cross-sectional view showing a manufacturing step subsequent to the step shown in FIG. 10A. [Figure 10C] FIG. 10C is a schematic cross-sectional view showing a manufacturing step subsequent to the step shown in FIG. 10B. [Figure 10D] FIG. 10D is a schematic cross-sectional view showing a manufacturing step subsequent to the step shown in FIG. 10C. [Figure 10E] FIG. 10E is a schematic cross-sectional view showing a manufacturing step subsequent to the step shown in FIG. 10D. [Figure 10F] FIG. 10F is a schematic cross-sectional view showing a manufacturing step subsequent to the step shown in FIG. 10E. [Figure 10G] FIG. 10G is a schematic cross-sectional view showing a manufacturing step subsequent to the step shown in FIG. 10F. [Figure 11A] FIG. 11A is a schematic cross-sectional view for explaining an exemplary manufacturing process of a nitride semiconductor transistor-type diode. [Figure 11B] FIG. 11B is a schematic cross-sectional view showing a manufacturing step subsequent to the step shown in FIG. 11A. [Figure 11C] FIG. 11C is a schematic cross-sectional view showing a manufacturing step subsequent to the step shown in FIG. 11B. [Figure 11D] FIG. 11D is a schematic cross-sectional view showing a manufacturing step subsequent to the step shown in FIG. 11C. [Figure 11E] FIG. 11E is a schematic cross-sectional view showing a manufacturing step subsequent to the step shown in FIG. 11D. [Figure 11F] FIG. 11F is a schematic cross-sectional view showing a manufacturing step subsequent to the step shown in FIG. 11E. [Figure 11G] FIG. 11G is a schematic cross-sectional view showing a manufacturing step subsequent to the step shown in FIG. 11F. [Figure 12] FIG. 12 is a schematic plan view of an exemplary nitride semiconductor package. [Figure 13] FIG. 13 is a schematic plan view of a chip having a plurality of bumps arranged on its surface. [Figure 14]FIG. 14 is a schematic plan view of the chip of FIG. 13 mounted bump-side down on a circuit board.

[0009] [Detailed explanation] Hereinafter, several embodiments of nitride semiconductor devices of the present disclosure will be described with reference to the accompanying drawings. The same reference numerals refer to the same elements throughout the drawings and detailed description. The drawings may not be to scale, and the relative size, proportions, and depictions of elements in the drawings may be exaggerated for clarity, explanation, and convenience.

[0010] The following detailed description provides a comprehensive understanding of the described methods, devices, and / or systems. Modifications and equivalents of the described methods, devices, and / or systems will be apparent to those skilled in the art. Except for operations that necessarily occur in a particular order, the order of operations is illustrative and may be changed as would be apparent to one skilled in the art. Descriptions of functions and structures well known to those skilled in the art may be omitted. Example embodiments may have different forms and are not limited to the described examples.

[0011] (Overall structure of nitride semiconductor device) The overall structure of an exemplary nitride semiconductor device 10 will be described with reference to FIGS. 1 and 2. FIG. 1 is a circuit diagram of the exemplary nitride semiconductor device 10. As shown in FIG. 1, the nitride semiconductor device 10 includes a nitride semiconductor bidirectional switch 12, a nitride semiconductor transistor-type diode 14, and a resistor 16. The nitride semiconductor transistor-type diode 14 and the resistor 16 are connected in parallel. The parallel connection of the nitride semiconductor transistor-type diode 14 and the resistor 16 may be connected between a first connection terminal 18 and the nitride semiconductor bidirectional switch 12. The nitride semiconductor bidirectional switch 12 may be connected between a second connection terminal 20 and a third connection terminal 22.

[0012] 2 is a schematic plan view of an exemplary nitride semiconductor device 10. In the nitride semiconductor device 10, the nitride semiconductor bidirectional switch 12, the nitride semiconductor transistor-type diode 14, and the resistor element 16 may be formed above a common semiconductor substrate 54 (see FIG. 6, etc.). In the example of FIG. 2, the nitride semiconductor bidirectional switch 12 occupies a relatively large area excluding the lower right corner of the nitride semiconductor device 10 in plan view. The nitride semiconductor transistor-type diode 14 and the resistor element 16 are arranged in the lower right corner of the nitride semiconductor device 10.

[0013] 2 and other drawings, the Z-axis direction of the mutually orthogonal X, Y, and Z axes is a direction that intersects (e.g., is perpendicular to) the surface (see FIG. 6, etc.) of the semiconductor substrate 54. As used herein, the term "plan view" refers to a view drawn from a perspective looking down on an object from above along the Z-axis direction, unless explicitly stated otherwise.

[0014] The nitride semiconductor device 10 further includes a gate pad 24. The gate pad 24 corresponds to the first connection terminal 18 shown in FIG. 1. The gate pad 24, like the nitride semiconductor transistor-type diode 14 and the resistor element 16, is arranged in the lower right corner of the nitride semiconductor device 10. In the example of FIG. 2, the gate pad 24 and the resistor element 16 are aligned in the X-axis direction. The gate pad 24 and the nitride semiconductor transistor-type diode 14 are aligned in the Y-axis direction. The nitride semiconductor transistor-type diode 14 is arranged between the nitride semiconductor bidirectional switch 12 and the gate pad 24, and is also arranged between the nitride semiconductor bidirectional switch 12 and the resistor element 16. The resistor element 16 is arranged between the nitride semiconductor bidirectional switch 12 and the gate pad 24. The gate pad 24 can be formed of any conductive material.

[0015] The nitride semiconductor bidirectional switch 12 may include a first drain pad 26 and a second drain pad 28. The first drain pad 26 and the second drain pad 28 correspond to the second connection terminal 20 and the third connection terminal 22, respectively, shown in FIG. 1. In the example of FIG. 2, the first drain pad 26 and the second drain pad 28 are spaced apart in the Y-axis direction. The first drain pad 26 and the second drain pad 28 can be formed of any conductive material.

[0016] The nitride semiconductor bidirectional switch 12, the nitride semiconductor transistor-type diode 14, the resistor element 16, and the gate pad 24 are configured as a single chip 30. In other words, it can be said that the nitride semiconductor device 10 includes the chip 30.

[0017] Within the chip 30, the nitride semiconductor bidirectional switch 12 may have a larger area than the nitride semiconductor transistor-type diode 14. Here, the area of ​​the nitride semiconductor bidirectional switch 12 may be the area of ​​the active region of the nitride semiconductor bidirectional switch 12. Furthermore, the area of ​​the nitride semiconductor transistor-type diode 14 may be the area of ​​the active region of the nitride semiconductor transistor-type diode 14. Additionally, within the chip 30, the nitride semiconductor transistor-type diode 14 may have a larger area than the resistor element 16. Here, the area of ​​the resistor element 16 may be the area occupied by the resistor layer 80 (see FIG. 9 , etc.).

[0018] It should be understood that the layout of the nitride semiconductor device 10 shown in FIG. 2 is an example, and that different layouts may be adopted depending on the desired design of the nitride semiconductor device 10. (Nitride semiconductor bidirectional switch) Next, the nitride semiconductor bidirectional switch 12 will be described in more detail with reference to Figures 3 to 6. Figures 3 and 4 are schematic plan views of an exemplary nitride semiconductor bidirectional switch 12.

[0019] 3 , the nitride semiconductor bidirectional switch 12 may include a gate wiring 32, a first drain wiring 34, and a second drain wiring 36. The first drain wiring 34 and the second drain wiring 36 may be located below the first drain pad 26 and the second drain pad 28. An insulating layer (not shown) may be disposed between the gate wiring 32, the first drain wiring 34, and the second drain wiring 36 and the first drain pad 26 and the second drain pad 28.

[0020] As will be described later, the gate wiring 32 may be electrically connected to the nitride semiconductor transistor-type diode 14 and the resistor element 16. Furthermore, the first drain wiring 34 and the second drain wiring 36 may be electrically connected to the first drain pad 26 and the second drain pad 28, respectively.

[0021] The first drain wiring 34 may at least partially overlap the first drain pad 26 in a plan view. The first drain wiring 34 may be electrically connected to the first drain pad 26, for example, via one or more vias (not shown). The second drain wiring 36 may at least partially overlap the second drain pad 28 in a plan view. The second drain wiring 36 may be electrically connected to the second drain pad 28, for example, via one or more vias (not shown).

[0022] 3 , the nitride semiconductor bidirectional switch 12 includes a plurality of first drain wirings 34 and a plurality of second drain wirings 36. Each of the plurality of first drain wirings 34 may be arranged adjacent to at least one of the plurality of second drain wirings 36. The gate wiring 32 may extend so as to surround the plurality of first drain wirings 34 and the plurality of second drain wirings 36 in a plan view. The numbers of the first drain wirings 34 and the second drain wirings 36 can be determined appropriately depending on the desired design of the nitride semiconductor bidirectional switch 12.

[0023] 4 , the nitride semiconductor bidirectional switch 12 may include a switch gate electrode 38, a first switch drain electrode 40, and a second switch drain electrode 42. The switch gate electrode 38, the first switch drain electrode 40, and the second switch drain electrode 42 may be located below the first drain wiring 34 and the second drain wiring 36. An insulating layer (not shown) may be disposed between the switch gate electrode 38, the first switch drain electrode 40, and the second switch drain electrode 42 and the first drain wiring 34 and the second drain wiring 36.

[0024] 4, the switch gate electrode 38, the first switch drain electrode 40, and the second switch drain electrode 42 extend in the X-axis direction. In a plan view, the switch gate electrode 38 is located between the first switch drain electrode 40 and the second switch drain electrode 42. The first switch drain electrode 40, the switch gate electrode 38, and the second switch drain electrode 42, which extend in the X-axis direction, may be aligned parallel to the Y-axis direction.

[0025] The unit structure of the nitride semiconductor bidirectional switch 12 includes a first switch drain electrode 40, a switch gate electrode 38, and a second switch drain electrode 42. In the nitride semiconductor bidirectional switch 12, this unit structure may be repeatedly arranged in the Y-axis direction. In this case, the first switch drain electrode 40 or the second switch drain electrode 42 may be shared by two unit structures adjacent to each other in the Y-axis direction.

[0026] The switch gate electrode 38 included in each unit structure may be connected to a gate electrode connection portion 44 extending in the Y-axis direction at the center of the nitride semiconductor bidirectional switch 12. The gate electrode connection portion 44 may be disposed so as to overlap with the gate wiring 32 in a plan view.

[0027] The nitride semiconductor bidirectional switch 12 may further include a gate field plate 46 electrically connected to the switch gate electrode 38. The gate field plate 46 may be located between the switch gate electrode 38 and the first switch drain electrode 40 in a plan view. Additionally or alternatively, the gate field plate 46 may be located between the switch gate electrode 38 and the second switch drain electrode 42 in a plan view. In the example of FIG. 4 , the gate field plate 46 extends in the X-axis direction and is aligned parallel to the switch gate electrode 38.

[0028] 5 is an enlarged view of the region indicated by F5 in FIG. 4. The gate electrode connection portion 44 may be connected to the gate wiring 32 by at least one gate connection via 48. Therefore, the switch gate electrode 38 is electrically connected to the gate wiring 32. The first switch drain electrode 40 may be connected to the first drain wiring 34 by at least one first drain connection via 50. The second switch drain electrode 42 may be connected to the second drain wiring 36 by at least one second drain connection via 52. Note that the number and arrangement of the vias 48, 50, 52 can be determined appropriately depending on the desired design of the nitride semiconductor bidirectional switch 12 and are not limited to the example shown in the figure.

[0029] As shown in FIG. 5, the gate field plate 46 may include a first portion 46A extending between the first switch drain electrode 40 and the switch gate electrode 38 in a plan view, and a second portion 46B extending between the second switch drain electrode 42 and the switch gate electrode 38 in a plan view.

[0030] FIG. 6 is a schematic cross-sectional view of the nitride semiconductor bidirectional switch 12 taken along line F6-F6 in FIG. 5. For simplicity, FIG. 6 omits the upper wiring structure. The nitride semiconductor device 10 may include a semiconductor substrate 54 and a buffer layer 56 located on the semiconductor substrate 54. The nitride semiconductor device 10 may further include a first nitride semiconductor layer 58, a second nitride semiconductor layer 60 located on the first nitride semiconductor layer 58, and a third nitride semiconductor layer 62 located on the second nitride semiconductor layer 60. The second nitride semiconductor layer 60 has a larger bandgap than the first nitride semiconductor layer 58. The third nitride semiconductor layer 62 contains acceptor-type impurities. A portion of the first nitride semiconductor layer 58, a portion of the second nitride semiconductor layer 60, and a portion of the third nitride semiconductor layer 62 included in the nitride semiconductor bidirectional switch 12 shown in FIG. 6 may also be referred to as the electron transit layer, the electron supply layer, and the gate layer of the nitride semiconductor bidirectional switch 12, respectively.

[0031] As will be described later, the nitride semiconductor bidirectional switch 12 and the nitride semiconductor transistor-type diode 14 can share the first nitride semiconductor layer 58, the second nitride semiconductor layer 60, and the third nitride semiconductor layer 62. That is, each of the nitride semiconductor bidirectional switch 12 and the nitride semiconductor transistor-type diode 14 may include a part of the first nitride semiconductor layer 58, a part of the second nitride semiconductor layer 60, and a part of the third nitride semiconductor layer 62.

[0032] The semiconductor substrate 54 may be made of silicon (Si), silicon carbide (SiC), GaN, sapphire, or other substrate materials, and may have a thickness of, for example, 100 μm to 1500 μm.

[0033] The buffer layer 56 may include one or more nitride semiconductor layers. The buffer layer 56 may be made of any material capable of reducing warping or cracking of the nitride semiconductor device 10 due to differences in thermal expansion coefficients between the semiconductor substrate 54 and layers formed on the buffer layer 56 (e.g., the first nitride semiconductor layer 58, etc.). For example, the buffer layer 56 may include at least one of an aluminum nitride (AlN) layer, an AlGaN layer, and a graded AlGaN layer having a different aluminum (Al) composition. For example, the buffer layer 56 may be made of a single AlN layer, a single AlGaN layer, a layer having an AlGaN / GaN superlattice structure, a layer having an AlN / AlGaN superlattice structure, or a layer having an AlN / GaN superlattice structure.

[0034] In one example, the buffer layer 56 may include a first buffer layer that is an AlN layer formed on the semiconductor substrate 54, and a second buffer layer that is an AlGaN layer formed on the AlN layer. The first buffer layer may be an AlN layer having a thickness of, for example, 100 nm to 300 nm, while the second buffer layer may include multiple AlGaN layers with different compositions, each having a thickness of 100 nm to 300 nm. In order to reduce leakage current in the buffer layer 56, impurities may be introduced into a portion of the buffer layer 56 to make the buffer layer 56 semi-insulating. In this case, the impurity may be, for example, carbon (C) or iron (Fe), and the impurity concentration may be, for example, 4×10 16 cm -3 It can be more than that.

[0035] The first nitride semiconductor layer 58 may be located on the buffer layer 56. In this embodiment, the first nitride semiconductor layer 58 may be a GaN layer. The thickness of the first nitride semiconductor layer 58 may be, for example, 0.5 μm or more and 2 μm or less. In order to reduce leakage current in the first nitride semiconductor layer 58, impurities may be introduced into a part of the first nitride semiconductor layer 58 to make the first nitride semiconductor layer 58 semi-insulating except for the surface region thereof. In this case, the impurity may be, for example, C. The impurity concentration in the first nitride semiconductor layer 58 may be, for example, 4×1016 cm -3 can be set as above.

[0036] That is, the first nitride semiconductor layer 58 can include a plurality of GaN layers having different impurity concentrations, for example, a C-doped GaN layer and an undoped GaN layer. In this case, the C-doped GaN layer may be in contact with the buffer layer 56. The C-doped GaN layer can have a thickness of 0.3 μm or more and 2 μm or less. The C concentration in the C-doped GaN layer is 5×10 17 cm -3 or more and 9×10 19 cm -3 or less. The undoped GaN layer is formed on the C-doped GaN layer and can have a thickness of 0.05 μm or more and 0.4 μm or less. The undoped GaN layer may be in contact with the second nitride semiconductor layer 60. In one example, the first nitride semiconductor layer 58 may include a C-doped GaN layer with a thickness of 0.4 μm and an undoped GaN layer with a thickness of 0.4 μm. Also, the C concentration in the C-doped GaN layer can be about 2×10 19 cm -3 or so.

[0037] The second nitride semiconductor layer 60 has a larger bandgap than the first nitride semiconductor layer 58. In the present embodiment, the second nitride semiconductor layer 60 may be an AlGaN layer. In one example, the second nitride semiconductor layer 60 is composed of Al x Ga 1-x N, where 0.1 < x < 0.4, and more preferably, 0.1 < x < 0.3. The second nitride semiconductor layer 60 can have a thickness of 5 nm or more and 20 nm or less. In one example, the second nitride semiconductor layer 60 can have a thickness of 8 nm or more.

[0038] The first nitride semiconductor layer 58 (e.g., a GaN layer) and the second nitride semiconductor layer 60 (e.g., an AlGaN layer) have different lattice constants. Therefore, the first nitride semiconductor layer 58 and the second nitride semiconductor layer 60 form a lattice-mismatched heterojunction. Due to spontaneous polarization of the first nitride semiconductor layer 58 and the second nitride semiconductor layer 60 and piezoelectric polarization caused by crystal distortion near the heterojunction interface, the energy level of the conduction band of the first nitride semiconductor layer 58 near the heterojunction interface is lower than the Fermi level. As a result, a 2DEG 64 extends within the first nitride semiconductor layer 58 at a position close to the heterojunction interface between the first nitride semiconductor layer 58 and the second nitride semiconductor layer 60 (e.g., within a range of about several nanometers from the interface). The 2DEG 64 within the first nitride semiconductor layer 58 functions as a channel of the nitride semiconductor bidirectional switch 12. The sheet carrier density of the 2DEG 64 formed in the first nitride semiconductor layer 58 can be increased by increasing at least one of the Al composition and the thickness of the second nitride semiconductor layer 60.

[0039] The third nitride semiconductor layer 62 contains acceptor-type impurities. In this embodiment, the third nitride semiconductor layer 62 may be a GaN layer (p-type GaN layer) doped with acceptor-type impurities. The acceptor-type impurities may include at least one of zinc (Zn), magnesium (Mg), and carbon (C). The maximum concentration of the acceptor-type impurities in the third nitride semiconductor layer 62 is 7×10 18 cm -3 More than 1×10 20 cm -3 The third nitride semiconductor layer 62 may have a thickness of 50 nm or more and 120 nm or less.

[0040] As shown in FIGS. 5 and 6 , the switch gate electrode 38 is located on the third nitride semiconductor layer 62. The switch gate electrode 38 may be composed of one or more metal layers. In one example, the switch gate electrode 38 may be composed of titanium nitride (TiN). In another example, the switch gate electrode 38 may include a titanium (Ti) layer and a TiN layer provided on the Ti layer. The switch gate electrode 38 can form a Schottky junction with the third nitride semiconductor layer 62. The thickness of the switch gate electrode 38 may be, for example, not less than 50 nm and not more than 200 nm.

[0041] The nitride semiconductor device 10 may include a first passivation layer 66 and a second passivation layer 68 located on the first passivation layer 66. The first passivation layer 66 may cover the second nitride semiconductor layer 60, the third nitride semiconductor layer 62, and the switch gate electrode 38. The gate field plate 46 may be located on the first passivation layer 66 and covered by the second passivation layer 68.

[0042] The first passivation layer 66 has a first opening 66A and a second opening 66B that expose the second nitride semiconductor layer 60. In the example of FIG. 6, the first opening 66A and the second opening 66B are spaced apart in the Y-axis direction. The switch gate electrode 38 and the third nitride semiconductor layer 62 are located between the first opening 66A and the second opening 66B in the Y-axis direction. The second passivation layer 68 may have a first opening 68A and a second opening 68B that communicate with the first opening 66A and the second opening 66B of the first passivation layer 66, respectively.

[0043] The first passivation layer 66 and the second passivation layer 68 may be formed of, for example, at least one of silicon nitride (SiN), silicon dioxide (SiO), silicon oxynitride (SiON), aluminum oxide (AlO), AlN, and aluminum oxynitride (AlON). The first passivation layer 66 and the second passivation layer 68 may be made of the same material or different materials.

[0044] The first switch drain electrode 40 and the second switch drain electrode 42 are spaced apart in the Y-axis direction in a plan view. The first switch drain electrode 40 and the second switch drain electrode 42 are in contact with the second nitride semiconductor layer 60. The third nitride semiconductor layer 62 is located on the second nitride semiconductor layer 60 between the first switch drain electrode 40 and the second switch drain electrode 42.

[0045] At least a portion of the first switch drain electrode 40 may be filled in the first opening 66A and the first opening 68A. The first switch drain electrode 40 is in contact with the second nitride semiconductor layer 60 via the first opening 66A and the first opening 68A. Furthermore, at least a portion of the second switch drain electrode 42 may be filled in the second opening 66B and the second opening 68B. The second switch drain electrode 42 is in contact with the second nitride semiconductor layer 60 via the second opening 66B and the second opening 68B.

[0046] The first switch drain electrode 40 can make ohmic contact with the 2DEG 64 immediately below the second nitride semiconductor layer 60 in contact with the first switch drain electrode 40. Similarly, the second switch drain electrode 42 can make ohmic contact with the 2DEG 64 immediately below the second nitride semiconductor layer 60 in contact with the second switch drain electrode 42.

[0047] In another example, the second nitride semiconductor layer 60 may have openings (not shown) that communicate with the first opening 66A and the second opening 66B of the first passivation layer 66, respectively. The openings can expose the first nitride semiconductor layer 58. As a result, the first switch drain electrode 40 and the second switch drain electrode 42 can be in contact with the second nitride semiconductor layer 60 in the openings and also with the first nitride semiconductor layer 58 exposed by the openings.

[0048] The distance D1 between the first switch drain electrode 40 and the switch gate electrode 38 in the Y-axis direction may be equal to the distance D2 between the second switch drain electrode 42 and the switch gate electrode 38 in the Y-axis direction. Here, the distance D1 between the first switch drain electrode 40 and the switch gate electrode 38 may be the distance between the first switch drain electrode 40 filled in the first opening 66A (or the first opening 68A) and the switch gate electrode 38. Similarly, the distance D2 between the second switch drain electrode 42 and the switch gate electrode 38 may be the distance between the second switch drain electrode 42 filled in the second opening 66B (or the second opening 68B) and the switch gate electrode 38. In the present disclosure, two distances or dimensions being equal means that they are within a range of manufacturing variation (for example, ±20%).

[0049] The first switch drain electrode 40 and the second switch drain electrode 42 may be formed of one or more metal layers (eg, any combination of Ti, TiN, Al, AlSiCu, and / or AlCu layers, etc.).

[0050] When a voltage exceeding the gate threshold voltage is applied to the switch gate electrode 38 of the nitride semiconductor bidirectional switch 12, a channel is formed by the 2DEG 64 in the first nitride semiconductor layer 58. As a result, a current can flow between the first switch drain electrode 40 and the second switch drain electrode 42. Depending on the potentials of the first switch drain electrode 40 and the second switch drain electrode 42, the current can flow in a direction from the first switch drain electrode 40 to the second switch drain electrode 42 or in a direction from the second switch drain electrode 42 to the first switch drain electrode 40.

[0051] On the other hand, in a state where a voltage lower than the gate threshold voltage is applied to the switch gate electrode 38 (including a case where no voltage is applied to the switch gate electrode 38), the 2DEG 64 is not formed in at least a part of the region of the first nitride semiconductor layer 58 located below the third nitride semiconductor layer 62. This is because the third nitride semiconductor layer 62 contains acceptor-type impurities, which raises the energy levels of the first nitride semiconductor layer 58 and the second nitride semiconductor layer 60, resulting in depletion of the 2DEG 64. This achieves a normally-off operation of the nitride semiconductor bidirectional switch 12.

[0052] (Nitride semiconductor transistor diodes and resistor elements) Next, the nitride semiconductor transistor-type diode 14 and the resistor element 16 will be further described with reference to Figures 7 to 9. Figure 7 is an enlarged view of a portion of Figure 2, showing the lower right corner of the chip 30 of the nitride semiconductor device 10.

[0053] 7, the nitride semiconductor transistor-type diode 14 includes a diode gate electrode 70, a diode source electrode 72, and a diode drain electrode 74. The diode drain electrode 74 is electrically connected to the diode gate electrode 70. The diode source electrode 72 is electrically connected to the gate pad 24. The diode drain electrode 74 is electrically connected to the gate wiring 32 of the nitride semiconductor bidirectional switch 12. Therefore, the switch gate electrode 38 of the nitride semiconductor bidirectional switch 12 is electrically connected to the diode drain electrode 74.

[0054] The resistive element 16 includes a first connection pad 76 and a second connection pad 78. The first connection pad 76 is electrically connected to the gate wiring 32 of the nitride semiconductor bidirectional switch 12. Therefore, the switch gate electrode 38 of the nitride semiconductor bidirectional switch 12 is electrically connected to the first connection pad 76. The second connection pad 78 is electrically connected to the gate pad 24. The resistive element 16 may include a resistive layer 80.

[0055] Within the chip 30, the gate pad 24 may be adjacent to the diode source electrode 72 and the second connection pad 78. More specifically, the gate pad 24 may be adjacent to the diode source electrode 72 in the Y-axis direction and adjacent to the second connection pad 78 in the X-axis direction.

[0056] FIG. 8 is a schematic cross-sectional view of an exemplary nitride semiconductor transistor-type diode 14 taken along line F8-F8 in FIG. 7 . For simplicity, FIG. 8 omits the upper-layer wiring structure. As described above, the nitride semiconductor bidirectional switch 12 and the nitride semiconductor transistor-type diode 14 can share the first nitride semiconductor layer 58, the second nitride semiconductor layer 60, and the third nitride semiconductor layer 62. Thus, as shown in FIG. 8 , the nitride semiconductor transistor-type diode 14 may include a portion of the first nitride semiconductor layer 58, a portion of the second nitride semiconductor layer 60, and a portion of the third nitride semiconductor layer 62, similar to the nitride semiconductor bidirectional switch 12. The portion of the first nitride semiconductor layer 58, a portion of the second nitride semiconductor layer 60, and a portion of the third nitride semiconductor layer 62 included in the nitride semiconductor transistor-type diode 14 shown in FIG. 8 can also be referred to as the electron transit layer, the electron supply layer, and the gate layer, respectively, of the nitride semiconductor transistor-type diode 14.

[0057] The nitride semiconductor transistor diode 14 may include a first electrode 82 electrically connected to the diode gate electrode 70, a second electrode 84 electrically connected to the diode source electrode 72, and a third electrode 86 electrically connected to the diode drain electrode 74. The diode drain electrode 74 is electrically connected to the diode gate electrode 70, and therefore the third electrode 86 is electrically connected to the first electrode 82.

[0058] 8, the first electrode 82 is located on the third nitride semiconductor layer 62. The first electrode 82 is located between the second electrode 84 and the third electrode 86 in a plan view.

[0059] The first electrode 82 may be made of the same material as the switch gate electrode 38. The first electrode 82 can form a Schottky junction with the third nitride semiconductor layer 62. The thickness of the first electrode 82 may be equal to the thickness of the switch gate electrode 38.

[0060] The first passivation layer 66 has a third opening 66C and a fourth opening 66D that expose the second nitride semiconductor layer 60. In the example of Fig. 8, the third opening 66C and the fourth opening 66D are spaced apart in the Y-axis direction. The first electrode 82 and the third nitride semiconductor layer 62 are located between the third opening 66C and the fourth opening 66D in the Y-axis direction. The second passivation layer 68 may have a third opening 68C and a fourth opening 68D that communicate with the third opening 66C and the fourth opening 66D of the first passivation layer 66, respectively.

[0061] The second electrode 84 and the third electrode 86 are spaced apart in the Y-axis direction in a plan view. The second electrode 84 and the third electrode 86 are in contact with the second nitride semiconductor layer 60. The third nitride semiconductor layer 62 is located on the second nitride semiconductor layer 60 between the second electrode 84 and the third electrode 86.

[0062] At least a portion of the second electrode 84 may be filled in the third openings 66C and 68C. The second electrode 84 is in contact with the second nitride semiconductor layer 60 via the third openings 66C and 68C. Furthermore, at least a portion of the third electrode 86 may be filled in the fourth openings 66D and 68D. The third electrode 86 is in contact with the second nitride semiconductor layer 60 via the fourth openings 66D and 68D.

[0063] The second electrode 84 can make ohmic contact with the 2DEG 64 immediately below the second nitride semiconductor layer 60 in contact with the second electrode 84. Similarly, the third electrode 86 can make ohmic contact with the 2DEG 64 immediately below the second nitride semiconductor layer 60 in contact with the third electrode 86.

[0064] In another example, the second nitride semiconductor layer 60 may have openings (not shown) that communicate with the third opening 66C and the fourth opening 66D of the first passivation layer 66, respectively. The openings can expose the first nitride semiconductor layer 58. As a result, the second electrode 84 and the third electrode 86 can be in contact with the second nitride semiconductor layer 60 in the openings and also with the first nitride semiconductor layer 58 exposed by the openings.

[0065] The distance D4 between the first electrode 82 and the third electrode 86 in the Y-axis direction may be greater than the distance D3 between the first electrode 82 and the second electrode 84 in the Y-axis direction. Here, the distance D3 between the first electrode 82 and the second electrode 84 may be the distance between the first electrode 82 and the second electrode 84 filled in the third opening 66C (or the third opening 68C). Similarly, the distance D4 between the first electrode 82 and the third electrode 86 may be the distance between the first electrode 82 and the third electrode 86 filled in the fourth opening 66D (or the fourth opening 68D).

[0066] The second electrode 84 and the third electrode 86 may be made of the same material as the first switch drain electrode 40 and the second switch drain electrode 42 . The nitride semiconductor transistor-type diode 14 may include a source field plate 88 electrically connected to the diode source electrode 72. The source field plate 88 may be located on the first passivation layer 66 and covered by the second passivation layer 68. The source field plate 88 may be made of the same material as the gate field plate 46 of the nitride semiconductor bidirectional switch 12. The source field plate 88 may extend between the first electrode 82 and the third electrode 86 in a plan view.

[0067] FIG. 9 is a schematic cross-sectional view of an exemplary resistor element 16 taken along line F9-F9 in FIG. 7. For simplicity, FIG. 9 omits the upper wiring structure. As shown in FIG. 9 , a third passivation layer 90 is formed on the first nitride semiconductor layer 58. A resistive layer 80 of the resistor element 16 is located on the third passivation layer 90. The resistive layer 80 may be formed of polysilicon. A fourth passivation layer 92 is located on the third passivation layer 90 and covers the resistive layer 80. The resistive layer 80 extends between a first terminal electrode 94 and a second terminal electrode 96. Each of the first terminal electrode 94 and the second terminal electrode 96 may be located on the fourth passivation layer 92 and extend through the fourth passivation layer 92 to the third passivation layer 90. The resistive layer 80 can extend between the first terminal electrode 94 and the second terminal electrode 96 along a path of any shape (e.g., a straight path, a serpentine path, etc.) depending on the desired resistance value. The first terminal electrode 94 can be electrically connected to the first connection pad 76 shown in FIG. 7. The second terminal electrode 96 can be electrically connected to the second connection pad 78 shown in FIG. 7.

[0068] (Manufacturing method) Next, an example of a method for manufacturing the nitride semiconductor device 10 will be described with reference to Figures 10A to 10G and Figures 11A to 11G. Figures 10A to 10G correspond to a method for manufacturing the nitride semiconductor bidirectional switch 12. Figures 11A to 11G correspond to a method for manufacturing the nitride semiconductor transistor-type diode 14. For ease of understanding, in Figures 10A to 10G and Figures 11A to 11G, components similar to those in Figures 6 and 8 are denoted by the same reference numerals.

[0069] The method for manufacturing the nitride semiconductor device 10 includes forming a first nitride semiconductor layer 58 above a semiconductor substrate 54, forming a second nitride semiconductor layer 60 having a band gap larger than that of the first nitride semiconductor layer 58 on the first nitride semiconductor layer 58, and forming a third nitride semiconductor layer 62 containing acceptor-type impurities on the second nitride semiconductor layer 60.

[0070] The method for manufacturing the nitride semiconductor device 10 further includes forming the nitride semiconductor bidirectional switch 12. The nitride semiconductor bidirectional switch 12 includes a switch gate electrode 38, a first switch drain electrode 40, and a second switch drain electrode 42.

[0071] The method for manufacturing the nitride semiconductor device 10 further includes forming a nitride semiconductor transistor-type diode 14. The nitride semiconductor transistor-type diode 14 includes a diode gate electrode 70, a diode source electrode 72, and a diode drain electrode 74 electrically connected to the diode gate electrode 70.

[0072] The method for manufacturing the nitride semiconductor device 10 further includes forming a resistive element 16 including a first connection pad 76 and a second connection pad 78, and forming a gate pad 24 electrically connected to the second connection pad 78 and the diode source electrode 72. The switch gate electrode 38 is electrically connected to the first connection pad 76 and the diode drain electrode 74.

[0073] Each of the nitride semiconductor bidirectional switch 12 and the nitride semiconductor transistor-type diode 14 includes a part of the first nitride semiconductor layer 58, a part of the second nitride semiconductor layer 60, and a part of the third nitride semiconductor layer 62. The nitride semiconductor bidirectional switch 12, the nitride semiconductor transistor-type diode 14, the resistor element 16, and the gate pad 24 are configured as a single chip.

[0074] 10A is a schematic cross-sectional view illustrating an exemplary manufacturing process for the nitride semiconductor bidirectional switch 12. As shown in FIG. 10A, a buffer layer 56, a first nitride semiconductor layer 58, a second nitride semiconductor layer 60, a third nitride semiconductor layer 62, and a first metal layer 102 are sequentially stacked on a semiconductor substrate 54, which is, for example, a Si substrate. The buffer layer 56, the first nitride semiconductor layer 58, the second nitride semiconductor layer 60, and the third nitride semiconductor layer 62 can be epitaxially grown on the semiconductor substrate 54 by using a metal organic chemical vapor deposition (MOCVD) method.

[0075] Although detailed illustration is omitted, in one example, the buffer layer 56 may be a multi-layer buffer layer. The multi-layer buffer layer may include an AlN layer (first buffer layer) formed on the semiconductor substrate 54 and a graded AlGaN layer (second buffer layer) formed on the AlN layer. The graded AlGaN layer may be formed, for example, by stacking three AlGaN layers with Al compositions of 75%, 50%, and 25%, in that order from the side closest to the AlN layer.

[0076] The first nitride semiconductor layer 58 formed on the buffer layer 56 may be a GaN layer. The second nitride semiconductor layer 60 formed on the first nitride semiconductor layer 58 may be an AlGaN layer. The second nitride semiconductor layer 60 has a larger bandgap than the first nitride semiconductor layer 58.

[0077] The third nitride semiconductor layer 62 may be a GaN layer containing acceptor-type impurities. In one example, the third nitride semiconductor layer 62 containing acceptor-type impurities can be formed by doping with magnesium during growth of the third nitride semiconductor layer 62. The amount of magnesium doped into the third nitride semiconductor layer 62 can be adjusted by controlling, for example, the flow rate of a doping gas (e.g., biscyclopentadienyl magnesium (CpMg)) introduced into the growth chamber, the growth temperature, etc. In one example, the third nitride semiconductor layer 62 is formed by doping with magnesium at a concentration of 1×10 18 cm -3More than 1×10 20 cm -3 It may contain magnesium as an impurity at a concentration of less than 10 ...

[0078] The first metal layer 102 may be, for example, a TiN layer. The first metal layer 102 may be formed on the third nitride semiconductor layer 62 by, for example, a sputtering method. 10A. As shown in FIG. 10B, the first metal layer 102 and the third nitride semiconductor layer 62 shown in FIG. 10A are selectively removed. The portion of the first metal layer 102 remaining on the third nitride semiconductor layer 62 corresponds to the switch gate electrode 38. The portion of the third nitride semiconductor layer 62 remaining on the second nitride semiconductor layer 60 can be called the gate layer of the nitride semiconductor bidirectional switch 12.

[0079] 10C is a schematic cross-sectional view showing a manufacturing step subsequent to the step shown in FIG. 10B. As shown in FIG. 10C, a first passivation layer 66 is formed to cover the second nitride semiconductor layer 60, the third nitride semiconductor layer 62, and the switch gate electrode 38. Furthermore, a second metal layer 104 is formed on the first passivation layer 66. In one example, the first passivation layer 66 may include at least one of a SiN layer, a SiO layer, a SiON layer, an AlO layer, an AlN layer, and an AlON layer. Furthermore, the second metal layer 104 may include at least one of a Ti layer, a TiN layer, an Al layer, an AlSiCu layer, and an AlCu layer.

[0080] Figure 10D is a schematic cross-sectional view showing a manufacturing step subsequent to the step shown in Figure 10C. As shown in Figure 10D, the second metal layer 104 shown in Figure 10C is selectively removed. The portion of the second metal layer 104 remaining on the first passivation layer 66 corresponds to the gate field plate 46 (first portion 46A and second portion 46B).

[0081] Figure 10E is a schematic cross-sectional view showing a manufacturing step subsequent to the step shown in Figure 10D. As shown in Figure 10E, a second passivation layer 68 is formed to cover the first passivation layer 66 and the gate field plate 46. In one example, the second passivation layer 68 may include at least one of a SiN layer, a SiO layer, a SiON layer, an AlO layer, an AlN layer, and an AlON layer.

[0082] FIG. 10F is a schematic cross-sectional view showing a manufacturing step subsequent to the step shown in FIG. 10E. As shown in FIG. 10F, the first passivation layer 66 and the second passivation layer 68 are selectively removed. A first opening 68A and a second opening 68B are formed in the second passivation layer 68. The first opening 68A and the second opening 68B may be formed so that the switch gate electrode 38 is located at the center between the first opening 68A and the second opening 68B in a plan view. A first opening 66A and a second opening 66B are formed in the first passivation layer 66. The first opening 66A in the first passivation layer 66 may be formed to communicate with the first opening 68A in the second passivation layer 68. The second opening 66B in the first passivation layer 66 may be formed to communicate with the second opening 68B in the second passivation layer 68.

[0083] 10F 。 As shown in FIG. 10G , a third metal layer 106 is formed on the second passivation layer 68. The third metal layer 106 fills the first openings 66A and 68A and can be in contact with the second nitride semiconductor layer 60 through the first openings 66A and 68A. The third metal layer 106 also fills the second openings 66B and 68B and can be in contact with the second nitride semiconductor layer 60 through the second openings 66B and 68B. In one example, the third metal layer 106 may include at least one of a Ti layer, a TiN layer, an Al layer, an AlSiCu layer, and an AlCu layer.

[0084] Next, the third metal layer 106 is selectively removed to form the first switch drain electrode 40 and the second switch drain electrode 42 shown in Fig. 6. In this way, the nitride semiconductor bidirectional switch 12 shown in Fig. 6 can be obtained.

[0085] 11A is a schematic cross-sectional view illustrating an exemplary manufacturing process for the nitride semiconductor transistor-type diode 14. As shown in FIG. 11A, a buffer layer 56, a first nitride semiconductor layer 58, a second nitride semiconductor layer 60, a third nitride semiconductor layer 62, and a first metal layer 102 are sequentially stacked on a semiconductor substrate 54, such as a Si substrate. The process illustrated in FIG. 11A may be performed simultaneously with the process illustrated in FIG. 10A for the nitride semiconductor bidirectional switch 12. The nitride semiconductor bidirectional switch 12 and the nitride semiconductor transistor-type diode 14 can be formed using different portions of the buffer layer 56, the first nitride semiconductor layer 58, the second nitride semiconductor layer 60, the third nitride semiconductor layer 62, and the first metal layer 102 formed on the semiconductor substrate 54.

[0086] 11B is a schematic cross-sectional view showing a manufacturing step subsequent to the step shown in FIG. 11A. As shown in FIG. 11B, the first metal layer 102 and the third nitride semiconductor layer 62 shown in FIG. 11A are selectively removed. The portion of the first metal layer 102 remaining on the third nitride semiconductor layer 62 corresponds to the first electrode 82. The portion of the third nitride semiconductor layer 62 remaining on the second nitride semiconductor layer 60 can be referred to as the gate layer of the nitride semiconductor transistor-type diode 14. The step shown in FIG. 11B may be performed simultaneously with the step shown in FIG. 10B for the nitride semiconductor bidirectional switch 12. That is, the gate layer and the first electrode 82 of the nitride semiconductor transistor-type diode 14 may be formed simultaneously (e.g., through the same etching process) with the gate layer and the switch gate electrode 38 of the nitride semiconductor bidirectional switch 12.

[0087] 11C is a schematic cross-sectional view showing a manufacturing step subsequent to the step shown in FIG. 11B. As shown in FIG. 11C, a first passivation layer 66 is formed to cover the second nitride semiconductor layer 60, the third nitride semiconductor layer 62, and the switch gate electrode 38. Furthermore, a second metal layer 104 is formed on the first passivation layer 66. The step shown in FIG. 11C may be performed simultaneously with the step shown in FIG. 10C for the nitride semiconductor bidirectional switch 12. The nitride semiconductor bidirectional switch 12 and the nitride semiconductor transistor-type diode 14 can be formed using different portions of the first passivation layer 66 and the second metal layer 104.

[0088] 11C 。 As shown in FIG. 11D , the second metal layer 104 shown in FIG. 11C is selectively removed. The portion of the second metal layer 104 remaining on the first passivation layer 66 corresponds to the source field plate 88. The process shown in FIG. 11D may be performed simultaneously with the process shown in FIG. 10D for the nitride semiconductor bidirectional switch 12. That is, the source field plate 88 of the nitride semiconductor transistor-type diode 14 may be formed simultaneously (e.g., through the same etching process) with the gate field plate 46 of the nitride semiconductor bidirectional switch 12.

[0089] 11E is a schematic cross-sectional view showing a manufacturing step subsequent to the step shown in FIG. 11D. As shown in FIG. 11E, a second passivation layer 68 is formed to cover the first passivation layer 66 and the source field plate 88. The step shown in FIG. 11E may be performed simultaneously with the step shown in FIG. 10E for the nitride semiconductor bidirectional switch 12. The nitride semiconductor bidirectional switch 12 and the nitride semiconductor transistor-type diode 14 may be formed using different portions of the second passivation layer 68.

[0090] 11F is a schematic cross-sectional view showing a manufacturing step subsequent to the step shown in FIG. 11E. As shown in FIG. 11F, the first passivation layer 66 and the second passivation layer 68 are selectively removed. A third opening 68C and a fourth opening 68D are formed in the second passivation layer 68. The third opening 68C and the fourth opening 68D may be formed such that the first electrode 82 is located between the third opening 68C and the fourth opening 68D in a plan view. The first electrode 82 may be located closer to the third opening 68C than the fourth opening 68D. A third opening 66C and a fourth opening 66D are formed in the first passivation layer 66. The third opening 66C in the first passivation layer 66 may be formed to communicate with the third opening 68C in the second passivation layer 68. 11F may be performed simultaneously with the process for the nitride semiconductor bidirectional switch 12 shown in FIG. 10F . That is, the first opening 66A, the second opening 66B, the third opening 66C, and the fourth opening 66D of the first passivation layer 66 may be formed simultaneously (e.g., through the same etching process). Similarly, the first opening 68A, the second opening 68B, the third opening 68C, and the fourth opening 68D of the second passivation layer 68 may be formed simultaneously (e.g., through the same etching process).

[0091] 11G is a schematic cross-sectional view showing a manufacturing step subsequent to the step shown in FIG. 11F. As shown in FIG. 11G, a third metal layer 106 is formed on the second passivation layer 68. The third metal layer 106 fills the third openings 66C and 68C and can be in contact with the second nitride semiconductor layer 60 through the third openings 66C and 68C. The third metal layer 106 also fills the fourth openings 66D and 68D and can be in contact with the second nitride semiconductor layer 60 through the fourth openings 66D and 68D. The step shown in FIG. 11G may be performed simultaneously with the step shown in FIG. 10G for the nitride semiconductor bidirectional switch 12. The nitride semiconductor bidirectional switch 12 and the nitride semiconductor transistor-type diode 14 can be formed using different portions of the third metal layer 106.

[0092] Next, the third metal layer 106 is selectively removed to form the second electrode 84 and the third electrode 86 shown in Fig. 8. In this way, the nitride semiconductor transistor diode 14 shown in Fig. 8 can be obtained.

[0093] (Functions of nitride semiconductor devices) The operation of the nitride semiconductor device 10 will be described below. The nitride semiconductor device 10 includes a nitride semiconductor bidirectional switch 12, a nitride semiconductor transistor-type diode 14, a resistor 16, and a gate pad 24. The nitride semiconductor transistor-type diode 14 and the resistor 16 may be provided to operate the nitride semiconductor bidirectional switch 12 with desired performance. The nitride semiconductor device 10 corresponds to a bidirectional switch circuit including these elements within a chip 30. The switch gate electrode 38 of the nitride semiconductor bidirectional switch 12 is electrically connected to a first connection pad 76 of the resistor 16 and a diode drain electrode 74 of the nitride semiconductor transistor-type diode 14. The gate pad 24 is electrically connected to a second connection pad 78 of the resistor 16 and a diode source electrode 72 of the nitride semiconductor transistor-type diode 14.

[0094] The nitride semiconductor bidirectional switch 12 may be an element that maintains an ON state in which current flows, or an OFF state in which current is blocked. When switching the nitride semiconductor bidirectional switch 12 to the ON state, it is not necessary to turn the nitride semiconductor bidirectional switch 12 ON quickly. Therefore, in order to reduce a gate surge that may occur in the nitride semiconductor bidirectional switch 12, a resistive element 16 (having a resistance of, for example, 1 kΩ to 10 kΩ) is connected to the switch gate electrode 38 of the nitride semiconductor bidirectional switch 12. On the other hand, when switching the nitride semiconductor bidirectional switch 12 to the OFF state, it is desirable to turn the nitride semiconductor bidirectional switch 12 OFF instantly. For this purpose, a nitride semiconductor transistor-type diode 14 that can function as a speed-up diode is connected in parallel to the resistive element 16.

[0095] In the nitride semiconductor device 10 of the present disclosure, the nitride semiconductor bidirectional switch 12, the nitride semiconductor transistor-type diode 14, the resistor element 16, and the gate pad 24 are configured as a single chip 30. Therefore, the nitride semiconductor device 10 can provide a miniaturized bidirectional switch circuit.

[0096] The nitride semiconductor device 10 according to the present disclosure has the following advantages. (1) The nitride semiconductor bidirectional switch 12, the nitride semiconductor transistor-type diode 14, the resistor element 16, and the gate pad 24 are configured as a single chip 30. Therefore, the nitride semiconductor device 10 can provide a miniaturized bidirectional switch circuit.

[0097] (2) Within the chip 30, the gate pad 24 may be adjacent to the diode source electrode 72 and the second connection pad 78. With this configuration, the gate pad 24, the nitride semiconductor transistor-type diode 14, and the resistor element 16 can be efficiently arranged within the chip 30, thereby reducing the size of the chip 30.

[0098] (3) The nitride semiconductor device 10 may further include a first nitride semiconductor layer 58, a second nitride semiconductor layer 60 located on the first nitride semiconductor layer 58 and having a bandgap larger than that of the first nitride semiconductor layer 58, and a third nitride semiconductor layer 62 located on the second nitride semiconductor layer 60 and containing acceptor-type impurities. The nitride semiconductor bidirectional switch 12 and the nitride semiconductor transistor-type diode 14 may each include a part of the first nitride semiconductor layer 58, a part of the second nitride semiconductor layer 60, and a part of the third nitride semiconductor layer 62. According to this configuration, the nitride semiconductor bidirectional switch 12 and the nitride semiconductor transistor-type diode 14 can be manufactured using the same nitride semiconductor stacked structure (the first nitride semiconductor layer 58, the second nitride semiconductor layer 60, and the third nitride semiconductor layer 62). Therefore, the nitride semiconductor device 10 can be provided at a lower cost than if the nitride semiconductor bidirectional switch 12 and the nitride semiconductor transistor-type diode 14 were manufactured from different materials.

[0099] (4) The nitride semiconductor bidirectional switch 12 may include a gate field plate 46 electrically connected to the switch gate electrode 38, and the nitride semiconductor transistor-type diode 14 may include a source field plate 88 electrically connected to the diode source electrode 72. According to this configuration, the gate field plate 46 and the source field plate 88 can reduce the electric field strength in the nitride semiconductor bidirectional switch 12 and the nitride semiconductor transistor-type diode 14. As a result, the breakdown voltage of the nitride semiconductor bidirectional switch 12 and the nitride semiconductor transistor-type diode 14 can be improved.

[0100] (5) The gate field plate 46 and the source field plate 88 may be made of the same material. This configuration allows the nitride semiconductor device 10 to be provided at lower cost than when the gate field plate 46 and the source field plate 88 are made of different materials.

[0101] (6) The nitride semiconductor bidirectional switch 12 includes a gate field plate 46 electrically connected to the switch gate electrode 38, and the gate field plate 46 may include a first portion 46A extending between the first switch drain electrode 40 and the switch gate electrode 38 in a plan view, and a second portion 46B extending between the second switch drain electrode 42 and the switch gate electrode 38 in a plan view. With this configuration, the gate field plate 46 can reduce the strength of the electric field between the first switch drain electrode 40 and the switch gate electrode 38 and between the second switch drain electrode 42 and the switch gate electrode 38. As a result, the gate-drain breakdown voltage of the nitride semiconductor bidirectional switch 12 can be improved.

[0102] (7) The nitride semiconductor transistor-type diode 14 includes a source field plate 88 electrically connected to the diode source electrode 72, and the source field plate 88 may extend between the first electrode 82 and the third electrode 86 in a plan view. With this configuration, the source field plate 88 can reduce the strength of the electric field between the first electrode 82 and the third electrode 86. As a result, the gate-drain breakdown voltage of the nitride semiconductor transistor-type diode 14 can be improved.

[0103] <Packaging of nitride semiconductor devices> Next, exemplary packaging of the nitride semiconductor device 10 will be described with reference to FIGS.

[0104] 12 is a schematic plan view of an exemplary nitride semiconductor package 200. As shown in FIG. 12, the nitride semiconductor device 10 may be disposed on a support member 202. The nitride semiconductor package 200 includes the nitride semiconductor device 10, an encapsulating member 204 that encapsulates the nitride semiconductor device 10, a gate terminal 206, a first drain terminal 208, and a second drain terminal 210. The encapsulating member 204 may be made of an electrically insulating resin material.

[0105] The gate terminal 206 may be connected to the gate pad 24 via one or more gate wires 212. This electrically connects the gate terminal 206 to the gate pad 24.

[0106] The first drain terminal 208 may be connected to the first drain pad 26 via one or more first drain wires 214. The first drain pad 26 is electrically connected to the first switch drain electrode 40 via the first drain wiring 34. Thus, the first drain terminal 208 is electrically connected to the first switch drain electrode 40.

[0107] The second drain terminal 210 may be connected to the second drain pad 28 via one or more second drain wires 216. The second drain pad 28 is electrically connected to the second switch drain electrode 42 via the second drain wiring 36. Thus, the second drain terminal 210 is electrically connected to the second switch drain electrode 42.

[0108] (chip size package) Next, application of a chip size package to the nitride semiconductor device 10 will be described with reference to Figures 13 and 14. Figure 13 is a schematic plan view of a chip 30 having a plurality of bumps 302, 304, and 306 arranged on its surface. As shown in Figure 13, the nitride semiconductor device 10 may include a gate bump 302, a first plurality of drain bumps 304, and a second plurality of drain bumps 306.

[0109] The gate bump 302 is electrically connected to the gate pad 24. The gate bump 302 may be disposed so as to contact the gate pad 24. The first plurality of drain bumps 304 are electrically connected to the first switch drain electrode 40. The first plurality of drain bumps 304 may be arranged to contact the first drain pad 26. The first plurality of drain bumps 304 may be arranged at intervals on the first drain pad 26.

[0110] The second plurality of drain bumps 306 are electrically connected to the second switch drain electrode 42. The second plurality of drain bumps 306 may be arranged to contact the second drain pad 28. The second plurality of drain bumps 306 may be arranged spaced apart on the second drain pad 28.

[0111] The chip 30 may have a rectangular shape in plan view, with long sides 30A extending in a first direction (the X-axis direction in the illustrated example) and short sides 30B extending in a second direction (the Y-axis direction in the illustrated example). The first plurality of drain bumps 304 are arranged to form a first row R1 extending in the first direction. The gate bump 302 and the second plurality of drain bumps 306 are arranged to form a second row R2 extending in the first direction. The gate bump 302 may be located at one end of the second row R2. The first row R1 and the second row R2 are aligned in the second direction.

[0112] 14 is a schematic plan view of the chip 30 of FIG. 13 mounted on a circuit board with the bumps 302, 304, and 306 facing downward. The chip 30 is arranged so that the gate bump 302 contacts the gate side wiring pattern 308, the first plurality of drain bumps 304 contacts the first drain side wiring pattern 310, and the second plurality of drain bumps 306 contacts the second drain side wiring pattern 312. The nitride semiconductor device 10 including the gate bump 302, the first plurality of drain bumps 304, and the second plurality of drain bumps 306 can be mounted on a circuit board in a relatively small area.

[0113] 13, the gate bump 302 in contact with the gate side wiring pattern 308 is located at one end of the second row R2. Therefore, the gate side wiring pattern 308 can extend relatively freely without being obstructed by the first drain side wiring pattern 310 and the second drain side wiring pattern 312. Such an arrangement of the gate bump 302 can facilitate connection of the nitride semiconductor device 10 to a control circuit (not shown).

[0114] <Example of change> The above embodiment can be modified as follows. 5 and 6, the first portion 46A and the second portion 46B are provided as separate gate field plates 46, but in another example, the first portion 46A and the second portion 46B may be included in an integrated gate field plate 46. In that case, the gate field plate 46 may extend continuously from the first portion 46A to the second portion 46B on the first passivation layer 66.

[0115] In the example of FIG. 8 , the source field plate 88 extends between the first electrode 82 and the third electrode 86 in a planar view, but in another example, the source field plate 88 may include a portion on the first passivation layer 66 that covers above the first electrode 82.

[0116] One or more of the various examples described herein may be combined to the extent that they are not technically inconsistent. In this specification, "at least one of A and B" should be understood to mean "A only, or B only, or both A and B."

[0117] The term "on" as used in this disclosure can mean both "on" and "above" unless the context clearly indicates otherwise. Thus, the phrase "a first layer is formed on a second layer" is intended to mean that in some embodiments, the first layer can be placed directly on the second layer in contact with the second layer, while in other embodiments, the first layer can be placed above the second layer without contacting the second layer. In other words, the term "on" does not exclude a structure in which another layer is formed between the first and second layers.

[0118] Directional terms such as "vertical," "horizontal," "upper," "lower," "top," "bottom," "front," "rear," "longitudinal," "lateral," "left," "right," "front," and "rear" used in this disclosure depend on the particular orientation of the device being described and illustrated. Various alternative orientations are contemplated in this disclosure, and therefore these directional terms should not be construed narrowly.

[0119] For example, the Z-axis direction used in this disclosure does not necessarily have to be the vertical direction, nor does it have to completely coincide with the vertical direction. Therefore, various structures according to this disclosure (e.g., the structure shown in FIG. 2) are not limited to the "up" and "down" in the Z-axis direction described herein being "up" and "down" in the vertical direction. For example, the X-axis direction may be the vertical direction, or the Y-axis direction may be the vertical direction.

[0120] Terms such as "first," "second," and "third" in this disclosure are used merely to distinguish between objects and do not rank the objects. <Additional Notes> The technical ideas that can be understood from the present disclosure are described below. Note that, for the purpose of aiding understanding and not intending to be limiting, the components described in the appendices are given the reference numerals of the corresponding components in the embodiments. The reference numerals are shown as examples to aid understanding, and the components described in each appendix should not be limited to the components indicated by the reference numerals.

[0121] (Appendix 1) a nitride semiconductor bidirectional switch (12) including a switch gate electrode (38), a first switch drain electrode (40), and a second switch drain electrode (42); a nitride semiconductor transistor-type diode (14) including a diode gate electrode (70), a diode source electrode (72), and a diode drain electrode (74) electrically connected to the diode gate electrode (70); a resistive element (16) including a first connection pad (76) and a second connection pad (78); Gate pad (24) and Equipped with the switch gate electrode (38) is electrically connected to the first connection pad (76) and the diode drain electrode (74); the gate pad (24) is electrically connected to the second connection pad (78) and the diode source electrode (72); The nitride semiconductor bidirectional switch (12), the nitride semiconductor transistor-type diode (14), the resistor element (16), and the gate pad (24) are configured as a single chip (30).

[0122] (Appendix 2) 2. The nitride semiconductor device (10) of claim 1, wherein, within the chip (30), the gate pad (24) is adjacent to the diode source electrode (72) and the second connection pad (78).

[0123] (Appendix 3) The nitride semiconductor device (10) according to claim 1 or 2, wherein, within the chip (30), the nitride semiconductor bidirectional switch (12) has a larger area than the nitride semiconductor transistor-type diode (14).

[0124] (Appendix 4) 3. The nitride semiconductor device (10) according to claim 1 or 2, wherein, within the chip (30), the nitride semiconductor bidirectional switch (12) has a larger area than the nitride semiconductor transistor-type diode (14), and the nitride semiconductor transistor-type diode (14) has a larger area than the resistor element (16).

[0125] (Appendix 5) a first nitride semiconductor layer (58); a second nitride semiconductor layer (60) located on the first nitride semiconductor layer (58) and having a band gap larger than that of the first nitride semiconductor layer (58); a third nitride semiconductor layer (62) located on the second nitride semiconductor layer (60) and containing acceptor-type impurities; and wherein each of the nitride semiconductor bidirectional switch (12) and the nitride semiconductor transistor-type diode (14) includes a portion of the first nitride semiconductor layer (58), a portion of the second nitride semiconductor layer (60), and a portion of the third nitride semiconductor layer (62).

[0126] (Appendix 6) The nitride semiconductor bidirectional switch (12) includes a gate field plate (46) electrically connected to the switch gate electrode (38); 6. The nitride semiconductor device (10) according to claim 5, wherein the nitride semiconductor transistor-type diode (14) includes a source field plate (88) electrically connected to the diode source electrode (72).

[0127] (Appendix 7) 7. The nitride semiconductor device (10) of claim 6, wherein the gate field plate (46) and the source field plate (88) are made of the same material.

[0128] (Appendix 8) 6. The nitride semiconductor device (10) according to claim 5, wherein the switch gate electrode (38) is located on the third nitride semiconductor layer (62), and the switch gate electrode (38) is located between the first switch drain electrode (40) and the second switch drain electrode (42) in a plan view.

[0129] (Appendix 9) The nitride semiconductor bidirectional switch (12) includes a gate field plate (46) electrically connected to the switch gate electrode (38); The gate field plate (46) a first portion (46A) extending between the first switch drain electrode (40) and the switch gate electrode (38) in a plan view; a second portion (46B) extending between the second switch drain electrode (42) and the switch gate electrode (38) in a plan view; 9. The nitride semiconductor device (10) according to claim 8, comprising:

[0130] (Appendix 10) The nitride semiconductor transistor diode (14) is a first electrode (82) electrically connected to the diode gate electrode (70); a second electrode (84) electrically connected to the diode source electrode (72); a third electrode (86) electrically connected to the diode drain electrode (74); Including, The nitride semiconductor device (10) according to claim 5, wherein the first electrode (82) is located on the third nitride semiconductor layer (62) and, in a planar view, is located between the second electrode (84) and the third electrode (86).

[0131] (Appendix 11) The nitride semiconductor transistor-type diode (14) includes a source field plate (88) electrically connected to the diode source electrode (72); 11. The nitride semiconductor device (10) according to claim 10, wherein the source field plate (88) extends between the first electrode (82) and the third electrode (86) in a plan view.

[0132] (Appendix 12) a gate bump (302) electrically connected to the gate pad (24); a first plurality of drain bumps (304) electrically connected to the first switch drain electrode (40); a second plurality of drain bumps (306) electrically connected to the second switch drain electrode (42); The tip (30) is rectangular in plan view having long sides (30A) extending in a first direction and short sides (30B) extending in a second direction, The nitride semiconductor device (10) according to any one of appendices 1 to 11, wherein the first plurality of drain bumps (304) are arranged to form a first row (R1) extending in the first direction, the gate bump (302) and the second plurality of drain bumps (306) are arranged to form a second row (R2) extending in the first direction, and the first row (R1) and the second row (R2) are aligned in the second direction.

[0133] (Appendix 13) 13. The nitride semiconductor device (10) according to claim 12, wherein the gate bump (302) is located at one end of the second row (R2).

[0134] (Appendix 14) A nitride semiconductor device (10) according to any one of Supplementary Notes 1 to 11; a sealing member (204) that seals the nitride semiconductor device (10); a gate terminal (206) electrically connected to the gate pad (24); a first drain terminal (208) electrically connected to the first switch drain electrode (40); a second drain terminal (210) electrically connected to the second switch drain electrode (42); A nitride semiconductor package (200) comprising:

[0135] (Appendix 15) forming a first nitride semiconductor layer (58) over a semiconductor substrate (54); forming a second nitride semiconductor layer (60) on the first nitride semiconductor layer (58), the second nitride semiconductor layer having a band gap larger than that of the first nitride semiconductor layer (58); forming a third nitride semiconductor layer (62) containing acceptor-type impurities on the second nitride semiconductor layer (60); forming a nitride semiconductor bidirectional switch (12) including a switch gate electrode (38), a first switch drain electrode (40), and a second switch drain electrode (42); forming a nitride semiconductor transistor-type diode (14) including a diode gate electrode (70), a diode source electrode (72), and a diode drain electrode (74) electrically connected to the diode gate electrode (70); forming a resistive element (16) including a first connection pad (76) and a second connection pad (78); forming a gate pad (24) electrically connected to the second connection pad (78) and the diode source electrode (72); the switch gate electrode (38) is electrically connected to the first connection pad (76) and the diode drain electrode (74); each of the nitride semiconductor bidirectional switch (12) and the nitride semiconductor transistor-type diode (14) includes a portion of the first nitride semiconductor layer (58), a portion of the second nitride semiconductor layer (60), and a portion of the third nitride semiconductor layer (62); A method for manufacturing a nitride semiconductor device (10), wherein the nitride semiconductor bidirectional switch (12), the nitride semiconductor transistor-type diode (14), the resistor element (16), and the gate pad (24) are configured as a single chip (30).

[0136] Various changes in form and detail may be made to the above-described examples without departing from the scope of the claims and their equivalents. The above-described examples are illustrative and not limiting. The description of a feature in each example should be considered applicable to similar features or aspects in other examples. Suitable results may be achieved if the sequential events are performed in a different order and / or if components within the described systems, architectures, devices, or circuits are combined in a different manner and / or replaced or supplemented by other components or their equivalents. The scope of the present disclosure is defined not by the detailed description, but by the claims and their equivalents. All variations within the scope of the claims and their equivalents are included herein. [Explanation of symbols]

[0137] 10...Nitride semiconductor device 12...Nitride semiconductor bidirectional switch 14...Nitride semiconductor transistor diode 16...Resistance element 18...First connection terminal 20...Second connection terminal 22...Third connection terminal 24...Gate pad 26...1st drain pad 28...Second drain pad 30...tip 30A...long side 30B...short side 32...Gate wiring 34...First drain wiring 36...Second drain wiring 38...Switch gate electrode 40...First switch drain electrode 42...Second switch drain electrode 44...Gate electrode connection part 46...Gate Field Plate 46A…First part 46B…Second part 48…Gate connection via 50...First drain connection via 52...Second drain connection via 54...Semiconductor substrate 56...Buffer layer 58...First nitride semiconductor layer 60...Second nitride semiconductor layer 62...Third nitride semiconductor layer 64...Two-dimensional electron gas (2DEG) 66...First passivation layer 66A…1st opening 66B…Second opening 66C…Third opening 66D…4th opening 68...Second passivation layer 68A…1st opening 68B…Second opening 68C…Third opening 68D…4th opening 70...Diode gate electrode 72...Diode source electrode 74...Diode drain electrode 76...First connection pad 78...Second connection pad 80…Resistance layer 82...1st electrode 84…Second electrode 86…Third electrode 88...Source Field Plate 90...Third passivation layer 92...Fourth passivation layer 94...1st terminal electrode 96…Second terminal electrode 102...first metal layer 104…Second metal layer 106…Third metal layer 200...Nitride semiconductor package 202...Support member 204...Sealing member 206...Gate terminal 208...First drain terminal 210...Second drain terminal 212...Gate wire 214...First drain wire 216...Second drain wire 302...Gate bump 304...first plurality of drain bumps 306...second plurality of drain bumps 308...Gate side wiring pattern 310...First drain side wiring pattern 312...Second drain side wiring pattern R1...first column R2...second column

Claims

1. a nitride semiconductor bidirectional switch including a switch gate electrode, a first switch drain electrode, and a second switch drain electrode; a nitride semiconductor transistor-type diode including a diode gate electrode, a diode source electrode, and a diode drain electrode electrically connected to the diode gate electrode; a resistive element including a first connection pad and a second connection pad; Gate pad and Equipped with the switch gate electrode is electrically connected to the first connection pad and the diode drain electrode; the gate pad is electrically connected to the second connection pad and the diode source electrode; The nitride semiconductor device, wherein the nitride semiconductor bidirectional switch, the nitride semiconductor transistor-type diode, the resistance element, and the gate pad are configured as a single chip.

2. The nitride semiconductor device according to claim 1 , wherein, within said chip, said gate pad is adjacent to said diode source electrode and said second connection pad.

3. The nitride semiconductor device according to claim 2 , wherein said nitride semiconductor bidirectional switch has an area larger than that of said nitride semiconductor transistor-type diode within said chip.

4. 3. The nitride semiconductor device according to claim 2, wherein, within said chip, said nitride semiconductor bidirectional switch has an area larger than that of said nitride semiconductor transistor-type diode, and said nitride semiconductor transistor-type diode has an area larger than that of said resistor element.

5. a first nitride semiconductor layer; a second nitride semiconductor layer located on the first nitride semiconductor layer and having a band gap larger than that of the first nitride semiconductor layer; a third nitride semiconductor layer located on the second nitride semiconductor layer and containing an acceptor-type impurity; 5. The nitride semiconductor device according to claim 1, further comprising: a first nitride semiconductor bidirectional switch; a second nitride semiconductor layer; and a third nitride semiconductor layer.

6. the nitride semiconductor bidirectional switch includes a gate field plate electrically connected to the switch gate electrode; The nitride semiconductor device according to claim 5 , wherein said nitride semiconductor transistor-type diode includes a source field plate electrically connected to said diode source electrode.

7. The nitride semiconductor device according to claim 6 , wherein the gate field plate and the source field plate are made of the same material.

8. 6. The nitride semiconductor device according to claim 5, wherein the switch gate electrode is located on the third nitride semiconductor layer, and the switch gate electrode is located between the first switch drain electrode and the second switch drain electrode in a plan view.

9. the nitride semiconductor bidirectional switch includes a gate field plate electrically connected to the switch gate electrode; The gate field plate is a first portion extending between the first switch drain electrode and the switch gate electrode in a plan view; a second portion extending between the second switch drain electrode and the switch gate electrode in a plan view; The nitride semiconductor device according to claim 8 , comprising:

10. The nitride semiconductor transistor-type diode is a first electrode electrically connected to the diode gate electrode; a second electrode electrically connected to the diode source electrode; a third electrode electrically connected to the diode drain electrode; Including, The nitride semiconductor device according to claim 5 , wherein the first electrode is located on the third nitride semiconductor layer and is located between the second electrode and the third electrode in a plan view.

11. the nitride semiconductor transistor-type diode includes a source field plate electrically connected to the diode source electrode; The nitride semiconductor device according to claim 10 , wherein said source field plate extends between said first electrode and said third electrode in a plan view.

12. a gate bump electrically connected to the gate pad; a first plurality of drain bumps electrically connected to the first switch drain electrode; a second plurality of drain bumps electrically connected to the second switch drain electrode; the chip has a rectangular shape in plan view having long sides extending in a first direction and short sides extending in a second direction; 5. The nitride semiconductor device according to claim 1, wherein the first plurality of drain bumps are arranged to form a first row extending in the first direction, the gate bump and the second plurality of drain bumps are arranged to form a second row extending in the first direction, and the first row and the second row are aligned in the second direction.

13. The nitride semiconductor device according to claim 12 , wherein the gate bump is located at one end of the second row.

14. a nitride semiconductor device according to any one of claims 1 to 4; a sealing member that seals the nitride semiconductor device; a gate terminal electrically connected to the gate pad; a first drain terminal electrically connected to the first switch drain electrode; a second drain terminal electrically connected to the second switch drain electrode; A nitride semiconductor package comprising:

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