Wiring circuit board, electric element mount board, electronic component, and manufacturing method for wiring circuit board

Abstract

To prevent separation of an electric element from a wiring circuit board after the electric element is mounted on the wiring circuit board.SOLUTION: A conductive layer 30 including a plurality of terminal parts 31 is formed on a first insulating layer 20. A second insulating layer 40 is formed on the first insulating layer 20 so as to cover a part of the conductive layer 30. The terminal parts 31 are arranged two-dimensionally so that a predetermined arrangement pattern is repeated. The second insulating layer 40 includes a unit structure US that projects upward in accordance with each terminal part 31. Each unit structure US includes an opening part 49 overlapping a central part of the terminal part 31 when viewed in a stacking direction of a wiring circuit board 1 so that the central part of the corresponding terminal part 31 is exposed, a first annular part 41 overlapping an outer part that surrounds the central part of the corresponding terminal part 31 when viewed in the stacking direction, and a second annular part 42 that surrounds the first annular part 41 when viewed in the stacking direction and is formed to be recessed as being separated from an outer edge of the first annular part 41.SELECTED DRAWING: Figure 6

Description

[Technical Field]

[0001] The present invention relates to a printed circuit board, an electrical element mounting board, an electronic component, and a method for manufacturing a printed circuit board. [Background technology]

[0002] 2. Description of the Related Art In electronic devices, a printed circuit board is used to transmit and receive electrical signals between a plurality of electronic components, and electronic components such as semiconductor chips are mounted on the printed circuit board.

[0003] In a wired circuit board, the mounting surface for electronic components is formed of an insulating coating layer such as solder resist. For example, in a semiconductor component package (wired circuit board) described in Patent Document 1, a coating layer made of solder resist is formed on each of one side and the other side of a multilayer laminate including a core material, multiple wiring layers, and multiple insulating layers. An opening is formed in the coating layer to expose a part of the wiring layer as a terminal portion. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2001-274034 Summary of the Invention [Problem to be solved by the invention]

[0005] When mounting electronic components on a wired circuit board, terminals of the electronic components are joined to terminals of the wired circuit board exposed on the mounting surface of the wired circuit board, for example, using solder. During this mounting process, an underfill is also provided to fill gaps formed between the mounting surface of the wired circuit board and the electronic components. The underfill improves adhesion between the mounting surface of the wired circuit board and the electronic components, thereby improving the reliability of the connection between the wired circuit board and the electronic components. However, depending on the condition of the mounting surface of the wired circuit board, sufficient adhesion may not be achieved even with the use of underfill. If sufficient adhesion is not achieved between the mounting surface of the wired circuit board and the electronic components, the electronic components may peel off from the wired circuit board.

[0006] An object of the present invention is to provide a wiring circuit board capable of preventing peeling of an electrical element after the electrical element is mounted, an electrical element mounting board including the wiring circuit board, an electronic component including the wiring circuit board, and a method for manufacturing the wiring circuit board. [Means for solving the problem]

[0007] A wired circuit board according to one aspect of the present invention comprises: a first insulating layer having a first surface; a conductor layer having a plurality of terminal portions and formed on the first surface of the first insulating layer; and a second insulating layer formed on the first surface of the first insulating layer so as to cover a portion of the conductor layer, wherein the plurality of terminal portions are two-dimensionally arranged on the first surface so as to be repeatedly arranged in a predetermined arrangement pattern, and the second insulating layer includes a plurality of mounting reinforcement portions corresponding to the plurality of terminal portions and each protruding in a direction in which the first surface faces, and each of the mounting reinforcement portions includes: an opening overlapping the central portion of the terminal portion when viewed in the stacking direction of the first insulating layer and the second insulating layer so as to expose the central portion of the corresponding terminal portion; a first annular portion overlapping an outer portion surrounding the central portion of the corresponding terminal portion when viewed in the stacking direction; and a second annular portion surrounding the first annular portion when viewed in the stacking direction and formed so as to be recessed as it moves away from the outer edge of the first annular portion.

[0008] An electrical element mounting board according to another aspect of the present invention comprises the above-described wiring circuit board and an electrical element having a plurality of electrical contacts, wherein the electrical element is mounted on the wiring circuit board by connecting the plurality of electrical contacts to the plurality of terminal portions of the wiring circuit board using solder, and an underfill is filled between the electrical element and the wiring circuit board.

[0009] An electronic component according to yet another aspect of the present invention includes the above-described electric component mounting board.

[0010] A method for manufacturing a wired circuit board according to yet another aspect of the present invention includes the steps of: preparing a first insulating layer having a first surface; forming a conductor layer having a plurality of terminal portions on the first surface of the first insulating layer; and forming a second insulating layer on the first surface of the first insulating layer so as to cover a portion of the conductor layer, wherein the step of forming the conductor layer includes two-dimensionally arranging the plurality of terminal portions so as to be repeatedly arranged on the first surface in a predetermined arrangement pattern; and forming the second insulating layer includes applying a thermal paste containing a solvent to the first surface of the first insulating layer so as to cover the plurality of terminal portions. The method includes a coating step of coating a varnish made of a curable resin or a thermoplastic resin, a pressing step of preparing a pressing member having a flat pressing surface after the coating step and flattening the exposed surface of the varnish by bringing the pressing surface of the pressing member into contact with the exposed surface of the varnish, a heat treatment step of heating the varnish after the pressing step to volatilize the solvent contained in the varnish and harden the varnish, and a step of forming a plurality of openings in the hardened varnish after the heat treatment step so that the central portion of each terminal portion is exposed and the outer portions surrounding the central portion of each terminal portion are covered by the varnish.

[0011] A method for manufacturing a wired circuit board according to yet another aspect of the present invention includes the steps of: preparing a first insulating layer having a first surface; forming a conductor layer having a plurality of terminal portions on the first surface of the first insulating layer; and forming a second insulating layer on the first surface of the first insulating layer so as to cover a portion of the conductor layer, wherein the step of forming the conductor layer includes two-dimensionally arranging the plurality of terminal portions so as to be repeatedly arranged on the first surface in a predetermined arrangement pattern; and the step of forming the second insulating layer includes forming a resin made of a thermosetting resin or a thermoplastic resin in a semi-cured state on the first surface of the first insulating layer so as to cover the plurality of terminal portions. a pressing step of, after the attaching step, preparing a pressing member having a flat pressing surface and bringing the pressing surface of the pressing member into contact with the exposed surface of the sheet-like member to flatten the exposed surface of the sheet-like member; a heat treatment step of, after the pressing step, heating the sheet-like member to volatilize the solvent contained in the sheet-like member and hardening the sheet-like member; and a step of, after the heat treatment step, forming a plurality of openings in the hardened sheet-like member so that a central portion of each terminal portion is exposed and outer portions surrounding the central portion of each terminal portion are covered by the sheet-like member. [Effects of the Invention]

[0012] According to the present invention, after an electrical component is mounted on a printed circuit board, it is possible to prevent the electrical component from peeling off from the printed circuit board. [Brief explanation of the drawings]

[0013] [Figure 1] FIG. 1 is a plan view of a printed circuit board according to a first embodiment. [Figure 2] FIG. 2 is a plan view of a mounting board including the printed circuit board of FIG. [Figure 3] 3 is a side view of the mounting board of FIG. 2 as viewed from the direction of the white arrow A. FIG. [Figure 4] 2 is an enlarged plan view of a portion of the printed circuit board shown in FIG. 1 enclosed by a dotted line. [Figure 5]FIG. 5 is a cross-sectional view taken along line BB in FIG. [Figure 6] 2 is a perspective view of a portion of the printed circuit board shown in FIG. 1 enclosed by a dotted line. [Figure 7] FIG. 1 is a schematic side view showing an example of a roll-to-roll apparatus used in the manufacturing process of a printed circuit board. [Figure 8] 2 is a cross-sectional view illustrating an example of a method for manufacturing the wired circuit board of FIG. 1. FIG. [Figure 9] 2 is a cross-sectional view illustrating an example of a method for manufacturing the wired circuit board of FIG. 1. FIG. [Figure 10] 2 is a cross-sectional view illustrating an example of a method for manufacturing the wired circuit board of FIG. 1. FIG. [Figure 11] 2 is a cross-sectional view illustrating an example of a method for manufacturing the wired circuit board of FIG. 1. FIG. [Figure 12] 2 is a cross-sectional view illustrating an example of a method for manufacturing the wired circuit board of FIG. 1. FIG. [Figure 13] 2 is a cross-sectional view illustrating an example of a method for manufacturing the wired circuit board of FIG. 1. FIG. [Figure 14] 2 is a cross-sectional view illustrating an example of a method for manufacturing the wired circuit board of FIG. 1. FIG. [Figure 15] 2 is a cross-sectional view illustrating an example of a method for manufacturing the wired circuit board of FIG. 1. FIG. [Figure 16] 2 is a cross-sectional view illustrating an example of a method for manufacturing the wired circuit board of FIG. 1. FIG. [Figure 17] 2 is a cross-sectional view illustrating an example of a method for manufacturing the wired circuit board of FIG. 1. FIG. [Figure 18] 2 is a cross-sectional view illustrating an example of a method for manufacturing the wired circuit board of FIG. 1. FIG. [Figure 19] 1. FIG. 4 is a cross-sectional view illustrating another example of a method for manufacturing the wired circuit board of FIG. [Figure 20] 1. FIG. 4 is a cross-sectional view illustrating another example of a method for manufacturing the wired circuit board of FIG. [Figure 21] 1. FIG. 4 is a cross-sectional view illustrating another example of a method for manufacturing the wired circuit board of FIG. [Figure 22]FIG. 4 is a cross-sectional view of a printed circuit board according to a second embodiment. [Figure 23] 23 is a cross-sectional view illustrating an example of a method for manufacturing the wired circuit board of FIG. 22. FIG. [Figure 24] 23 is a cross-sectional view illustrating an example of a method for manufacturing the wired circuit board of FIG. 22. FIG. [Figure 25] 23 is a cross-sectional view illustrating an example of a method for manufacturing the wired circuit board of FIG. 22. FIG. [Figure 26] 23 is a cross-sectional view illustrating an example of a method for manufacturing the wired circuit board of FIG. 22. FIG. [Figure 27] 23 is a cross-sectional view illustrating an example of a method for manufacturing the wired circuit board of FIG. 22. FIG. [Figure 28] 23 is a cross-sectional view illustrating an example of a method for manufacturing the wired circuit board of FIG. 22. FIG. [Figure 29] 23 is a cross-sectional view illustrating an example of a method for manufacturing the wired circuit board of FIG. 22. FIG. [Figure 30] 23 is a cross-sectional view illustrating an example of a method for manufacturing the wired circuit board of FIG. 22. FIG. [Figure 31] FIG. 10 is a cross-sectional view of a printed circuit board according to a third embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0014] 1. First embodiment Hereinafter, a printed circuit board, an electric element mounting board, an electronic component, and a method for manufacturing a printed circuit board according to a first embodiment will be described with reference to the drawings.

[0015] <1> Overview of the configuration of wiring circuit boards, electrical element mounting boards, and electronic components Fig. 1 is a plan view of a wired circuit board according to a first embodiment. Fig. 2 is a plan view of a semiconductor chip mounting board (hereinafter referred to as a mounting board) including the wired circuit board 1 of Fig. 1. Fig. 3 is a side view of the mounting board 3 of Fig. 2 as viewed from the direction of the white arrow A.

[0016] The wired circuit board 1 according to this embodiment is formed by laminating a plurality of layers (a metal support 10, a first insulating layer 20, a conductor layer 30, and a second insulating layer 40, which are shown in FIG. 5 and described later). As shown in FIG. 1, the upper surface of the wired circuit board 1 is mostly formed by the second insulating layer 40. A plurality of openings 49 (25 in this example) are formed in the second insulating layer 40. A terminal portion 31 is provided at the bottom of each of the plurality of openings 49 so as to be exposed above the wired circuit board 1 through the opening 49.

[0017] In a plan view, the plurality of terminal portions 31 (25 in this example) provided on the wired circuit board 1 are two-dimensionally arranged so that a predetermined arrangement pattern is repeatedly arranged. More specifically, in the example of Fig. 1, the plurality of terminal portions 31 are arranged at equal intervals in a matrix shape in a plan view of the wired circuit board 1.

[0018] As shown in Fig. 2, a plurality of (four in this example) semiconductor chips 2 are mounted on the upper surface of the wired circuit board 1 in Fig. 1. A mounting board 3 is fabricated by mounting a predetermined number of semiconductor chips 2 on the wired circuit board 1. As shown by the dashed dotted lines in Figs. 2 and 3, the fabricated mounting board 3 is incorporated into an electronic component 4 such as a mobile terminal.

[0019] Each semiconductor chip 2 has a mounting surface that faces the wired circuit board 1 when it is incorporated into the mounting substrate 3. On the mounting surface, a plurality of terminal portions are formed that correspond to any of the plurality of terminal portions 31 of the wired circuit board 1. In the following description, each terminal portion of the semiconductor chip 2 is referred to as a chip terminal portion.

[0020] When mounting multiple semiconductor chips 2 on the wiring circuit board 1, each semiconductor chip 2 is positioned so that each of the multiple chip terminal portions faces a corresponding terminal portion 31 of the wiring circuit board 1. Furthermore, each chip terminal portion of the semiconductor chip 2 is connected to the corresponding terminal portion 31 of the wiring circuit board 1 using solder 5. At this time, a gap is generated between the upper surface of the wiring circuit board 1 and each semiconductor chip 2. An underfill 6 is filled into this gap.

[0021] In the wired circuit board 1 according to the present embodiment, in the mounting substrate 3 fabricated as described above, the shape of the upper surface of the wired circuit board 1 is devised to improve the adhesive strength between the upper surface of the wired circuit board 1 and the semiconductor chip 2. The configuration of the wired circuit board 1 will be described in detail below.

[0022] <2> Configuration of the wiring circuit board 1 The wired circuit board 1 of FIG. 1 has a rectangular shape in a plan view. In the following description, a direction parallel to one of the four sides of the wired circuit board 1 of FIG. 1 that extends in the horizontal direction (left-right direction on the paper) is referred to as a first direction D1. Furthermore, a direction parallel to another of the four sides of the wired circuit board 1 of FIG. 1 that extends in the vertical direction (up-down direction on the paper) is referred to as a second direction D2. The first direction D1 and the second direction D2 are orthogonal to each other within a single plane. Furthermore, a direction orthogonal to the first direction D1 and the second direction D2 (a direction intersecting the paper) is referred to as a third direction D3. The third direction D3 is the stacking direction of the metal support 10, the first insulating layer 20, the conductor layer 30, and the second insulating layer 40 in FIG. 5 (described later). In certain drawings described below, the first direction D1, the second direction D2, and the third direction D3 are indicated by arrows as appropriate.

[0023] Fig. 4 is an enlarged plan view of a portion enclosed by a dotted line in the wired circuit board 1 of Fig. 1. Fig. 5 is a cross-sectional view taken along line BB in Fig. 4. Fig. 6 is a perspective view of a portion enclosed by a dotted line in the wired circuit board 1 of Fig. 1.

[0024] Fig. 4 shows a plan view of a portion of the wired circuit board 1 including nine terminal portions 31, as the portion enclosed by the dotted line in Fig. 1. In the plan view of Fig. 4, the nine terminal portions 31 are arranged at equal intervals in a matrix of three rows and three columns.

[0025] First, the configuration of the wired circuit board 1 will be described based on the cross-sectional view of Fig. 5. In Fig. 5, a cross-sectional view taken along line BB in Fig. 4 is shown in the upper part. A portion of the cross-sectional view in the upper part is shown enlarged in a balloon in the lower part. As shown in the upper and lower parts of Fig. 5, the wired circuit board 1 includes a metal support 10, a first insulating layer 20, a conductor layer 30, and a second insulating layer 40.

[0026] The metal support 10 is a plate-shaped member made of metal, and is formed of, for example, stainless steel. Instead of stainless steel, the metal support 10 may be formed of copper, a copper alloy, aluminum, titanium, or an alloy containing iron and nickel. The metal support 10 has higher rigidity than the first insulating layer 20 and the second insulating layer 40. The metal support 10 has an upper surface 11 and a lower surface 12 that face in opposite directions in the third direction D3. The thickness of the metal support 10 is 10 μm or more and 30 μm or less.

[0027] The first insulating layer 20 is made of a photosensitive resin and is laminated on the upper surface 11 of the metal support 10. The photosensitive resin constituting the first insulating layer 20 is, for example, a photosensitive polyimide. Instead of photosensitive polyimide, the first insulating layer 20 may be made of other photosensitive resins (such as acrylic resin, epoxy resin, polyamide resin, polybenzoxazole resin, or polyvinyl chloride resin). The first insulating layer 20 covers the upper surface 11 of the metal support 10. The first insulating layer 20 has an upper surface 21 and a lower surface 22 that face in opposite directions in the third direction D3. The thickness of the first insulating layer 20 is 1 μm or more and 10 μm or less. The first insulating layer 20 may also be made of a non-photosensitive resin. Therefore, the first insulating layer 20 may be made of a thermoplastic resin or a thermosetting resin, similar to the second insulating layer 40 described later.

[0028] In addition to the above examples, the first insulating layer 20 may have a configuration in which a plurality of different types of resins are laminated. For example, the first insulating layer 20 may have a configuration in which a layer of a thermoplastic resin and a layer of a thermosetting resin are laminated. More specifically, the first insulating layer 20 may have a configuration in which two or more layers of two or more materials selected from thermoplastic polyimide, thermosetting polyimide, thermoplastic epoxy, thermosetting epoxy, thermoplastic acrylic, and thermosetting acrylic are laminated.

[0029] The conductor layer 30 includes a plurality of terminal portions 31 and a plurality of wiring portions 32 (FIG. 4), and is formed in a predetermined pattern on the upper surface 21 of the first insulating layer 20. Specifically, the plurality of terminal portions 31 are arranged in a matrix at equal intervals on the upper surface 21 of the first insulating layer 20. On the other hand, the plurality of wiring portions 32 correspond to the plurality of terminal portions 31, respectively. Each wiring portion 32 is formed to extend from the corresponding terminal portion 31, as indicated by the thick dotted line in FIG. 4.

[0030] The conductor layer 30 is formed by growing a plating layer on a seed layer by electrolytic plating. Specific examples of this formation method will be described later. The seed layer that forms the conductor layer 30 is made of, for example, a thin chromium film and a thin copper film. Alternatively, the seed layer is made of a thin titanium film and a thin copper film. Alternatively, the seed layer is made of a thin copper film. On the other hand, the plating layer is formed of a metal or alloy containing one or more of copper, gold, silver, platinum, lead, tin, nickel, cobalt, indium, rhodium, chromium, tungsten, ruthenium, and the like. In this embodiment, the plating layer is copper.

[0031] The thickness of the conductor layer 30 in the third direction D3 (the stacking direction of the wired circuit board 1) is 1 μm or more and 20 μm or less. In the wired circuit board 1 according to this embodiment, each of the plurality of terminal portions 31 of the conductor layer 30 has a circular shape in a plan view. In a plan view, the outer diameter (diameter) of each terminal portion 31 is 5 μm or more and 400 μm or less. In the wired circuit board 1 according to this embodiment, the distance d1 (FIG. 4) between the centers 31c of each two adjacent terminal portions 31 in the first direction D1 is 5 μm or more and 500 μm or less. In addition, the distance d2 (FIG. 4) between the centers 31c of each two adjacent terminal portions 31 in the second direction D2 is also 5 μm or more and 500 μm or less. The distances d1 and d2 may be the same length or may be different lengths.

[0032] The second insulating layer 40 is made of a thermoplastic resin or a thermosetting resin and is formed on the upper surface 21 of the first insulating layer 20 so as to cover some of the terminal portions 31 and the wiring portions 32. The thermoplastic resin or thermosetting resin constituting the second insulating layer 40 may be, for example, a thermoplastic polyimide or a thermosetting polyimide. Instead of a thermoplastic polyimide or a thermosetting polyimide, the second insulating layer 40 may be formed of another thermoplastic resin (an acrylic resin, an epoxy resin, a polyamide resin, a polybenzoxazole resin, a polyvinyl chloride resin, or another thermosetting resin) or another thermosetting resin (an acrylic resin, an epoxy resin, a polyamide resin, a polyvinyl chloride resin, or another thermosetting resin). The second insulating layer 40 has an upper surface 40a and a lower surface 40b (FIG. 5) facing in opposite directions in the third direction D3.

[0033] In addition to the above examples, the second insulating layer 40 may have a configuration in which a plurality of different types of resins are laminated. For example, the second insulating layer 40 may have a configuration in which a layer of a thermoplastic resin and a layer of a thermosetting resin are laminated. More specifically, the second insulating layer 40 may have a configuration in which two or more layers of two or more materials selected from thermoplastic polyimide, thermosetting polyimide, thermoplastic epoxy, thermosetting epoxy, thermoplastic acrylic, and thermosetting acrylic are laminated.

[0034] 4 and 5, the second insulating layer 40 has a plurality of openings 49 corresponding to the plurality of terminal portions 31. Each of the plurality of openings 49 has a circular shape in a plan view, and is formed so as to overlap the corresponding terminal portion 31. The inner diameter of each opening 49 in a plan view is smaller than the outer diameter (diameter) of the corresponding terminal portion 31, and is not less than 2 μm and not more than 300 μm.

[0035] The plurality of openings 49 overlap the plurality of terminal portions 31, respectively, so that the central portion of each terminal portion 31 is exposed to the space above the wired circuit board 1 through the corresponding opening 49. On the other hand, the outer portion of each terminal portion 31 that surrounds the central portion of the terminal portion 31 in plan view is covered with the second insulating layer 40.

[0036] In the following description, the portion of the second insulating layer 40 that covers the outer portion of each terminal portion 31 in a plan view, i.e., the portion that covers the outer portion of each terminal portion 31 when viewed in the third direction D3, will be referred to as a first annular portion 41. Furthermore, the portion of the second insulating layer 40 that surrounds each of the multiple first annular portions 41 in a plan view, i.e., the portion that surrounds each of the multiple first annular portions 41 when viewed in the third direction D3, will be referred to as a second annular portion 42.

[0037] In FIG. 4, the first annular portion 41 is given a dark dot pattern and the second annular portion 42 is given a light dot pattern so that the first annular portion 41 and the second annular portion 42 in the second insulating layer 40 can be clearly distinguished from each other.

[0038] 4, it can be seen that the wired circuit board 1 has, in a plan view, a plurality of unit structures US, each including a first annular portion 41 and a second annular portion 42 corresponding to one terminal portion 31. Furthermore, the plurality of unit structures US are arranged continuously in the first direction D1 and the second direction D2, similar to the plurality of terminal portions 31.

[0039] The lower balloon in Figure 5 shows an enlarged view of a unit structure US including one terminal portion 31 and its corresponding first annular portion 41 and second annular portion 42. Here, assuming that the upper surface 21 of the first insulating layer 20 is a reference plane perpendicular to the third direction D3, the distance in the third direction D3 between the reference plane and the upper surface 40a of the second insulating layer 40 varies among multiple portions. Specifically, the distance between the reference plane and the upper surface 40a of the second annular portion 42 is smaller than the distance between the reference plane and the upper surface 40a of the first annular portion 41. Furthermore, in the unit structure US, the second annular portion 42 is formed to be recessed as it moves away from the outer edge of the first annular portion 41.

[0040] As a result, in the unit structure US corresponding to each terminal portion 31, the second insulating layer 40 protrudes upward from a position outside the terminal portion 31 on the upper surface 21 of the first insulating layer 20 to the center 31c of the terminal portion 31.

[0041] 6, to facilitate understanding of the shape of the upper surface 40a of the second insulating layer 40, the shortest path on the upper surface 40a connecting each two adjacent first annular portions 41 is represented by a dotted line. As shown in Fig. 6, the plurality of unit structures US of the second insulating layer 40 protrude upward on the first insulating layer 20, so that a plurality of concave and convex portions corresponding to the plurality of terminal portions 31 are formed in a matrix on the upper surface of the wired circuit board 1.

[0042] According to the above configuration, when the multiple semiconductor chips 2 shown in FIG. 1 are mounted on the wired circuit board 1, gaps are formed between the wired circuit board 1 and each semiconductor chip 2, with narrow and wide spaces intermingled. The gaps are then filled with underfill 6. In this case, when the underfill 6 comes into contact with the uneven portions of the multiple unit structures US within the gaps and hardens, the adhesive strength between the wired circuit board 1 and each semiconductor chip 2 after mounting is strengthened by an anchor effect. As a result, the semiconductor chips 2 are prevented from peeling off from the wired circuit board 1 in the resulting mounting substrate 3.

[0043] <3> Preferred Shape of Second Insulating Layer 40 (a) In the above-described wired circuit board 1, the total area of ​​the second insulating layer 40 when viewed in a plan view (when viewed in the third direction D3) is defined as a first area value S1. The total area (opening area) of the openings 49 of the multiple unit structures US is defined as a second area value S2. In this case, the second insulating layer 40 is preferably formed so that the value (S2 / S1) obtained by dividing the second area value S2 by the first area value S1 is 0.01 or more and 0.5 or less.

[0044] When the value (S2 / S1) is 0.01 or more, it becomes easier to mount the semiconductor chip 2 on the wiring circuit board 1 using solder compared to when the value (S2 / S1) is less than 0.01. Also, the reliability of the electrical connection between the mounted semiconductor chip 2 and the wiring circuit board 1 is improved. On the other hand, when the value (S2 / S1) is 0.5 or less, it is possible to ensure a larger contact area of ​​the underfill 6 in the second insulating layer 40 compared to when the value (S2 / S1) is greater than 0.5. Therefore, it is possible to improve the adhesion between the wiring circuit board 1 and each semiconductor chip 2 after mounting.

[0045] (b) As shown in the balloon in FIG. 5, the maximum value of the distance between the reference plane (top surface 21 of first insulating layer 20) and the top surface 40a of second insulating layer 40 in the third direction D3 is defined as a first thickness value T1. The minimum value of the distance between the reference plane and the top surface 40a of second insulating layer 40 in the third direction D3 is defined as a second thickness value T2. In this case, second insulating layer 40 is preferably formed so that the value (T2 / T1) obtained by dividing second thickness value T2 by first thickness value T1 is greater than 0.3 and less than 1. For second insulating layer 40, the value (T2 / T1) is preferably greater than 0.5 and less than 1, more preferably greater than 0.75 and less than 1, and even more preferably greater than 0.8 and less than 1.

[0046] When the value (T2 / T1) is greater than 0.3, significantly large irregularities are not formed on the upper surface 40a of the second insulating layer 40. This prevents the underfill 6 from being unable to conform to the irregular shape, thereby preventing poor filling of the underfill 6. Furthermore, since significantly large irregularities are not formed on the upper surface 40a of the second insulating layer 40, the overall thickness of the second insulating layer 40 can be reduced. This allows the wired circuit board 1 to be made thinner.

[0047] (c) The difference (T1-T2) between the first thickness value T1 and the second thickness value T2 can be said to be the depth of the recess formed in the upper surface 40a of the second insulating layer 40. The difference (T1-T2) is greater than 0 μm and less than or equal to 10 μm, and preferably greater than 0 μm and less than or equal to 5 μm.

[0048] (d) When the first thickness value T1 is defined as above, it is preferable that the first thickness value T1 is smaller than 25 μm. When the second thickness value T2 is defined as above, it is preferable that the second thickness value T2 is smaller than 20 μm. In these cases, the wired circuit board 1 can be made thinner.

[0049] (e) Here, in the above-described wired circuit board 1, the distance in the third direction D3 between the upper surface 21 of the first insulating layer 20 and the upper end surface of each first annular portion 41 is referred to as the reinforced portion height. There may be variation in the reinforced portion heights of the multiple first annular portions 41 formed in one wired circuit board 1. The largest height among the multiple reinforced portion heights corresponding to the multiple first annular portions 41 is referred to as the reinforced portion maximum height Hmax, and the smallest height among the multiple reinforced portion heights is referred to as the reinforced portion minimum height Hmin.

[0050] In this case, the second insulating layer 40 is preferably formed so that the value (Hmin / Hmax) obtained by dividing the reinforced portion minimum height Hmin by the reinforced portion maximum height Hmax is greater than 0.7. In this way, when the value (Hmin / Hmax) is greater than 0.7, the amount of underfill 6 filled between the semiconductor chip 2 and multiple portions of the wiring circuit board 1 when the semiconductor chip 2 is mounted on the wiring circuit board 1 is more uniform than when the value (Hmin / Hmax) is 0.7 or less. Therefore, a decrease in adhesion between the wiring circuit board 1 and the semiconductor chip 2 after mounting due to a local lack of underfill 6 is suppressed.

[0051] <4> An example of a method for manufacturing the wired circuit board 1 In this embodiment, the wired circuit board 1 is manufactured by, for example, a roll-to-roll method. Fig. 7 is a schematic side view showing an example of a roll-to-roll apparatus used in the manufacturing process of the wired circuit board 1.

[0052] 7, the roll-to-roll apparatus 500 includes an unwinding section 501, a winding section 502, and a plurality of processing sections 510, 520, etc. First, a roll (unwinding roll) R1 around which the long metal support 10 is wound is prepared and set in the unwinding section 501 of the roll-to-roll apparatus 500.

[0053] The metal support 10 is unwound from a prepared unwinding roll R1. The unwound metal support 10 is then wound onto another roll (winding roll) R2 set in a winding section 502, as indicated by the dotted arrow in FIG.

[0054] In the roll-to-roll apparatus 500, a plurality of processing sections 510, 520, etc. are arranged between two rolls (R1, R2) in the direction of movement of the metal support 10. The plurality of processing sections 510, 520, etc. respectively form the first insulating layer 20, the conductor layer 30, and the second insulating layer 40 on the long metal support 10 moving between the two rolls (R1, R2). As a result, a plurality of wired circuit boards 1 are formed on the metal support 10 taken up by the take-up roll R2. An example of a method for manufacturing the wired circuit board 1 will be described in detail below.

[0055] Figures 8 to 18 are cross-sectional views illustrating an example of a method for manufacturing the wired circuit board 1 of Figure 1. The cross-sectional views shown in Figures 8 to 18 correspond to the cross-sectional view of the portion of the wired circuit board 1 of Figure 1 shown in the upper part of Figure 5.

[0056] As described above, a payout roll R1 (FIG. 7) around which the metal support 10 is wound is prepared, and the metal support 10 is paid out from the payout roll R1. FIG. 8 shows a cross-sectional view of the metal support 10 paid out from the payout roll R1. The metal support 10 has an upper surface 11 and a lower surface 12 facing in opposite directions.

[0057] Next, as shown in FIG. 9 , a first insulating layer 20 is formed on the upper surface 11 of the metal support 10. Specifically, the first insulating layer 20 is formed, for example, as follows. First, a photosensitive resin varnish is applied to the upper surface 11 of the metal support 10 so as to cover the entire upper surface 11. In this example, a photosensitive polyimide varnish is used as the photosensitive resin varnish. The applied photosensitive polyimide varnish is then subjected to a drying process, an exposure process, a development process, and a curing process, in that order. As a result, the first insulating layer 20 is formed on the upper surface 11 of the metal support 10. The first insulating layer 20 has an upper surface 21 and a lower surface 22 facing in opposite directions.

[0058] The first insulating layer 20 may be formed by attaching a sheet-like member (film) made of photosensitive polyimide to the upper surface 11 of the metal support 10, instead of applying a photosensitive polyimide varnish to the upper surface 11 of the metal support 10. Alternatively, the first insulating layer 20 may be formed by attaching a sheet-like member (film) made of photosensitive epoxy to the upper surface 11 of the metal support 10, instead of applying a photosensitive polyimide varnish to the upper surface 11 of the metal support 10. Alternatively, the first insulating layer 20 may be formed by attaching a laminate of a sheet-like member (film) made of photosensitive polyimide and a sheet-like member (film) made of photosensitive epoxy to the upper surface 11 of the metal support 10.

[0059] Next, as shown by the thick solid line in Fig. 10, a seed layer 39 is formed on the exposed upper surface 21 of the first insulating layer 20. Thereafter, as shown in Fig. 11, a plating resist layer 51 having openings in a predetermined pattern is formed on the upper surface 11 of the first insulating layer 20. Specifically, the plating resist layer 51 is formed, for example, as follows.

[0060] First, a positive photosensitive resin varnish is applied to the upper surface 11 of the first insulating layer 20. After the varnish has spread over the entire upper surface 11 of the first insulating layer 20, the varnish is dried. This hardens the varnish, forming a photosensitive resin layer. Next, a portion of the formed photosensitive resin layer is irradiated with exposure light corresponding to the photosensitive resin in a predetermined pattern. The predetermined pattern corresponds to the pattern of the conductor layer 30 to be formed in a subsequent process. The photosensitive resin layer is then developed. In this example, the photosensitive resin is a positive photosensitive resin. In this case, the exposed portion dissolves in a developer. This forms a plating resist layer 51 having openings in the predetermined pattern. At this time, portions of the seed layer 39 are exposed upward through the openings in the plating resist layer 51.

[0061] Next, electrolytic plating is performed using the exposed portions of the seed layer 39. As a result, a conductor (copper in this example) is filled into the openings of the plating resist layer 51, forming a plating layer 38, as shown in FIG.

[0062] Next, as shown in FIG. 13, the plating resist layer 51 is removed. The plating resist layer 51 is removed, for example, by exposing and developing the plating resist layer 51 remaining on the upper surface 21 of the first insulating layer 20. Thereafter, as shown in FIG. 14, the portion of the seed layer 39 where the plating layer 38 was not formed is removed by etching. As a result, the conductor layer 30 is formed by a laminate of the seed layer 39 and the plating layer 38. In FIGS. 13 to 18, three terminal portions 31 of the conductor layer 30 are shown. At this time, on the upper surface 21 of the first insulating layer 20, parts of the conductor layer 30 are two-dimensionally arranged as multiple terminal portions 31 so that a predetermined arrangement pattern is repeatedly arranged. In FIGS. 15 to 18, the seed layer 39 is not shown.

[0063] Next, a varnish 60 made of a thermoplastic resin or a thermosetting resin is applied to the upper surface 21 of the first insulating layer 20 so as to cover the entire exposed portion of the conductor layer 30. In this example, a thermoplastic polyimide or a thermosetting polyimide varnish is used as the thermoplastic resin or thermosetting resin varnish 60. As a result, a layer of liquid varnish 60 is formed on the first insulating layer 20, as shown in FIG. 15. In FIGS. 15 to 18, a dot pattern is applied to the varnish 60.

[0064] The varnish 60 contains a volatile solvent. When the varnish 60 is applied, the varnish 60 has high fluidity. As a result, the upper surface of the varnish 60 layer is flat. The thickness of the varnish 60 layer is small in the portion that overlaps the conductor layer 30 (hereinafter referred to as the conductor overlapping portion) and is large in the portion that does not overlap the conductor layer 30 (hereinafter referred to as the non-conductor overlapping portion).

[0065] Next, a drying process is performed to volatilize the solvent in the varnish 60 to such an extent that fluidity is not lost. This drying process is performed by, for example, heating the laminate including the varnish 60. At this time, the upper surface 60a of the layer of varnish 60 is deformed according to the thickness of each portion of the varnish 60 as the solvent contained in the varnish 60 volatilizes.

[0066] Specifically, the amount of solvent volatilizing from the thin conductor overlapping portion is smaller than the amount of solvent volatilizing from the thick non-conductor overlapping portion. Therefore, the conductor overlapping portion shrinks at a smaller rate than the non-conductor overlapping portion. In other words, the non-conductor overlapping portion shrinks more than the conductor overlapping portion. As a result, the upper surface 60a of the varnish 60 layer after the drying process protrudes upward at the conductor overlapping portion (portion overlapping with the terminal portion 31) and is recessed at the non-conductor overlapping portion (portion not overlapping with the terminal portion 31), as shown in FIG. 16.

[0067] Next, a pressing member (not shown) having a flat pressing surface is prepared. The pressing surface of the pressing member is brought into contact with the upper surface 60a of the varnish 60, thereby pressing the upper surface 60a of the varnish 60. At this point in time, the varnish 60 has fluidity. As a result, the upper surface 60a of the varnish 60 is flattened, as shown in FIG. 17 . In this case, too, the thickness of the varnish 60 layer is small in the conductor overlapping portions and large in the non-conductor overlapping portions.

[0068] Thereafter, the varnish 60 is cured. This curing is a heat treatment that volatilizes the solvent contained in the varnish 60 and hardens the varnish 60. During this heat treatment, as in the drying treatment described above, the amount of solvent that volatilizes from the conductor overlapping portions differs from the amount of solvent that volatilizes from the thicker non-conductor overlapping portions. As a result, as shown in FIG. 18, the upper surface 60a of the varnish 60 layer after the curing treatment protrudes upward at the conductor overlapping portions (portions that overlap the terminal portions 31) and is recessed at the non-conductor overlapping portions (portions that do not overlap the terminal portions 31).

[0069] The size of the irregularities formed on the upper surface 60a of the varnish 60 layer after the curing process (FIG. 18) is smaller than the size of the irregularities formed on the upper surface 60a of the varnish 60 layer after the drying process (FIG. 16). This difference in the size of the irregularities is thought to be due to the fact that the total amount of solvent volatilized from the varnish 60 during the curing process is smaller than the total amount of solvent volatilized from the varnish 60 during the drying process.

[0070] Finally, multiple openings are formed in the layer of varnish 60 so that the central portion of each of the multiple terminal portions 31 is exposed upward and the outer portions of the terminal portions 31 are covered with the hardened varnish 60. The multiple openings can be formed, for example, by laser processing, drilling, or photolithographic exposure and development. As a result, as shown in FIG. 5, a second insulating layer 40 including multiple openings 49 is formed on the first insulating layer 20, completing the wired circuit board 1. The completed wired circuit board 1 is taken up on a take-up roll R2.

[0071] The second insulating layer 40 may be formed by attaching a sheet-like member (film) made of photosensitive polyimide to the upper surface 21 of the first insulating layer 20 instead of applying the varnish 60 thereon. Alternatively, the second insulating layer 40 may be formed by attaching a sheet-like member (film) made of photosensitive epoxy to the upper surface 21 of the first insulating layer 20 instead of applying the varnish 60 thereon. Alternatively, the second insulating layer 40 may be formed by attaching a laminate of a sheet-like member (film) made of photosensitive polyimide and another sheet-like member (film) made of photosensitive epoxy to the upper surface 21 of the first insulating layer 20.

[0072] The wired circuit board 1 wound up by the winding roll R2 is cut according to predetermined design dimensions, for example, depending on the size of the mounting board 3 to be produced and the electronic component 4 into which the mounting board 3 will be incorporated. This makes it possible to obtain multiple pieces of wired circuit boards 1 having sizes suited to the intended use.

[0073] In this case, the second insulating layer 40 of each piece of the wired circuit board 1 is preferably formed so that the value (T2 / T1) obtained by dividing the second thickness value T2 in Fig. 5 by the first thickness value T1 in Fig. 5 is greater than 0.3 and less than 1. Furthermore, the second insulating layer 40 is preferably formed so that the value (Hmin / Hmax) obtained by dividing the reinforced portion minimum height Hmin by the reinforced portion maximum height Hmax is greater than 0.7.

[0074] <5> Another example of the method for manufacturing the wired circuit board 1 Another example of a method for manufacturing the wired circuit board 1 will be described, focusing on the differences from the above-described example of a method for manufacturing the wired circuit board 1. Figures 19 to 21 are cross-sectional views for explaining another example of a method for manufacturing the wired circuit board 1 of Figure 1. The cross-sectional views shown in Figures 19 to 21 correspond to the cross-sectional view of the portion of the wired circuit board 1 of Figure 1 shown in the upper part of Figure 5.

[0075] In the method for manufacturing the wired circuit board 1 of this example, first, the first insulating layer 20 is formed on the metal support 10, and the conductor layer 30 is formed on the first insulating layer 20, according to the method shown in Figures 8 to 14 above. Additionally, unnecessary portions of the seed layer 39 are removed.

[0076] Thereafter, a sheet-like member 60s containing a thermoplastic resin or a thermosetting resin is attached to the upper surface 21 of the first insulating layer 20 so as to cover the entire conductor layer 30 exposed in the laminate shown in FIG. 14. Here, the sheet-like member 60s is a sheet-like member in which a varnish 60 of a thermoplastic resin or a thermosetting resin has been brought to a so-called B-stage. More specifically, the sheet-like member 60s is a member in which the varnish 60 of a thermoplastic resin or a thermosetting resin is formed into a sheet shape in a semi-cured state that does not have tackiness and appears cured. As a result, a layer of the sheet-like member 60s is formed on the first insulating layer 20, as shown in FIG. 19. In FIGS. 19 to 21, the sheet-like member 60s is hatched to clearly distinguish it from the varnish 60 shown in FIGS. 15 to 18 used in an example of a method for manufacturing the wired circuit board 1.

[0077] When the sheet-like member 60s is attached, the sheet-like member 60s deforms to follow the outer shape of the upper surface 21 of the first insulating layer 20 and the conductor layer 30. As a result, after being attached onto the first insulating layer 20, the upper surface 60a of the sheet-like member 60s has unevenness corresponding to the pattern of the conductor layer 30 formed on the first insulating layer 20.

[0078] Next, a pressing member (not shown) having a flat pressing surface is prepared. The pressing surface of the pressing member is brought into contact with the upper surface 60a of the sheet-like member 60s, thereby pressing the upper surface 60a of the sheet-like member 60s. At this point in time, the sheet-like member 60s, which is in a semi-hardened state, is deformed. As a result, the upper surface 60a of the sheet-like member 60s is flattened, as shown in FIG. 20 .

[0079] Thereafter, the sheet-shaped member 60s is subjected to a curing process. This curing process is a heat treatment that volatilizes the solvent contained in the semi-cured sheet-shaped member 60s and hardens the sheet-shaped member 60s. During this heat treatment, as in the example of the varnish 60 described above (the example of the process in FIG. 18), the amount of solvent that volatilizes varies between multiple portions of the sheet-shaped member 60s. As a result, the upper surface 60a of the layer of the sheet-shaped member 60s protrudes upward in the portions that overlap the terminal portions 31 and is recessed in the portions that do not overlap the terminal portions 31, as shown in FIG.

[0080] Finally, a plurality of openings are formed in the layer of the sheet-like member 60s so that the central portion of each of the plurality of terminal portions 31 is exposed upward and the outer portions of the terminal portions 31 are covered with the cured sheet-like member 60s. This completes the wired circuit board 1. The completed wired circuit board 1 is taken up on a take-up roll R2.

[0081] In another example of the method for manufacturing the wired circuit board 1, as described above, a sheet-like member 60s is used to form the second insulating layer 40. This reduces the number of steps compared to the manufacturing methods shown in Figures 15 to 18, which include the "step of applying varnish 60 onto the first insulating layer 20" and the "step of drying the varnish 60 to volatilize the solvent therein to the extent that fluidity is not lost."

[0082] <6> Effects of the First Embodiment (a) As described above, in the wired circuit board 1, the second insulating layer 40 forming the mounting surface of the plurality of semiconductor chips 2 has a plurality of unit structures US that protrude upward in correspondence with the plurality of terminal portions 31, respectively.

[0083] The multiple unit structures US, together with the multiple terminal portions 31, are arranged at equal intervals in a matrix in a plan view of the wiring circuit board 1. As a result, when multiple semiconductor chips 2 are mounted on the wiring circuit board 1, a gap consisting of a mixture of narrow and wide spaces is formed between the wiring circuit board 1 and the semiconductor chips 2. An underfill 6 is filled into the gap, and the underfill 6 comes into contact with the surfaces of the unit structures US and hardens. In this case, the adhesive force between the wiring circuit board 1 and the multiple semiconductor chips 2 after mounting is strengthened by the anchor effect. As a result, the multiple semiconductor chips 2 are prevented from peeling off from the wiring circuit board 1 in the mounting substrate 3.

[0084] (b) The thickness of the conductor layer 30 is 1 μm or more and 20 μm or less. This size range is relatively small for the thickness range of the conductor layer 30 used in the wired circuit board 1. Therefore, the wired circuit board 1 can be made thinner and flatter.

[0085] (c) The above-described wired circuit board 1 includes a metal support 10. The metal support 10 supports the first insulating layer 20, the conductor layer 30, and the second insulating layer 40. The metal support 10 has relatively high rigidity. Therefore, the occurrence of deformation such as warping in the wired circuit board 1 is suppressed, and the handleability of the wired circuit board 1 is improved.

[0086] (d) As described above, for example, photosensitive polyimide is used as the photosensitive resin that constitutes the first insulating layer 20. Furthermore, for example, thermoplastic polyimide or thermosetting polyimide is used as the thermoplastic resin or thermosetting resin that constitutes the second insulating layer 40.

[0087] In this case, since the dielectric constant of polyimide is relatively low, a wired circuit board 1 suitable for transmitting high-frequency signals is realized. Polyimide also has high dimensional stability and high heat resistance. Furthermore, it is relatively easy to match the thermal expansion coefficient of polyimide with the conductor layer 30 used in the wired circuit board 1. Therefore, when polyimide is used as the material for the first insulating layer 20 and the second insulating layer 40 as described above, deformation of the wired circuit board 1, such as warping, is suppressed. As a result, the reliability of the wired circuit board 1 is improved.

[0088] As described above, epoxy can also be used as the material for the first insulating layer 20. Like polyimide, epoxy has high dimensional stability and high heat resistance. Furthermore, it is relatively easy for epoxy to match the thermal expansion coefficient with the conductor layer 30 used in the wired circuit board 1. Therefore, even when epoxy is used as the material for the first insulating layer 20 and the second insulating layer 40, deformation of the wired circuit board 1, such as warping, is suppressed.

[0089] 2. Second embodiment The following describes the differences between the wired circuit board and the method for manufacturing the wired circuit board according to the second embodiment and the wired circuit board and the method for manufacturing the wired circuit board according to the first embodiment.

[0090] The wired circuit board 1 according to the second embodiment basically has the same appearance as the wired circuit board 1 according to the first embodiment. On the other hand, the wired circuit board 1 according to the second embodiment has a structure of the plurality of terminal portions 31 that is different from the structure of the plurality of terminal portions 31 according to the first embodiment.

[0091] <1> Configuration of the wiring circuit board 1 Fig. 22 is a cross-sectional view of the wired circuit board 1 according to the second embodiment. The cross-sectional view of Fig. 22 corresponds to the cross-sectional view of the wired circuit board 1 according to the first embodiment in Fig. 5. In Fig. 22, as in the example of Fig. 5, a cross-sectional view corresponding to line BB in Fig. 4 is shown in the upper part. In addition, a portion of the cross-sectional view in the upper part is shown enlarged in a balloon in the lower part.

[0092] 22, in the wired circuit board 1 according to the present embodiment, each of the plurality of terminal portions 31 in the conductor layer 30 is configured as two layers, a lower conductor layer 31a and an upper conductor layer 31b, which are stacked in the third direction D3. Specifically, the terminal portion 31 in this example is configured as a lower conductor layer 31a formed directly on the upper surface 21 of the first insulating layer 20, and an upper conductor layer 31b formed on the lower conductor layer 31a. On the other hand, in the present embodiment, the plurality of wiring portions 32 in the conductor layer 30 (see the plurality of wiring portions 32 indicated by thick dotted lines in FIG. 4) are configured as a single layer, that is, the lower conductor layer 31a.

[0093] With this configuration, the positions of the exposed portions of the plurality of terminal portions 31 (height positions of the terminal portions 31) can be made different from the formation position of the wiring portion 32 (height position of the wiring portion 32) in the third direction D3. Therefore, the degree of freedom in the layout of the plurality of wiring portions 32 and the plurality of terminal portions 31 in the wired circuit board 1 is improved.

[0094] Here, the thickness of the lower conductor layer 31a in the third direction D3 (stacking direction of the wired circuit board 1) is 1 μm or more and 10 μm or less. Therefore, the thickness of the plurality of wiring portions 32 is 1 μm or more and 10 μm or less. Furthermore, the thickness of the upper conductor layer 31b in the third direction D3 (stacking direction of the wired circuit board 1) is 1 μm or more and 20 μm or less. These dimensional ranges are relatively small as the range of thicknesses of the conductor layers 30 used in the wired circuit board 1. Therefore, the wired circuit board 1 can be made thinner and flatter.

[0095] Furthermore, the thickness of the plurality of terminals 31 in the third direction D3 (the stacking direction of the wired circuit board 1) is smaller than the second thickness value T2 of the second insulating layer 40 in the third direction D3. In this case, unintended portions of the plurality of terminals 31, excluding the central portions, are prevented from being exposed to the space above the second insulating layer 40.

[0096] As described above, in this embodiment, each terminal 31 is formed of a lower conductor layer 31a and an upper conductor layer 31b. The lower conductor layer 31a constituting each terminal 31 has a circular shape in a plan view, and its outer diameter (diameter) is 5 μm or more and 400 μm or less. On the other hand, the upper conductor layer 31b constituting each terminal 31 has a circular shape in a plan view, and its outer diameter (diameter) is 2 μm or more and 300 μm or less.

[0097] In this embodiment as well, the second insulating layer 40 is preferably formed so that the value (T2 / T1) obtained by dividing the second thickness value T2 by the first thickness value T1 is greater than 0.3 and less than 1. Furthermore, in the second insulating layer 40, the value (T2 / T1) is more preferably greater than 0.5 and less than 1, even more preferably greater than 0.75 and less than 1, and even more preferably greater than 0.8 and less than 1.

[0098] When the value (T2 / T1) is greater than 0.3, poor filling of the underfill 6 due to the underfill 6 being unable to conform to the uneven shape is suppressed. Furthermore, since significantly large unevenness is not formed on the upper surface 40a of the second insulating layer 40, the wired circuit board 1 can be made thinner.

[0099] 22 having the above configuration can be used as one component of a mounting board 3, similar to the wiring circuit board 1 according to the first embodiment. In addition, the mounting board 3 including the wiring circuit board 1 of FIG. 22 can be used as one component of an electronic component 4.

[0100] <2> Manufacturing method of wired circuit board 1 A method for manufacturing the wired circuit board 1 according to the second embodiment will be described. The wired circuit board 1 according to this embodiment is manufactured by a roll-to-roll method using, for example, the roll-to-roll apparatus 500 shown in FIG. 7, as in the first embodiment. FIGS. 23 to 30 are cross-sectional views for explaining an example of a method for manufacturing the wired circuit board 1 shown in FIG. 22. The cross-sectional views shown in FIGS. 23 to 30 correspond to the cross-sectional view of the portion shown in the upper part of FIG. 22.

[0101] In the method for manufacturing the wired circuit board 1 according to this embodiment, first, a laminate (a part of the wired circuit board 1) is produced according to the method described in the first embodiment and shown in Figures 8 to 13. At this point, the laminate in the process of being produced has a configuration in which a plurality of plating layers 38 are formed on one surface (upper surface 21 of first insulating layer 20) of the laminate of metal support 10 and first insulating layer 20 via seed layer 39.

[0102] 23, a plating resist layer 52 having openings in a predetermined pattern is formed on the upper surface 11 of the first insulating layer 20. The plating resist layer 52 is formed by a method similar to the method for forming the plating resist layer 51 in FIG.

[0103] The plating resist layer 52 is formed on the first insulating layer 20 so as to cover the portions of the plating layer 38 where the plurality of wiring portions 32 (FIG. 4) are to be formed. The plating resist layer 52 also has a plurality of openings in the portions of the plating layer 38 where the plurality of terminal portions 31 are to be formed. As a result, parts of the plating layer 38 are exposed upward through the plurality of openings.

[0104] Next, electrolytic plating is performed using the portions of the plating layer 38 exposed through the multiple openings in the plating resist layer 52. As a result, a conductor (copper in this example) is filled into the openings of the plating resist layer 52, forming a new plating layer, as shown in Fig. 24. This plating layer forms the upper conductor layer 31b in Fig. 22.

[0105] Next, as shown in Fig. 25, the plating resist layer 52 is removed. Furthermore, as shown in Fig. 26, the exposed portion of the seed layer 39 is removed by etching. As a result, the seed layer 39 and the plating layer 38 form a laminated body, which constitutes the lower conductor layer 31a in Fig. 22. Furthermore, the lower conductor layer 31a and the upper conductor layer 31b form a laminated body, which constitutes the conductor layer 30.

[0106] More specifically, a plurality of terminal portions 31 each consisting of a lower conductor layer 31a and an upper conductor layer 31b are formed as a portion of the conductor layer 30. A plurality of wiring portions 32 (FIG. 4) each consisting of the lower conductor layer 31a are formed as another portion of the conductor layer 30. At this time, on the upper surface 21 of the first insulating layer 20, a portion of the conductor layer 30 is two-dimensionally arranged as a plurality of terminal portions 31 so that a predetermined arrangement pattern is repeatedly arranged. In FIGS. 26 to 30, three terminal portions 31 of the conductor layer 30 are shown. In FIGS. 27 to 30, the seed layer 39 is not shown.

[0107] Next, the second insulating layer 40 is formed on the upper surface 21 of the first insulating layer 20 according to the method shown in FIGS. 15 to 18 and described in the first embodiment.

[0108] Specifically, as shown in Fig. 27, a layer of liquid varnish 60 made of thermoplastic polyimide or thermosetting polyimide is formed on the first insulating layer 20. A drying process is then performed to volatilize the solvent in the varnish 60 to such an extent that fluidity is not lost. As a result, as shown in Fig. 28, unevenness is formed on the upper surface 60a of the layer of varnish 60 after the drying process.

[0109] Next, a pressing member (not shown) having a flat pressing surface is prepared, and the pressing member is used to press the upper surface 60a of the layer of varnish 60. As a result, the upper surface 60a of the layer of varnish 60 is flattened, as shown in FIG.

[0110] Thereafter, the varnish 60 is cured. As a result, as shown in FIG. 30, unevenness is again formed on the upper surface 60a of the cured varnish 60 layer. Finally, multiple openings are formed in the layer of varnish 60 so that the central portions of each of the multiple terminal portions 31 are exposed upward and the outer portions of the terminal portions 31 are covered with the cured varnish 60. This completes the wired circuit board 1 shown in FIG. 22. The completed wired circuit board 1 is taken up by the take-up roll R2. The wired circuit board 1 taken up by the take-up roll R2 is cut, for example, according to predetermined design dimensions. This allows multiple pieces of wired circuit boards 1 having sizes appropriate for the intended use to be obtained.

[0111] 27 to 30, the wired circuit board 1 according to the present embodiment may have the second insulating layer 40 formed according to the method described in the first embodiment and shown in Figures 19 to 21. That is, the second insulating layer 40 may be formed by adhering a sheet-like member 60s (Figure 19) onto the first insulating layer 20 on which the conductor layer 30 has been formed, pressing the sheet-like member 60s, and performing a curing process.

[0112] 3. Third Embodiment The following describes the wired circuit board according to the third embodiment, focusing on the differences from the wired circuit board according to the second embodiment.

[0113] FIG. 31 is a cross-sectional view of a wired circuit board 1 according to a third embodiment. The cross-sectional view of FIG. 31 corresponds to the cross-sectional view of the wired circuit board 1 according to the second embodiment in FIG. 22. As shown in FIG. 31, the wired circuit board 1 according to the third embodiment has a configuration in which an additional wired circuit structure is provided on the lower surface 12 of the metal support 10 of the wired circuit board 1 according to the second embodiment. Furthermore, the wired circuit board 1 according to the third embodiment has a configuration in which the wired circuit structure on the upper surface 11 of the metal support 10 and the additional wired circuit structure on the lower surface 12 of the metal support 10 are electrically connected by vias 91 through through holes 19 formed in the metal support 10.

[0114] Specifically, in the wired circuit board 1 according to the present embodiment, a through hole 19 is formed in the metal support 10, penetrating from the upper surface 11 to the lower surface 12. The first insulating layer 20 is formed so as to cover the upper surface 11 of the metal support 10 and the inner circumferential surface of the through hole 19.

[0115] As in the example of the second embodiment, a conductor layer 30 is formed in a predetermined pattern on the upper surface 21 of the first insulating layer 20. Furthermore, as in the example of the second embodiment, a second insulating layer 40 having a plurality of openings 49 is formed on the upper surface 21 of the first insulating layer 20 so as to cover part of the conductor layer 30. The second insulating layer 40 has a plurality of openings 49 and includes a plurality of unit structures US that protrude upward.

[0116] A third insulating layer 70 is formed on the lower surface 12 of the metal support 10. The third insulating layer 70 has an upper surface 71 and a lower surface 72 that face in opposite directions in the third direction D3. The upper surface 71 of the third insulating layer 70 is in contact with the lower surface 12 of the metal support 10. A conductor layer 90 is formed in a predetermined pattern on the lower surface 72 of the third insulating layer 70. Furthermore, a fourth insulating layer 80 is formed on the lower surface 72 of the third insulating layer 70 so as to cover the conductor layer 90.

[0117] A through hole 99 is formed in the first insulating layer 20 and the third insulating layer 70, penetrating the inside of the through hole 19 of the metal support 10 in the third direction D3. A via 91 is formed inside the through hole 99. The via 91 is electrically connected to a part of the conductor layer 30 on the upper surface 21 of the first insulating layer 20. The via 91 is also electrically connected to a part of the conductor layer 90 on the lower surface 72 of the third insulating layer 70.

[0118] 4. Other embodiments (a) Although the wired circuit board 1 according to the first to third embodiments has the metal support 10, the present invention is not limited to this. The wired circuit board 1 does not have to be provided with the metal support 10. In this case, the wired circuit board 1 can be made thinner.

[0119] (b) The wired circuit board 1 according to the first and second embodiments is manufactured by a roll-to-roll process and has flexibility, but the present invention is not limited to this. The wired circuit board 1 may be manufactured by a process other than the roll-to-roll process. For example, it may be manufactured by a sheet-by-sheet process in which processing is performed sequentially on a single sheet. In this case, the wired circuit board 1 may be a rigid board that does not have flexibility.

[0120] (c) In the wired circuit board 1 according to the first to third embodiments, two insulating layers (20, 40) are laminated on the upper surface 11 of the metal support 10, and the conductor layer 30 is formed between those layers, but the present invention is not limited to this. The wired circuit board 1 may have a configuration in which three or more insulating layers are laminated on the upper surface 11 of the metal support 10, and the conductor layer 30 is formed inside those insulating layers.

[0121] (d) In the wired circuit board 1 according to the first to third embodiments, the terminal portions 31 are arranged in a matrix in plan view in the third direction D3, but the present invention is not limited to this. The terminal portions 31 may also be arranged in a staggered pattern.

[0122] (e) In the wired circuit board 1 according to the first to third embodiments, each of the plurality of openings 49 formed in the second insulating layer 40 has a circular shape in plan view, but the present invention is not limited to this. Each of the plurality of openings 49 may have an elliptical shape in plan view, or a polygonal shape such as a triangle or a rectangle.

[0123] (f) In one example of the method for manufacturing the wired circuit board 1 according to the first embodiment, after the varnish 60 is applied to the first insulating layer 20, a drying process is performed to volatilize the solvent in the varnish 60 to an extent that the varnish 60 does not lose its fluidity, but the present invention is not limited to this. The drying process may not be performed. In this case, after the varnish 60 is applied, the applied varnish 60 may be directly cured.

[0124] 5. Correspondence between each part of the embodiment and each element of the claims The following describes examples of correspondence between the elements of the claims and the elements of the embodiments. Various other elements having the configurations or functions described in the claims may also be used as the elements of the claims.

[0125] In the above-described embodiment, the wired circuit board 1 is an example of a wired circuit board, the upper surface 21 of the first insulating layer 20 is an example of a first surface, the first insulating layer 20 is an example of a first insulating layer, the terminal portion 31 is an example of a terminal portion, the conductor layer 30 is an example of a conductor layer, and the second insulating layer 40 is an example of a second insulating layer.

[0126] Furthermore, the unit structure US is an example of a mounting reinforcement portion, the opening 49 is an example of an opening, the first annular portion 41 is an example of a first annular portion, the second annular portion 42 is an example of a second annular portion, the upper surface 40a of the second insulating layer 40 is an example of a second surface, and the metal support 10 is an example of a metal support.

[0127] Furthermore, the lower conductor layer 31a is an example of a first conductor layer, the upper conductor layer 31b is an example of a second conductor layer, the semiconductor chip 2 is an example of an electrical element, the solder 5 is an example of solder, the underfill 6 is an example of underfill, the mounting board 3 is an example of an electrical element mounting board, the electronic component 4 is an example of an electronic component, and the sheet-like member 60s is an example of a sheet-like member.

[0128] 6. Summary of the embodiment (Item 1) The printed circuit board according to item 1 is a first insulating layer having a first surface; a conductor layer having a plurality of terminal portions and formed on the first surface of the first insulating layer; a second insulating layer formed on the first surface of the first insulating layer so as to cover a portion of the conductor layer; the plurality of terminal portions are two-dimensionally arranged on the first surface so that a predetermined arrangement pattern is repeatedly arranged; the second insulating layer includes a plurality of mounting reinforcement portions that respectively correspond to the plurality of terminal portions and protrude in a direction in which the first surface faces, Each of the plurality of mounting reinforcement units includes: an opening overlapping the central portion of the corresponding terminal portion when viewed in a stacking direction of the first insulating layer and the second insulating layer so that the central portion of the corresponding terminal portion is exposed; a first annular portion overlapping an outer portion surrounding the central portion of the corresponding terminal portion when viewed in the stacking direction; and a second annular portion that surrounds the first annular portion when viewed in the stacking direction and is formed so as to become recessed with increasing distance from the outer edge of the first annular portion.

[0129] The wired circuit board includes a plurality of mounting reinforcement portions provided to correspond to the plurality of terminal portions, respectively. Each mounting reinforcement portion has an opening that exposes a central portion of the corresponding terminal portion. The mounting reinforcement portion also covers an outer portion of the terminal portion. This allows the plurality of electrical contacts of the electrical element to be soldered onto the plurality of terminal portions through the plurality of openings in the second insulating layer when mounting the electrical element on the wired circuit board.

[0130] When an electrical component is mounted on the wired circuit board, an underfill is filled between the wired circuit board and the electrical component. According to the above configuration, the mounting reinforcement portions correspond to the terminal portions, respectively, and are two-dimensionally arranged on the first surface in a predetermined pattern. Therefore, a regular unevenness is present between the electronic component and the wired circuit board due to the two-dimensional arrangement of the mounting reinforcement portions of the second insulating layer.

[0131] When the underfill filled between the electronic component and the wiring circuit board comes into contact with the uneven surface of the second insulating layer and hardens, the adhesive strength between the mounted wiring circuit board and electronic component is strengthened by the anchoring effect, which prevents the electrical component from peeling off from the wiring circuit board after mounting.

[0132] (Item 2) In the printed circuit board according to item 1, The second insulating layer may be formed so that, when the total area of ​​the second insulating layer viewed in the stacking direction is a first area value S1 and the total area of ​​the openings of the multiple mounting reinforcement portions is a second area value S2, the value (S2 / S1) obtained by dividing the second area value S2 by the first area value S1 is 0.01 or more and 0.5 or less.

[0133] In this case, when the value (S2 / S1) is 0.01 or more, mounting of electrical components onto the wiring circuit board using solder becomes easier than when the value (S2 / S1) is less than 0.01. Furthermore, the reliability of the electrical connection between the mounted electrical components and the wiring circuit board is improved. On the other hand, when the value (S2 / S1) is 0.5 or less, a larger contact area of ​​the underfill on the second insulating layer can be ensured than when the value (S2 / S1) is greater than 0.5. Therefore, the adhesion between the wiring circuit board and the electronic components after mounting can be improved.

[0134] (Item 3) In the printed circuit board according to item 1 or 2, the second insulating layer has a second surface exposed in the same direction as the first surface; The film may be formed so that, when the maximum value of the distance between the first surface and the second surface in the stacking direction is a first thickness value T1 and the minimum value of the distance between the first surface and the second surface in the stacking direction is a second thickness value T2, the value (T2 / T1) obtained by dividing the second thickness value T2 by the first thickness value T1 is greater than 0.3 and less than 1.

[0135] In this case, significantly large irregularities are not formed on the second surface of the second insulating layer. This prevents underfill filling defects caused by the underfill being unable to conform to the irregular shape. Furthermore, since significantly large irregularities are not formed on the second surface, the overall thickness of the second insulating layer can be reduced. This allows for a thinner printed circuit board.

[0136] (Item 4) In the wired circuit board according to any one of items 1 to 3, The thickness of the conductor layer in the stacking direction may be 1 μm or more and 20 μm or less.

[0137] The above-mentioned size range is relatively small for the range of thicknesses of conductor layers used in printed circuit boards, and therefore, the printed circuit board can be made thinner and flatter.

[0138] (Item 5) In the wired circuit board according to any one of items 1 to 4, The printed circuit board is Further comprising a metal support; The first insulating layer may be formed on the metal support.

[0139] In this case, the first insulating layer, the conductor layer, and the second insulating layer are each supported by a metal support, which has a relatively high rigidity, thereby suppressing deformation such as warping in the wired circuit board and improving the handleability of the wired circuit board.

[0140] (Item 6) In the wired circuit board according to any one of items 1 to 5, At least one of the first insulating layer and the second insulating layer may be made of a resin containing at least one of polyimide and epoxy.

[0141] In this case, since the dielectric constants of polyimide and epoxy are relatively low, a printed circuit board suitable for transmitting high-frequency signals is realized. Furthermore, polyimide and epoxy have high dimensional stability and high heat resistance. Furthermore, it is relatively easy to match the thermal expansion coefficients of polyimide and epoxy with the conductor layers used in the printed circuit board. Therefore, with the above configuration, deformation such as warping is suppressed. As a result, the reliability of the printed circuit board is improved.

[0142] (Item 7) In the wired circuit board according to any one of items 1 to 6, The conductor layer is a first conductor layer formed directly on the first insulating layer; a plurality of second conductor layers respectively stacked on a plurality of portions of the first conductor layer; The plurality of terminal portions may be formed by a plurality of portions of the first conductor layer and the plurality of second conductor layers.

[0143] In this case, a wiring portion connected to a plurality of terminal portions can be formed by the first conductor layer, and the positions of the exposed portions of the plurality of terminal portions can be made different from the position of the wiring portion in the stacking direction, thereby improving the degree of freedom in the layout of the wiring portion and terminal portions in the printed circuit board.

[0144] (Item 8) In the printed circuit board according to item 7, The thickness of the second conductor layer in the stacking direction may be 1 μm or more and 20 μm or less.

[0145] The above-mentioned size range is relatively small for the range of thicknesses of conductor layers used in printed circuit boards, and therefore, the printed circuit board can be made thinner and flatter.

[0146] (Item 9) In the wired circuit board according to any one of items 1 to 8, The thickness of the plurality of terminal portions in the stacking direction may be smaller than the minimum thickness of the second insulating layer in the stacking direction.

[0147] According to the above configuration, unintended portions of the terminals, excluding the central portions, are prevented from being exposed in the space above the second insulating layer.

[0148] (Item 10) In the wired circuit board according to any one of items 1 to 9, When the distance in the stacking direction between the first surface and the upper end surface of the first annular portion of each mounting reinforcement portion is defined as the reinforcement portion height, the largest height among the multiple reinforcement portion heights corresponding to the multiple mounting reinforcement portions is defined as the reinforcement portion maximum height Hmax, and the smallest height among the multiple reinforcement portion heights is defined as the reinforcement portion minimum height Hmin, the value (Hmin / Hmax) obtained by dividing the reinforcement portion minimum height Hmin by the reinforcement portion maximum height Hmax may be greater than 0.7.

[0149] In this case, the amount of underfill filled between the electrical components and multiple portions of the wiring circuit board when the electrical components are mounted on the wiring circuit board is more uniform than when the value (Hmin / Hmax) is 0.7 or less, which prevents a decrease in adhesion between the mounted wiring circuit board and the electronic components due to a local lack of underfill.

[0150] (Item 11) The electrical component mounting board according to item 11 is A wired circuit board according to any one of items 1 to 10, an electrical element having a plurality of electrical contacts; the electrical element is mounted on the wiring circuit board by connecting the plurality of electrical contacts to the plurality of terminal portions of the wiring circuit board using solder; An underfill is filled between the electrical components and the printed circuit board.

[0151] The electrical component mounting board includes the above-described wiring circuit board, which makes it difficult for the electrical components to peel off from the wiring circuit board.

[0152] (12) The electronic parts related to 12 are: The electrical component mounting board according to claim 10 is provided.

[0153] The electronic component has high reliability because it includes the above-mentioned electrical element mounting board.

[0154] (Item 13) A method for manufacturing a printed circuit board according to item 13 includes: providing a first insulating layer having a first surface; forming a conductor layer having a plurality of terminal portions on the first surface of the first insulating layer; forming a second insulating layer on the first surface of the first insulating layer so as to cover a portion of the conductor layer; the step of forming the conductor layer includes two-dimensionally arranging the plurality of terminal portions so that a predetermined arrangement pattern is repeatedly arranged on the first surface; The step of forming the second insulating layer includes: a coating step of coating a varnish of a thermosetting resin or a thermoplastic resin containing a solvent onto the first surface of the first insulating layer so as to cover the plurality of terminal portions; a pressing step of preparing a pressing member having a flat pressing surface after the application step, and flattening the exposed surface of the varnish by bringing the pressing surface of the pressing member into contact with the exposed surface of the varnish; a heat treatment step of heating the varnish after the pressing step to volatilize the solvent contained in the varnish and harden the varnish; and forming a plurality of openings in the hardened varnish after the heat treatment step so that a central portion of each terminal is exposed and an outer portion surrounding the central portion of each terminal is covered with the varnish.

[0155] In the method for manufacturing the wired circuit board, the exposed surface of the fluidized varnish is flattened in the pressing step when the second insulating layer is formed. At this time, the thickness of the varnish layer formed on the first surface is small in the areas that overlap with the multiple terminal portions (hereinafter referred to as terminal overlapping areas) and is large in the areas that do not overlap with the multiple terminal portions (hereinafter referred to as non-terminal overlapping areas).

[0156] Then, the solvent contained in the varnish is evaporated in a heat treatment process. The amount of solvent evaporating from the terminal-overlapping portions of the varnish layer is less than the amount of solvent evaporating from the non-terminal-overlapping portions of the varnish layer. Therefore, the terminal-overlapping portions shrink at a smaller rate than the non-terminal-overlapping portions. In other words, in the heat treatment process, the non-terminal-overlapping portions shrink more than the terminal-overlapping portions. As a result, the non-terminal-overlapping portions after the heat treatment are formed to be recessed relative to the terminal-overlapping portions. After the heat treatment process, multiple openings are formed so that the central portions of each of the multiple terminal portions are exposed.

[0157] When mounting electrical elements on the wired circuit board completed as described above, the electrical contacts of the electrical elements can be soldered onto the terminal portions through the openings in the second insulating layer.

[0158] When the electrical components are mounted on the wired circuit board, an underfill is filled between the wired circuit board and the electrical components. In the wired circuit board, the plurality of terminal overlapping portions and the plurality of non-terminal overlapping portions surrounding each terminal overlapping portion are formed so as to protrude in the direction toward the first surface of the first insulating layer.

[0159] Each terminal overlapping portion and the non-terminal overlapping portion surrounding that terminal overlapping portion are referred to as a mounting reinforcement portion. In this case, since the multiple mounting reinforcement portions correspond to the multiple terminal portions, the multiple mounting reinforcement portions are arranged two-dimensionally on the first surface so as to be repeatedly arranged in a predetermined arrangement pattern. Therefore, between the electronic component and the printed circuit board, a regular unevenness is present due to the two-dimensional arrangement of the multiple mounting reinforcement portions of the second insulating layer.

[0160] When the underfill filled between the electronic component and the wiring circuit board comes into contact with the uneven surface of the second insulating layer and hardens, the adhesive strength between the mounted wiring circuit board and electronic component is strengthened by the anchoring effect, which prevents the electrical component from peeling off from the wiring circuit board after mounting.

[0161] (Item 14) A method for manufacturing a printed circuit board according to item 14 includes: providing a first insulating layer having a first surface; forming a conductor layer having a plurality of terminal portions on the first surface of the first insulating layer; forming a second insulating layer on the first surface of the first insulating layer so as to cover a portion of the conductor layer; the step of forming the conductor layer includes two-dimensionally arranging the plurality of terminal portions so that a predetermined arrangement pattern is repeatedly arranged on the first surface; The step of forming the second insulating layer includes: a bonding step of bonding a sheet-like member made of a semi-cured thermosetting resin or a thermoplastic resin onto the first surface of the first insulating layer so as to cover the plurality of terminal portions; a pressing step of preparing a pressing member having a flat pressing surface after the attaching step, and flattening the exposed surface of the sheet-like member by bringing the pressing surface of the pressing member into contact with the exposed surface of the sheet-like member; a heat treatment step of heating the sheet-shaped member after the pressing step to volatilize the solvent contained in the sheet-shaped member and harden the sheet-shaped member; After the heat treatment step, a step of forming a plurality of openings in the hardened sheet-like member so that the central portion of each terminal portion is exposed and the outer portions surrounding the central portion of each terminal portion are covered by the sheet-like member is included.

[0162] In the method for manufacturing the wired circuit board, the exposed surface of the semi-cured sheet-like member is flattened in a pressing step during the formation of the second insulating layer, and the thickness of the layer of the sheet-like member formed on the first surface is small in the portions that overlap with the terminal portions (hereinafter referred to as terminal overlapping portions) and large in the portions that do not overlap with the terminal portions (hereinafter referred to as non-terminal overlapping portions).

[0163] Thereafter, the solvent contained in the sheet-like member is volatilized in a heat treatment process. The amount of solvent volatilized from the terminal-overlapping portions of the layer of sheet-like member is less than the amount of solvent volatilized from the non-terminal-overlapping portions of the layer of sheet-like member. Therefore, the terminal-overlapping portions shrink at a smaller rate than the non-terminal-overlapping portions. In other words, in the heat treatment process, the non-terminal-overlapping portions shrink more than the terminal-overlapping portions. As a result, the non-terminal-overlapping portions after the heat treatment are formed to be recessed relative to the terminal-overlapping portions. After the heat treatment process, multiple openings are formed so that the central portions of each of the multiple terminal portions are exposed.

[0164] When mounting electrical elements on the wired circuit board completed as described above, the electrical contacts of the electrical elements can be soldered onto the terminal portions through the openings in the second insulating layer.

[0165] When the electrical components are mounted on the wired circuit board, an underfill is filled between the wired circuit board and the electrical components. In the wired circuit board, the plurality of terminal overlapping portions and the plurality of non-terminal overlapping portions surrounding each terminal overlapping portion are formed so as to protrude in the direction toward the first surface of the first insulating layer.

[0166] Each terminal overlapping portion and the non-terminal overlapping portion surrounding that terminal overlapping portion are referred to as a mounting reinforcement portion. In this case, since the multiple mounting reinforcement portions correspond to the multiple terminal portions, the multiple mounting reinforcement portions are arranged two-dimensionally on the first surface so as to be repeatedly arranged in a predetermined arrangement pattern. Therefore, between the electronic component and the printed circuit board, a regular unevenness is present due to the two-dimensional arrangement of the multiple mounting reinforcement portions of the second insulating layer.

[0167] When the underfill filled between the electronic component and the wiring circuit board comes into contact with the uneven surface of the second insulating layer and hardens, the adhesive strength between the mounted wiring circuit board and electronic component is strengthened by the anchoring effect, which prevents the electrical component from peeling off from the wiring circuit board after mounting. [Explanation of symbols]

[0168] 1... Wired circuit board, 2... Semiconductor chip, 3... Mounting board, 4... Electronic component, 5... Solder, 6... Underfill, 10... Metal support, 11, 21, 40a, 60a, 71... Upper surface, 12, 22, 40b, 72... Lower surface, 19, 99... Through hole, 20... First insulating layer, 30, 90... Conductive layer, 31... Terminal portion, 31a... Lower conductor layer, 31b... Upper conductor layer, 31c... Center, 32... Wiring portion, 38... Plating layer, 39... Seed layer, 40... Second insulating Layer, 41...first annular portion, 42...second annular portion, 49...opening, 51, 52...plating resist layer, 60...varnish, 60s...sheet-like member, 70...third insulating layer, 80...fourth insulating layer, 91...via, 500...roll device, 501...unwinding section, 502...winding section, 510, 520...processing section, D1...first direction, D2...second direction, D3...third direction, R1...unwinding roll, R2...winding roll, US...unit structure

Claims

1. a first insulating layer having a first surface; a conductor layer having a plurality of terminal portions and formed on the first surface of the first insulating layer; a second insulating layer formed on the first surface of the first insulating layer so as to cover a portion of the conductor layer; the plurality of terminal portions are two-dimensionally arranged on the first surface so that a predetermined arrangement pattern is repeatedly arranged; the second insulating layer includes a plurality of mounting reinforcement portions that respectively correspond to the plurality of terminal portions and protrude in a direction in which the first surface faces, Each of the plurality of mounting reinforcement units includes: an opening overlapping the central portion of the corresponding terminal portion when viewed in a stacking direction of the first insulating layer and the second insulating layer so that the central portion of the corresponding terminal portion is exposed; a first annular portion overlapping an outer portion surrounding the central portion of the corresponding terminal portion when viewed in the stacking direction; a second annular portion that surrounds the first annular portion when viewed in the stacking direction and is formed to be recessed with increasing distance from the outer edge of the first annular portion.

2. 2. The wired circuit board according to claim 1, wherein the second insulating layer is formed so that, when a first area value S1 is a total area of ​​the second insulating layer viewed in the stacking direction and a second area value S2 is a total area of ​​the openings of the plurality of mounting reinforcement portions, a value (S2 / S1) obtained by dividing the second area value S2 by the first area value S1 is 0.01 or more and 0.5 or less.

3. the second insulating layer has a second surface exposed in the same direction as the first surface; 3. The wired circuit board according to claim 1, wherein the wired circuit board is formed so that, when a first thickness value T1 is a maximum value of the distance between the first surface and the second surface in the stacking direction and a second thickness value T2 is a minimum value of the distance between the first surface and the second surface in the stacking direction, a value (T2 / T1) obtained by dividing the second thickness value T2 by the first thickness value T1 is greater than 0.3 and less than 1.

4. 3. The printed circuit board according to claim 1, wherein the thickness of the conductor layer in the stacking direction is 1 [mu]m or more and 20 [mu]m or less.

5. Further comprising a metal support; 3. The printed circuit board according to claim 1, wherein said first insulating layer is formed on said metal support.

6. 3. The printed circuit board according to claim 1, wherein at least one of said first insulating layer and said second insulating layer is made of a resin containing at least one of polyimide and epoxy.

7. The conductor layer is a first conductor layer formed directly on the first insulating layer; a plurality of second conductor layers respectively stacked on a plurality of portions of the first conductor layer; 3. The printed circuit board according to claim 1, wherein said plurality of terminal portions are formed by a plurality of portions of said first conductor layer and said plurality of second conductor layers.

8. 8. The printed circuit board according to claim 7, wherein the thickness of the second conductor layer in the stacking direction is 1 [mu]m or more and 20 [mu]m or less.

9. 3. The printed circuit board according to claim 1, wherein the thickness of the plurality of terminals in the stacking direction is smaller than the minimum thickness of the second insulating layer in the stacking direction.

10. 3. The wired circuit board according to claim 1, wherein the distance in the stacking direction between the first surface and an upper end surface of the first annular portion of each mounting reinforcement portion is defined as a reinforcement portion height, the largest height among a plurality of reinforcement portion heights corresponding to the plurality of mounting reinforcement portions is defined as a reinforcement portion maximum height Hmax, and the smallest height among the plurality of reinforcement portion heights is defined as a reinforcement portion minimum height Hmin, and the value (Hmin / Hmax) obtained by dividing the reinforcement portion minimum height Hmin by the reinforcement portion maximum height Hmax is greater than 0.

7.

11. The wired circuit board according to claim 1 or 2; an electrical element having a plurality of electrical contacts; the electrical element is mounted on the wiring circuit board by connecting the plurality of electrical contacts to the plurality of terminal portions of the wiring circuit board using solder; An electric element mounting board, wherein an underfill is filled between the electric element and the printed circuit board.

12. An electronic component comprising the electrical component mounting board according to claim 11.

13. providing a first insulating layer having a first surface; forming a conductor layer having a plurality of terminal portions on the first surface of the first insulating layer; forming a second insulating layer on the first surface of the first insulating layer so as to cover a portion of the conductor layer; the step of forming the conductor layer includes two-dimensionally arranging the plurality of terminal portions so that a predetermined arrangement pattern is repeatedly arranged on the first surface; The step of forming the second insulating layer includes: a coating step of coating a varnish made of a thermosetting resin or a thermoplastic resin containing a solvent onto the first surface of the first insulating layer so as to cover the plurality of terminal portions; a pressing step of preparing a pressing member having a flat pressing surface after the application step, and flattening the exposed surface of the varnish by bringing the pressing surface of the pressing member into contact with the exposed surface of the varnish; a heat treatment step of heating the varnish after the pressing step to volatilize the solvent contained in the varnish and harden the varnish; and after the heat treatment step, forming a plurality of openings in the hardened varnish so that a central portion of each terminal portion is exposed and an outer portion surrounding the central portion of each terminal portion is covered with the varnish.

14. providing a first insulating layer having a first surface; forming a conductor layer having a plurality of terminal portions on the first surface of the first insulating layer; forming a second insulating layer on the first surface of the first insulating layer so as to cover a portion of the conductor layer; the step of forming the conductor layer includes two-dimensionally arranging the plurality of terminal portions so that a predetermined arrangement pattern is repeatedly arranged on the first surface; The step of forming the second insulating layer includes: a bonding step of bonding a sheet-like member made of a semi-cured thermosetting resin or a thermoplastic resin onto the first surface of the first insulating layer so as to cover the plurality of terminal portions; a pressing step of preparing a pressing member having a flat pressing surface after the attaching step, and flattening the exposed surface of the sheet-like member by bringing the pressing surface of the pressing member into contact with the exposed surface of the sheet-like member; a heat treatment step of heating the sheet-shaped member after the pressing step to volatilize the solvent contained in the sheet-shaped member and harden the sheet-shaped member; and forming a plurality of openings in the hardened sheet-like member after the heat treatment step so that a central portion of each terminal portion is exposed and an outer portion surrounding the central portion of each terminal portion is covered by the sheet-like member.

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