Electro-optic device and electronic appliance

Abstract

To narrow the pitch of data lines.SOLUTION: In a case where data lines 14 are arranged along an X direction, a transistor P1 of a transmission gate Trs corresponding to the data line 14 in a certain column is adjacent in the X direction to a transistor N1 of a transmission gate Trs corresponding to the data line 14 adjacent in the X direction to the aforementioned column and the transistor N1 of the transmission gate Trs corresponding to the data line 14 in a certain column is adjacent in the X direction to the transistor P1 of the transmission gate Trs corresponding to the data line 14 adjacent in the X direction to the aforementioned column.SELECTED DRAWING: Figure 8

Description

[Technical Field]

[0001] The present invention relates to an electro-optical device and an electronic device. [Background technology]

[0002] In a demultiplexer-type electro-optical device, data lines are grouped into groups of several lines, and data signals supplied to data signal lines provided corresponding to each group are distributed to each data line by switching elements. In such an electro-optical device, in order to improve the speed at which data signals are written to the data lines, a technology has been proposed in which the switching elements are made up of P-channel transistors and N-channel transistors connected in parallel and complementarily (see Patent Document 1).

[0003] When the above switching elements are connected in parallel, if the characteristics of the P-channel and N-channel transistors, especially the on-resistance, are not uniform, it can cause display unevenness. To align the transistor characteristics, it is possible to adjust the transistor sizes of the P-channel and N-channel types. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Publication No. 2021-140056 Summary of the Invention [Problem to be solved by the invention]

[0005] However, adjusting the transistor size results in wasted space in the transistor arrangement, which poses a problem in that it is not possible to narrow the arrangement pitch of the data lines or to miniaturize the device itself. [Means for solving the problem]

[0006] In order to solve the above problem, an electro-optical device according to one aspect of the present disclosure includes data lines grouped every k (k is an integer of 2 or more), data signal lines from which data signals according to pixel gradations are output corresponding to the k groups, and transmission gates provided in one-to-one correspondence with the data lines, wherein the transmission gates have input terminals connected to the data signal lines and output terminals connected to the data lines, and a conduction state between the input terminals and the output terminals is determined based on a positive logic selection signal and a negative logic selection signal, and the transmission gates include a first transistor of a first conductivity type to whose gate node the positive logic selection signal is supplied, and a second transistor of a second conductivity type to whose gate node the negative logic selection signal is supplied, and the data lines are , a first data line and a second data line adjacent to the first data line in a first direction, the transmission gate includes a first transmission gate provided corresponding to the first data line and a second transmission gate provided corresponding to the second data line, when the arrangement direction of the data lines is defined as a first direction, the first transistor of the first transmission gate is adjacent to the second transistor of the second transmission gate in the first direction, the second transistor of the first transmission gate is adjacent to the first transistor of the second transmission gate in the first direction, and a channel length of the first transistor is different from a channel length of the second transistor. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 is a perspective view showing an electro-optical device according to an embodiment. [Figure 2] FIG. 2 is a block diagram showing the configuration of an electro-optical layer; [Figure 3] FIG. 2 is a diagram illustrating a configuration of a pixel circuit in an electro-optical device. [Figure 4] FIG. 2 is a diagram showing the arrangement of each part in the electro-optical device. [Figure 5] 5A and 5B are diagrams illustrating the operation of the electro-optical device. [Figure 6]FIG. 10 is a diagram showing a transistor arrangement in a transmission gate of an electro-optical device according to a comparative example. [Figure 7] FIG. 1 is a diagram showing an equivalent circuit of a transistor arrangement. [Figure 8] FIG. 3 is a diagram showing a transistor arrangement in a transmission gate of an electro-optical device according to an embodiment. [Figure 9] FIG. 2 is a diagram showing an arrangement of transistors that configure a NOT circuit of an electro-optical device according to an embodiment. [Figure 10] 1 is a diagram showing a projection display device to which an electro-optical device according to an embodiment is applied. DETAILED DESCRIPTION OF THE INVENTION

[0008] Projection display devices according to embodiments will be described below with reference to the drawings. In each drawing, the dimensions and scale of each part are appropriately different from those of the actual device. The embodiments described below are preferred examples, and therefore various technically preferable limitations are applied. However, the scope of the present disclosure is not limited to these embodiments unless otherwise specified in the following description to the effect that the present disclosure is limited.

[0009] FIG. 1 is a perspective view showing the configuration of a module 1 including an electro-optical device 100 according to an embodiment. The electro-optical device 100 is a transmissive liquid crystal panel used, for example, as a light valve in a projection display device. The electro-optical device 100 is housed in a frame-shaped case 72 that opens to a rectangular display area 10. One end of an FPC board 74 is connected to the electro-optical device 100. FPC is an abbreviation for Flexible Printed Circuits. A plurality of terminals 76 are provided on the other end of the FPC board 74, and are connected to a higher-level circuit (not shown).

[0010] The display control circuit 30, which is a semiconductor chip, is mounted on the FPC board 74 by face-down bonding, and video data is supplied from a higher-level circuit in synchronization with a synchronization signal via multiple terminals 76. The video data defines the gradation of pixels in the image to be displayed, for example, in 8 bits.

[0011] In the drawing, the X direction is the longitudinal direction of the display area 10, that is, the direction in which the scanning lines extend, and the Y direction is the lateral direction of the display area 10, that is, the direction in which the data lines extend. When the electro-optical device 100 is used as a light valve in a projection display device, transmitted images from three electro-optical devices 100 corresponding to the primary colors R (red), G (green), and B (blue) are synthesized to display a color image, as will be described later. Therefore, a pixel, which is the smallest unit of a color image, is expressed by additive color mixing of a red subpixel formed by an electro-optical device corresponding to R, a green subpixel formed by an electro-optical device corresponding to G, and a blue subpixel formed by an electro-optical device corresponding to B. However, when it is not necessary to specify the color of the red, green, and blue subpixels or when only brightness is an issue, there is no need to refer to them as subpixels. Therefore, in this explanation, the red, green, and blue subpixels will also be referred to simply as "pixels."

[0012] The synchronization signals include a vertical synchronization signal that instructs the pixels arranged in the display area 10 to start vertical scanning, a horizontal synchronization signal that instructs the pixels to start horizontal scanning, and a clock signal that indicates the timing of one pixel of video data. The display control circuit 30 processes the video data and synchronization signals, and outputs data signals and control signals necessary for driving the electro-optical device 100. The data signals are analog signals obtained by converting the video data, and the control signals are signals for controlling vertical scanning and horizontal scanning in the electro-optical device 100. The display control circuit 30 may be provided in a higher-level circuit, rather than being mounted on the FPC board 74, and may receive video signals and control signals via terminals .

[0013] 2 is a block diagram showing the electrical configuration of the module 1. The module 1 includes the above-described electro-optical device 100 and a display control circuit 30. A scanning line driving circuit 130 and a peripheral circuit 150 are provided on the periphery of the display area 10 of the electro-optical device 100. The electro-optical device 100 is configured by sealing liquid crystal between an element substrate on which thin film transistors and the like are formed and an opposing substrate on which a common electrode is formed, and a scanning line driving circuit 130 and a peripheral circuit 150 are formed on the element substrate.

[0014] In the display region 10 of the electro-optical device 100, pixel circuits 110 corresponding to the pixels of the image to be displayed are arranged in a matrix. More specifically, in the display region 10, m scanning lines 12 are provided extending horizontally in the figure, and a total of (3n) columns of data lines 14, grouped into groups of three, extend vertically in the figure and are provided electrically insulated from the scanning lines 12. Pixel circuits 110 are provided corresponding to the intersections of the m scanning lines 12 and the (3n) data lines 14. Therefore, in this embodiment, the pixel circuits 110 are arranged in a matrix of m rows and (3n) columns.

[0015] Here, m is an integer of 2 or more. n is an integer of 2 or more, but in this embodiment, n is set to 3. An integer i between 1 and m is used to generally describe the rows of the scanning lines 12 and the rows in the matrix-arranged pixel circuits 110. For example, the scanning lines 12 may be referred to as rows 1, 2, 3, ..., (i-1), i, ..., (m-1), and m from top to bottom in the figure. Similarly, an integer j between 1 and n is used to generalize and describe the columns of data lines 14 and the columns of matrix-arranged pixel circuits 110. For example, to distinguish the data lines 14, they may be referred to as columns 1, 2, 3, ..., (3j-2), (3j-1), (3j), ..., (3n-2), (3n-1), and (3n) from left to right in the drawing. For convenience of explanation, the configuration of the pixel circuit 110 will be described with reference to FIG.

[0016] FIG. 3 is a diagram showing an equivalent circuit of four pixel circuits 110 (2×2) corresponding to the intersections of two adjacent scanning lines 12 and two adjacent data lines 14. As shown in the figure, the pixel circuit 110 includes a transistor 116 and a liquid crystal element 120. The transistor 116 is, for example, an N-channel thin film transistor. In the pixel circuit 110, the gate node of the transistor 116 is connected to the scan line 12, the source node is connected to the data line 14, and the drain node is connected to the pixel electrode 118.

[0017] In this description, "connection" means a direct or indirect connection or coupling between two or more elements, and includes, for example, coupling between two or more elements in a semiconductor substrate through different wiring layers and contact holes, even if the elements are not directly connected to each other.

[0018] A common electrode 108 is provided on the opposing substrate in common to all pixels so as to face the pixel electrode 118. The common electrode 108 is maintained at a substantially constant potential LCcom over time. A liquid crystal 105 is sandwiched between the pixel electrode 118 and the common electrode 108. Therefore, for each pixel circuit 110, a liquid crystal element 120 is formed by the pixel electrode 118, the common electrode 108, and the liquid crystal 105. Furthermore, a storage capacitor 109 is provided electrically in parallel with the liquid crystal element 120. One end of the storage capacitor 109 is connected to the pixel electrode 118, and the other end is connected to a capacitance line 107. The capacitance line 107 is maintained at a constant potential over time, for example, the same potential LCcom as the common electrode 108.

[0019] 2, in this embodiment, the (3n) data lines 14 are grouped into groups of 3. The j-th group counting from the left corresponds to the three data lines 14 in the (3j-2)th, (3j-2)th, and (3j)th columns. Furthermore, in the j-th group, the data lines 14 may be described as the first series in the (3j-2)th column, the second series in the (3j-1)th column, and the third series in the (3j)th column. In other words, in the j-th group, the first series of data lines 14 is the (3j-2)th column, the second series of data lines 14 is the (3j-1)th column, and the third series of data lines 14 is the (3j)th column.

[0020] The display control circuit 30 processes the video data and synchronization signals supplied from the higher-level circuit, and outputs control signals to the scanning line driving circuit 130 as well as data signals Vid(1), Vid(2), Vid(3), ..., Vid(n) and selection signals Sel(1) to Sel(3). Data signals Vid(1), Vid(2), Vid(3), . . . , Vid(n) are supplied to the electro-optical device 100 via n data signal lines 13. The data signals Vid(1), Vid(2), Vid(3), ..., Vid(n) will be generally described below. Data signal Vid(j) is a signal that supplies potentials corresponding to the gray levels of three pixels corresponding to the intersections of three data lines 14 belonging to the j-th group and horizontally scanned scanning line 12 in a time-division manner during the horizontal scanning period. The selection signal Sel(1) is a signal for selecting the first series of data lines 14. Similarly, the selection signal Sel(2) is a signal for selecting the second series of data lines 14, and the selection signal Sel(3) is a signal for selecting the third series of data lines 14.

[0021] The scanning line driving circuit 130 supplies scanning signals individually to m rows of scanning lines 12 under the control of the display control circuit 30. Here, the scanning signal supplied to the first scanning line 12 is denoted as Gwr(1), and similarly, the scanning signals supplied to the second, third, ..., (i-1), i, ..., (m-1), and m-th scanning lines 12 are denoted as Gwr(2), Gwr(3), ..., Gwr(i-1), Gwr(i), ..., Gwr(m-1), and Gwr(m), respectively.

[0022] The display control circuit 30 outputs various control signals for controlling the scanning line driving circuit 130, but since the control signals to the scanning line driving circuit 130 are not important in this case, only the signal paths are illustrated and detailed descriptions of the control signals are omitted.

[0023] The peripheral circuit 150 is a circuit that distributes data signals to the data lines 14 in accordance with selection signals Sel(1) to Sel(3). In detail, the peripheral circuit 150 has a transmission gate Trs and NOT circuits Iv1, Iv2, and Iv3 for each column of the data lines 14.

[0024] The transmission gate Trs is an analog switch in which a P-channel transistor P1 and an N-channel transistor N1 are connected in parallel. The transistors P1 and N1 are thin-film transistors similar to the transistor 116 in the pixel circuit 110.

[0025] In the transmission gate Trs corresponding to the jth data line 14 of the first series, the input terminal is connected to the data signal line 13 corresponding to the jth group, and the output terminal is connected to the jth data line of the first series. In the transmission gate Trs corresponding to the j-th data line 14 of the second series, the input terminal is connected to the data signal line 13 corresponding to the j-th group, and the output terminal is connected to the j-th data line of the second series. Similarly, in the transmission gate Trs corresponding to the j-th data line 14 of the third series, the input terminal is connected to the data signal line 13 corresponding to the j-th group, and the output terminal is connected to the j-th data line of the second series. In other words, the input terminals of the transmission gates Trs corresponding to the three data lines 14 belonging to the j-th group are commonly connected to the data signal line 13 corresponding to the j-th group. The output terminals of the transmission gates Trs are connected to the corresponding data lines 14.

[0026] In the j-th group, of the NOT circuits Iv1 and Iv2 corresponding to the first data line 14, the NOT circuit Iv1 inverts the logic level of the selection signal Sel(1) and outputs it, and the NOT circuit Iv2 re-inverts the logic level of the inverted signal by the NOT circuit Iv2 and outputs it. That is, the two NOT circuits Iv1 and Iv2 corresponding to the first data line 14 are buffer circuits that buffer the logic level of the selection signal Sel(1). Note that in the j-th group, the NOT circuit Iv2 corresponding to the first data line 14 supplies the buffered selection signal Sel(1) to the gate node of the transistor N1 in the first transmission gate Trs. In the j-th group, the NOT circuit Iv3 corresponding to the data line 14 of the first series inverts the logic level of the selection signal Sel(1) and supplies it to the gate node of the transistor P1 in the transmission gate Trs of the first series.

[0027] In the jth group, the NOT circuits Iv1 and Iv2 corresponding to the second data line 14 buffer the selection signal Sel(2) and supply it to the gate node of the transistor N1 in the second transmission gate Trs. In the jth group, the NOT circuit Iv3 corresponding to the second data line 14 inverts the logic level of the selection signal Sel(2) and supplies it to the gate node of the transistor P1 in the second transmission gate Trs. In the jth group, the NOT circuits Iv1 and Iv2 corresponding to the third data line 14 buffer the selection signal Sel(3) and supply it to the gate node of the transistor N1 in the transmission gate Trs of that third group. In the jth group, the NOT circuit Iv3 corresponding to the third data line 14 similarly inverts the logic level of the selection signal Sel(3) and supplies it to the gate node of the transistor P1 in the transmission gate Trs of that third group.

[0028] 2 is a diagram showing the electrical configuration of the electro-optical device 100, and in reality, the elements of the electro-optical device 100 are arranged as shown in FIG. If m<3n, the display area 10 has a rectangular shape with the X direction longer than the Y direction. As described above, one end of the FPC board 74 is connected to one longitudinal side of the electro-optical device 100. Between the one end of the FPC board 74 and the display area 10, the peripheral circuit 150 is provided.

[0029] A scanning line driving circuit 130 is provided on each of the two sides of the display area 10 along the Y direction. That is, two scanning line driving circuits 130 are provided, and scanning signals are supplied to the scanning lines 12 from both ends. The reason for this configuration is that the effect of delay in the scanning signal on the display can be reduced compared to when the scanning signal is supplied from only one end. The two scanning line driving circuits 130 are supplied with the same control signal from the display control circuit 30. Although the selection signals Sel(1) to Sel(3) are supplied from one end in FIG. 2, they are supplied from both the left and right ends in order to reduce the effect of delay, as in the case of the scanning signals, as shown in FIG.

[0030] FIG. 5 is a timing chart showing the operation of the electro-optical device 100. As shown in FIG. In the electro-optical device 100, m scanning lines 12 are scanned one by one during a frame (V) period in the order of 1st, 2nd, 3rd, ..., mth rows. In detail, as shown in the figure, the scanning signals Gwr(1), Gwr(2), ..., Gwr(i-1), Gwr(i), ..., Gwr(m-1), Gwr(m) are sequentially and exclusively set to H level by the scanning line driving circuit 130 for each horizontal scanning period (H). In this embodiment, the periods during which adjacent scanning signals Gwr(1) to Gwr(m) are at H level are separated in time. Specifically, after scanning signal Gwr(i-1) changes from H level to L level, the next scanning signal / wr(i) becomes H level after a period. This period corresponds to the horizontal blanking interval.

[0031] In this description, the period of one frame (V) refers to the period required to display one frame of an image specified by video data supplied from a higher-level circuit. If the length of one frame (V) is the same as the vertical synchronization period, for example, if the frequency of the vertical synchronization signal included in the synchronization signal Sync is 60 Hz, it is 16.7 milliseconds, which corresponds to one cycle of the vertical synchronization signal. Furthermore, the horizontal scanning period (H) is the time interval during which the scanning signals Gwr(1) to Gwr(m) sequentially go to H level, but for convenience in the figure, the start timing of the horizontal scanning period (H) is shown approximately in the center of the horizontal blanking period.

[0032] When one of the scanning signals Gwr(1) to Gwr(m), for example the scanning signal Gwr(i) for the ith row, goes high, the transistor 121 of the pixel circuit 110 located in the ith row is turned on. As a result, in the pixel circuit 110, one end of the liquid crystal element 120 and one end of the storage capacitor 109 are electrically connected to the corresponding data line 14. In the case of the pixel circuit 110 in the ith row and (3j-2)th column, one end of the liquid crystal element 120 and one end of the storage capacitor 109 in the pixel circuit 110 are electrically connected to the (3j-2)th column data line 14.

[0033] In this description, the "on state" of a transistor means that the source node and drain node of the transistor are electrically closed, resulting in a low impedance state, and the "off state" of a transistor means that the source node and drain node are electrically open, resulting in a high impedance state.

[0034] During the period in which the scanning signal Gwr(i) is at H level, the selection signals Sel(1), Sel(2), and Sel(3) successively and exclusively become H level. When the selection signal Sel(1) goes high, the output of the NOT circuit Iv2 in the first system goes high and the output of the NOT circuit Iv3 goes low, turning on the transmission gate Trs in the first system. The display control circuit 30 outputs the potentials of the data signals Vid(1), Vid(2), ..., Vid(j), ..., Vid(n) in order according to the gradation of the pixels in the i-th row and the 1st, 4th, ..., (3j-2), ..., (3n-2)th columns, and according to the write polarity.

[0035] Therefore, the data signal Vid(j) is applied to one end of the liquid crystal element 120 and one end of the storage capacitor 109 in the pixel circuit 110 in the i-th row and (3j-2)th column via the data line 14 in the (3j-2)th column. The potential of the data signal Vid(j) applied to one end of the liquid crystal element 120 is maintained by the capacitive nature of the liquid crystal element 120 and the storage capacitance 109 even when the transmission gate Trs in the (3j-2) column is turned off and further when the horizontal scanning period for the i-th row ends and the scanning signal Gwr(i) becomes L level.

[0036] As is well known, in the liquid crystal element 120, the orientation of the liquid crystal molecules changes in response to the electric field generated by the pixel electrode 118 and the common electrode 108. Therefore, the liquid crystal element 120 has a transmittance that corresponds to the effective value of the applied voltage. In this embodiment, the transmittance is minimum when the voltage applied to the liquid crystal element 120 is zero, and the transmittance increases as the applied voltage increases, in a normally black mode.

[0037] The data signal Vid(j) is a potential corresponding to the gradation of the pixel in the i-th row (3j-2) column, and is a potential corresponding to the write polarity. When driving the liquid crystal element 120, AC driving is required to prevent deterioration of the liquid crystal 105. For this reason, a positive potential on the higher side and a negative potential on the lower side relative to the amplitude center potential Vcen are alternately applied to the pixel electrode 118, for example, every one frame (V). The potential Vcen can be considered to be approximately the same potential as the potential LCcom applied to the common electrode 108. This is the range Rng(+) that the positive polarity potential can take. The range Rng(+) is, for example, from the potential Vwt(+) when the gradation is at its highest value to the potential Vbk(+) when the gradation is at its lowest value. This is the range Rng(-) that the negative polarity potential can take. The range Rng(-) is, for example, from the potential Vwt(-) when the gradation is at its highest value to the potential Vbk(-) when the gradation is at its lowest value. Here, the (3j-2)th column of the horizontal scanning of the ith row has been described, but the same operation is similarly performed in the first series of 1st, 4th, 7th, . . . , (3n-2)th columns. The selection signal Sel(1) goes to L level, and then the selection signal Sel(2) goes to H level.

[0038] When the selection signal Sel(2) goes high, the second-system transmission gate Trs is turned on. The display control circuit 30 outputs the data signals Vid(1), Vid(2), ..., Vid(j), ..., Vid(n) in sequence at potentials corresponding to the gradation and write polarity of the pixels in the i-th row and the 2nd, 5th, ..., (3j-1), ..., (3n-1)th columns. As a result, the liquid crystal element 120 of the pixel circuit 110 corresponding to the intersection of the i-th row scanning line and the second-system data line 14 exhibits a transmittance corresponding to the gradation. The selection signal Sel(2) goes to L level, and then the selection signal Sel(3) goes to H level.

[0039] When the selection signal Sel(3) goes high, the third-series transmission gate Trs is turned on. The display control circuit 30 outputs the data signals Vid(1), Vid(2), ..., Vid(j), ..., Vid(n) in sequence at potentials corresponding to the gradation and write polarity of the pixels in the i-th row and the 3rd, 6th, ..., (3j), ..., (3n) columns. As a result, the liquid crystal element 120 of the pixel circuit 110 corresponding to the intersection of the i-th row scanning line and the third-series data line 14 exhibits a transmittance corresponding to the gradation. After this, the selection signal Sel(3) goes low, and horizontal scanning of the i-th row ends.

[0040] Here, horizontal scanning of the i-th row has been described, but similar operations are performed sequentially for horizontal scanning of the 1st, 2nd, 3rd, . . . , mth rows. When horizontal scanning of the m-th row is completed, the next frame period begins, and horizontal scanning resumes from row 1. During the next frame period, the display control circuit 30 inverts the potential polarity of the data signal.

[0041] Even if the transmission gate Trs is replaced with only one transistor, either transistor P1 or N1, it is still possible to write, i.e., transmit, the data signal supplied to the data signal line 13 to the data line 14.

[0042] However, in such a configuration, for example, transistor N1 alone has a high resistance value in the on state, and from the perspective of the time constant, the data signal supplied to data signal line 13 cannot be written sufficiently to data line 14. Furthermore, in the transistor P1 or N1, if the potential difference between the gate node and the source node is small, it becomes more difficult for the data signal supplied to the data signal line 13 to be written to the data line than when the potential difference is large. Specifically, in the case of transistor N1, the more positive the data signal is and the closer it is to a high gradation potential, i.e., potential Vwt(+), the smaller the potential difference between the gate node and source node, and therefore the less sufficient the data signal is written to the data line 14. Conversely, in the case of transistor P1, the more negative the data signal is and the closer it is to a high gradation potential, i.e., potential Vwt(-), the less sufficient the data signal is written to the data line 14.

[0043] If the element that writes the data signal supplied to the data signal line 13 to the data line 14 is only one of the transistors P1 and N1, not only will the writing be insufficient, but there will also be problems with display unevenness due to differences in polarity. This problem becomes more pronounced when a data signal is distributed to many data lines 14 in a limited period of time, that is, when a high resolution is desired.

[0044] Therefore, in this embodiment, the element that writes the data signal supplied to the data signal line 13 to the data line 14 is configured by a transmission gate Trs in which the transistors P1 and N1 are connected in parallel and complementary to each other, as described above. In the transmission gate Trs, transistors P1 and N1 are turned on simultaneously, so the on-resistance is roughly half that of a configuration in which only one transistor is used. Also, in the transmission gate Trs, transistor P1 compensates for insufficient writing to transistor N1 at high gradation potentials when the data signal is positive. Conversely, transistor N1 compensates for insufficient writing to transistor P1 at high gradation potentials when the data signal is negative. For this reason, using the transmission gate Trs also reduces display unevenness caused by differences in polarity. Thus, in order to achieve high resolution, it is considered preferable to configure the switching element that writes the data signal supplied to the data signal line 13 onto the data line 14 with the transmission gate Trs.

[0045] Next, we will consider the problems that arise when the switching element is configured as a transmission gate Trs. It is desirable that the characteristics, especially the on-resistance, of the transistors P1 and N1 that make up the transmission gate Trs are the same. When the transistors P1 and N1 are designed according to the same design rules, specifically when the channel length and channel width are designed to be the same, it is known that it is difficult to match the characteristics of the transistors P1 and N1 by adjusting the process conditions alone. For this reason, adjustment of the transistor sizes of transistors P1 and N1 was considered. Specifically, for example, if the characteristics of transistor P1 are inferior to those of transistor N1, a design could be considered in which the channel length of transistor P1 is made shorter than the channel length of transistor P1.

[0046] Next, in such a design, a case will be considered where the transistors P1 and N1 are arranged in correspondence with the data lines 14. The transistors P1 and N1 must be provided in one-to-one correspondence with the data lines 14. Furthermore, since the data signal lines 13 and 14 extend in the Y direction, the gate nodes, source nodes, drain nodes, and wiring connected to these in the transistors P1 and N1 should preferably be configured to extend in the Y direction. For this reason, the following arrangement was considered for the transistors P1 and N1 that make up a certain row of transmission gates Trs.

[0047] FIG. 6 is a plan view showing the arrangement of transistors P1 and N1 of a transmission gate Trs in an electro-optical device according to a comparative example. In the comparative example, the transistors P1 and N1 that configure the transmission gate Trs are arranged along the Y direction, which is the direction in which the data signal lines 13 and 14 extend, and such transmission gates Trs are arranged along the X direction.

[0048] In the comparative example, transistor P1 is configured with two P-channel transistors connected in parallel. Specifically, as shown in Figure 7, two P-channel transistors are connected in parallel, with one of the source node or the drain node shared and the other of the source node or the drain node independent. Similarly, transistor N1 is configured with two N-channel transistors connected in parallel.

[0049] In Figures 6 and 7, in order to clearly show the arrangement of transistors P1 and N1, the semiconductor layers Act of transistors P1 and N1 are shown as independent islands, but they may be configured to extend in the X direction or to be solid on one surface. In addition, in order to clearly explain the arrangement of the transistors, wiring and the like connected to the gate, source, and drain nodes are omitted from FIGS. 6 and 7, as well as FIGS. 8 and 9 described later.

[0050] If the characteristics of the transistor P1 are inferior to those of the transistor N1, then as described above, the transistor sizes are designed so that the channel length Lp of the transistor P1 is shorter than the channel length Ln of the transistor N1. In such a design, consider the case where the transistors P1 and N1 of a certain transmission gate Trs are arranged along the Y direction, and further, this transmission gate Trs is provided in one-to-one correspondence with the data lines 14 along the X direction. In this case, it is necessary to ensure a clearance Clr determined by the design rule between transistors N1 adjacent to each other in the X direction, and therefore the pitch Px2 of the data lines 14 is determined by the channel length Ln of the transistor N1.

[0051] 7, the pitch Px2 of the data lines 14 is determined by the channel length Ln of the transistor N1, which means that it is not possible to achieve narrower pitches or smaller sizes. On the other hand, the transistors P1 adjacent to each other in the X direction are arranged at intervals greater than the clearance Clr, which means that wasted space is generated. 7, the channel width Wp of the transistor P1 is the same as the channel width Wn of the transistor N1. The channel widths Wp and Wn do not affect the pitch Px2 of the data lines 14. To solve the above problem, in this embodiment, the transistors P1 and N1 are arranged as follows.

[0052] FIG. 8 is a diagram showing the arrangement of the transistors P1 and N1 that configure the transmission gate Trs in the electro-optical device 100 according to this embodiment. 6 in that the transistors P1 and N1 of the transmission gates Trs of a certain column are arranged along the Y direction. However, in this embodiment, the transistor P1 of the transmission gates Trs corresponding to the data line 14 of a certain column is adjacent to the transistor N1 of the transmission gates Trs corresponding to the data line 14 adjacent to that data line 14 in the X direction. Furthermore, the transistor N1 of the transmission gates Trs corresponding to a certain data line 14 is adjacent to the transistor P1 of the transmission gates Trs corresponding to the data line 14 adjacent to that data line 14 in the X direction. In other words, if the transistors P1 and N1 are arranged in this order along the Y direction in the transmission gate Trs corresponding to the data line 14 of a certain column, then the transistors N1 and P1 are arranged in the opposite order along the Y direction in the transmission gate Trs corresponding to the data line 14 adjacent to that data line 14 in the X direction.

[0053] For this reason, in this embodiment, the clearance between a transistor P1 and a transistor N1 adjacent to the transistor P1 in the X direction, and the clearance between a transistor N1 and a transistor P1 adjacent to the transistor N1 in the X direction can both be set to the same value Clr. Therefore, the pitch Px1 of the data lines 14 in this embodiment can be made narrower than the pitch Px2 in the comparative example, and therefore it is possible to accommodate a narrower pitch or a smaller size compared to the comparative example. For example, even if the pitch Px1 of the data lines 14 in this embodiment is only about 0.2 μm smaller than the pitch Px2 of the data lines 14 in the comparative example, if the number of data lines 14 is 1920, the length in the X direction in the display area 10 can be shortened by about 0.38 mm compared to the comparative example, which is a large difference in terms of a microdisplay.

[0054] 8, the arrangement of the transistors P1 and N1 that constitute the transmission gate Trs has been described. However, the present invention is not limited to this, and a similar arrangement can be applied to the P-channel transistors and N-channel transistors that constitute the NOT circuits Iv1, Iv2, and Iv3, respectively.

[0055] 9 is a plan view showing an example of the arrangement of P-channel transistors and N-channel transistors that respectively constitute the NOT circuits Iv1, Iv2, and Iv3. In this example, the NOT circuits Iv3, Iv2, and Iv1 are arranged in this order in the Y direction, starting from the transmission gate Trs.

[0056] As is well known, an inverter such as the NOT circuit Iv1 has a configuration in which a P-channel transistor P11 and an N-channel transistor N11 are connected in series between the power supply voltage. The NOT circuit Iv2 has a similar configuration in which a P-channel transistor P21 and an N-channel transistor N21 are connected in series between the power supply voltage. The NOT circuit Iv3 has a similar configuration in which a P-channel transistor P31 and an N-channel transistor N31 are connected in series between the power supply voltage.

[0057] The transistor P11 of the NOT circuit Iv1 corresponding to a certain column of data lines 14 is adjacent to the transistor N11 of the NOT circuit Iv1 corresponding to the data line 14 adjacent to that data line 14 in the X direction. Furthermore, the transistor N11 of the NOT circuit Iv1 corresponding to a certain column of data lines 14 is adjacent to the transistor P11 of the NOT circuit Iv1 corresponding to the data line 14 adjacent to that data line 14 in the X direction.

[0058] Similarly, the transistor P21 of the NOT circuit Iv2 corresponding to a certain column of data lines 14 is adjacent to the transistor N21 of the NOT circuit Iv2 corresponding to the data line 14 adjacent to that data line 14 in the X direction. Furthermore, the transistor N21 of the NOT circuit Iv2 corresponding to a certain column of data lines 14 is adjacent to the transistor P21 of the NOT circuit Iv2 corresponding to the data line 14 adjacent to that data line 14 in the X direction.

[0059] Similarly, the transistor P31 of the NOT circuit Iv3 corresponding to a certain column of data lines 14 is adjacent to the transistor N31 of the NOT circuit Iv3 corresponding to the data line 14 adjacent to that data line 14 in the X direction. Furthermore, the transistor N31 of the NOT circuit Iv3 corresponding to a certain column of data lines 14 is adjacent to the transistor P31 of the NOT circuit Iv3 corresponding to the data line 14 adjacent to that data line 14 in the X direction.

[0060] The reason why the channel widths of the transistors P11 and N11 in the NOT circuit Iv1 are narrower than the channel widths of the transistors P21 and N21 in the NOT circuit Iv2 is as follows: More specifically, the NOT circuit Iv2 is a main amplifier that amplifies and supplies one of the selection signals Sel(1) to Sel(3) to the gate node of the transistor N1, while the NOT circuit Iv1 is a preamplifier that precedes the NOT circuit Iv2. The NOT circuit Iv3 is a main amplifier that amplifies and supplies the inverted signal of one of the selection signals Sel(1) to Sel(3) to the gate node of the transistor P1. For this reason, the channel widths of the transistors P31 and N31 in the NOT circuit Iv3 are approximately the same as the channel widths of the transistors P11 and N11 in the NOT circuit Iv1 of the same main amplifier.

[0061] The channel lengths of the transistors P11, P21, and P31 are aligned with the channel length Lp of the transistor P1, and the channel lengths of the transistors N11, N21, and N31 are aligned with the channel length Ln of the transistor N1. In this way, the NOT circuits Iv1, Iv2, and Iv3 can be arranged at the pitch Px2 of the data lines 14, similar to the transmission gate Trs.

[0062] Of the NOT circuits Iv1, Iv2, and Iv3, if the driving capability of the display control circuit 30 is high, the NOT circuits Iv1 and Iv2 that buffer the selection signals Sel(1) to Sel(3) are not necessarily required. In other words, by providing the NOT circuits Iv1 and Iv2, high driving capability is not required of the display control circuit 30. Furthermore, if the display control circuit 30 supplies inverted signals of the selection signals Sel(1) to Sel(3), the NOT circuit Iv3 is not necessary.

[0063] The P-channel type is an example of a "first conductivity type," the transistor P1 is an example of a "first transistor," the N-channel type is an example of a "second conductivity type," and the transistor N1 is an example of a "second transistor." The data line 14 in the (3j-2)th column is an example of a “first data line,” and the data line 14 in the (3j-1)th column is an example of a “second data line.” The transmission gate Trs in the (3j-2)th column is an example of a “first transmission gate,” and the transmission gate Trs in the (3j-1)th column is an example of a “second transmission gate.” The X direction is an example of a "first direction," and the Y direction is an example of a "second direction." The NOT circuit Iv2 is an example of a “first NOT circuit,” the transistor P21 is an example of a “third transistor,” and the transistor N21 is an example of a “fourth transistor.” The NOT circuit Iv3 is an example of a “second NOT circuit,” the transistor P31 is an example of a “fifth transistor,” and the transistor N31 is an example of a “sixth transistor.”

[0064] In the embodiment, in the transmission gate Trs, assuming that the characteristics of the transistor P1 are inferior to the characteristics of the transistor N1, the channel length Lp of the transistor P1 is configured to be shorter than the channel length Ln of the transistor N1. If the characteristics of the transistor N1 are inferior to the characteristics of the transistor P1, the channel length Ln of the transistor N1 should be made shorter than the channel length Lp of the transistor P1.

[0065] In the embodiment, the number k of data lines 14 constituting one group is described as "3", but it may be "2" or an integer equal to or greater than "4".

[0066] 9, the arrangement of the NOT circuits Iv1, Iv2, and Iv3 starting from the transmission gate Trs is merely an example. For example, the NOT circuits Iv3, Iv2, and Iv1 may be arranged in this order starting from the transmission gate Trs. The electro-optical device 100 according to the embodiment is a transmissive type, but may be a reflective type.

[0067] Next, a projection display device will be described as an example of an electronic device to which the electro-optical device 100 according to the embodiment is applied.

[0068] 10 is a diagram showing the optical configuration of a projection display device 200. As shown in the figure, the projection display device 200 includes electro-optical devices 100R, 100G, and 100B.

[0069] A lamp unit 2102 consisting of a white light source such as a halogen lamp or an LED is provided inside the projection display device 200. The projection light emitted from this lamp unit 2102 is separated into three primary colors, red (R), green (G), and blue (B), by three mirrors 2106 and two dichroic mirrors 2108 arranged inside. Of these, the R light enters the electro-optical device 100R, the G light enters the electro-optical device 100G, and the B light enters the electro-optical device 100B. Since the optical path of B is longer than the optical paths of R and G, it is necessary to prevent loss in the optical path of B. For this reason, a relay lens system 2121 consisting of an input lens 2122, a relay lens 2123, and an output lens 2124 is provided in the optical path of B.

[0070] The electro-optical devices 100R, 100G, and 100B are common to the electro-optical device 100 according to the embodiment, but because the colors of the incident light are different, they are distinguished by symbols for convenience. The liquid crystal elements of the electro-optical device 100R are driven based on a data signal corresponding to R supplied from a higher-level device, and have a transmittance that corresponds to the voltage of the data signal. Therefore, in the electro-optical device 100R, an R transmission image is generated by individually controlling the transmittance of the liquid crystal elements. Similarly, in the electro-optical device 100G, a G transmission image is generated based on a data signal corresponding to G, and in the electro-optical device 100B, a B transmission image is generated based on a data signal corresponding to B.

[0071] The transmitted images of each color generated by the electro-optical devices 100R, 100G, and 100B are incident on the dichroic prism 2112 from three directions. In the dichroic prism 2112, the R and B light are refracted at 90 degrees, while the G light travels straight. Therefore, the dichroic prism 2112 combines the images of each color. The combined image formed by the dichroic prism 2112 is incident on the projection lens 2114. The projection lens 2114 enlarges and projects the combined image onto the screen Scr.

[0072] The transmission images of the electro-optical devices 100R and 100B are projected after being reflected by the dichroic prism 2112, whereas the transmission image of the electro-optical device 100G is projected in a straight line. Therefore, the transmission images of the electro-optical devices 100R and 100B are left-right inverted relative to the transmission image of the electro-optical device 100G.

[0073] Furthermore, although a projection display device 200 has been used as an example of an electronic device here, the present invention is not limited to this and can also be applied to, for example, the display panel of a head-mounted display, an electronic viewfinder in a video camera or a digital camera with interchangeable lenses, a personal digital assistant, a display part of a wristwatch, and the like.

[0074] From the above-described exemplary embodiments, the following aspects can be understood, for example.

[0075] In order to solve the above problem, an electro-optical device according to one aspect of the present disclosure includes data lines grouped every k (k is an integer of 2 or more), data signal lines from which data signals according to pixel gradations are output corresponding to the k groups, and transmission gates provided in one-to-one correspondence with the data lines, wherein the transmission gates have input terminals connected to the data signal lines and output terminals connected to the data lines, and a conduction state between the input terminals and the output terminals is defined based on a positive logic selection signal and a negative logic selection signal, and the transmission gates include a first transistor of a first conductivity type to whose gate node the positive logic selection signal is supplied, and a second transistor of a second conductivity type to whose gate node the negative logic selection signal is supplied. the data lines include a first data line and a second data line adjacent to the first data line in a first direction, the transmission gates include a first transmission gate provided corresponding to the first data line and a second transmission gate provided corresponding to the second data line, when the arrangement direction of the data lines is defined as a first direction, the first transistor of the first transmission gate is adjacent to the second transistor of the second transmission gate in the first direction, the second transistor of the first transmission gate is adjacent to the first transistor of the second transmission gate in the first direction, and a channel length of the first transistor is different from a channel length of the second transistor.

[0076] In the electro-optical device according to the first aspect, the elements that write the data signals supplied to the data signal lines are transmission gates, which not only enables sufficient writing but also reduces the occurrence of display unevenness due to differences in polarity. Furthermore, by devising the transistor arrangement of the transmission gates, it becomes easier to achieve high resolution.

[0077] In the electro-optical device according to a second specific aspect of the first aspect, the channel length of the first transistor is shorter than the channel length of the second transistor.

[0078] In an electro-optical device according to a specific aspect 3 of aspect 1, when the extension direction of the data lines is defined as a second direction, the first transistor and the second transistor of the first transmission gate corresponding to the first data line are arranged along the second direction, and the second transistor and the first transistor of the second transmission gate corresponding to the second data line are arranged along the second direction.

[0079] An electro-optical device according to a specific embodiment 4 of embodiment 1 includes a first NOT circuit that supplies the positive logic selection signal to a gate node of the first transistor, the first NOT circuit including a third transistor of the first conductivity type and a fourth transistor of the second conductivity type, the third transistor of the first NOT circuit corresponding to the first data line being adjacent to the fourth transistor of the first NOT circuit corresponding to the second data line in the first direction, and the fourth transistor of the first NOT circuit corresponding to the first data line being adjacent to the third transistor of the first NOT circuit corresponding to the second data line in the first direction. Note that a transistor being adjacent to another transistor in the first direction means that a part or all of the one transistor overlaps a part or all of the other transistor when viewed in the first direction.

[0080] An electro-optical device according to a specific embodiment 5 of embodiment 1 includes a second NOT circuit that supplies the negative logic selection signal to a gate node of the second transistor, the second NOT circuit including a fifth transistor of the first conductivity type and a sixth transistor of the second conductivity type, the fifth transistor of the second NOT circuit corresponding to the first data line being adjacent to the sixth transistor of the second NOT circuit corresponding to the second data line in the first direction, and the sixth transistor of the second NOT circuit corresponding to the first data line being adjacent to the fifth transistor of the second NOT circuit corresponding to the second data line in the first direction.

[0081] An electronic device according to a sixth aspect includes the electro-optical device according to any one of the first to fifth aspects. [Explanation of symbols]

[0082] 1...projection display device, 100...electro-optical device, 110...pixel circuit, 118...pixel electrode, 120...liquid crystal element, 30...display control circuit, Trs...transmission gate, Iv1, Iv2, Iv3...NOT circuit, P1, P11, P21, P31, N1, N11, N21, N31...transistors.

Claims

1. data lines grouped in k units (k is an integer equal to or greater than 2); data signal lines to which data signals corresponding to the gradations of pixels are output in correspondence with the groups of k lines; transmission gates provided in one-to-one correspondence with the data lines; and The transmission gate is an input terminal connected to the data signal line, an output terminal connected to the data line, and a conduction state between the input terminal and the output terminal defined based on a positive logic selection signal and a negative logic selection signal; a first transistor of a first conductivity type, the gate node of which is supplied with the positive logic selection signal; and a second transistor of a second conductivity type, the gate node of which is supplied with the negative logic selection signal; Including, The data line is a first data line and a second data line adjacent to the first data line in a first direction; The transmission gate is a first transmission gate provided corresponding to the first data line; a second transmission gate provided corresponding to the second data line; Including, When the arrangement direction of the data lines is defined as a first direction, the first transistor of the first transmission gate is adjacent to the second transistor of the second transmission gate in the first direction; the second transistor of the first transmission gate is adjacent to the first transistor of the second transmission gate in the first direction; The channel length of the first transistor is different from the channel length of the second transistor. Electro-optical device.

2. The channel length of the first transistor is shorter than the channel length of the second transistor. The electro-optical device according to claim 1 .

3. When the extending direction of the data line is defined as a second direction, the first transistor and the second transistor of the first transmission gate corresponding to the first data line are arranged along the second direction; The second transistor and the first transistor of the second transmission gate corresponding to the second data line are arranged along the second direction. The electro-optical device according to claim 1 .

4. a first NOT circuit that supplies the positive logic selection signal to a gate node of the first transistor; The first NOT circuit is a third transistor of the first conductivity type and a fourth transistor of the second conductivity type; Including, the third transistor of the first NOT circuit corresponding to the first data line is adjacent to the fourth transistor of the first NOT circuit corresponding to the second data line in the first direction; The fourth transistor of the first NOT circuit corresponding to the first data line is adjacent to the third transistor of the first NOT circuit corresponding to the second data line in the first direction. The electro-optical device according to claim 1 .

5. a second NOT circuit that supplies the negative logic selection signal to a gate node of the second transistor; The second NOT circuit is a fifth transistor of the first conductivity type and a sixth transistor of the second conductivity type; Including, the fifth transistor of the second NOT circuit corresponding to the first data line is adjacent to the sixth transistor of the second NOT circuit corresponding to the second data line in the first direction; The sixth transistor of the second NOT circuit corresponding to the first data line is adjacent to the fifth transistor of the second NOT circuit corresponding to the second data line in the first direction. The electro-optical device according to claim 1 .

6. 6. An electronic device comprising the electro-optical device according to claim 1.

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