Reference voltage source

Abstract

To provide a reference voltage source unsusceptible to a manufacturing variance.SOLUTION: A first transistor M1 is an enhancement-mode n-channel MOSFET whose source is connected to a ground line VSS and whose gate and drain are connected to an output node VREF. A second transistor M2 is a depletion-mode n-channel MOSFET whose drain is connected to a power supply line VDD and whose gate, source, and back gate are connected to the output node VREF. A reference voltage Vref that is an output of a reference voltage source 100 is fed back to a back-gate voltage adjustment circuit 110. A bias voltage Vsb1 that has a positive correlation with the reference voltage Vref is supplied to the back gate of the first transistor M1.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present disclosure relates to a reference voltage source. [Background technology]

[0002] Various semiconductor integrated circuits incorporate reference voltage sources, which are circuits that generate a reference voltage that is independent of the power supply voltage and temperature. A typical example of such a circuit is a bandgap reference circuit. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2007-188245

[0004] [overview] The present disclosure has been made in this situation, and one exemplary purpose of an embodiment thereof is to provide a reference voltage source that is less susceptible to manufacturing variations.

[0005] A reference voltage source according to an embodiment of the present disclosure includes a power supply line, a ground line, an output node, a first transistor that is an enhancement-type N-channel MOSFET (Metal Oxide Semiconductor Field Effect Transistor) having a source connected to the ground line and a gate and a drain connected to the output node, a second transistor that is a depletion-type N-channel MOSFET having a drain connected to the power supply line and a gate, a source, and a backgate connected to the output node, and a backgate voltage adjustment circuit that supplies a bias voltage to the backgate of the first transistor that has a positive correlation with a reference voltage generated at the output node.

[0006] Another aspect of the present disclosure is also a reference voltage source. The reference voltage source includes a power supply line, a ground line, an output node, a first transistor that is an enhancement-type N-channel MOSFET (Metal Oxide Semiconductor Field Effect Transistor) having a source connected to the ground line and a gate and a drain connected to the output node, a second transistor that is a depletion-type N-channel MOSFET having a drain connected to the power supply line and a gate, a source, and a backgate connected to the output node, and a third transistor that is a depletion-type N-channel MOSFET having a gate connected to the output node. A bias voltage corresponding to the source voltage of the third transistor is supplied to the backgate of the first transistor.

[0007] Any combination of the above components, or mutual substitution of the components or expressions of the present disclosure between methods, devices, systems, etc., are also valid aspects of the present invention. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a circuit diagram illustrating a reference voltage source according to a comparative technique. [Figure 2] FIG. 2 is a diagram showing the characteristics (simulation results) of the reference voltage source of FIG. [Figure 3] FIG. 3 is a circuit diagram of a reference voltage source according to the embodiment. [Figure 4] FIG. 4 is a circuit diagram of a reference voltage source according to the first embodiment. [Figure 5] FIG. 5 is a diagram showing the characteristics (simulation results) of the reference voltage source of FIG. [Figure 6] FIG. 6 is a diagram illustrating an example of optimizing the temperature coefficients of the first resistor and the second resistor. [Figure 7] FIG. 7 is a circuit diagram of a reference voltage source according to the third embodiment. [Figure 8] FIG. 8 is a diagram showing the characteristics (simulation results) of the reference voltage source of FIG.

[0009] [Detailed explanation] (Outline of the embodiment) A summary of some exemplary embodiments of the present disclosure is provided. This summary is intended to provide a simplified overview of some concepts of one or more embodiments in order to provide a basic understanding of the embodiments as a prelude to the more detailed description that follows. It is not intended to limit the scope of the invention or disclosure. This summary is not an exhaustive overview of all possible embodiments, and is not intended to identify key elements of all embodiments or to delineate the scope of some or all aspects. For convenience, the term "one embodiment" may refer to one embodiment (example or variant) or multiple embodiments (examples or variants) disclosed herein.

[0010] A reference voltage source according to one embodiment includes a power supply line, a ground line, an output node, a first transistor which is an enhancement-type N-channel MOSFET (Metal Oxide Semiconductor Field Effect Transistor) having a source connected to the ground line and a gate and a drain connected to the output node, a second transistor which is a depletion-type N-channel MOSFET having a drain connected to the power supply line and a gate, a source, and a backgate connected to the output node, and a backgate voltage adjustment circuit which supplies a bias voltage to the backgate of the first transistor, the bias voltage having a positive correlation with a reference voltage generated at the output node.

[0011] The threshold voltage of a MOSFET varies depending on the potential difference between the backgate voltage and the source voltage, a phenomenon known as the body bias effect. With the above configuration, when the reference voltage increases, the bias voltage supplied to the backgate of the first transistor increases, causing the threshold voltage of the first transistor to decrease due to the body bias effect, resulting in a feedback effect that lowers the reference voltage. Conversely, when the reference voltage decreases, the bias voltage supplied to the backgate of the first transistor decreases, causing the threshold voltage of the first transistor to increase due to the body bias effect, resulting in a feedback effect that raises the reference voltage. In this way, with the above configuration, the body bias effect of the first transistor can be used to suppress variations in the reference voltage.

[0012] In one embodiment, the back-gate voltage adjustment circuit may include a third transistor that is a depletion-type N-channel MOSFET whose gate is connected to the output node and that outputs a bias voltage corresponding to a source voltage of the third transistor, which operates as a source follower and can generate a bias voltage that tracks a reference voltage.

[0013] In one embodiment, the back-gate voltage adjusting circuit further includes a first resistor and a second resistor connected in series between the source of the third transistor and a ground line, and a voltage at a connection node between the first resistor and the second resistor may be a bias voltage. A voltage division ratio between the first resistor and the second resistor may be a circuit constant that defines a feedback gain to the back-gate of the first transistor.

[0014] In one embodiment, the first resistor and the second resistor may have different temperature coefficients. By optimizing the temperature coefficients of the first resistor and the second resistor, the reference voltage V ref The temperature characteristics can be made closer to flat.

[0015] In one embodiment, the back-gate voltage adjustment circuit may further include a stabilization circuit that adjusts the voltage between the back-gate and source of the third transistor in accordance with the currents flowing through the first and second transistors. This configuration makes it possible to adjust the potential difference between the back-gate voltage and the source voltage of the third transistor, suppress variations in the gate-source voltage of the third transistor due to the substrate bias effect, and further stabilize the reference voltage.

[0016] In one embodiment, the stabilization circuit may include a fourth transistor having a gate that receives a reference voltage, a source that is connected to a ground line, and a back gate that receives a bias voltage, a third resistor connected between the back gate and source of the third transistor, and a current mirror circuit that mirrors the current flowing through the fourth transistor and supplies it to the third resistor.

[0017] A reference voltage source according to one embodiment includes a power supply line, a ground line, an output node, a first transistor that is an enhancement-type N-channel MOSFET (Metal Oxide Semiconductor Field Effect Transistor) having a source connected to the ground line and a gate and a drain connected to the output node, a second transistor that is a depletion-type N-channel MOSFET having a drain connected to the power supply line and a gate, a source, and a backgate connected to the output node, and a third transistor that is a depletion-type N-channel MOSFET having a gate connected to the output node. A bias voltage corresponding to the source voltage of the third transistor is supplied to the backgate of the first transistor.

[0018] In one embodiment, the reference voltage source may further include a first resistor and a second resistor connected in series between the source of the third transistor and a ground line, and a voltage at a connection node between the first resistor and the second resistor may be a bias voltage.

[0019] In one embodiment, the reference voltage source may further include a fourth transistor having a gate that receives the reference voltage generated at the output node, a source that is connected to the ground line, and a back gate that receives a bias voltage, a third resistor connected between the back gate and source of the third transistor, and a current mirror circuit that mirrors the current flowing through the fourth transistor and supplies it to the third resistor.

[0020] (Embodiment) Preferred embodiments will be described below with reference to the drawings. The same or equivalent components, parts, and processes shown in each drawing will be given the same reference numerals, and redundant explanations will be omitted as appropriate. Furthermore, the embodiments are examples and do not limit the disclosure and invention, and all features and combinations thereof described in the embodiments are not necessarily essential to the disclosure and invention.

[0021] In this specification, "a state in which component A is connected to component B" includes not only a case in which component A and component B are directly physically connected to each other, but also a case in which component A and component B are indirectly connected to each other via other components that do not substantially affect the electrical connection between them or that do not impair the function or effect achieved by their connection.

[0022] Similarly, "a state in which component C is connected (provided) between component A and component B" includes not only a case in which component A and component C, or component B and component C, are directly connected, but also a case in which they are indirectly connected via other components that do not substantially affect the electrical connection state between them or that do not impair the function or effect achieved by their combination.

[0023] In addition, in this specification, symbols attached to electrical signals such as voltage signals and current signals, or circuit elements such as resistors, capacitors, and inductors, represent the respective voltage values, current values, or circuit constants (resistance values, capacitance values, inductances) as necessary.

[0024] First, the basic configuration of the reference voltage source will be described.

[0025] 1 is a circuit diagram illustrating a reference voltage source 100R according to a comparative technique. The reference voltage source 100R includes a first transistor M91 and a second transistor M92. The first transistor M91 and the second transistor M92 are N-channel MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) stacked vertically between a power supply line VDD and a ground line VSS. The first transistor M91 is an enhancement type, and the second transistor M92 is a depletion type. In this specification, depletion type transistors are indicated by thicker gate electrodes in their circuit symbols.

[0026] The reference voltage source 100R sets the voltage at the connection node between the second transistor M92 and the first transistor M91, i.e., the voltage at the source of the second transistor M92 and the drain of the first transistor M91, to a reference voltage V ref Output as

[0027] The above is the configuration of the reference voltage source 100R. Next, its operation will be described.

[0028] The condition for the second transistor M92 to operate in the saturation region is expressed by equation (1). V ds2 >V gs2 -V th2 …(1) V ds2 : Drain-source voltage of second transistor M92 V gs2 : Gate-source voltage of second transistor M92 V th2 : Threshold voltage of the second transistor M92

[0029] The gate and back gate of the second transistor M92 are connected to the source, and the gate-source voltage V gs2 is always 0 V, the condition under which the second transistor M92 operates in the saturation region is expressed by equation (2). V ds2 >-Vth2 …(2)

[0030] The second transistor M92 is a depletion type transistor with a threshold voltage V th2 is a negative voltage (for example, about -0.5V), so V ds2 At >0.5V, a constant current flows through the second transistor M92.

[0031] On the other hand, the drain-source voltage V of the second transistor M92 ds2 is expressed by equation (3). V ds2 =V dd -V ref …(3)

[0032] Reference voltage V ref is the gate-source voltage V of the first transistor M91 gs1 and equation (4) holds. V ref =V gs1 …(4) Equation (5) is obtained from equations (3) and (4). V ds2 =V dd -V gs1 …(5)

[0033] The gate-source voltage V of the first transistor M91 is calculated using the current Id flowing through the first transistor M91 and the second transistor M92. gs1 is expressed by equation (6).

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[0034] That is, the threshold voltage V of the first transistor M91 th1 The variation in the gate-source voltage V of the first transistor M91 gs1The variation of the reference voltage V ref This results in variation.

[0035] 2 is a diagram showing the characteristics (simulation results) of the reference voltage source 100R of FIG. 1. In the simulation, the parameters of the first transistor M91 and the second transistor M92 are varied. ref The temperature characteristics are shown for three cases: the standard value, the maximum value, and the minimum value.

[0036] At 25°C, the typical value is V ref =727mV, minimum value is V ref =699mV, maximum value is V ref =778mV. At 150°C, the minimum value is V ref =664mV, maximum value is V ref =788mV.

[0037] For example, the reference voltage V ref is multiplied by a constant (2.06 times) to obtain the reference voltage V of 1.5V. REF At 25°C, the typical value is V REF =1.497V, the minimum value is V REF =1.44V, maximum value is V REF =1.60V. At 150°C, the minimum value is V REF =1.36V, maximum value is V REF =1.62V.

[0038] In this way, the comparison technique uses a reference voltage V ref (V REF ) may vary significantly, which may cause problems with circuit operation.

[0039] Next, a description will be given of a reference voltage source 100 according to an embodiment. The reference voltage source 100 according to an embodiment is a circuit obtained by improving the reference voltage source 100R in FIG. 1 in order to suppress variations in the reference voltage.

[0040] 3 is a circuit diagram of a reference voltage source 100 according to an embodiment. The reference voltage source 100 includes a power supply line VDD, a ground line VSS, an output node VREF, a first transistor M1, a second transistor M2, and a back-gate voltage adjusting circuit 110. The reference voltage source 100 supplies a power supply voltage V dd and a reference voltage V ref occurs.

[0041] The first transistor M1 is an enhancement type N-channel MOSFET (Metal Oxide Semiconductor Field Effect Transistor), with a source connected to the ground line VSS and a gate and drain connected to the output node VREF.

[0042] The second transistor M2 is a depletion-type N-channel MOSFET, with its drain connected to the power supply line VDD and its gate, source, and back gate connected to the output node VREF.

[0043] The back gate voltage adjusting circuit 110 receives the reference voltage V ref The back gate voltage adjusting circuit 110 applies a reference voltage V ref The bias voltage V has a positive correlation with sb1 supply.

[0044] The above is the configuration of reference voltage source 100. Next, the operation of reference voltage source 100 will be described.

[0045] Before explaining the operation of the reference voltage source 100, the substrate bias effect, which is the premise of the operation, will be explained.

[0046] When the back gate and source of the MOSFET are connected as in the first transistor M91 in Figure 1, the threshold voltage V th0 is expressed by equation (7).

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[0047] On the other hand, the back gate of the MOSFET is connected to a voltage range V sb , when a low voltage is applied, the substrate bias effect causes the threshold voltage V th is the threshold voltage V in equation (7). th0 is higher than that, and is expressed by equation (8).

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[0048] Conversely, the back gate of the MOSFET is connected to a voltage range V sb When a high voltage is applied, the threshold voltage V th is the threshold voltage V in equation (7). th0 will be lower than

[0049] The operation of the reference voltage source 100 according to the embodiment will be described.

[0050] Similar to the comparison technique, the reference voltage V generated by the reference voltage source 100 ref is the gate-source voltage V of the first transistor M1 gs1 is equal to. V ref =Vgs1

[0051] The gate-source voltage V of the first transistor M1 gs1 is expressed by equation (6).

[0052] Reference voltage V ref When the voltage V supplied to the back gate of the first transistor M1 increases, sb1 becomes higher, and the threshold voltage V th becomes low, and the reference voltage V ref On the other hand, the reference voltage V ref When the voltage V supplied to the back gate of the first transistor M1 decreases, sb1 becomes low, and the threshold voltage V of the first transistor M1 becomes low due to the substrate bias effect. th becomes higher, and the reference voltage V ref In this way, in this embodiment, the reference voltage V ref is fed back and the back gate voltage of the first transistor M1 is adjusted to obtain the reference voltage V ref This can suppress variations in

[0053] The present disclosure covers various devices and methods that can be understood as the block diagram or circuit diagram of Figure 3 or that can be derived from the above description, and is not limited to a specific configuration. Below, more specific configuration examples and examples will be described not to narrow the scope of the present disclosure, but to aid in understanding and clarify the essence and operation of the present disclosure and the present invention.

[0054] 4 is a circuit diagram of a reference voltage source 100A according to the first embodiment. The back-gate voltage adjusting circuit 110A includes a third transistor M3, which is a depletion-type N-channel MOSFET. The gate of the third transistor M3 is connected to the output node VREF, and the reference voltage V refA resistor voltage divider circuit, which is a series circuit of a first resistor R1 and a second resistor R2, is connected between the source of the third transistor M3 and the ground line VSS. The third transistor M3 and the resistor voltage divider circuit form a source follower circuit, and the source of the third transistor M3 is connected to the reference voltage V ref Voltage V s3 This voltage V s3 is divided by resistors R1 and R2, and the bias voltage V sb1 is generated.

[0055] The operation of the reference voltage source 100A will now be described.

[0056] The drain-source voltage of the second transistor M2 is expressed by equation (9). V ds2 =V dd -V gs1 …(9)

[0057] The current I2 flowing through the second transistor M2 is expressed by equation (10). I2=β2 / 2×(V gs2 -V th2 ) …(10) The gate and source of the second transistor M2 are connected, so V gs2 =0. The second transistor M2 is a depletion type, and the threshold voltage V th is the negative voltage -V th2 Therefore, the current I2 flowing through the second transistor M2 is given by equation (11). I2=β2 / 2·(V th2 ) 2 …(11)

[0058] The reference voltage V generated at the output node VREF ref is expressed by equation (12).

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[0059] The back gate bias voltage V of the first transistor M1 sb1is expressed by equation (13).

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[0060] Reference voltage V ref When increases, the bias voltage V in equation (13) sb1 rises, and the threshold voltage V th1 becomes low, and the reference voltage V ref On the other hand, the reference voltage V ref When the bias voltage V in equation (13) decreases, sb1 decreases, and the threshold voltage V th1 becomes higher, and the reference voltage V ref According to the reference voltage source 100A, the reference voltage V ref This can suppress variations in

[0061] FIG. 5 is a diagram showing the characteristics (simulation results) of the reference voltage source 100A of FIG. 4. The simulation was performed by giving variations to the parameters of the first transistor M1 to the third transistor M3. ref The temperature characteristics are shown for three cases: the standard value, the maximum value, and the minimum value.

[0062] At 25°C, the typical value is V ref =727mV, minimum value is V ref =719mV, maximum value is V ref =754mV. At 150°C, the minimum value is V ref =708mV, maximum value is V ref =741mV. At any temperature, the reference voltage V ref The variation is suppressed.

[0063] Example 2 As can be seen from equation (8), the threshold voltage V of the MOSFET th1 is that φ FSince includes a thermal voltage term, it has a temperature T dependency. The current I2 also has a temperature characteristic. Therefore, the reference voltage V expressed by equation (12) ref The temperature dependence of the saturation voltage is also obtained.

[0064] In the second embodiment, the first resistor R1 and the second resistor R2 are designed to have different temperature dependencies. If the temperature coefficient of the first resistor R1 is ρ1 and the temperature coefficient of the second resistor R2 is ρ2, then the bias voltage V at a temperature ΔT away from room temperature (25°C) is sb1 is expressed by equation (14), and can have temperature characteristics according to ρ1 and ρ2.

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[0065] Therefore, by optimizing the temperature coefficients ρ1 and ρ2 of the first resistor R1 and the second resistor R2, φ F and I2 temperature fluctuations can be canceled, and the reference voltage V ref The temperature characteristics can be made closer to flat.

[0066] 6 is a diagram illustrating an example of optimizing the temperature coefficients ρ1 and ρ2 of the first resistor R1 and the second resistor R2. The upper part of FIG. 6 shows the reference voltage V ref The temperature characteristics of the first transistor M1 are shown in the lower part. sb1 The temperature characteristics are shown below.

[0067] Example 3 7 is a circuit diagram of a reference voltage source 100B according to Example 3. The back-gate voltage adjusting circuit 110B includes a stabilizing circuit 120B in addition to a third transistor M3, a first resistor R1, and a second resistor R2.

[0068] The stabilization circuit 120B adjusts the voltage between the back gate and source of the third transistor M3 according to the current I2 flowing through the first transistor M1 and the second transistor M2.

[0069] The stabilization circuit 120B includes a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, and a third resistor R3. The third resistor R3 is connected between the back gate and source of the third transistor M3. The fourth transistor M4 has a gate connected to a reference voltage V ref The source is connected to the ground line VSS, and the back gate is supplied with a bias voltage V sb1 The fourth transistor M4 forms a current mirror circuit together with the first transistor M1, and a current I4 proportional to the current I2 flowing through the first transistor M1 flows through the fourth transistor M4. The fifth transistor M5 and the sixth transistor M6 form a current mirror circuit CM1, which mirrors the current flowing through the fourth transistor M4. The mirrored current I6 is supplied to the third resistor R3. The voltage V of the back gate of the third transistor M3 sb3 is the source voltage V s3 It is higher by R3×I6 than V sb3 =V s3 +R3×I6

[0070] The above is the configuration of the reference voltage source 100B.

[0071] The back gate bias voltage V of the third transistor M3 sb3 is expressed by equation (15).

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[0072] In the third embodiment, the temperature coefficient of the third resistor R3 is optimized to reduce the back gate bias voltage V sb3 When the temperature coefficient of the third resistor R3 is ρ3, the back gate bias voltage V sb3 is expressed by equation (16).

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[0073] The gate-source voltage V of the third transistor M3 gs3 has a temperature characteristic, the back gate bias voltage V of the first transistor M1 sb1 has temperature characteristics, and as a result, φ F and I2 temperature fluctuations can be canceled, and the reference voltage V ref The temperature characteristics can be made closer to flat.

[0074] FIG. 8 is a diagram showing the characteristics (simulation results) of the reference voltage source 100B of FIG. 7. The simulation was performed by giving variations to the parameters of the first transistor M1 to the third transistor M3. In FIG. 8, ref The temperature characteristics are shown for three cases: the standard value, the maximum value, and the minimum value.

[0075] At 25°C, the typical value is V ref =727mV, minimum value is V ref =721mV, maximum value is V ref =735mV. At 150°C, the minimum value is V ref =702mV, maximum value is V ref At any temperature, the reference voltage V ref The variation is suppressed.

[0076] (Addendum) The present specification discloses the following techniques.

[0077] (Item 1) The power line and A ground line and an output node; a first transistor which is an enhancement-type N-channel MOSFET (Metal Oxide Semiconductor Field Effect Transistor) having a source connected to the ground line and a gate and a drain connected to the output node; a second transistor which is a depletion-type N-channel MOSFET having a drain connected to the power supply line and a gate, a source, and a back gate connected to the output node; a back-gate voltage adjusting circuit that supplies a bias voltage having a positive correlation with a reference voltage generated at the output node to a back-gate of the first transistor; a reference voltage source comprising:

[0078] (Item 2) The back-gate voltage adjustment circuit includes a third transistor that is a depletion-type N-channel MOSFET whose gate is connected to the output node, and outputs the bias voltage according to a source voltage of the third transistor.

[0079] (Item 3) 3. The reference voltage source according to item 2, wherein the back-gate voltage adjustment circuit further includes a first resistor and a second resistor connected in series between the source of the third transistor and the ground line, and a voltage at a connection node between the first resistor and the second resistor is the bias voltage.

[0080] (Item 4) 4. The reference voltage source of claim 3, wherein the first resistor and the second resistor have different temperature coefficients.

[0081] (Item 5) The back gate voltage adjusting circuit includes: 5. The reference voltage source according to item 3 or 4, further comprising a stabilization circuit that adjusts the voltage between the back gate and the source of the third transistor according to the current flowing through the first transistor and the second transistor.

[0082] (Item 6) The stabilization circuit a fourth transistor having a gate receiving the reference voltage, a source connected to the ground line, and a back gate receiving the bias voltage; a third resistor connected between the back gate and the source of the third transistor; a current mirror circuit that mirrors the current flowing through the fourth transistor and supplies the current to the third resistor; Item 6. The reference voltage source according to item 5, comprising:

[0083] (Item 7) The power line and A ground line and an output node; a first transistor which is an enhancement-type N-channel MOSFET (Metal Oxide Semiconductor Field Effect Transistor) having a source connected to the ground line and a gate and a drain connected to the output node; a second transistor which is a depletion-type N-channel MOSFET having a drain connected to the power supply line and a gate, a source, and a back gate connected to the output node; a third transistor which is a depletion-type N-channel MOSFET having a gate connected to the output node; Equipped with a reference voltage source that supplies a bias voltage corresponding to the source voltage of the third transistor to the back gate of the first transistor;

[0084] (Item 8) further comprising a first resistor and a second resistor connected in series between the source of the third transistor and the ground line; 8. The reference voltage source according to item 7, wherein the voltage at the connection node between the first resistor and the second resistor is the bias voltage.

[0085] (Item 9) a fourth transistor having a gate receiving the reference voltage generated at the output node, a source connected to the ground line, and a back gate receiving the bias voltage; a third resistor connected between the back gate and the source of the third transistor; a current mirror circuit that mirrors the current flowing through the fourth transistor and supplies the current to the third resistor; Item 9. The reference voltage source according to item 7 or 8, further comprising: [Explanation of symbols]

[0086] 100 Reference voltage source M1 First transistor M2 Second transistor M3 Third transistor M4 4th transistor M5 Fifth transistor M6 6th transistor R1 First resistor R2 2nd resistor R3 3rd resistor 110 Backgate voltage adjustment circuit 120B stabilization circuit CM1 current mirror circuit

Claims

1. The power line and A ground line and an output node; a first transistor which is an enhancement type N-channel MOSFET (Metal Oxide Semiconductor Field Effect Transistor) having a source connected to the ground line and a gate and a drain connected to the output node; a second transistor which is a depletion-type N-channel MOSFET having a drain connected to the power supply line and a gate, a source, and a back gate connected to the output node; a back-gate voltage adjusting circuit that supplies a bias voltage having a positive correlation with a reference voltage generated at the output node to the back-gate of the first transistor; a reference voltage source comprising:

2. 2. The reference voltage source according to claim 1, wherein the back-gate voltage adjustment circuit includes a third transistor that is a depletion-type N-channel MOSFET having a gate connected to the output node, and outputs the bias voltage according to a source voltage of the third transistor.

3. 3. The reference voltage source according to claim 2, wherein the back-gate voltage adjustment circuit further includes a first resistor and a second resistor connected in series between the source of the third transistor and the ground line, and a voltage at a connection node between the first resistor and the second resistor is the bias voltage.

4. 4. The reference voltage source of claim 3, wherein the first resistor and the second resistor have different temperature coefficients.

5. The back gate voltage adjusting circuit includes:

5. The reference voltage source according to claim 3, further comprising a stabilization circuit that adjusts the voltage between the back gate and the source of the third transistor in accordance with the currents flowing through the first transistor and the second transistor.

6. The stabilization circuit a fourth transistor having a gate receiving the reference voltage, a source connected to the ground line, and a back gate receiving the bias voltage; a third resistor connected between the back gate and the source of the third transistor; a current mirror circuit that mirrors the current flowing through the fourth transistor and supplies the current to the third resistor; 6. The reference voltage source of claim 5, comprising:

7. The power line and A ground line and an output node; a first transistor which is an enhancement type N-channel MOSFET (Metal Oxide Semiconductor Field Effect Transistor) having a source connected to the ground line and a gate and a drain connected to the output node; a second transistor which is a depletion-type N-channel MOSFET having a drain connected to the power supply line and a gate, a source, and a back gate connected to the output node; a third transistor which is a depletion-type N-channel MOSFET having a gate connected to the output node; Equipped with a reference voltage source, the back gate of the first transistor being supplied with a bias voltage according to the source voltage of the third transistor;

8. a first resistor and a second resistor connected in series between the source of the third transistor and the ground line; 8. The reference voltage source according to claim 7, wherein a voltage at a connection node between said first resistor and said second resistor is said bias voltage.

9. a fourth transistor having a gate receiving the reference voltage generated at the output node, a source connected to the ground line, and a back gate receiving the bias voltage; a third resistor connected between the back gate and the source of the third transistor; a current mirror circuit that mirrors the current flowing through the fourth transistor and supplies the current to the third resistor; 9. The reference voltage source of claim 7 or 8, further comprising:

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