System and method for measuring post bonding overlay

Abstract

To solve the problem in limitations in density of achievable measurements because placement of metrology targets on a carrier wafer may require additional processing and targets are needed depending on bonding flows.SOLUTION: A wafer shape metrology system includes a wafer shape metrology sub-system configured to perform one or more stress-free shape measurements on a first wafer, a second wafer, and a post-bonding pair of the first and second wafers. The wafer shape metrology system includes a controller communicatively coupled to the wafer shape metrology sub-system. The controller receives stress-free shape measurements from the wafer shape sub-system, and predicts overlay between one or more features on the first wafer and the second wafer based on the stress-free shape measurements of the first wafer, the second wafer, and the post-bonding pair of the first wafer and the second wafer.SELECTED DRAWING: Figure 1A

Description

[Technical Field]

[0001] The present invention relates generally to the field of metrology, and more particularly to a system and method for measuring post-bonding overlay using a wafer shape metrology tool. [Background technology]

[0002] (CROSS-REFERENCE TO RELATED APPLICATIONS)

[0003] This application claims the benefit under 35 U.S.C. §119(e) of U.S. Provisional Application No. 63 / 124,629, filed December 11, 2020, the entire contents of which are incorporated herein by reference.

[0004] The traditional method for measuring post-bonding overlay after bonding two semiconductor wafers is to place an overlay metrology target (such as a box-in-box structure or AIM target) on one of the wafers being bonded. Using infrared light transmitted through the silicon wafer, the relative positions of the targets can be compared to obtain overlay results. Traditional overlay measurements such as those described above require the presence of metrology targets on both wafers. This can be disadvantageous for two reasons. First, depending on the bonding flow, placing the metrology target on a so-called carrier wafer may require additional processing. Second, the need for targets limits the achievable measurement density. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] International Publication No. 2020 / 226152 [Patent Document 2] U.S. Patent Application Publication No. 2015 / 0120216 [Patent Document 3] U.S. Patent Application Publication No. 2018 / 0342410 Summary of the Invention [Problem to be solved by the invention]

[0006] It would therefore be desirable to provide a system and method that overcomes the shortcomings of conventional approaches such as those discussed above. [Means for solving the problem]

[0007] A wafer metrology system is disclosed in accordance with one or more embodiments of the present disclosure. In one embodiment, the wafer metrology system includes a wafer shape metrology subsystem configured to perform one or more stress-free shape measurements on a first wafer, a second wafer, and a post-bonding pair of the first wafer and the second wafer. In another embodiment, the wafer metrology system includes a controller communicatively coupled to the wafer shape metrology subsystem, the controller including one or more processors configured to execute a set of program instructions stored in a memory. In another embodiment, the set of program instructions is configured to cause the one or more processors to receive one or more stress-free shape measurements from the wafer shape subsystem, predict overlay between one or more features on the first wafer and one or more features on the second wafer based on the one or more stress-free shape measurements of the first wafer, the second wafer, and the post-bonding pair of the first wafer and the second wafer, and provide feedback adjustments to one or more process tools based on the predicted overlay.

[0008] In accordance with one or more alternative and / or additional embodiments of the present disclosure, a wafer metrology system is disclosed. In one embodiment, the wafer metrology system includes a wafer shape metrology subsystem configured to perform one or more stress-free shape measurements on a first wafer and a second wafer. In another embodiment, the wafer shape metrology system includes a controller communicatively coupled to the wafer shape metrology subsystem, the controller including one or more processors configured to execute a set of program instructions stored in a memory. In another embodiment, the set of program instructions is configured to cause the one or more processors to receive one or more stress-free shape measurements of the first wafer and the second wafer from the wafer shape subsystem, measure a first shape distortion of the first wafer by comparing the shape of the first wafer to a first reference structure, measure a second shape distortion of the second wafer by comparing the shape of the second wafer to a second reference structure, predict an overlay between one or more features on the first wafer and one or more features on the second wafer based on the one or more stress-free shape measurements of the first wafer and the second wafer, the first shape distortion, and the second wafer shape distortion, and provide feedforward adjustments to one or more process tools based on the predicted overlay.

[0009] It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not necessarily restrictive of the invention as claimed. The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and, together with the general description, serve to explain the principles of the invention.

[0010] The many advantages of the present disclosure may be better understood by those skilled in the art by reference to the accompanying drawings. [Brief explanation of the drawings]

[0011] [Figure 1A] FIG. 1 is a simplified block diagram of a wafer shape metrology system in accordance with one or more embodiments of the present disclosure. [Figure 1B]FIG. 1 is a conceptual diagram of a wafer shape measurement system that performs wafer shape measurements on a first wafer, a second wafer, and a post-bonded pair of wafers in accordance with one or more embodiments of the present disclosure. [Figure 1C] FIG. 1 is a simplified block diagram of a wafer shape measurement system depicting feedback and / or feedforward control of a process tool in accordance with one or more embodiments of the present disclosure. [Figure 2] 1 is a flow chart depicting a method for determining overlay between wafer features in a post-bonded pair of wafers in accordance with one or more embodiments of the present disclosure. [Figure 3] 1 is a flow chart depicting a method for predicting overlay caused by bonding two wafers in accordance with one or more embodiments of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0012] The present disclosure has been particularly shown and described with respect to certain embodiments and certain features thereof. The embodiments shown herein are considered to be illustrative and not limiting. It should be readily apparent to those skilled in the art that various changes and modifications in form and detail can be made therein without departing from the spirit and scope of the present disclosure. Reference will now be made in detail to the disclosed subject matter, which is illustrated in the accompanying drawings.

[0013] 1A-3, a system and method for post-bonding overlay metrology is illustrated in accordance with one or more embodiments of the present disclosure.

[0014] Embodiments of the present disclosure are directed to measuring relative overlay between two bonded wafers caused by shape-based distortion. Embodiments of the present disclosure may utilize shape measurements performed on first and second incoming wafers and post-bonding wafer pairs. Embodiments of the present disclosure may transform shape data collected from the first and second wafers (pre-bonding) and the post-bonding pair (post-bonding) to predict overlay data and provide feedback control. Additional embodiments of the present disclosure may transform shape data collected from the first and second wafers (pre-bonding) to measure shape distortion of the first and second wafers relative to a reference structure and provide feedforward control. The transformation of shape data into predicted overlay information may be performed using machine learning algorithms and / or machine models.

[0015] Embodiments of the present disclosure may be implemented to achieve tight overlay requirements on two wafers after a wafer-to-wafer bonding process (e.g., hybrid bonding or fusion bonding). For example, embodiments of the present disclosure may be utilized to minimize / mitigate overlay in wafer-to-wafer bonding processes involved in the fabrication of image sensors (e.g., backlit image sensor technology), 3D NAND technology in which a device wafer and a memory wafer are bonded together, and logic device backside power rail processes in which a device wafer is bonded to a carrier wafer. All of these examples require tight overlay tolerances. In image sensor and 3D NAND technologies, the overlay requirement is implemented to ensure a reliable connection due to the direct electrical connection between Cu pads on one wafer and Cu pads on another wafer. In the case of backside power rail technologies, it is desirable to have low wafer distortion, given the typical correction capabilities of the scanner (e.g., correction-per-field (CPE) correction), so that subsequent lithographic exposure of through-vias can achieve the required overlay tolerance.

[0016] A process for measuring post-bonding overlay may include, but is not limited to, i) performing a wafer shape metrology step, ii) performing a feature extraction step in which wafer-specific parameters are extracted from the wafer shape data, and iii) converting the extracted parameters into overlay between features of a first wafer and a second wafer via an algorithm (e.g., a machine learning algorithm or a mechanical model). Based on the results of the overlay prediction, a control algorithm (e.g., a feedback or feedforward algorithm) may be implemented. In the case of feedback control, the control algorithm may be used to optimize bonder settings for subsequent wafers. In the case of feedforward control, shape distortions of the incoming wafer may be used to adjust the bonder settings.

[0017] FIG. 1A shows a simplified block diagram of a wafer shape metrology system 100 for post-bonding overlay metrology in accordance with one or more embodiments of the present disclosure.

[0018] In an embodiment, system 100 includes a wafer shape metrology subsystem 102. System 100 may also include a controller 104 communicatively coupled to a detector output of wafer shape metrology subsystem 102. Controller 104 may include one or more processors 106 and memory 108. The one or more processors 106 of controller 104 may be configured to execute a set of program instructions stored in memory 108. The set of program instructions may be configured to cause the one or more processors 106 to perform various steps and processes of the present disclosure.

[0019] The wafer shape metrology subsystem 102 may include any wafer shape tool or system known in the art capable of acquiring one or more shape parameters from one or more wafers. In an embodiment, the wafer shape metrology subsystem 102 includes an interferometer subsystem configured to perform one or more metrology and / or characterization processes on one or more wafers. For example, the wafer shape metrology subsystem 102 may include a dual interferometer system (e.g., a dual Fizeau interferometer) configured to perform measurements on both sides of the wafer. For example, the wafer shape metrology subsystem 102 may include a first interferometer subsystem 105a configured to generate a first illumination beam 101a to perform one or more measurements on a first surface of the wafer and a second interferometer subsystem 105b configured to generate a second illumination beam 101b to perform one or more measurements on a second surface of the wafer opposite the first surface. The wafer metrology subsystem 102 may also include a patterned wafer shape (PWG) tool, such as a PWG tool manufactured by KLA INC. The use of interferometers for wafer characterization is generally described in U.S. Patent No. 6,847,458, filed March 20, 2003, U.S. Patent No. 8,949,057, filed October 27, 2011, and U.S. Patent No. 9,121,684, filed January 15, 2013, which are incorporated herein by reference in their entireties.

[0020] It should be noted that double-sided interferometers, such as PWG tools, can be particularly useful for implementation in the context of the disclosed processes. For example, thickness and / or thickness change information can be input to the disclosed machine learning algorithms and / or machine models. Furthermore, double-sided measurements offer flexibility when one surface has attributes that make the measurement uncertain. Furthermore, double-sided measurements allow for averaging of shape information from the two measurements, improving certainty.

[0021] It should be noted that the scope of this disclosure is not limited to PWG-implemented dual interferometer systems, but may be extended to encompass any wafer metrology system or tool known in the art, including but not limited to single-sided interferometer systems.

[0022] In an embodiment, the wafer shape metrology subsystem 102 is configured to perform wafer shape metrology on the wafer while it is in a stress-free or near-stress-free state. For purposes of this disclosure, the term "stress-free" should be interpreted to mean a configuration in which little or no force is applied to the wafer from external sources. The term "stress-free" may alternatively be interpreted as "freestanding." With external stresses removed, any remaining deviations from a flat wafer shape are typically induced through a stress layer present on the front side of the wafer or due to stresses imposed by the bonding process. Note that these stresses caused by layers present on the wafer are interpreted as internal stresses. In this sense, the "shape" of a wafer is a combination of its "natural shape" (i.e., the shape of the bare wafer) and the shape induced by internal stresses on any surface of the wafer, such as thin films.

[0023] 1B, the wafer metrology subsystem 102 may perform (1) shape measurements of the first wafer, (2) shape measurements of the second wafer, and (3) shape measurements of the post-bonded pair of wafers. Note that the measurements of the pre-bonded first and second wafers may be used to predict the shape of the post-bonded pair of wafers based on the shape discrepancy between the first and second wafers and the effects of the bonder and bonding process on the post-bonded pair.

[0024] In an embodiment, the wafer metrology subsystem 102 may perform a first shape measurement on the first wafer 110a and then transmit the shape measurement data to the controller 104 via data signal 103a. The wafer metrology subsystem 102 may perform a second shape measurement on the second wafer 110b and then transmit the shape measurement data to the controller 104 via data signal 103b. The first wafer 110a and the second wafer 110b may then undergo a bonding process via a bonder (not shown) to form a post-bonding wafer pair 110c. The wafer metrology subsystem 102 may perform a third shape measurement on the post-bonding wafer pair 110c and then transmit the shape measurement data to the controller 104 via data signal 103c.

[0025] In an embodiment, following the bonding process, the controller 104 converts the measured shape information of the first wafer 110a, the second wafer 110b, and the post-bonding wafer pair 110 into local shape parameters that characterize local shape characteristics. For example, these parameters may include first and second partial derivatives of the shape, or predictions of in-plane displacement from the shape using different mechanical models. For example, local shape parameters may include, but are not limited to, local shape curvature (LSC) and / or in-plane distortion (IPD). Additional metrics traditionally used to predict wafer distortion on a scanner may also be utilized. Such metrics include, but are not limited to, mechanical models that describe the relationship between wafer shape and overlay based on approaches such as plate theory, finite element methods, or proprietary modeling approaches such as parameters from the Gen3, Gen4, and / or Gen5 models manufactured by KLA Corporation.

[0026] A description to capture the effects of both the incoming wafer and the post-bonded wafer is given in K. Turner's 2004 PhD thesis, "Wafer Bonding: Mechanics-based Models and Experiments, Massachusetts Institute of Technology." In this approximation, the overall bow localized from the bow of the final bonded wafer (and the resulting IPD) can be described by the following equation:

number

number

[0027] In an embodiment, the first algorithm executed by the controller 104 includes a machine learning algorithm. The machine learning algorithm applied by the controller 104 may include any machine learning algorithm known in the art, including, but not limited to, a deep learning algorithm. For example, the deep learning algorithm may include, but is not limited to, a neural network (e.g., a convolutional neural network (CNN), a generative adversarial network (GAN), a recurrent neural network (RNN), etc.). In this embodiment, the controller 104 generates multiple parameters from the wafer geometry for each measurement (first wafer 110a, second wafer 110b, and post-bonding wafer pair 110c). For example, the controller 104 may locally generate IPD, Gen4, etc. for the first wafer 110a, second wafer 110b, and post-bonding wafer pair 110c. The controller 104 may then use any of these generated parameters as inputs to the machine learning algorithm. For example, in the case of a neural network, the controller 104 may generate IPD, Gen4, etc. for the first wafer 110a, the second wafer 110b, and the post-bonding wafer pair 110c on a local basis and input these metrics into the neural network.

[0028] In an embodiment, the controller 104 may train a machine learning algorithm. For example, the controller 104 may receive and then utilize IR overlay data measured at the same location for training. In an embodiment, alignment-induced overlay errors due to relative x-y shifts as well as rigid body rotation errors are removed from the overlay data used for training. In an embodiment, once trained, a machine learning algorithm such as a neural network may be used to make overlay predictions.

[0029] In alternative and / or additional embodiments, a mechanical model may be used instead of (or in combination with) a machine learning algorithm. Similar to the procedure used to predict the overlay of a warped wafer chucked on a lithography scanner, a set of mechanical equations describing the wafer shape may be approximately solved. In embodiments, the mechanical model may be based on plate theory or beam theory. In embodiments, the mechanical model is based on the numerical solution of continuum mechanics equations governing the linear elastic deformation of solids. For example, the mechanical model may include, but is not limited to, techniques such as plate theory or the finite element method. Consistent with the equations presented above, the intermediate shape of the wafer during bonding provides the primary adjustment.

[0030] 1C , the controller 104 may provide one or more control signals 113 to one or more process tools 112. For example, the controller 104 may generate one or more feedforward and / or feedback control signals configured to adjust one or more upstream and / or downstream process tools. The process tools that may be adjusted may include, but are not limited to, lithography tools, deposition tools, polishing tools, etching tools, bonders, etc. In this regard, the predicted overlay information may be used to minimize (or at least mitigate) the overlay observed on the bonded wafer pairs.

[0031] In an embodiment, the controller 104 may provide feedback control. For example, the predicted post-bonding overlay may be used to adjust the bonder's process controls. Examples of such process adjustments include adjusting the vacuum pressure applied during bonding or adjusting for uneven temperature distribution. The effects of these changes may be characterized as a control signature. Using standard optimization algorithms, the characterized signatures for the bonder adjustments, and a scaled combination of the signatures, the resulting overlay may be minimized.

[0032] In additional and / or alternative embodiments, the controller 104 may provide feedforward control. In an embodiment, prior to the bonding process, the controller 104 may apply a model to determine a first shape distortion of the first wafer 110a by comparing the first wafer shape to a first reference structure and to determine a second shape distortion of the second wafer 110a by comparing the second wafer shape to a second reference structure. The first and second reference structures may include, but are not limited to, ideal flat wafers. The controller 104 may then predict overlay between one or more features on the first wafer 110a and one or more features on the second wafer 110b based on the shape measurements, the first shape distortion, and the second wafer shape distortion of the first wafer 110a and the second wafer 110b. In this regard, the controller 104 may apply machine learning algorithms and / or machine models, as described earlier herein. The controller 104 may then provide feedforward adjustments to one or more process tools (e.g., a bonder) based on the predicted overlay. For example, for wafers with high initial bow, the changing signature of the incoming wafer bow affects the outgoing post-bonding distortion. In this case, a post-bonding signature can be generated with a modified process. A bonding signature can be generated from an initial calibration run using pre-measurements of two incoming wafers and one outgoing wafer. In feedforward control, the incoming signatures are combined to generate a predicted overlay result, which can be optimized according to procedures described herein to provide the lowest possible post-bonding overlay. Note that pre-bonding shape measurements of the wafers 110a, 110b combined with a model for determining distortion can be used to select wafer pairs for bonding to minimize overlay error.

[0033] The one or more processors 106 of the controller 104 may include any processor or processing element known in the art. For purposes of this disclosure, the term “processor” or “processing element” may be broadly defined to encompass any apparatus having one or more processing or logic elements (e.g., one or more microprocessor devices, one or more application-specific integrated circuit (ASIC) devices, one or more field-programmable gate arrays (FPGAs), or one or more digital signal processors (DSPs)). In this sense, the one or more processors 106 may include any device configured to execute algorithms and / or instructions (e.g., program instructions stored in a memory). In one embodiment, the one or more processors 106 may be embodied as a desktop computer, a mainframe computer system, a workstation, an image computer, a parallel processor, a network computer, or any other computer system configured to execute programs configured to operate as described throughout this disclosure or to operate in conjunction with the measurement system 100. Additionally, different subsystems of the system 100 may include processors or logic elements suitable for performing at least some of the steps described in this disclosure. Therefore, the above description should not be construed as a limitation on embodiments of the present disclosure, but merely as an example. Furthermore, steps described throughout the present disclosure may be performed by a single controller or, alternatively, by multiple controllers. Furthermore, the controller 104 may include one or more controllers housed within a common housing or within multiple housings. In this manner, any controller or combination of controllers may be individually packaged as a module suitable for integration into the metrology system 100. Furthermore, the controller 104 may analyze data received from the wafer metrology subsystem 102 and provide data to additional components within the metrology system 100 or external to the metrology system 100.

[0034] The memory medium 108 may include any storage medium known in the art suitable for storing program instructions executable by the associated one or more processors 106. For example, the memory medium 108 may include a non-transitory memory medium. As another example, the memory medium 108 may include, but is not limited to, read-only memory (ROM), random access memory (RAM), magnetic or optical memory devices (e.g., disks), magnetic tape, solid-state drives, etc. It is further noted that the memory medium 108 may be housed in a common controller housing with the one or more processors 106. In one embodiment, the memory medium 108 may be located remotely relative to the physical locations of the one or more processors 106 and the controller 104. For example, the one or more processors 106 of the controller 104 may access a remote memory (e.g., a server) accessible via a network (e.g., the Internet, an intranet, etc.).

[0035] It should be noted that one or more components of the disclosed system 100 may be communicatively coupled to various other components of the system in any manner known in the art. For example, the wafer metrology subsystem 102, the controller 104, the process tool 112, and the user interface may be communicatively coupled to each other and to the other components by wires (e.g., copper wire, fiber optic cable, etc.) or wireless connections (e.g., RF coupling, IR coupling, data network communication (e.g., WiFi, WiMax, 3G, 4G, 4G LTE, 5G, Bluetooth, etc.)).

[0036] 2 illustrates a method for measuring overlay between features on a post-bonded wafer pair in accordance with one or more embodiments of the present disclosure. It should be noted that the steps of method 200 may be performed in whole or in part by wafer metrology system 100. However, it is further recognized that method 200 is not limited to wafer metrology system 100 in that additional or alternative system-level embodiments may perform all or a portion of the steps of method 200.

[0037] Wafer shape metrology is performed on the first wafer in step 202. For example, as shown in Figure 1B, the wafer shape subsystem 102 may perform wafer shape metrology on the first wafer 110a before the wafer bonding process.

[0038] Wafer shape metrology is performed on the second wafer in step 204. For example, as shown in Figure 1B, the wafer shape subsystem 102 may perform wafer shape metrology on the second wafer 110b before the wafer bonding process.

[0039] In step 206, the first wafer and the second wafer are bonded to form a bonded pair of wafers. For example, a bonder (not shown) may bond the first wafer 110a and the second wafer 110b in a wafer-to-wafer bonding process. The bonder may be configured for hybrid wafer bonding or fusion wafer bonding.

[0040] Wafer shape metrology is performed on the second post-bonded pair of wafers in step 208. For example, as shown in Figure 1B, wafer shape subsystem 102 may perform wafer shape metrology on post-bonded pair of wafers 110c after the bonding process.

[0041] In step 210, overlay between features on the first wafer and features on the second wafer is predicted based on shape measurements from the first wafer, the second wafer, and the bonded pair of wafers. In an embodiment, the controller 104 may measure or predict overlay between features on the first wafer 110a and features on the second wafer 110b based on shape measurements from the first wafer 110a, the second wafer 110b, and the bonded pair of wafers 110c. For example, the controller 104 may execute an algorithm that correlates shape information from the first wafer 110a, the second wafer 110b, and the bonded pair of wafers 110c to the overlay between features on the first wafer 110a and the second wafer 110b. In a first step, the measured shape information of steps 204, 206, and 208 may be converted by the controller 104 into local shape parameters that characterize local shape properties. Examples of such parameters are local shape curvature, IPD, and any other shape metrics used in the art to predict wafer distortion (e.g., scanner distortion predicted by a mechanical model used to describe the relationship between wafer shape and overlay based on approaches such as plate theory, finite element methods, or proprietary modeling approaches such as parameters from KLA Corporation's Gen3, Gen4, and / or Gen5 models). The obtained parameters are then used by the controller 104 to predict overlay. For example, the controller 104 may input the obtained shape parameters into a machine learning algorithm (e.g., a neural network) that correlates the obtained shape parameters to overlay between features of the first wafer 110a and the second wafer 110b in the pair of wafers 110c. Suitable shape parameters for the machine learning algorithm may include local metrics such as curvature or shape gradient, or may be used to predict the shape of the wafer as a function of a polynomial (e.g., X, Y, X). 2 , XY, Y 2, ...) or global metrics such as fitting to Zernike polynomials naturally defined on the disk. These terms are not intended to be limiting and are provided by way of example only. As another example, the controller 104 may input one or more of the obtained shape parameters into a physical / mechanical model to predict overlay between features on the first wafer 110a and the second wafer 110b of the wafer pair 110c.

[0042] In step 212, one or more feedback adjustments are provided to the process tools. For example, as shown in FIG. 1C , one or more control signals 113 may be sent to one or more process tools 112 to adjust one or more conditions of the one or more process tools 112 to minimize / maximize overlay between the first wafer 110 a and the second wafer 110 b. For example, the controller 104 may generate one or more feedback control signals configured to adjust one or more upstream process tools. Process tools that may be adjusted may include, but are not limited to, lithography tools, deposition tools, polishing tools, etching tools, bonders, etc. In this regard, the predicted overlay information may be used to minimize (or at least mitigate) the overlay observed in future bonded wafer pairs.

[0043] 3 illustrates a method for predicting overlay between features on a post-bonded wafer pair in accordance with one or more embodiments of the present disclosure. It should be noted that the steps of method 300 may be performed in whole or in part by wafer metrology system 100. However, it should be further recognized that method 300 is not limited to wafer metrology system 100, in that additional or alternative system-level embodiments may perform all or a portion of the steps of method 300. Additionally, it should be noted that various steps of method 200 may be construed as applying to method 300 unless otherwise noted.

[0044] Wafer shape metrology is performed on the first wafer in step 302. For example, as shown in Figure 1B, the wafer shape subsystem 102 may perform wafer shape metrology on the first wafer 110a before the wafer bonding process.

[0045] Wafer shape metrology is performed on the second wafer in step 304. For example, as shown in Figure 1B, the wafer shape subsystem 102 may perform wafer shape metrology on the second wafer 110b before the wafer bonding process.

[0046] In step 306, a first shape distortion of the first wafer and a second shape distortion of the second wafer are measured. For example, the controller 104 may apply a model (e.g., a mechanical model based on plate theory) to compare the shape of the first wafer 110a to a reference structure to identify distortions in the first wafer 110a. Similarly, the controller 104 may apply a model to compare the shape of the second wafer 110b to a reference structure to identify distortions in the second wafer 110b. In an embodiment, the reference structure may include an idealized flat wafer. In an additional embodiment, the reference structure may include shape information obtained from a previously measured wafer.

[0047] In step 308, overlay between features on the first wafer and features on the second wafer is predicted based on shape measurements from the first wafer and the second wafer and shape distortion of the first wafer and the second wafer. In an embodiment, after receiving shape information of the first wafer 110a and the second wafer 110b from the wafer metrology subsystem 102 and measuring the shape distortion based on the reference structure, the controller 104 may predict overlay between features on the first wafer 110a and the second wafer 110b based on the shape measurements and shape distortion of the first wafer 110a and the second wafer 110b. For example, the controller 104 may execute an algorithm that correlates the shape and shape distortion of the first wafer 110a and the second wafer 110b to the overlay between features on the first wafer 110a and the second wafer 110b. In a first step, the measured shape information of steps 204 and 206 may be converted by the controller 104 into local shape parameters that characterize local shape characteristics. As in method 200, examples of such parameters are local shape curvature, IPD, and any other shape metrics used in the art to predict wafer distortion (e.g., distortion on a scanner (e.g., Gen3, Gen4, Gen5 parameters)). The acquired parameters and the shape distortion information of step 306 are then used by the controller 104 to predict overlay. For example, the controller 104 may input the acquired shape parameters and shape distortion information into a machine learning algorithm (e.g., a neural network), which correlates the acquired shape parameters and shape distortion (before bonding) to overlay between features of the first wafer 110a and the second wafer 110b when the wafers 110a and 110b are bonded. Similar to method 200, suitable shape parameters for the machine learning algorithm may include local metrics such as curvature or shape gradient, or may be calculated by expressing the shape of the wafer as a polynomial (e.g., X, Y, X 2 , XY, Y 2, ...) or global metrics such as fitting to Zernike polynomials naturally defined on the disk. As another example, the controller 104 may input one or more of the acquired shape parameters and shape distortions into a physical / mechanical model to predict overlay between features of a first wafer 110a and a second wafer 110b in a pair of wafers 110c. It is further noted that machine learning models and mechanical models may be used in combination with each other.

[0048] In step 310, one or more feedforward adjustments are provided to the process tools. For example, as shown in FIG. 1C , one or more feedforward control signals 113 may be sent to one or more process tools 112 to adjust one or more conditions of the one or more process tools 112 to minimize / mitigate overlay between the first wafer 110a and the second wafer 110b. For example, the controller 104 may generate one or more feedforward control signals configured to adjust one or more downstream process tools. Process tools that may be adjusted may include, but are not limited to, lithography tools, deposition tools, polishing tools, etching tools, bonders, etc. In this regard, the predicted overlay information may be used to minimize (or at least mitigate) the overlay observed on the bonded wafer pair 110c.

[0049] In an embodiment, pre-bonding shape measurements of the wafers 110a, 110b combined with a model to determine distortion may be used to select pairs of wafers to bond to minimize overlay error.

[0050] Those skilled in the art will recognize that the components, operations, devices, objects, and accompanying discussion described herein are used as examples for conceptual clarity, and that various configurations are contemplated. Consequently, as used herein, the specific examples described and accompanying discussion are intended to be representative of their more general classes. In general, the use of any specific example is intended to be representative of its class, and the absence of a particular component, operation, device, or object should not be considered limiting.

[0051] Those skilled in the art will understand that there are a variety of media (e.g., hardware, software, and / or firmware) in which the processes and / or systems and / or other techniques described herein may be implemented, and that the preferred media will vary depending on the context in which the processes and / or systems and / or other techniques are deployed. For example, if an implementer determines that speed and accuracy are paramount, the implementer may choose a primarily hardware and / or firmware media; alternatively, if flexibility is paramount, the implementer may choose a primarily software implementation; or, still alternatively, the implementer may choose some combination of hardware, software, and / or firmware. Thus, while there are several possible media in which the processes and / or devices and / or other techniques described herein may be implemented, no one is inherently superior to another, in that the media utilized is a choice that depends on the context in which the media is deployed and the implementer's particular concerns (e.g., speed, flexibility, or predictability), all of which may vary.

[0052] The previous description is presented to enable one skilled in the art to make and use the invention as provided in the context of a particular application and its requirements. As used herein, directional terms such as "top," "bottom," "over," "under," "upper," "upward," "lower," "down," and the like are intended to provide relative positions for purposes of description and are not intended to specify an absolute frame of reference. Various modifications to the described embodiments will be apparent to those skilled in the art, and the general principles defined herein may be applied to other embodiments. Thus, the present invention is not intended to be limited to the particular embodiments shown and described, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

[0053] With respect to the use of substantially any plural and / or singular term herein, those skilled in the art may convert from plural to singular and / or from singular to plural as appropriate depending on the context and / or application. The various singular / plural permutations are not expressly defined herein for the sake of clarity.

[0054] All of the methodologies described herein may include storing results of one or more steps of a method embodiment in memory. The results may include any of the results described herein and may be stored in any manner known in the art. The memory may include any of the memories described herein or any other suitable storage medium known in the art. After the results are stored, they may be accessed from the memory, used by any of the method or system embodiments described herein, formatted for display to a user, used by another software module, method, or system, etc. Furthermore, the results may be stored "permanently," "semi-permanently," "temporarily," or for a period of time. For example, the memory may be random access memory (RAM), and the results do not necessarily have to remain in memory indefinitely.

[0055] It is further contemplated that each of the above-described method embodiments may include any other step(s) of the other method(s) described herein. In addition, each of the above-described method embodiments may be performed by any of the systems described herein.

[0056] The subject matter described herein may depict different components contained within or connected to other components. It should be understood that such depicted architectures are merely exemplary, and that in fact many other architectures may be implemented that achieve the same functionality. Conceptually, any arrangement of components to achieve the same functionality is effectively "associated" with one another such that the desired functionality is achieved. Accordingly, for the purposes of this specification, any two components that combine to achieve a particular function may be considered to be "associated" with one another such that the desired functionality is achieved, regardless of the architecture or intervening components. Similarly, any two components so associated may also be considered to be "connected" or "coupled" with one another to achieve the desired functionality, and any two components that can be associated in this manner may also be considered to be "couplable" with one another to achieve the desired functionality. Examples of combinable include, but are not limited to, components that are physically interlockable and / or physically interacting, components that are wirelessly interoperable and / or wirelessly interacting, and components that are logically interoperable and / or logically interacting.

[0057] It will further be understood that the present invention is defined by the appended claims. In general, those skilled in the art will understand that the terms used in this specification, and particularly in the appended claims (e.g., the body of the appended claims), are generally intended as "open" terms (e.g., the term "comprises" should be interpreted as "including, but not limited to," the term "having" should be interpreted as "having at least," the term "including" should be interpreted as "including, but not limited to," etc.). Furthermore, those skilled in the art will understand that if a specific number is intended in an introduced claim recitation, such intention will be clearly recited in the claim, and that, in the absence of such recitation, such intention also does not exist. To aid in understanding, for example, the appended claims may include introducing claim recitations using introductory phrases such as "at least one" and "one or more." However, the use of such phrases should not be construed as suggesting that introducing a claim statement with an indefinite article such as "a" or "an" implies that a particular claim containing the introduced claim statement is limited to instances containing only one of that statement, even if the same claim contains both an introductory phrase such as "one or more" or "at least one" and an indefinite article such as "a" or "an" (e.g., "a" and / or "an" should generally be construed to mean "at least one" or "one or more"). The same is true when a claim statement is introduced using a definite article. Additionally, even if a specific number is explicitly stated in the introduced claim statement, those skilled in the art will understand that such a statement should generally be construed to mean at least the recited number (e.g., a statement simply stating "two statements" without any other modifiers means "at least" two statements or "two or more" statements).Furthermore, when notation similar to "at least one of A, B, and C, etc." is used, such syntax is generally intended to mean the way one of ordinary skill in the art would understand the notation (e.g., "a system having at least one of A, B, and C" may include, but is not limited to, systems having only A, only B, only C, both A and B, both A and C, both B and C, and / or all of A, B, and C, etc.). Furthermore, when notation similar to "at least one of A, B, or C, etc." is used, such syntax is generally intended to mean the way one of ordinary skill in the art would understand the notation (e.g., "a system having at least one of A, B, or C" may include, but is not limited to, systems having only A, only B, only C, both A and B, both A and C, both B and C, and / or all of A, B, and C, etc.). Furthermore, those skilled in the art will understand that any disjunctive word and / or disjunctive phrase presenting two or more alternative terms, whether in the specification, claims, or drawings, should be understood to contemplate the possibility of including one of those terms, either of those terms, or both of those terms. For example, the phrase "A or B" will be understood to include the possibilities of "A" or "B," or "A and B."

[0058] The present disclosure and many of its attendant advantages will be understood from the foregoing description, and it will be apparent that various changes can be made in the form, construction and arrangement of the elements without departing from the disclosed subject matter or sacrificing all of its important advantages. The described forms are merely illustrative, and it is the intent of the following claims to embrace and include all such modifications. It will further be understood that the invention is defined by the appended claims.

Claims

1. A wafer shape measurement system, a wafer shape metrology subsystem configured to perform one or more stress-free shape measurements on a first wafer, a second wafer, and a post-bonding pair of the first wafer and the second wafer; a controller communicatively coupled to the wafer shape metrology subsystem, the controller including one or more processors configured to execute a set of program instructions stored in a memory, the set of program instructions configuring the one or more processors to: receiving the one or more stress-free shape measurements from the wafer shape subsystem; predicting an overlay between one or more features on the first wafer and one or more features on the second wafer based on the one or more stress-free shape measurements of the first wafer, the second wafer, and the post-bonding pair of the first wafer and the second wafer; causing one or more process tools to provide feedback adjustments based on the predicted overlay. The wafer shape measurement system is configured as follows.

2. Predicting overlay between one or more features on the first wafer and one or more features on the second wafer based on the one or more stress-free shape measurements of the first wafer, the second wafer, and the post-bonding pair of the first wafer and the second wafer includes:

2. The system of claim 1, further comprising extracting one or more wafer shape parameters from the one or more stress-free shape measurements of the first wafer, the second wafer, and the post-bonding pair of the first wafer and the second wafer.

3. The system of claim 2 , wherein the extracted one or more wafer shape parameters include at least one of local shape curvature (LSC) or in-plane distortion (IPD).

4. 3. The system of claim 2, further comprising inputting the extracted one or more wafer shape parameters into a machine learning algorithm to predict overlay between one or more features on the first wafer and one or more features on the second wafer.

5. The system of claim 4 , further comprising training the machine learning algorithm.

6. The system of claim 5 , wherein training the machine learning algorithm comprises training the machine learning algorithm with infrared overlay data.

7. 3. The system of claim 2, further comprising inputting the extracted one or more wafer shape parameters into a mechanical model to predict overlay between one or more features on the first wafer and one or more features on the second wafer.

8. providing one or more feedback control signals to one or more process tools based on the predicted overlay; The system of claim 1 , further comprising providing one or more feedback control signals to a bonder to adjust one or more process controls of the bonder based on the predicted overlay.

9. The system of claim 1 , wherein the wafer shape metrology subsystem comprises a first interferometer subsystem and a second interferometer subsystem.

10. 1. A system comprising: a controller configured to receive shape measurements from a wafer shape metrology subsystem, the controller including one or more processors configured to execute a set of program instructions stored in a memory, the set of program instructions causing the one or more processors to: receiving one or more stress-free shape measurements from the wafer shape subsystem; predicting an overlay between one or more features on a first wafer and one or more features on a second wafer based on one or more stress-free shape measurements of the first wafer, the second wafer, and a post-bonding pair of the first wafer and the second wafer; causing one or more process tools to provide feedback adjustments based on the predicted overlay. The system is configured as follows:

11. Predicting overlay between one or more features on the first wafer and one or more features on the second wafer based on the one or more stress-free shape measurements of the first wafer, the second wafer, and the post-bonding pair of the first wafer and the second wafer includes:

11. The system of claim 10, further comprising extracting one or more wafer shape parameters from the one or more stress-free shape measurements of the first wafer, the second wafer, and the post-bonding pair of the first wafer and the second wafer.

12. 12. The system of claim 11, wherein the extracted one or more wafer shape parameters include at least one of local shape curvature (LSC) or in-plane distortion (IPD).

13. 12. The system of claim 11, further comprising inputting the extracted one or more wafer shape parameters into a machine learning algorithm to predict overlay between one or more features on the first wafer and one or more features on the second wafer.

14. The system of claim 13 , further comprising training the machine learning algorithm.

15. The system of claim 14 , wherein training the machine learning algorithm comprises training the machine learning algorithm with infrared overlay data.

16. 11. The system of claim 10, further comprising inputting the extracted one or more wafer shape parameters into a mechanical model to predict overlay between one or more features on the first wafer and one or more features on the second wafer.

17. providing one or more feedback control signals to one or more process tools based on the predicted overlay; The system of claim 10 further comprising providing one or more feedback control signals to a bonder based on the predicted overlay to adjust one or more process controls of the bonder.

18. The system of claim 10 , wherein the wafer shape metrology subsystem comprises a first interferometer subsystem and a second interferometer subsystem.

19. 1. A method comprising: obtaining one or more stress-free shape measurements for a first wafer, a second wafer, and a post-bonding pair of the first wafer and the second wafer; predicting overlay between one or more features on the first wafer and one or more features on the second wafer based on the one or more stress-free shape measurements of the first wafer, the second wafer, and the post-bonding pair of the first wafer and the second wafer; providing feedback adjustments to one or more process tools based on the predicted overlay; A method comprising:

20. A wafer shape measurement system, a wafer shape metrology subsystem configured to perform one or more stress-free shape measurements on the first wafer and the second wafer; a controller communicatively coupled to the wafer shape metrology subsystem, the controller including one or more processors configured to execute a set of program instructions stored in a memory, the set of program instructions configuring the one or more processors to: receiving the one or more stress-free shape measurements for the first wafer and the second wafer from the wafer shape subsystem; measuring a first wafer shape distortion of the first wafer by comparing the shape of the first wafer with a first reference structure, and measuring a second wafer shape distortion of the second wafer by comparing the shape of the second wafer with a second reference structure; predicting overlay between one or more features on the first wafer and one or more features on the second wafer based on the one or more stress-free shape measurements of the first wafer and the second wafer, the first wafer shape distortion, and the second wafer shape distortion; and a wafer shape metrology system configured to cause one or more process tools to provide feedforward adjustments based on the predicted overlay.

21. 21. The wafer shape metrology system of claim 20, wherein at least one of the first reference structure or the second reference structure comprises an idealized plate.

22. Predicting overlay between one or more features on the first wafer and one or more features on the second wafer based on the one or more stress-free shape measurements of the first wafer and the second wafer, the first shape distortion, and the shape distortion of the second wafer includes:

21. The system of claim 20, further comprising extracting one or more wafer shape parameters from the one or more stress-free shape measurements of the first wafer and the second wafer.

23. 23. The system of claim 22, wherein the extracted one or more wafer shape parameters include at least one of local shape curvature (LSC) or in-plane distortion (IPD).

24. 23. The system of claim 22, further comprising inputting the extracted one or more wafer shape parameters of the first wafer and the second wafer, and the first shape distortion and the second wafer shape distortion into a machine learning algorithm to predict overlay between one or more features on the first wafer and one or more features on the second wafer.

25. 25. The system of claim 24, further comprising training the machine learning algorithm.

26. 26. The system of claim 25, wherein training the machine learning algorithm comprises training the machine learning algorithm with infrared overlay data.

27. 23. The system of claim 22, further comprising inputting the extracted one or more wafer shape parameters of the first wafer and the second wafer, and the first shape distortion and the second wafer shape distortion into a mechanical model to predict overlay between one or more features on the first wafer and one or more features on the second wafer.

28. providing one or more feedforward controls to one or more process tools based on the predicted overlay, 21. The system of claim 20, further comprising providing one or more feedforward control signals to a bonder based on the predicted overlay.

29. 21. The system of claim 20, wherein the wafer shape metrology subsystem comprises a first interferometer subsystem and a second interferometer subsystem.

30. 1. A system comprising: a controller configured to receive wafer shape measurements from a wafer shape metrology subsystem, the controller including one or more processors configured to execute a set of program instructions stored in a memory, the set of program instructions causing the one or more processors to: receiving one or more stress-free shape measurements of the first wafer and the second wafer from the wafer shape subsystem; determining a first wafer shape distortion of the first wafer by comparing the shape of the first wafer with a first reference structure, and determining a second wafer shape distortion of the second wafer by comparing the shape of the second wafer with a second reference structure; predicting overlay between one or more features on the first wafer and one or more features on the second wafer based on the one or more stress-free shape measurements of the first wafer and the second wafer, the first wafer shape distortion, and the second wafer shape distortion; causing one or more process tools to provide feedforward adjustments based on the predicted overlay; The system is configured as follows:

31. 31. The wafer shape metrology system of claim 30, wherein at least one of the first reference structure or the second reference structure comprises an idealized plate.

32. Predicting overlay between one or more features on the first wafer and one or more features on the second wafer based on the one or more stress-free shape measurements of the first wafer and the second wafer, the first shape distortion, and the shape distortion of the second wafer includes:

31. The system of claim 30, comprising extracting one or more wafer shape parameters from the one or more stress-free shape measurements of the first wafer and the second wafer.

33. 33. The system of claim 32, wherein the extracted one or more wafer shape parameters include at least one of local shape curvature (LSC) or in-plane distortion (IPD).

34. 33. The system of claim 32, further comprising inputting the extracted one or more wafer shape parameters of the first wafer and the second wafer, and the first shape distortion and the second wafer shape distortion into a machine learning algorithm to predict overlay between one or more features on the first wafer and one or more features on the second wafer.

35. 35. The system of claim 34, further comprising training the machine learning algorithm.

36. 36. The system of claim 35, wherein training the machine learning algorithm comprises training the machine learning algorithm with infrared overlay data.

37. 33. The system of claim 32, further comprising inputting the extracted one or more wafer shape parameters of the first wafer and the second wafer, and the first shape distortion and the second wafer shape distortion into a mechanical model to predict overlay between one or more features on the first wafer and one or more features on the second wafer.

38. providing one or more feedforward controls to one or more process tools based on the predicted overlay, 31. The system of claim 30, further comprising providing one or more feedforward control signals to a bonder based on the predicted overlay.

39. 31. The system of claim 30, wherein the wafer shape metrology subsystem comprises a first interferometer subsystem and a second interferometer subsystem.

40. 1. A method comprising: obtaining one or more stress-free shape measurements of the first wafer and the second wafer; measuring a first wafer shape distortion of the first wafer by comparing a shape of the first wafer with a first reference structure, and measuring a second wafer shape distortion of the second wafer by comparing a shape of the second wafer with a second reference structure; predicting overlay between one or more features on the first wafer and one or more features on the second wafer based on the one or more stress-free shape measurements of the first wafer and the second wafer, the first wafer shape distortion, and the second wafer shape distortion; and providing feedforward adjustments to one or more process tools based on the predicted overlay.

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