Semiconductor chip processing method

Abstract

To provide a semiconductor chip processing method that reduces barrier metal residue.SOLUTION: A processing method is performed on the gate of a semiconductor chip 10, which has an active region A1 and a termination region A2 surrounding the active region A1, by applying a pulsed voltage to the gate and intermittently flowing a current through the semiconductor chip 10 to burn off barrier metal residue M1 in the termination region A2. In this process, the peak value of the intermittently flowing current through the semiconductor chip 10 is, for example, at least 1 / 10 and at most 1 / 2 of the rated current of the semiconductor chip 10.SELECTED DRAWING: Figure 2B

Description

[Technical Field]

[0001] The present disclosure relates to a method for processing semiconductor chips. [Background technology]

[0002] A known semiconductor chip structure includes an active region through which the main current flows and a termination region surrounding the active region. The termination region is provided with a multi-layered field plate structure to ensure breakdown voltage. These field plates are formed by patterning a conductive film, but if conductive film residue (barrier metal residue) remains between the field plates, surge currents are more likely to occur.

[0003] A known technology for reducing such barrier metal residues is described, for example, in Patent Document 1. Patent Document 1 describes that "an isotropic etching process is performed between multiple field plates under conditions that allow the barrier metal film to be more easily etched than the conductive film." [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Publication No. 2020-174165 Summary of the Invention [Problem to be solved by the invention]

[0005] However, improvements to the manufacturing process such as those described in Patent Document 1 may not be able to sufficiently reduce barrier metal residue due to variations in process conditions and the influence of foreign matter.

[0006] Therefore, an object of the present disclosure is to provide a method for processing semiconductor chips that reduces barrier metal residue. [Means for solving the problem]

[0007] In order to solve the above-mentioned problems, the semiconductor chip processing method according to the present disclosure applies a pulsed voltage to the gate of a semiconductor chip having an active area and a termination area surrounding the active area, and causes a current to flow intermittently through the semiconductor chip, thereby burning off the barrier metal residue in the termination area. [Effects of the Invention]

[0008] According to the present disclosure, a method for processing semiconductor chips that aims to reduce barrier metal residue can be provided. [Brief explanation of the drawings]

[0009] [Figure 1] 1A and 1B are schematic plan views of semiconductor chips in a semiconductor chip processing method according to an embodiment; [Figure 2A] 2 is a cross-sectional view taken along line II-II in FIG. 1, illustrating a method for processing a semiconductor chip according to an embodiment. [Figure 2B] 2 is a cross-sectional view taken along line II-II in FIG. 1 showing a state where barrier metal residues are present, in relation to the semiconductor chip processing method according to the embodiment; FIG. [Figure 3A] 1 is a diagram showing the configuration of a circuit used in a process for burning off barrier metal residue in a semiconductor chip processing method according to an embodiment; [Figure 3B] 1 is an explanatory diagram showing a current flow in a circuit used in a process for burning off barrier metal residue in a semiconductor chip processing method according to an embodiment; [Figure 4] 1 is a time chart relating to a method for processing a semiconductor chip according to an embodiment. [Figure 5] 10A and 10B are explanatory diagrams relating to main currents of semiconductor chips in a semiconductor chip processing method according to an embodiment. [Figure 6A] 10 is an explanatory diagram showing the relationship between the collector-emitter voltage of a semiconductor chip and loss in barrier metal residue in the semiconductor chip processing method according to the embodiment. FIG. [Figure 6B] 10 is an explanatory diagram showing the relationship between the peak value of the main current of the semiconductor chip and the loss in the barrier metal residue in the semiconductor chip processing method according to the embodiment; FIG. DETAILED DESCRIPTION OF THE INVENTION

[0010] <Embodiment> <Semiconductor chip configuration> FIG. 1 is a schematic plan view of a semiconductor chip 10 in a semiconductor chip processing method according to an embodiment. The semiconductor chip 10 shown in Fig. 1 is an electronic component including a predetermined semiconductor. The semiconductor chip 10 may be used in a power conversion device such as an inverter or a converter, or may be used in other electric circuits. The type of such semiconductor chip 10 may be, for example, an IGBT (Insulated Gate Bipolar Transistor) or a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), but is not limited thereto.

[0011] 1, the semiconductor chip 10 includes an active area A1 and a termination area A2. The active area A1 is an area through which a main current flows, and is provided in the center of the semiconductor chip 10.

[0012] The termination region A2 is a region for alleviating electric field concentration at the end of the gate electrode (not shown) and ensuring a predetermined breakdown voltage. The termination region A2 is formed to surround the active region A1. As shown in FIG. 1, the termination region A2 includes field plates 12a and 12b.

[0013] The inner field plate 12a is provided to surround the active region A1. The outer field plate 12b is provided to surround the inner field plate 12a. By providing the double-structure field plates 12a and 12b in this manner, the electric field at the end of the gate electrode (not shown) is dispersed to the two field plates 12a and 12b, thereby reducing the concentration of the electric field. Note that FIG. 1 is just an example, and the number of field plates may be three or more. The semiconductor substrate 1 in FIG. 1 will be described later.

[0014] FIG. 2A is a cross-sectional view taken along line II-II in FIG. 2A shows an example in which the type of semiconductor chip 10 is an IGBT. As shown in FIG. 2A, the active region A1 includes a drift layer formed of an n-type semiconductor substrate 1, a p-type body layer 2 that is a main junction layer, a barrier metal layer 3 provided on the body layer 2, and a front-side main electrode 4 provided on the barrier metal layer 3.

[0015] In addition to the above-described components, the active region A1 also includes an n-type buffer layer 5, a p-type collector layer 6, and a backside main electrode 7. As shown in FIG. 2A, the backside main electrode 7, the collector layer 6, and the buffer layer 5 are provided in this order from the bottom up. A semiconductor substrate 1 is provided above the buffer layer 5. Incidentally, the impurity concentration of the semiconductor substrate 1 is lower than that of the buffer layer 5, so the semiconductor substrate 1 is indicated by "n-" in FIG. 2A. A gate electrode (not shown) and a gate insulating film (not shown) are also provided in the active region A1, but are not shown in FIG. 2A. The conductivity types, such as n-type and p-type, may be reversed.

[0016] Termination region A2 includes semiconductor substrate 1, guard rings 8a and 8b, insulating films 9a, 9b, and 9c, barrier metal layers 11a and 11b, and field plates 12a and 12b. Semiconductor substrate 1 functions as a drift layer and is made of a semiconductor such as Si (silicon) or SiC (silicon carbide).

[0017] The guard rings 8a and 8b are p-type semiconductor layers provided outside the body layer 2 of the active region A1 (to the right of the page in FIG. 2A). In the example of FIG. 2A, the guard ring 8a is provided outside the active region A1, and another guard ring 8b is provided outside the guard ring 8a. These guard rings 8a and 8b are spaced apart from each other. The guard rings 8a and 8b are formed, for example, by partially implanting predetermined ions into the surface of the semiconductor substrate 1. By providing multiple guard rings 8a and 8b in this manner, the surface electric field strength of the semiconductor chip 10 is reduced. The number of guard rings may be three or more.

[0018] Insulating film 9a is formed to bridge between the outer edge of body layer 2 and the inner edge of guard ring 8a, and is laminated on the upper side (the portion between body layer 2 and guard ring 8a) of semiconductor substrate 1. Another insulating film 9b is formed to bridge between the outer edge of guard ring 8a and the inner edge of another guard ring 8b, and is laminated on the upper side (the portion between guard rings 8a and 8b) of semiconductor substrate 1. Insulating film 3c extends outward from the outer edge of guard ring 8b, and is laminated on the upper side of semiconductor substrate 1 (the portion outside guard ring 8b).

[0019] 2A, an opening Ha is provided in the insulating film 9a. The opening Ha is a region of the insulating film 9a on which the front-side main electrode 4 and the field plates 12a and 12b are not provided. Similarly, openings Hb and Hc are provided in the other insulating films 9b and 9c.

[0020] Barrier metal layer 11a has the function of preventing diffusion of the metal (e.g., Al) constituting field plate 12a into guard ring 8a. As shown in Fig. 2A, barrier metal layer 11a is provided below field plate 12a in a region that overlaps field plate 12a in a plan view.

[0021] More specifically, in regions where insulating films 9a and 9b are not provided, barrier metal layer 11a is interposed between field plate 12a and guard ring 8a. Furthermore, in regions where insulating films 9a and 9b are provided, barrier metal layer 11a is interposed between field plate 12a and insulating films 9a and 9b. Furthermore, the entire area of ​​barrier metal layer 11a is covered by field plate 12a, and barrier metal layer 11a is formed so as not to protrude beyond field plate 12a. Similarly, another barrier metal layer 11b is provided below field plate 12b in a region that overlaps field plate 12b in a plan view.

[0022] The barrier metal layer 3 in the active region A1 has the function of preventing diffusion of a metal (e.g., Al) constituting the front-side main electrode 4 into the body layer 2. The barrier metal layer 3 is provided below the front-side main electrode 4 in a region overlapping the front-side main electrode 4 in a plan view. As shown in FIG. 2A, the barrier metal layer 3 in the active region A1 and the barrier metal layers 11a and 11b in the termination region A2 are spaced apart from each other. The barrier metal layers 3, 11a, and 11b may be made of, for example, Ti, TiN, TiW, or MoSi2.

[0023] Field plate 12a is an electrode connected to guard ring 8a via barrier metal layer 11a. By providing such field plate 12a, the depletion layer region extends horizontally, thereby mitigating the electric field associated with high voltage. Field plate 12a is provided above guard ring 8a via barrier metal layer 11a. Furthermore, the edge of field plate 12a in a plan view is located outside the edge of guard ring 8a. Similarly, another field plate 12b is provided above guard ring 8b via barrier metal layer 11b. As shown in FIG. 2A, field plates 12a and 12b are spaced apart from each other. These field plates 12a and 12b may be made of, for example, Al, AlSi, AlCu, or AlSiCu. The configuration of semiconductor chip 10 is not limited to the example shown in FIG. 2A.

[0024] <About barrier metal residue> For example, in the manufacturing process of semiconductor chip 10, when forming field plates 12a and 12b by patterning a conductive film, barrier metal layers 11a and 11b may not be sufficiently etched due to the influence of foreign matter, etc., and may remain as barrier metal residue. Such barrier metal residue will be described with reference to FIG. 2B.

[0025] FIG. 2B is a cross-sectional view taken along line II-II in FIG. 1, showing a state in which barrier metal residues M1 are present. In the example of FIG. 2B, barrier metal residue M1 exists in the gap between barrier metal layers 11a and 11b. In other words, barrier metal layers 11a and 11b and barrier metal residue M1 are substantially integrated. When such barrier metal residue M1 exists, field plates 12a and 12b are electrically connected via barrier metal residue M1. As a result, guard rings 8a and 8b connected to field plates 12a and 12b have the same potential, making it difficult to ensure sufficient breakdown voltage in termination region A2.

[0026] Furthermore, in termination region A2, a surge voltage of 1000 V or more may be applied to field plates 12a, 12b, which may lead to a surge current occurring between field plates 12a, 12b and barrier metal residue M1. As a result, the dielectric strength of field plates 12a, 12b may decrease, potentially reducing the reliability of semiconductor chip 10. Therefore, in this embodiment, a pulsed voltage is applied to semiconductor chip 10 to cause current to flow intermittently, thereby burning out barrier metal residue M1. This reduces barrier metal residue M1, thereby improving the reliability of semiconductor chip 10.

[0027] <Circuits for processing semiconductor chips> FIG. 3A is a diagram showing the configuration of a circuit 100 used in the process of burning off the barrier metal residue of the semiconductor chip 10. As shown in FIG. 3A, the semiconductor chip 10 enclosed by the dashed line frame is the target of treatment when the barrier metal residue is burned off. In FIG. 3A, the semiconductor chip 10 is an IGBT.

[0028] Incidentally, when the barrier metal residue of the semiconductor chip 10 is burned using the circuit 100 shown in FIG. 3A, the semiconductor chip 10 may be sealed with a predetermined resin or may not be sealed with a resin. The state where the semiconductor chip 10 is not sealed with a resin is also considered to be a "semiconductor chip." Furthermore, the predetermined process using the circuit 100 shown in FIG. 3A may be performed during the manufacturing or inspection stage of the semiconductor chip 10, in addition to the testing stage. Furthermore, the predetermined process using the circuit 100 may be performed when the semiconductor chip 10 is mounted on a printed circuit board (not shown) or incorporated into a predetermined device (not shown).

[0029] As shown in FIG. 3A, the circuit 100 includes a DC power supply 21, a capacitor 22, a first diode 23, a semiconductor chip 10, a switching element 24, a second diode 25, and a reactor 26.

[0030] The DC power supply 21 generates a predetermined DC voltage V cc The DC power supply 21 is a power supply for applying the DC voltage V cc The range may be, for example, 500V or more and 4500V or less, but is not limited to this. The capacitor 22 is an element for storing the electric charge flowing from the DC power supply 21 and discharging this electric charge, and is connected in parallel to the DC power supply 21 .

[0031] The first diode 23 is an element for blocking the flow of current from the capacitor 22 toward the semiconductor chip 10 without passing through the switching element 24. As shown in FIG. 3A, the first diode 23 has an anode connected to the collector of the semiconductor chip 10 and a cathode connected to the positive electrodes of the DC power supply 21 and the capacitor 22 via a wiring K1. The emitter of the semiconductor chip 10 is connected to the negative electrodes of the DC power supply 21 and the capacitor 22 via another wiring K2. The series connection of the first diode 23 and the semiconductor chip 10 is connected in parallel to the DC power supply 21 and the capacitor 22.

[0032] The switching element 24 is an element for switching between passing and cutting off current to the semiconductor chip 10. In the example of FIG. 3A, an IGBT is used as the switching element 24, but other types of elements such as a MOSFET or a bipolar transistor may also be used. As shown in FIG. 3A, the collector of the switching element 24 is connected to the positive electrodes of the DC power supply 21 and the capacitor 22 via wiring K1, and the emitter is connected to the cathode of the second diode 25. A predetermined pulse-like voltage is applied to the switching element 24 and each gate of the semiconductor chip 10 from a signal generator (not shown).

[0033] The second diode 25 is an element for circulating current when the switching element 24 is in the off state (see the dashed arrow in state C in FIG. 3B). The anode of the second diode 25 is connected to the negative electrodes of the DC power supply 21 and the capacitor 22 via the wiring K2. As described above, the cathode of the second diode 25 is connected to the emitter of the switching element 24. The series connection of the switching element 24 and the second diode 25 is connected in parallel to the DC power supply 21 and the capacitor 22.

[0034] The reactor 26 functions as a load inductance when a current flows through the semiconductor chip 10 and the switching element 24. One end of the reactor 26 is connected to the connection point between the first diode 23 and the semiconductor chip 10. The other end of the reactor 26 is connected to the connection point between the switching element 24 and the second diode 25.

[0035] FIG. 3B is an explanatory diagram showing the flow of current in the circuit 100 used in the process of burning off the barrier metal residue of the semiconductor chip 10. As shown in FIG. 3B indicate the flow of current in state A, state B, state C, and state D, respectively. State A, state B, state C, and state D in FIG. 3B correspond to state A, state B, state C, and state D in the time chart (see FIG. 4) described next. The flow of current in circuit 100 will be described in chronological order using this time chart (see FIG. 4).

[0036] FIG. 4 is a time chart relating to the method of processing the semiconductor chip (also see FIG. 3B as appropriate). 4, the horizontal axis represents time. The vertical axis represents, from the top of the page, the gate voltage of the switching element 24, the gate voltage of the semiconductor chip 10 to be processed, and the main current I flowing through the semiconductor chip 10. c (collector current), and the collector-emitter voltage V of the semiconductor chip 10 ce is.

[0037] For example, at time t1 in FIG. 4, the gate voltage of the semiconductor chip 10 is negative and the semiconductor chip 10 is in an off state, so that the DC voltage V cc is divided by the first diode 23 and the semiconductor chip 10. As a result, at time t1 in FIG. 4, the collector-emitter voltage V ce is at a predetermined value V1 (see also state A in FIG. 3B). At time t1, a predetermined voltage is applied to the gate of the switching element 24, turning the switching element 24 on. However, since the semiconductor chip 10 to be processed is off, the main current I c is not flowing.

[0038] At a subsequent time t2, a positive voltage is applied to the gate of the semiconductor chip 10, and the semiconductor chip 10 is also turned on. In other words, both the switching element 24 and the semiconductor chip 10 are turned on, and a predetermined main current I c Specifically, as shown by the dashed arrow in state B in FIG. 3B, a current from the capacitor 22 flows sequentially through the switching element 24, the reactor 26, and the semiconductor chip 10. Note that while the semiconductor chip 10 is in the on state, the collector-emitter voltage V ce becomes approximately zero (the voltage V ce ) In addition, since the reactor 26 has a predetermined inductance, the main current I c The waveform of does not become pulse-shaped, but increases over time from time t2, and at time t3, the main current I c reaches a predetermined peak value (predetermined value I1).

[0039] At time t3, the semiconductor chip 10 is in the ON state, but the switching element 24 is switched to the OFF state during this ON state. As a result, as shown by the dashed arrow in state C of FIG. 3B, the main current I cAt a subsequent time t4, the semiconductor chip 10 to be processed is also switched to the off state while the switching element 24 is maintained in the off state. As a result, the main current I c Also, the collector-emitter voltage V of the semiconductor chip 10 ce When the semiconductor chip 10 is switched to the OFF state, the main current I c However, current flows through another path in the circuit 100. Specifically, as indicated by the dashed arrow in state D of FIG. 3B, current flows sequentially through the second diode 25 and the parasitic diode (reference number not shown) of the switching element 24.

[0040] This series of processes is repeated periodically. As a result, a main current I c The switching frequencies of the semiconductor chip 10 and the switching element 24 are set appropriately within a range of, for example, 1 kHz or more and 10 kHz or less. c The duration of the current flow is set appropriately within a range of, for example, 1 to 100 seconds. c After performing the process of transmitting the signal for a predetermined time, the processing unit (not shown) of the signal generator (not shown) ends the process.

[0041] If barrier metal residue M1 (see FIG. 2B) is present on semiconductor chip 10, the high resistance of this barrier metal residue M1 causes a predetermined potential difference to occur between field plates 12a, 12b (see FIG. 2B) adjacent to barrier metal residue M1, causing current to flow. As a result, current also flows through barrier metal residue M1, causing barrier metal residue M1 to generate heat and burn out. This reduces barrier metal residue M1.

[0042] Incidentally, the electrical load on the termination region A2 (see FIG. 2B) becomes particularly large when the semiconductor chip 10 is turned off. Therefore, the rapid repetition of turning on and off the semiconductor chip 10 accelerates the burnout of the barrier metal residue M1.

[0043] In this embodiment, a pulsed voltage is applied to the gate of the semiconductor chip 10 having the active region A1 (see FIG. 1) and the termination region A2 (see FIG. 1) surrounding the active region A1, and a main current I c The current (current) is passed intermittently to burn off the barrier metal residue M1 (see FIG. 2B) in the termination region A2, thereby reducing the amount of barrier metal residue M1 on the semiconductor chip 10.

[0044] Figure 5 shows the main current I c FIG. 3B is an explanatory diagram of the above (see also FIG. 3B as appropriate). 5, the horizontal axis represents time, and the vertical axis represents the main current I c 5 is a graph showing the state of the semiconductor chip 10 when a main current I is supplied to the semiconductor chip 10 using a predetermined switching element 24, as in the circuit 100 of FIG. c 5 shows the waveform of one time when the main current I is intermittently applied. The dashed line graph in FIG. 5 shows the waveform of one time when the main current I is applied to the gate of the semiconductor chip 10 without using the switching element 24. c The waveform shown is for one time when the voltage is applied intermittently.

[0045] For example, it is possible to burn out the barrier metal residue M1 even when a pulsed voltage is applied to the semiconductor chip 10 without using the switching element 24. However, if an attempt is made to ensure a sufficient turn-on time for the semiconductor chip 10 in this case, carriers continue to be injected from the capacitor 22 into the semiconductor chip 10 during the on-state (in the case of "follow current" in FIG. 5). As a result, as shown by the dashed line in the graph of FIG. 5, the main current I cAs the value of I increases, the main current I becomes larger than necessary (i.e., larger than the predetermined value I1). c may flow into the semiconductor chip 10.

[0046] Therefore, in this embodiment, when the semiconductor chip 10 is in the on state, the switching element 24 is switched to the off state to stop the supply of carriers (follow-through current) from the capacitor 22. That is, in the process of burning out the barrier metal residue M1 (see FIG. 2B) in the termination region A2 (see FIG. 2B), the supply of carriers to the semiconductor chip 10 is stopped by switching a predetermined switching element 24 electrically connected to the semiconductor chip 10 from the on state to the off state.

[0047] As a result, the main current I c While ensuring the current flow time t, the main current I c It is possible to provide a period during which the peak value of becomes substantially constant at a predetermined value I1. Furthermore, by stabilizing the injection of carriers into the semiconductor chip 10, the electrical load on the termination region A2 (see FIG. 2B) can be made uniform, thereby suppressing current imbalance.

[0048] Figure 6A shows the collector-emitter voltage V of a semiconductor chip. ce 10 is an explanatory diagram showing the relationship between the loss in the barrier metal residue and the loss in the barrier metal residue. The horizontal axis of FIG. 6A represents the collector-emitter voltage V applied to the semiconductor chip 10 to be processed in the circuit 100 of FIG. 3A. ce (Test voltage). The vertical axis of FIG. 6A represents the loss in the barrier metal residue M1 of the semiconductor chip 10. Here, "loss" refers to the amount of heat generated in the barrier metal residue M1 due to the passage of current. As shown in FIG. 6A, the collector-emitter voltage V ce The higher the temperature, the greater the loss in the barrier metal residue M1, i.e., the more likely the barrier metal residue M1 is to be burned away.

[0049] The resistance value of the barrier metal residue M1 is relatively high, but by applying a certain high voltage, a moderate amount of main current I c (collector current) flows through the semiconductor chip 10, and the barrier metal residue M1 is burned. Note that the collector-emitter voltage V ce is set appropriately within the range of the rated voltage.

[0050] FIG. 6B shows the main current I c 10 is an explanatory diagram showing the relationship between the peak value of the resistance and the loss in the barrier metal residue. The horizontal axis of FIG. 6B represents the main current I that flows intermittently through the semiconductor chip 10 to be processed. c 6B. In other words, the magnitude of the predetermined value I1 shown in FIG. 4 and FIG. 5 corresponds to the horizontal axis of FIG. 6B. The vertical axis of FIG. 6B represents the loss in the barrier metal residue M1 of the semiconductor chip 10. As shown in FIG. 6B, the main current I c The larger the value of , the greater the loss of the barrier metal residue M1. In other words, the barrier metal residue M1 is more likely to be burned.

[0051] In addition, in the process of burning off the barrier metal residue M1 (see FIG. 2B) in the termination region A2 (see FIG. 2B), a main current I c It is preferable to set the peak value of the current to be greater than or equal to 1 / 10 and less than or equal to 1 / 2 (the "predetermined range" shown in FIG. 6B) of the rated current of the semiconductor chip 10. Experiments by the inventors have confirmed that this allows the barrier metal residue M1 of the semiconductor chip 10 to be appropriately burned (removed).

[0052] When a large current flows through the semiconductor chip 10, screws are often used to reduce contact resistance in the electrical connection of the semiconductor chip 10. In contrast, in this embodiment, the main current I cis relatively small. Therefore, in the process of burning off the barrier metal residue M1 (see FIG. 2B) in the termination region A2 (see FIG. 2B), it becomes possible to use contact probes (not shown) for electrical connection (connection of the collector and emitter) of the semiconductor chip 10. This reduces the effort and cost required for electrical connection of the semiconductor chip 10.

[0053] The main current I of the semiconductor chip 10 c 6B. In other words, it is not necessary for the barrier metal residue M1 to be completely burned away, and the main current I c The peak value of the main current I may be less than 1 / 10 of the rated current (for example, in the range of 1 / 20 or more and less than 1 / 10 of the rated current). c The peak value of may be greater than 1 / 2 of the rated current (for example, in the range of greater than 1 / 2 and equal to or less than 2 / 3 of the rated current).

[0054] <Effects> According to this embodiment, a pulsed voltage is applied to the gate of the semiconductor chip 10, causing a current to flow intermittently through the semiconductor chip 10, thereby burning off the barrier metal residue M1 in the termination region A2. This reduces the barrier metal residue M1, ensuring sufficient breakdown voltage in the termination region A2. Furthermore, surge currents are less likely to occur in the semiconductor chip 10, ensuring sufficient breakdown voltage between the field plates 12a and 12b. This improves the reliability of the semiconductor chip 10.

[0055] In this embodiment, the supply of carriers to the semiconductor chip 10 is stopped by switching the switching element 24 to the off state. This allows a current with a moderately suppressed peak value to flow intermittently through the semiconductor chip 10.

[0056] Furthermore, by setting the peak current value of the semiconductor chip 10 within the range of 1 / 10 to 1 / 2 of the rated current, the barrier metal residue M1 can be burned appropriately. Since there is no particular need to pass a large current through the semiconductor chip 10 when burning off the barrier metal residue M1, the device used for this process (device including the circuit 100 in FIG. 3A; not shown) can be made smaller. This allows for lower costs and space savings for devices including the semiconductor chip 10.

[0057] Also, since there is no particular need to pass a large current through the semiconductor chip 10 and the amount of heat generated by the semiconductor chip 10 is reduced, there is no need for a cooling device (not shown) to cool the device. Furthermore, by using contact probes (not shown) for electrical connection of the semiconductor chip 10, the connection work can be simplified. This not only improves the production efficiency of the semiconductor chip 10 but also improves maintainability.

[0058] <<Variations>> Although the method for processing the semiconductor chip 10 according to the present disclosure has been described above in the embodiments, it is not limited to these descriptions and various modifications can be made. For example, in the embodiment, the case where the supply of carriers to the semiconductor chip 10 is stopped by switching the switching element 24 from the on state to the off state has been described, but this is not limiting. That is, without using the switching element 24, a pulsed voltage may be applied to the gate of the semiconductor chip 10 so that the semiconductor chip 10 is alternately turned on and off. Even in this type of process, the peak value of the current in the semiconductor chip 10 becomes slightly larger, but the barrier metal residue M1 can be burned.

[0059] In addition, although the embodiment has been described with reference to a case where the semiconductor chip 10 is an IGBT, the present invention is not limited to this. That is, the embodiment can also be applied to other types of elements that have an active region and a termination region and in which barrier metal residue may occur in the termination region.

[0060] The present disclosure is not limited to the above-described embodiments and includes various modifications. For example, the embodiments have been described in detail to clearly explain the present disclosure, and the present disclosure is not necessarily limited to those including all of the described configurations. Furthermore, it is possible to add, delete, or replace part of the configuration of the embodiments with other configurations.

[0061] Furthermore, the above-mentioned configurations, functions, processing units, processing means, etc. may be partly or entirely implemented in hardware, for example, by designing them as integrated circuits. Furthermore, the above-mentioned configurations, functions, etc. may be implemented in software, with a processor interpreting and executing a program that implements each function. Information such as the programs, tables, and files that implement each function can be stored in a memory, a recording device such as a hard disk or SSD (Solid State Drive), or a recording medium such as an IC card, SD card, or DVD. In addition, the control lines and information lines shown are those that are considered necessary for the explanation, and do not necessarily show all the control lines and information lines in the product. In reality, it can be assumed that almost all components are interconnected. [Explanation of symbols]

[0062] 1. Semiconductor substrate 2. Body Layer 3 Barrier metal layer 4 Main electrode on the front side 5. Buffer layer 6 Collector layer 7 Back side main electrode 8a, 8b Guard ring 9a, 9b, 9c insulating film 10 Semiconductor chips 11a, 11b Barrier metal layer 12a, 12b Field plate 21 DC power supply 22 Capacitor 23 First diode 24 Switching element 25 Second diode 26 Reactor 100 circuits A1 active area A2 Termination Area Ha,Hb,Hc opening M1 Barrier metal residue

Claims

1. A method for processing a semiconductor chip, comprising applying a pulsed voltage to a gate of the semiconductor chip having an active area and a termination area surrounding the active area, and passing a current intermittently through the semiconductor chip to burn off any barrier metal residue in the termination area.

2. The peak value of the current that flows intermittently through the semiconductor chip during the process is equal to or greater than 1 / 10 and equal to or less than 1 / 2 of the rated current of the semiconductor chip.

2. The method for processing semiconductor chips according to claim 1, wherein:

3. In the process, a predetermined switching element electrically connected to the semiconductor chip is switched from an on state to an off state to stop the supply of carriers to the semiconductor chip.

2. The method for processing semiconductor chips according to claim 1, wherein:

4. In the process, contact probes are used for electrical connection of the semiconductor chips.

4. The method for processing semiconductor chips according to claim 1, wherein:

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