Frequency monitoring circuit and frequency monitoring program

Abstract

To provide a frequency monitoring circuit and a frequency monitoring program which can detect a deviation of clock frequency even when no clocks are inputted.SOLUTION: A frequency monitoring circuit includes a frequency drift determination unit for generating a frequency-divided clock from a clock of specific frequency by dividing it by a specific division number, detects an edge corresponding to the cycle of the frequency-divided clock, outputs an edge pulse corresponding to the cycle of the detected edge, counts the cycles of the edge pulse with a clock of a frequency different from the specific frequency, compares the counted count number with a specific expected value, and determines whether or not there is a drift of the specific frequency according to the result of comparison.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present disclosure relates to a frequency monitoring circuit and a frequency monitoring program. [Background technology]

[0002] As in-vehicle systems become more electronic, functional safety is required of on-board components. Display controllers are required to implement a function to detect abnormalities in the telltale displays that show the vehicle's operating status and notify the outside world. For example, one abnormal state is when the input video synchronization signal or input clock is stuck at a high or low level, or when the input video clock is not at the intended frequency, causing the telltale display of the input video itself to be input in a corrupted state, and this must be detected as an abnormal state.

[0003] Patent Document 1 discloses a technique for improving the detection accuracy of a synchronization signal by utilizing the clock edge of a clock signal. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Patent No. 5363056 Summary of the Invention [Problem to be solved by the invention]

[0005] However, with conventional technology, even if it is possible to detect an abnormal state when there is no clock input, it is not possible to detect a deviation in the frequency of the clock signal. In other words, when the clock is fixed at a high level or a low level, it is difficult to detect even if the clock frequency deviates from the intended frequency.

[0006] In view of the above circumstances, the present disclosure aims to provide a frequency monitoring circuit and a frequency monitoring program that can detect deviations in the frequency of an input clock even when no clock is input. [Means for solving the problem]

[0007] In order to solve the above-described problems, a frequency monitoring circuit according to the present disclosure is a frequency monitoring circuit provided in a semiconductor device, and the frequency monitoring circuit includes a frequency deviation determination unit that generates a divided clock by dividing a clock of a specific frequency by a specific division number, detects an edge corresponding to a period of the divided clock, outputs an edge pulse corresponding to the period of the detected edge, counts the period of the edge pulse using a clock of a frequency different from the specific frequency, compares the counted number with a specific expected value, and determines whether or not there is a deviation in the specific frequency depending on the result of the comparison.

[0008] The frequency monitoring program according to the present disclosure causes a computer to execute the following process: generate a divided clock by dividing a clock of a specific frequency by a specific division number; detect an edge corresponding to the period of the divided clock; output an edge pulse corresponding to the period of the detected edge; count the period of the edge pulse using a clock of a frequency different from the specific frequency; compare the counted number with a specific expected value; and determine whether or not there is a deviation in the specific frequency depending on the result of the comparison. [Brief explanation of the drawings]

[0009] [Figure 1] FIG. 1 is a diagram showing an example of the configuration of a display system 10 including a frequency monitoring circuit 100 according to an embodiment of the present disclosure. [Figure 2] FIG. 2 is a diagram illustrating a hardware configuration of the frequency monitoring circuit 100 according to an embodiment of the present disclosure. [Figure 3] FIG. 3 is a diagram showing an example of the configuration of the frequency monitoring circuit 100. As shown in FIG. [Figure 4] FIG. 4 is a timing chart for explaining the operation of the frequency monitoring circuit 100. In FIG. [Figure 5] FIG. 5 is a diagram showing an example of the configuration of a frequency monitoring circuit 100A according to a comparative example. [Figure 6] FIG. 6 is a diagram showing an example of the configuration of a frequency monitoring circuit 100-1 according to the first modified example. [Figure 7] FIG. 7 is a diagram showing an example of the configuration of a frequency monitoring circuit 100-2 according to the second modified example. [Figure 8A] FIG. 8A is a diagram for explaining the operation of the frequency monitoring circuit 100-2 according to the second modified example. [Figure 8B] FIG. 8B is a diagram for explaining the operation of the frequency monitoring circuit 100-2 according to the second modified example. DETAILED DESCRIPTION OF THE INVENTION

[0010] Hereinafter, embodiments will be described with reference to the drawings. Note that the same or similar reference numerals are used to designate the same functions or configurations, and descriptions thereof will be omitted as appropriate.

[0011] (Embodiment) FIG. 1 is a diagram showing an example of the configuration of a display system 10 including a frequency monitoring circuit 100 according to an embodiment of the present disclosure.

[0012] The display system 10 may include a graphics generation unit 11, a video processing device 12, a frame memory 13, a display device 14, and an MCU (Micro Controller Unit) 15. The display system 10 is mounted on, for example, a vehicle.

[0013] The graphics generation unit 11 is connected to a video processing device 12. The video processing device 12 is connected to a frame memory 13 and a display device 14. The MCU 15 is connected to the graphics generation unit 11, the video processing device 12, and the display device 14.

[0014] The graphics generation unit 11 generates video data that graphically represents information such as navigation information required for vehicle travel. The graphics generation unit 11 sequentially supplies the video data for each frame to the video processing device 12 in frame order. The video data here refers to the image data for each frame.

[0015] The video processing device 12 includes a processor 15. An example of the processor 15 is a programmable logic device (PLD) such as a field programmable gate array (FPGA), whose circuit configuration can be changed after manufacturing. The processor 15 may be a central processing unit (CPU), which is a general-purpose processor that executes software (programs). The processor 15 may also be a combination of two or more processors of the same or different types.

[0016] The video processing device 12 acquires video data sequentially supplied from the graphics generation unit 11, divides the video data into data blocks of a predetermined size, and writes each data block to the frame memory 13. The video processing device 12 then sequentially reads out the data blocks written to the frame memory 13. The video processing device 12 can change the read frequency relative to the write frequency. The video processing device 12 performs burst transfer when writing data blocks to the frame memory 13 and when reading data blocks from the frame memory 13.

[0017] The frame memory 13 includes a RAM (Random Access Memory) having multiple storage areas so that data blocks of video data for multiple frames can be stored. The frame memory 13 is an example of a memory according to the disclosed technology.

[0018] The display device 14 includes a display (not shown) and is a device that displays an image based on the image data input from the image processing device 12 on the display.

[0019] The MCU 15 is a control unit that controls the entire display system 10. The control contents of the MCU 15 include, for example, control of the operation timing of the graphics generation unit 11, the video processing device 12, and the display device 14.

[0020] Each of the graphic generation unit 11, the video processing device 12, and the display device 14 may include a frequency monitoring circuit 100. The frequency monitoring circuit 100 may be provided in one or more of the graphic generation unit 11, the video processing device 12, and the display device 14. The frequency monitoring circuit 100 may be interpreted as a circuit that uses at least two clocks, such as a reference clock generated by a reference clock generation source such as a crystal oscillator, and an internal clock generated by a device other than the reference clock generation source such as the display system 10, or an input video clock, and monitors the frequency deviation of each clock. When a deviation in the clock frequency occurs, the frequency monitoring circuit 10 can notify the occurrence of the frequency deviation.

[0021] Specifically, the frequency monitoring circuit 100 can use the clock used by the video processing device 12 and the clock used by one of the peripheral devices of the video processing device 12, such as the graphics generation unit 11 and the display device 14, to report a frequency deviation of at least one of these clocks.

[0022] Next, a hardware configuration of the frequency monitoring circuit 100 will be described with reference to Fig. 2. Fig. 2 is a diagram showing a hardware configuration of the frequency monitoring circuit 100 according to an embodiment of the present disclosure.

[0023] The frequency monitoring circuit 100 may include an input / output I / F (Interface) 41, a memory 42, and a processor 43. The input / output I / F 41 may be considered an interface for communicating with an in-vehicle device. The memory 42 may store a frequency monitoring program 42a that monitors the frequency of a clock. The processor 43 may execute specific processing by deploying the frequency monitoring program 42a. The function realized by the frequency monitoring program 42a may be considered as a frequency deviation determination unit, which will be described later. Note that the frequency deviation determination unit may be realized by a circuit other than the frequency monitoring program 42a.

[0024] Next, an example of the configuration of the frequency monitoring circuit 100 will be described with reference to Fig. 3. Fig. 3 is a diagram showing an example of the configuration of the frequency monitoring circuit 100.

[0025] The frequency monitoring circuit 100 may include a setting register 101 that stores various information, and a frequency deviation determining unit 102.

[0026] The frequency deviation determination unit 102 may generate a divided clock by dividing a clock of a specific frequency by a specific division number, detect an edge corresponding to the period of the divided clock, and output an edge pulse corresponding to the period of the detected edge.The frequency deviation determination unit 102 may count the period of the edge pulse using a clock of a frequency different from the specific frequency, compare the counted number with a specific expected value, determine whether or not there is a deviation in the clock frequency depending on the comparison result, and transmit the determination result to an external device.

[0027] The frequency deviation determination unit 102 may include a first frequency divider unit 20, a first edge detector unit 21, a first counter 22, a first judgment unit 23, a second frequency divider unit 30, a second edge detector unit 31, a second counter 32, a second judgment unit 33, and a result output unit 60.

[0028] The first frequency divider 20 may generate a divided clock DC1 by dividing a clock CLK1 of a first frequency by a specific frequency division number D1. The clock CLK1 may be interpreted as a reference clock or as a clock other than the reference clock. The frequency division number D1 may be interpreted as a divided clock number. The frequency division number D1 can be set from outside the frequency deviation determination unit 102 and may be stored in the setting register 101, for example.

[0029] The first edge detecting section 21 may detect an edge corresponding to the period of the divided clock DC1 from the first frequency dividing section 20, and output an edge pulse P1 corresponding to the period of the detected edge. Specifically, the first edge detecting section 21 may output the edge pulse P1 at a timing when the divided clock DC1 and the clock CLK2 of the second frequency are synchronized. The second frequency of the clock CLK2 may be interpreted as being different from the first frequency. The clock CLK2 may be interpreted as a reference clock, or as a clock other than the reference clock.

[0030] The first counter 22 may count the period of the edge pulse P1 from the first edge detector 21 using the clock CLK2 of the second frequency.

[0031] The first determination unit 23 may compare the count number C1 counted by the first counter 22 with a specific expected value Ce1 and determine whether or not there is a deviation in the first frequency of the clock CLK1 based on the comparison result. The expected value Ce1 may be interpreted as a value in a specific range ranging from a first value obtained by adding a value X to a specific value to a second value obtained by subtracting a value from the specific value. More specifically, if the first frequency of the clock CLK1 is, for example, 10.00 MHz, the expected value Ce1 may be interpreted as a value ranging from 9.98 MHz to 10.02 MHz. The expected value Ce1 can be set externally to the frequency deviation determination unit 102 and may be stored in, for example, the setting register 101. If there is a deviation in the first frequency of the clock CLK1, the first determination unit 23 may output a signal CR1 indicating that a deviation in the first frequency has occurred.

[0032] The second frequency divider 30 may generate a frequency-divided clock DC2 by dividing the second frequency clock CLK2 by a specific frequency division number D2. The frequency division number D2 may be interpreted as the number of divided clocks. The frequency division number D2 can be set externally to the frequency deviation determination unit 102 and may be stored in the setting register 101, for example.

[0033] The second edge detecting section 31 may detect an edge corresponding to the period of the frequency-divided clock DC2 from the second frequency dividing section 30, and output an edge pulse P2 corresponding to the period of the detected edge. Specifically, the second edge detecting section 31 may output the edge pulse P2 at a timing when the frequency-divided clock DC2 and the clock CLK1 of the first frequency are synchronized.

[0034] The second counter 32 may count the period of the edge pulse P2 from the second edge detector 31 using the clock CLK1 of the first frequency.

[0035] The second determination unit 33 may compare the count number C2 counted by the second counter 32 with a specific expected value Ce2 and determine whether or not there is a deviation in the second frequency of the clock CLK2 based on the comparison result. The expected value Ce2 may be interpreted as a value in a specific range, similar to the aforementioned expected value Ce1. For example, if the second frequency of the clock CLK2 is 100.00 MHz, the expected value Ce2 may be interpreted as a value between 99.98 MHz and 100.02 MHz. The expected value Ce2 can be set externally to the frequency deviation determination unit 102 and may be stored in, for example, the setting register 101. If there is a deviation in the second frequency of the clock CLK2, the second determination unit 33 may output a signal CR2 indicating that a deviation in the second frequency has occurred.

[0036] When the result output section 60 receives the outputs (signals CR1 and CR2) from the first judgment section 23 and the second judgment section 33, it may output a signal ER indicating that a frequency deviation has occurred in at least one of the first frequency of clock CLK1 and the second frequency of clock CLK2. The signal ER may be interpreted as an error signal indicating that a frequency deviation has occurred in either clock CLK1 or clock CLK2, that is, that an abnormality has occurred in either clock CLK1 or clock CLK2.

[0037] In this way, the frequency monitoring circuit 100 can use two paths to determine whether there is an error in each of the two clocks, i.e., whether there is a deviation in their frequencies. By performing error determination on multiple paths, it is possible to notify an external device that a frequency deviation has occurred in one of the multiple clocks.

[0038] Furthermore, in the frequency monitoring circuit 100, the frequency division numbers D1 and D2 for setting the frequency-divided clocks DC1 and DC2 can be set externally. Furthermore, in the frequency monitoring circuit 100, the expected values ​​Ce1 and Ce2 for determining whether or not there is a deviation in the first frequency of the clock CLK1 and whether or not there is a deviation in the second frequency of the clock CLK2 can be set externally. This allows the value of the frequency to be subject to error determination to be set at any timing, so that, for example, even after a video processing device 12 equipped with the frequency monitoring circuit 100 has been shipped, it is possible to detect a frequency deviation in any of the multiple clocks.

[0039] Next, the operation of the frequency monitoring circuit 100 will be described with reference to Fig. 4. Fig. 4 is a timing chart for explaining the operation of the frequency monitoring circuit 100. Fig. 4 shows an example of an error determination operation when the frequency of clock CLK1 is lower than the frequency of clock CLK2. Fig. 4 shows the waveform of clock CLK1, the divided clock DC1 when the division number D1 is 4, the waveform of clock CLK2, the waveform of edge pulse P1, the count number C1 counted by the first counter 22, and the signal CR1.

[0040] For example, if the value of the count number C1 is within the expected value Ce1 (10±3), CR1 is not output. Specifically, if the value of the count number C1 is equal to or greater than the lower limit 7 of the expected value Ce1 and equal to or less than the upper limit 13 of the expected value Ce1, no deviation of the first frequency has occurred, and therefore the output level of the first judgment unit 23 becomes low level L. In other words, the signal CR1 indicating that a deviation of the first frequency has occurred is not output.

[0041] When the value of the count number C1 is not within the expected value Ce1, a signal CR1 of high level H is output. Specifically, when the value of the count number C1 is less than the lower limit 7 of the expected value Ce1 or exceeds the upper limit 13 of the expected value Ce1, the output level of the first judgment unit 23 becomes high level H. In other words, a signal CR1 indicating that a deviation of the first frequency has occurred is output.

[0042] FIG. 5 illustrates a configuration example of a frequency monitoring circuit 100A according to a comparative example. The frequency monitoring circuit 100A synchronizes the vertical synchronization signal Vsync and the horizontal synchronization signal Hsync with an input clock CLK, such as a reference clock, and then synchronizes the vertical synchronization signal Vsync and the horizontal synchronization signal Hsync with an oscillator clock CLK. At this time, synchronization detection is performed by checking whether the oscillator clock synchronized synchronization signal transitions within a set Line and set time. If any of the vertical synchronization signal Vsync, the horizontal synchronization signal Hsync, or the input clock CLK is not input, the vertical synchronization signal Vsync and the horizontal synchronization signal Hsync synchronized with the input clock CLK are fixed at a high or low level, and these signals do not transition, resulting in a non-detection of the synchronization signal. In other words, even if the input clock CLK deviates from the intended frequency, synchronization detection is performed as long as signals such as the input clock CLK are transitioning.

[0043] The frequency monitoring circuit 100 of the present disclosure uses at least two clocks to monitor the frequency deviation of each clock, and if a frequency deviation occurs in either clock, it can notify that a frequency deviation has occurred.

[0044] (First Modification) 6 is a diagram showing an example of the configuration of a frequency monitoring circuit 100-1 according to a first modified example. The frequency monitoring circuit 100-1 may include a frequency deviation determining unit 102-1 instead of the frequency deviation determining unit 102. When the counted number exceeds a specific value, the frequency deviation determining unit 102-1 may output a signal indicating that the count number has exceeded the specific value. This signal may be interpreted as an overflow signal indicating that the count number has overflowed.

[0045] Specifically, when the clock CLK1 is not input, the first edge detection unit 21 cannot detect the edge pulse P1. Therefore, when the first counter 22 counts the period of the edge pulse P1 from the first edge detection unit 21 using the clock CLK2 of the second frequency, the count C1 exceeds a specific value. When the first counter 22 detects this state, it outputs an overflow signal OV1. When the result output unit 60 receives the overflow signal OV1, it may output a signal ER.

[0046] When the clock CLK2 is not input, the second edge detection unit 31 cannot detect the edge pulse P2. Therefore, when the second counter 32 counts the period of the edge pulse P2 from the second edge detection unit 31 using the clock CLK1 of the first frequency, the count C2 exceeds a specific value. When the second counter 32 detects this state, it outputs an overflow signal OV2. When the result output unit 60 receives the overflow signal OV2, it may output a signal ER.

[0047] According to the frequency monitoring circuit 100-1 of the first modified example, an error signal can be output not only when a frequency deviation occurs in either the clock CLK1 or the clock CLK2, but also when either the clock CLK1 or the clock CLK2 is in a no-input state.

[0048] (Second Modification) Fig. 7 is a diagram showing an example of the configuration of a frequency monitoring circuit 100-2 according to the second modified example. Fig. 8A and Fig. 8B are diagrams for explaining the operation of the frequency monitoring circuit 100-2 according to the second modified example.

[0049] The frequency monitoring circuit 100-2 may include a frequency deviation determination unit 102-2 instead of the frequency deviation determination unit 102. The frequency deviation determination unit 102-2 may include a first error determination unit 24 and a second error determination unit 34 in addition to the functions of the frequency deviation determination unit 102.

[0050] The frequency deviation determining section 102-2 may have the following first and second functions.

[0051] (First function) The frequency deviation determination unit 102-2 may count up a signal indicating that a specific frequency deviation has occurred, and if the counted up value exceeds a specific number of times, output a signal indicating that an abnormality has occurred in one of the clocks.

[0052] Specifically, when the first error judgment unit 24 receives the selection signal E1, it counts up the signal CR1 as shown in FIG. 8A, and when the counted up value exceeds a specific number T1 (error count threshold), it outputs a signal ER1 indicating that an abnormality has occurred in the clock CLK1 because a deviation in the first frequency of the clock CLK1 is occurring steadily.

[0053] Similarly, when the second error judgment unit 34 receives the selection signal E1, it counts up the signal CR2, and when the counted up value exceeds a specific number T1 (error count threshold), it outputs a signal ER2 indicating that an abnormality has occurred in the clock CLK2 because a deviation in the second frequency of the clock CLK2 is occurring steadily.

[0054] The selection signal E1 may be interpreted as a signal that causes the frequency deviation determination unit 102-2 to execute the first function. The number of times T1 may be interpreted as a threshold value for determining whether an abnormality has occurred in each clock. The selection signal E1 and the number of times T1 may be output from the setting register 101, or may be provided to the frequency monitoring circuit 100-2 directly from outside the frequency monitoring circuit 100-2.

[0055] With the first function, even if temporary noise occurs around the frequency monitoring circuit 100-2, error notification is suppressed until a signal indicating that a frequency shift has occurred is detected a certain number of times, thereby avoiding false detection of a frequency shift.

[0056] (Second function) The frequency deviation determination unit 102-2 may count up and down a signal indicating that a specific frequency deviation has occurred, and when the counted up and down values ​​exceed a specific number of times, output a signal indicating that an abnormality has occurred in one of the clocks.

[0057] 8B, depending on whether or not the signal CR1 is generated. That is, the first error determination unit 24 up-counts the signal CR1 when the signal CR1 is generated at a specific timing, and down-counts the counter when the signal CR1 is not generated after the specific timing. If the up-counted or down-counted value exceeds a specific number T2 (error count threshold), deviation of the first frequency of the clock CLK1 is steadily occurring, and the first error determination unit 24 may output the signal ER1.

[0058] Similarly, when the second error determination unit 34 receives the selection signal E2, it counts up or down the counter depending on whether or not the signal CR2 is generated. That is, the second error determination unit 34 counts up the signal CR2 when the signal CR2 is generated at a specific timing, and counts down the counter when the signal CR2 is not generated after the specific timing. If the counted up or counted down value exceeds a specific number T2 (error count threshold), this indicates that a deviation in the second frequency of the clock CLK2 is steadily occurring, and the second error determination unit 34 may output the signal ER2.

[0059] The selection signal E2 may be interpreted as a signal that causes the frequency deviation determination unit 102-2 to execute the second function. The number of times T2 may be interpreted as a threshold value for determining that an abnormality has occurred in each clock. The selection signal E2 and the number of times T2 may be output from the setting register 101, or may be provided to the frequency monitoring circuit 100-2 from outside the frequency monitoring circuit 100-2.

[0060] The second function prevents unnecessary error notifications, even when the clock frequency is generated while fluctuating up and down within a specific range, thereby making it possible to avoid erroneous detection of frequency deviation.

[0061] The frequency monitoring circuit 100-2 according to the second modification can suppress unnecessary error notifications even when a sudden disturbance or a fluctuation within the normal range of the clock frequency occurs.

[0062] In addition, the following supplementary notes are provided in relation to the above description.

[0063] (Appendix 1) A frequency monitoring circuit provided in a semiconductor device, The frequency monitoring circuit A clock having a specific frequency is divided by a specific division number to generate a divided clock. Detecting an edge corresponding to the period of the divided clock, and outputting an edge pulse corresponding to the period of the detected edge; Counting the period of the edge pulse with a clock having a frequency different from the specific frequency, comparing the counted number with a specific expected value, and determining whether or not there is a deviation in the specific frequency depending on the result of the comparison; A frequency monitoring circuit including a frequency deviation determination unit.

[0064] (Appendix 2) The frequency deviation determination unit a first frequency dividing unit that generates a frequency-divided clock by dividing a clock of a first frequency by a specific frequency division number; a first edge detection unit that detects an edge corresponding to a period of the divided clock from the first frequency division unit and outputs an edge pulse corresponding to the period of the detected edge; a first counter that counts the period of the edge pulse from the first edge detection unit using a clock having a second frequency different from the first frequency; a first determination unit that compares the count number counted by the first counter with a specific expected value and determines whether or not there is a deviation in the first frequency depending on the comparison result; a second frequency dividing unit that generates a frequency-divided clock by dividing the second frequency clock by a specific frequency division number; a second edge detection unit that detects an edge corresponding to a period of the divided clock from the second frequency division unit and outputs an edge pulse corresponding to the period of the detected edge; a second counter that counts the period of the edge pulse from the second edge detection unit using a clock of the first frequency; a second determination unit that compares the count number counted by the second counter with a specific expected value and determines whether or not there is a deviation in the second frequency depending on the comparison result; 2. The frequency monitoring circuit of claim 1, comprising:

[0065] (Appendix 3) The frequency deviation determination unit 3. The frequency monitoring circuit according to claim 1, wherein, when the counted number exceeds a specific value, the frequency monitoring circuit outputs a signal indicating that the count number has exceeded the specific value.

[0066] (Appendix 4) The frequency deviation determination unit 4. The frequency monitoring circuit according to any one of claims 1 to 3, wherein a signal indicating that a deviation of the specific frequency has occurred is counted up, and when the counted up value exceeds a specific number of times, a signal indicating that an abnormality has occurred in one of the clocks is output.

[0067] (Appendix 5) The frequency deviation determination unit 5. The frequency monitoring circuit according to claim 1, wherein the frequency monitoring circuit up-counts and down-counts a signal indicating that a deviation in the specific frequency has occurred, and when the up-counted and down-counted value exceeds a specific number of times, outputs a signal indicating that an abnormality has occurred in one of the clocks.

[0068] (Appendix 6) On the computer, A clock having a specific frequency is divided by a specific division number to generate a divided clock. Detecting an edge corresponding to the period of the divided clock, and outputting an edge pulse corresponding to the period of the detected edge; Counting the period of the edge pulse with a clock having a frequency different from the specific frequency, comparing the counted number with a specific expected value, and determining whether or not there is a deviation in the specific frequency depending on the result of the comparison; A frequency monitoring program to execute the process. [Explanation of symbols]

[0069] 10 Display System 11 Graphics Generation Unit 12 Image processing device 13 Frame Memory 14 Display device 15 processors 20 1st dividing section 21 First edge detection unit 22 First Counter 23 1st Judgment Section 24 First error determination unit 30 2nd dividing section 31 Second edge detection unit 32 Second Counter 33 Second Judgment Section 34 Second error detection unit 42 memory 42a Frequency Monitoring Program 43 processors 60 Result output section 100, 100A, 100-1, 100-2 Frequency monitoring circuit 101 Configuration Register 102, 102-1, 102-2 Frequency deviation determination unit

Claims

1. A frequency monitoring circuit provided in a semiconductor device, The frequency monitoring circuit A clock having a specific frequency is divided by a specific division number to generate a divided clock. Detecting an edge corresponding to the period of the divided clock, and outputting an edge pulse corresponding to the period of the detected edge; Counting the period of the edge pulse with a clock having a frequency different from the specific frequency, comparing the counted number with a specific expected value, and determining whether or not there is a deviation in the specific frequency depending on the result of the comparison; A frequency monitoring circuit including a frequency deviation determination unit.

2. The frequency deviation determination unit a first frequency dividing unit that generates a frequency-divided clock by dividing a clock of a first frequency by a specific frequency division number; a first edge detection unit that detects an edge corresponding to a period of the divided clock from the first frequency division unit and outputs an edge pulse corresponding to the period of the detected edge; a first counter that counts the period of the edge pulse from the first edge detection unit using a clock having a second frequency different from the first frequency; a first determination unit that compares the count number counted by the first counter with a specific expected value and determines whether or not there is a deviation in the first frequency depending on a result of the comparison; a second frequency divider that generates a frequency-divided clock by dividing the second frequency clock by a specific frequency division number; a second edge detection unit that detects an edge corresponding to a period of the divided clock from the second frequency division unit and outputs an edge pulse corresponding to the period of the detected edge; a second counter that counts the period of the edge pulse from the second edge detection unit using a clock of the first frequency; a second determination unit that compares the count number counted by the second counter with a specific expected value and determines whether or not there is a deviation in the second frequency depending on the comparison result; 2. The frequency monitoring circuit of claim 1, comprising:

3. The frequency deviation determination unit 2. The frequency monitoring circuit according to claim 1, wherein when the counted number exceeds a specific value, the frequency monitoring circuit outputs a signal indicating that the count number has exceeded the specific value.

4. The frequency deviation determination unit 2. The frequency monitoring circuit according to claim 1, wherein a signal indicating that a deviation of the specific frequency has occurred is counted up, and when the counted up value exceeds a specific number of times, a signal indicating that an abnormality has occurred in one of the clocks is output.

5. The frequency deviation determination unit 2. The frequency monitoring circuit according to claim 1, wherein the frequency monitoring circuit counts up and down a signal indicating that a deviation of the specific frequency has occurred, and when the counted up and down values ​​exceed a specific number of times, outputs a signal indicating that an abnormality has occurred in one of the clocks.

6. On the computer, A clock having a specific frequency is divided by a specific division number to generate a divided clock. Detecting an edge corresponding to the period of the divided clock, and outputting an edge pulse corresponding to the period of the detected edge; Counting the period of the edge pulse with a clock having a frequency different from the specific frequency, comparing the counted number with a specific expected value, and determining whether or not there is a deviation in the specific frequency depending on the result of the comparison; A frequency monitoring program that executes the process.

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