A digital voltage output circuit

Abstract

The application provides a digital voltage output circuit, relates to the technical field of circuit design, and comprises a power supply monitoring circuit, a pulse driving circuit, an isolated output circuit, a central processing unit and an interface protection circuit; the central processing unit is connected with the power supply monitoring circuit and the pulse driving circuit respectively; the isolated output circuit is connected with the pulse driving circuit and the power supply monitoring circuit respectively; and the isolated output circuit is connected with the interface protection circuit. The circuit of the application can relieve the technical problems of poor reliability of a digital circuit, easy output error and difficult monitoring in the prior art, and improves the reliability of the digital circuit.

Description

Technical Field

[0001] This invention relates to the technical field of circuit design, and in particular to a digital voltage output circuit. Background Technology

[0002] In the fields of power and industrial control, it is often necessary to drive external relays in control devices, which requires a digital voltage output circuit. (Digital voltage output means outputting either voltage or no voltage; when there is voltage, it can drive the external circuit, and when there is no voltage, the external circuit does not operate. If the external circuit is a 24V driven relay coil, then the digital voltage output circuit needs to output 24V when the relay operates, and does not output voltage when the external relay does not need to operate.)

[0003] In the existing technology, mathematical output circuits have the following disadvantages:

[0004] 1) Reliability is generally poor. When components in the circuit fail, it may not be able to guarantee correct output, and it may be impossible to detect whether there is output.

[0005] 2. Common digital voltage output circuits output signals from a single CPU pin, which are then converted into digital voltage outputs. When the CPU pin has faults such as poor soldering, correct output cannot be guaranteed, and the fault cannot be detected.

[0006] 3. When the CPU program malfunctions, it may cause erroneous output, which poses a significant risk.

[0007] 4. Some implementations use methods similar to dualization to ensure reliability, which leads to large circuit size and high cost.

[0008] In summary, a failure in the digital voltage output circuit can lead to undetected erroneous outputs, potentially posing a system risk. Certain critical external circuit controls are extremely important, and their digital voltage output circuits also need to ensure reliability. Therefore, a highly reliable digital voltage output circuit must be designed to drive these critical external circuits. Summary of the Invention

[0009] In view of this, the purpose of the present invention is to provide a digital voltage output circuit to alleviate the technical problems of poor reliability, easy error in output, and difficulty in monitoring of digital circuits in the prior art, and to improve the reliability of digital circuits.

[0010] This invention provides a digital voltage output circuit, including: a power monitoring circuit, a pulse driving circuit, an isolated output circuit, a central processing unit, and an interface protection circuit;

[0011] The central processing unit is connected to both the power monitoring circuit and the pulse drive circuit.

[0012] The isolated output circuit is connected to the pulse drive circuit and the power monitoring circuit respectively;

[0013] The isolation output circuit is connected to the interface protection circuit.

[0014] Preferably, the power monitoring circuit includes a first resistor R1, a second resistor R2, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a tenth resistor R10, an operational amplifier, and a first MOSFET.

[0015] The source of the first MOSFET is connected to an external power supply, the gate of the first MOSFET is connected to the central processing unit, the drain of the first MOSFET is connected to one end of the first resistor R1, and the other end of the first resistor R1 is connected to the isolation output circuit.

[0016] One end of the first resistor R1 is connected to the fifth resistor R5, the other end of the fifth resistor R5 is connected to one end of the seventh resistor R7, and the other end of the seventh resistor R7 is grounded.

[0017] The other end of the first resistor R1 is connected to one end of the sixth resistor R6, the other end of the sixth resistor R6 is connected to one end of the eighth resistor R8, and the other end of the eighth resistor R8 is connected to the output terminal of the operational amplifier.

[0018] The non-inverting input terminal of the operational amplifier is connected to the other end of the fifth resistor R5, and the inverting input terminal of the operational amplifier is connected to the other end of the sixth resistor R6.

[0019] The output of the operational amplifier is connected to the analog-to-digital converter interface of the central processing unit;

[0020] One end of the tenth resistor R10 is connected to an external power supply, and the other end of the tenth resistor R10 is connected to one end of the ninth resistor R9, and the other end of the ninth resistor R9 is grounded.

[0021] The ninth resistor R9 is connected to the central processing unit so that the central processing unit can obtain the voltage across the ninth resistor R9;

[0022] One end of the second resistor R2 is connected to an external power supply, and the other end of the second resistor R2 is connected to the gate of the first MOS transistor.

[0023] Preferably, the pulse driving circuit includes a third resistor R3, a fourth resistor R4, a second MOSFET Q2, a third MOSFET Q3, and a NOR gate circuit;

[0024] One end of the third resistor is connected to the central processing unit;

[0025] The other end of the third resistor R3 is connected to one end of the fourth resistor R4, and the other end of the fourth resistor R4 is grounded.

[0026] The number of NOR gates is two. One input terminal of the first NOR gate is connected to the other end of the third resistor R3, the other input terminal of the first NOR gate is connected to the first pulse output interface of the central processing unit, and the output terminal of the first NOR gate is connected to the gate of the second MOS transistor Q2.

[0027] One input terminal of the second NOR gate is connected to the other end of the third resistor R3, the other input terminal of the second NOR gate is connected to the second pulse output interface of the central processing unit, and the output terminal of the second NOR gate is connected to the gate of the third MOS transistor Q3.

[0028] The source of the second MOSFET Q2 is grounded and the source of the third MOSFET Q3 is grounded;

[0029] The drains of the second MOSFET Q2 and the third MOSFET Q3 are both connected to the isolated output circuit.

[0030] Preferably, the isolated output circuit includes a first inductor L1, a first capacitor C1, a transformer T1, a rectifier circuit, and a second capacitor C2;

[0031] One end of the first inductor L1 is connected to the other end of the first resistor R1, and the other end of the first inductor L1 is connected to the center tap on the primary side of the transformer T1.

[0032] One end of the primary side of the transformer T1 is connected to the drain of the second MOSFET Q2.

[0033] The other end of the primary side of the transformer T1 is connected to the drain of the third MOS transistor Q3;

[0034] The secondary side of the transformer T1 is connected to the input terminal of the rectifier circuit, and the output terminal of the rectifier circuit is connected in parallel with the second capacitor C2.

[0035] Preferably, the rectifier circuit includes a first diode D1, a second diode D2, a third diode D3, and a fourth diode D4;

[0036] The cathode of the first diode D1 is connected to the anode of the second diode D2, the anode of the second diode D2 is connected to the cathode of the fourth diode D4, the anode of the fourth diode D4 is connected to the cathode of the third diode D3, and the anode of the third diode D3 is connected to the anode of the first diode D1.

[0037] One end of the secondary side of transformer T1 is connected to the cathode of the first diode D1, and the other end of the secondary side of transformer T1 is connected to the cathode of the third diode D3.

[0038] One end of the second capacitor C2 is connected to the anode of the first diode D1;

[0039] The other end of the second capacitor C2 is connected to the anode of the first diode D1.

[0040] Preferably, the interface protection circuit includes a second inductor L2, a third capacitor C3, and a varistor RV1;

[0041] The second inductor L2 is a common-mode inductor. The second capacitor C2 is connected in parallel on one side of the second inductor L2, and the third capacitor C3 and the varistor RV1 are connected in parallel on the other side of the second inductor L2.

[0042] Preferably, the first MOSFET Q1 is a P-channel MOSFET, and the second MOSFET Q2 and the third MOSFET Q3 are all N-channel MOSFETs.

[0043] The embodiments of this invention bring the following beneficial effects: This invention provides a digital voltage output circuit, including: a power monitoring circuit, a pulse driving circuit, an isolated output circuit, a central processing unit (CPU), and an interface protection circuit; the CPU is connected to both the power monitoring circuit and the pulse driving circuit; the isolated output circuit is connected to both the pulse driving circuit and the power monitoring circuit; and the isolated output circuit is connected to the interface protection circuit. The circuit of this invention can alleviate the technical problems of poor reliability, easy output errors, and difficulty in monitoring in existing digital circuits, thereby improving the reliability of digital circuits.

[0044] Other features and advantages of the invention will be set forth in the description which follows, and will be apparent in part from the description, or may be learned by practicing the invention. The objects and other advantages of the invention are realized and obtained in accordance with the structures particularly pointed out in the description, claims and drawings.

[0045] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0046] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0047] Figure 1 A circuit diagram of a digital voltage output circuit provided in an embodiment of the present invention. Detailed Implementation

[0048] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0049] Currently, if a digital voltage output circuit malfunctions, undetected erroneous outputs may occur, potentially leading to system risks. Based on this, the digital voltage output circuit provided in this invention can alleviate the technical problems of poor reliability, easy error in output, and difficulty in monitoring of existing digital circuits, thereby improving the reliability of digital circuits.

[0050] To facilitate understanding of this embodiment, a digital voltage output circuit disclosed in this embodiment of the invention will first be described in detail.

[0051] Example 1:

[0052] This invention provides an embodiment of a digital voltage output circuit, comprising: a power monitoring circuit, a pulse driving circuit, an isolated output circuit, a central processing unit, and an interface protection circuit;

[0053] The central processing unit is connected to both the power monitoring circuit and the pulse drive circuit.

[0054] The isolated output circuit is connected to the pulse drive circuit and the power monitoring circuit respectively;

[0055] The isolation output circuit is connected to the interface protection circuit.

[0056] In the embodiments provided by this invention, the power monitoring circuit mainly converts and processes the voltage and current information of the circuit before handing it over to the central processing unit (CPU) for processing. This ensures that the external power supply VCC voltage amplitude is normal, the output power consumption is normal, and the circuit operates safely. The external power supply VCC is an internal power supply provided for the output, powering the primary side of transformer T1. The power monitoring circuit includes a ninth resistor R9 and a tenth resistor R10. It divides the external voltage VCC to a voltage that meets the input range of the CPU and inputs it to the CPU. The CPU monitors whether the amplitude of the external VCC voltage is normal through the CPU's analog-to-digital converter interface and AD2 interface.

[0057] The function of the power monitoring circuit is to protect the entire circuit. When the Alert interface of the central processing unit is low, the first MOSFET Q1 is turned on, which will form a small voltage drop across the first resistor R1. This voltage drop is then amplified by the arithmetic circuit to a voltage that can be collected by the analog-to-digital converter interface (ACD1) of the central processing unit. Through the calculation of the central processing unit, the current flowing from the external power supply VCC to the transformer can be monitored. When the output current is abnormal, the first MOSFET Q1 is turned off, which can ensure the safety and reliability of the circuit and prevent it from burning out.

[0058] Preferably, the power monitoring circuit includes a first resistor R1, a second resistor R2, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a tenth resistor R10, an operational amplifier, and a first MOSFET.

[0059] The source of the first MOSFET is connected to an external power supply, the gate of the first MOSFET is connected to the central processing unit, the drain of the first MOSFET is connected to one end of the first resistor R1, and the other end of the first resistor R1 is connected to the isolation output circuit.

[0060] One end of the first resistor R1 is connected to the fifth resistor R5, the other end of the fifth resistor R5 is connected to one end of the seventh resistor R7, and the other end of the seventh resistor R7 is grounded.

[0061] The other end of the first resistor R1 is connected to one end of the sixth resistor R6, the other end of the sixth resistor R6 is connected to one end of the eighth resistor R8, and the other end of the eighth resistor R8 is connected to the output terminal of the operational amplifier.

[0062] The non-inverting input terminal of the operational amplifier is connected to the other end of the fifth resistor R5, and the inverting input terminal of the operational amplifier is connected to the other end of the sixth resistor R6.

[0063] The output of the operational amplifier is connected to the analog-to-digital converter interface of the central processing unit;

[0064] One end of the tenth resistor R10 is connected to an external power supply, and the other end of the tenth resistor R10 is connected to one end of the ninth resistor R9, and the other end of the ninth resistor R9 is grounded.

[0065] The ninth resistor R9 is connected to the central processing unit so that the central processing unit can obtain the voltage across the ninth resistor R9;

[0066] One end of the second resistor R2 is connected to an external power supply, and the other end of the second resistor R2 is connected to the gate of the first MOS transistor.

[0067] Preferably, the pulse driving circuit includes a third resistor R3, a fourth resistor R4, a second MOSFET Q2, a third MOSFET Q3, and a NOR gate circuit;

[0068] One end of the third resistor is connected to the central processing unit;

[0069] The other end of the third resistor R3 is connected to one end of the fourth resistor R4, and the other end of the fourth resistor R4 is grounded.

[0070] The number of NOR gates is two. One input terminal of the first NOR gate is connected to the other end of the third resistor R3, the other input terminal of the first NOR gate is connected to the first pulse output interface of the central processing unit, and the output terminal of the first NOR gate is connected to the gate of the second MOS transistor Q2.

[0071] One input terminal of the second NOR gate is connected to the other end of the third resistor R3, the other input terminal of the second NOR gate is connected to the second pulse output interface of the central processing unit, and the output terminal of the second NOR gate is connected to the gate of the third MOS transistor Q3.

[0072] The source of the second MOSFET Q2 is grounded and the source of the third MOSFET Q3 is grounded;

[0073] The drains of the second MOSFET Q2 and the third MOSFET Q3 are both connected to the isolated output circuit;

[0074] The first pulse output interface of the central processing unit has the same pulse frequency as the second pulse output interface of the central processing unit, but the output pulses are opposite.

[0075] Preferably, the isolated output circuit includes a first inductor L1, a first capacitor C1, a transformer T1, a rectifier circuit, and a second capacitor C2;

[0076] One end of the first inductor L1 is connected to the other end of the first resistor R1, and the other end of the first inductor L1 is connected to the center tap on the primary side of the transformer T1.

[0077] One end of the primary side of the transformer T1 is connected to the drain of the second MOSFET Q2.

[0078] The other end of the primary side of the transformer T1 is connected to the drain of the third MOS transistor Q3;

[0079] The secondary side of the transformer T1 is connected to the input terminal of the rectifier circuit, and the output terminal of the rectifier circuit is connected in parallel with the second capacitor C2.

[0080] Preferably, the rectifier circuit includes a first diode D1, a second diode D2, a third diode D3, and a fourth diode D4;

[0081] The cathode of the first diode D1 is connected to the anode of the second diode D2, the anode of the second diode D2 is connected to the cathode of the fourth diode D4, the anode of the fourth diode D4 is connected to the cathode of the third diode D3, and the anode of the third diode D3 is connected to the anode of the first diode D1.

[0082] One end of the secondary side of transformer T1 is connected to the cathode of the first diode D1, and the other end of the secondary side of transformer T1 is connected to the cathode of the third diode D3.

[0083] One end of the second capacitor C2 is connected to the anode of the first diode D1;

[0084] The other end of the second capacitor C2 is connected to the anode of the first diode D1.

[0085] Preferably, the interface protection circuit includes a second inductor L2, a third capacitor C3, and a varistor RV1;

[0086] The second inductor L2 is a common-mode inductor. The second capacitor C2 is connected in parallel on one side of the second inductor L2, and the third capacitor C3 and the varistor RV1 are connected in parallel on the other side of the second inductor L2.

[0087] Preferably, the first MOSFET Q1 is a P-channel MOSFET, and the second MOSFET Q2 and the third MOSFET Q3 are all N-channel MOSFETs.

[0088] Example 2:

[0089] Embodiment 2 of the present invention illustrates the working principle of the circuit provided in Embodiment 1 of the present invention:

[0090] When the circuit is working normally, the external power supply VCC is normal. After the external power supply VCC is divided by the tenth resistor R10 and the ninth resistor R9, the central processing unit ADC2 interface obtains a stable voltage. The CPU determines whether the voltage of VCC is normal by monitoring the voltage input to ADC2.

[0091] During normal circuit operation, the central processing unit's Alert interface outputs a low level, the first MOSFET Q1 is turned on, and the external power supply VCC voltage supplies power to the primary side of the transformer through the first MOSFET Q1, the first resistor R1, and the first inductor L1.

[0092] When the circuit outputs, the central processing unit's PO1 and PO2 interfaces provide PWM waves of the same frequency but opposite magnitudes. That is, at the same time, PO1 and PO2 output 0 and 1 respectively, or 1 and 0 respectively.

[0093] Under normal circuit conditions, the central processing unit's Alert output interface is low. When PO1 outputs 0, the inputs of NOR gate U1 are 0 and 0, so the NOR gate outputs 1, and MOSFET Q2 is turned on. When PO2 outputs 1, the inputs of NOR gate U2 are 0 and 1, so MOSFET Q3 is not turned on. Similarly, when PO1 and PO2 output 0 and 1 respectively, the second MOSFET Q2 is not turned on, and the third MOSFET Q3 is turned on. Therefore, during normal operation, the two ends of the primary side are alternately turned on by the second MOSFET Q2 and the third MOSFET Q3 respectively. By setting a reasonable PWM wave frequency, the voltage can be obtained from the intermediate tap, so the primary side of the transformer works normally, providing input voltage to the aforementioned rectifier circuit and performing rectification. After filtering by the second capacitor C2, a DC voltage output is obtained. After passing through the second inductor L2, the third capacitor C3, and the varistor RV1, a stable DC voltage is output at BO+ and BO-, that is, the digital voltage output circuit outputs logic "1".

[0094] When the circuit is not outputting, PO1 and PO2 are both pulled up to a high level internally. As a result, the inputs to the second MOSFET Q2 and the third MOSFET Q3 are both 0, so neither the second MOSFET Q2 nor the third MOSFET Q3 is turned on. The transformer T1 will not output voltage, that is, the digital voltage output circuit outputs logic "0".

[0095] When the digital voltage output circuit is not outputting, the power supplied by the external power supply VCC is almost zero, the current through the first resistor R1 is basically zero, and the voltage amplified by the operational amplifier circuit is also almost zero. After the analog-to-digital conversion interface of the central processing unit collects the data, it is considered that the output current is almost zero and the circuit is working normally.

[0096] When the digital voltage output circuit outputs, a threshold for output power consumption can be preset through the program of the central processing unit. Specifically, this can be achieved by obtaining the current flowing through the first resistor R1 read by the ADC1 of the central processing unit.

[0097] If the current flowing through the first resistor R1 exceeds the threshold, it is considered that there is a short circuit or overcurrent in the external circuit (output circuits of BO+ and BO-). To ensure safety, the Alert port of the central processing unit is set to output a high level to turn off the first MOS transistor, and PO1 and PO2 are not output, thus preventing the digital voltage output circuit from outputting.

[0098] In the embodiments provided by the present invention, the PI1 and PI2 interfaces of the central processing unit are read back from PO1 and PO2. The central processing unit (CPU) determines whether the output is abnormal by judging whether PI1 and PO1 are consistent and whether PI2 and PO2 are consistent. If they are inconsistent, the output is considered abnormal, and the CPU's Alert interface needs to output a high level to turn off the first MOS transistor. The outputs of the CPU's PO1 and PO2 interfaces are both 0 to ensure safety.

[0099] If the external power supply VCC is abnormal, the voltage across the ninth resistor R9 obtained by the central processing unit will change. In order to ensure output safety, the central processing unit's Alert interface will output a high level to turn off the first MOS transistor, and the CPU's PO1 and PO2 interfaces will both output 0 to ensure safety.

[0100] If the CPU's Alert output is abnormal, even if the Alert outputs a low level incorrectly, the entire circuit can be prevented from outputting incorrectly by not outputting PO1 and PO2. That is, if the control logic of the entire CPU is abnormal, causing the Alert to output a low level incorrectly, the CPU's PO1 and PO2 interfaces will also output incorrectly. However, since the waveform frequencies output by the CPU's PO1 and PO2 interfaces are different, the primary side of the transformer will experience magnetic saturation due to the excessive DC component, preventing the secondary side from outputting voltage. Therefore, there will be no incorrect output voltage.

[0101] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working process of the system and apparatus described above can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0102] Those skilled in the art will understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0103] In addition, the functional units in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0104] Finally, it should be noted that the above-described embodiments are merely specific implementations of the present invention, used to illustrate the technical solutions of the present invention, and not to limit it. The scope of protection of the present invention is not limited thereto. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that any person skilled in the art can still modify or easily conceive of changes to the technical solutions described in the foregoing embodiments within the technical scope disclosed in the present invention, or make equivalent substitutions for some of the technical features; and these modifications, changes, or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be covered within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A digital voltage output circuit, characterized by, include: Power monitoring circuit, pulse drive circuit, isolation output circuit, central processing unit, and interface protection circuit; The central processing unit is connected to both the power monitoring circuit and the pulse drive circuit. The isolated output circuit is connected to the pulse drive circuit and the power monitoring circuit respectively; The isolation output circuit is connected to the interface protection circuit; The power monitoring circuit includes a first resistor R1, a second resistor R2, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a tenth resistor R10, an operational amplifier, and a first MOSFET. The source of the first MOSFET is connected to an external power supply, the gate of the first MOSFET is connected to the central processing unit, the drain of the first MOSFET is connected to one end of the first resistor R1, and the other end of the first resistor R1 is connected to the isolation output circuit. One end of the first resistor R1 is connected to the fifth resistor R5, the other end of the fifth resistor R5 is connected to one end of the seventh resistor R7, and the other end of the seventh resistor R7 is grounded. The other end of the first resistor R1 is connected to one end of the sixth resistor R6, the other end of the sixth resistor R6 is connected to one end of the eighth resistor R8, and the other end of the eighth resistor R8 is connected to the output terminal of the operational amplifier. The non-inverting input terminal of the operational amplifier is connected to the other end of the fifth resistor R5, and the inverting input terminal of the operational amplifier is connected to the other end of the sixth resistor R6. The output of the operational amplifier is connected to the analog-to-digital converter interface of the central processing unit; One end of the tenth resistor R10 is connected to an external power supply, and the other end of the tenth resistor R10 is connected to one end of the ninth resistor R9, and the other end of the ninth resistor R9 is grounded. The ninth resistor R9 is connected to the central processing unit so that the central processing unit can obtain the voltage across the ninth resistor R9; One end of the second resistor R2 is connected to an external power supply, and the other end of the second resistor R2 is connected to the gate of the first MOS transistor.

2. The circuit of claim 1, wherein, The pulse driving circuit includes a third resistor R3, a fourth resistor R4, a second MOSFET Q2, a third MOSFET Q3, and an OR gate circuit; One end of the third resistor is connected to the central processing unit; The other end of the third resistor R3 is connected to one end of the fourth resistor R4, and the other end of the fourth resistor R4 is grounded. The number of NOR gates is two, and one input terminal of the first NOR gate is connected to the third resistor R3. The other end is connected, and the other input terminal of the first NOR gate is connected to the first pulse output interface of the central processing unit, and the output terminal of the first NOR gate is connected to the gate of the second MOS transistor Q2; One input terminal of the second NOR gate is connected to the other end of the third resistor R3, the other input terminal of the second NOR gate is connected to the second pulse output interface of the central processing unit, and the output terminal of the second NOR gate is connected to the gate of the third MOS transistor Q3. The source of the second MOSFET Q2 is grounded and the source of the third MOSFET Q3 is grounded; The drains of the second MOSFET Q2 and the third MOSFET Q3 are both connected to the isolated output circuit.

3. The circuit of claim 2, wherein, The isolated output circuit includes a first inductor L1, a first capacitor C1, a transformer T1, a rectifier circuit, and a second capacitor C2; One end of the first inductor L1 is connected to the other end of the first resistor R1, and the other end of the first inductor L1 is connected to the center tap on the primary side of the transformer T1. One end of the primary side of the transformer T1 is connected to the drain of the second MOS transistor Q2; The other end of the primary side of the transformer T1 is connected to the drain of the third MOS transistor Q3; The secondary side of the transformer T1 is connected to the input terminal of the rectifier circuit, and the output terminal of the rectifier circuit is connected in parallel with the second capacitor C2.

4. The circuit of claim 3, wherein, The rectifier circuit includes a first diode D1, a second diode D2, a third diode D3, and a fourth diode D4; The cathode of the first diode D1 is connected to the anode of the second diode D2, the anode of the second diode D2 is connected to the cathode of the fourth diode D4, the anode of the fourth diode D4 is connected to the cathode of the third diode D3, and the anode of the third diode D3 is connected to the anode of the first diode D1. One end of the secondary side of transformer T1 is connected to the cathode of the first diode D1, and the other end of the secondary side of transformer T1 is connected to the cathode of the third diode D3. One end of the second capacitor C2 is connected to the anode of the first diode D1; The other end of the second capacitor C2 is connected to the anode of the first diode D1.

5. The circuit of claim 3, wherein, The interface protection circuit includes a second inductor L2, a third capacitor C3, and a varistor RV1; the second inductor L2 is a common-mode inductor, the second capacitor C2 is connected in parallel on one side of the second inductor L2, and the third capacitor C3 and the varistor RV1 are connected in parallel on the other side of the second inductor L2.

6. The circuit of claim 4, wherein, The first MOSFET Q1 is a P-channel MOSFET, and the second MOSFET Q2 and the third MOSFET Q3 are both N-channel MOSFETs.

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