Semiconductor device

Abstract

To improve ease of layout by relaxing a layout pitch of a sense amplifiers even when the layout pitch of a bit line connected to a memory cells is small.SOLUTION: A semiconductor device includes: a first cell array and a second cell array each having a plurality of word lines extending in a second direction intersecting with a first direction, a plurality of first bit lines extending in the first direction, and a plurality of memory cells, and disposed along the second direction; a plurality of sense amplifiers disposed along the first direction at portions where the first cell array and the second cell array face each other in a plan view; a second bit line extending in the second direction and connecting the first bit line of the first cell array to the sense amplifier; and a third bit line extending in the second direction and connecting the first bit line of the second cell array to the sense amplifier.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device. [Background technology]

[0002] A known method for manufacturing semiconductor wafers includes multiple semiconductor devices by stacking multiple dynamic random access memories (DRAMs) on a substrate to form a wafer containing a 3D memory. This wafer is then bonded to a wafer with peripheral circuits formed on it. The multiple semiconductor devices included in the semiconductor wafer are then singulated to form high-bit-density memories. For example, the 3D memory wafer and the peripheral circuit wafer are interconnected by bumpless through-silicon vias (TSVs).

[0003] For example, in a 3D-DRAM memory cell in which DRAMs are stacked, the cell capacitor that stores data extends horizontally along the wafer surface and is connected to a bit line that extends vertically or horizontally across the wafer via a transfer transistor. The cell capacitor is formed horizontally to ensure the required memory cell capacitance. Extending the cell capacitor vertically increases the load capacitance of the word line, resulting in wasted area around the transistor. As a result, the bit line pitch becomes smaller, and the word line pitch becomes relatively loose. This is the origin of the problem that this invention aims to solve. The word line connected to the gate of the transfer transistor extends horizontally when the bit line extends vertically, and vertically when the bit line extends horizontally. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] U.S. Patent Application Publication No. 2021 / 0225810 [Non-patent literature]

[0005] [Non-Patent Document 1] JW Han et al., "Ongoing Evolution of DRAM Scaling via Third Dimension - Vertically Stacked DRAM -", 2023 Symposium on VLSI Technology and Circuits Digest of Technical Papers, TFS1-1 [Non-patent document 2] Mayu Aoki, Kazuyuki Hozawa, and Kenichi Takeda, "Wafer-Level Hybrid Bonding Technology with Copper / Polymer Co-planarization", Proceedings of 3D System Integration Conference, 2012. Summary of the Invention [Problem to be solved by the invention]

[0006] Data read from the cell capacitors onto the bit lines is amplified by sense amplifiers connected to the bit lines. When memory cells each including a long and narrow cell capacitor are arranged in a matrix, the layout pitch of the transfer transistors connected to each bit line becomes larger than the length of the cell capacitor. Therefore, the layout pitch of the word lines is relaxed to match the layout pitch of the transfer transistors. However, no method has been proposed for relaxing the layout pitch of the sense amplifiers by utilizing the relaxed layout pitch of the word lines.

[0007] Therefore, an object of the present invention is to improve the ease of layout by widening the layout pitch of sense amplifiers even when the layout pitch of bit lines connected to memory cells is small. [Means for solving the problem]

[0008] A semiconductor device according to one aspect of the present invention comprises: a first cell array and a second cell array each having a plurality of word lines spaced apart in a first direction and extending in a second direction intersecting the first direction; a plurality of first bit lines spaced apart in the second direction and extending in the first direction; and a plurality of memory cells each arranged at an intersection of the word lines and the first bit lines, the first cell array and the second cell array arranged along the second direction; a plurality of sense amplifiers arranged along the first direction at opposing portions of the first cell array and the second cell array in a planar view; a plurality of second bit lines spaced apart in the first direction and extending in the second direction, connecting any one of the plurality of first bit lines of the first cell array to any one of the plurality of sense amplifiers; and a plurality of third bit lines spaced apart in the first direction and extending in the second direction, connecting any one of the plurality of first bit lines of the second cell array to any one of the plurality of sense amplifiers. [Effects of the Invention]

[0009] According to the present invention, even when the layout pitch of the bit lines connected to the memory cells is small, the layout pitch of the sense amplifiers can be relaxed, thereby improving the ease of layout. [Brief explanation of the drawings]

[0010] [Figure 1] FIG. 2 is a plan view showing an example of the layout of memory cells MC of a DRAM. [Figure 2] FIG. 1 is a block diagram showing an example of the layout of a semiconductor device such as a DRAM. [Figure 3] 1 is a block diagram showing an example of a layout of a semiconductor device according to a first embodiment of the present invention. [Figure 4] FIG. 10 is an exploded perspective view showing an example of a layout of a semiconductor device according to a second embodiment of the present invention. [Figure 5] FIG. 5 is an enlarged perspective view of an area A in FIG. [Figure 6]5 is a partial perspective view showing an outline of a 3D-DRAM formed on the semiconductor substrate SS1 of FIG. 4. FIG. [Figure 7] 5 is a flow chart showing an example of a method for manufacturing the semiconductor device of FIG. 4. [Figure 8] FIG. 10 is a plan view showing an example of a layout of a semiconductor device according to a third embodiment of the present invention. [Figure 9] FIG. 9 is an exploded perspective view showing the semiconductor device of FIG. 8. [Figure 10] FIG. 9 is a plan view showing an example of a circuit layout of the semiconductor substrate SS2 of FIG. [Figure 11] FIG. 10 is a diagram showing an example of a layout of a semiconductor device according to a fourth embodiment of the present invention. [Figure 12] 12 is a plan view showing an example of a circuit layout of the semiconductor substrate SS2 of FIG. 11. FIG. [Figure 13] FIG. 10 is an exploded perspective view showing an example of a layout of a semiconductor device according to a fifth embodiment of the present invention. [Figure 14] FIG. 13 is an exploded perspective view showing an example of a layout of a semiconductor device according to a sixth embodiment of the present invention. [Figure 15] FIG. 13 is an exploded perspective view showing an example of a layout of a semiconductor device according to a seventh embodiment of the present invention. [Figure 16] 16 is a plan view showing an example of a circuit layout of the semiconductor substrate SS1 of FIG. 15. FIG. DETAILED DESCRIPTION OF THE INVENTION

[0011] Hereinafter, embodiments will be described with reference to the drawings. In each drawing, the same components are designated by the same reference numerals, and duplicate explanations may be omitted. Reference numerals indicating signal names are also used to indicate signal line names or terminal names. A single signal line may be composed of multiple lines.

[0012] Figure 1 is a plan view showing an example of the layout of a DRAM memory cell MC. Well-known DRAM memory cells have a high integration density by using a stacked capacitor type in which a cell capacitor is stacked on a transistor formed on a substrate. To obtain the required storage capacitance, the cell capacitor is formed in a tall shape extending vertically (for example, in the Z direction in Figure 1).

[0013] However, when the cell capacitor CCAP is formed in a planar type in which it is horizontally oriented due to some necessity, such as ease of manufacturing, reliability, or the manufacturing of a 3D-DRAM, the cell capacitor CCAP has a shape extending in the X direction, for example, as shown in FIG. 1. As a result, the memory cell MC has a shape elongated in the X direction. The X direction is an example of a first direction. For example, the cell capacitor CCAP is disposed between a pair of word lines WL adjacent in the X direction in a plan view.

[0014] FIG. 1 shows an example in which three memory cells MC are arranged in the X direction and four memory cells MC are arranged in the Y direction. The Y direction is an example of the second direction. Each memory cell MC has a cell capacitor CCAP that stores data as an electric charge and a transfer transistor TRT that connects the cell capacitor CCAP to a bit line BL, and stores one bit of data. The transfer transistor TRT is connected to a bit line BL that is wired in the X direction on the memory cell MC via a bit line contact BLCNT. The gate of the transfer transistor TRT is connected to a word line WL.

[0015] The cell capacitor CCAP can be shaped like a square, which makes it easier to increase the area. However, for example, increasing the size in the Y direction in FIG. 1 increases the wiring length of the word line WL. This increases the load capacitance of the word line WL, reduces the layout efficiency of the transfer transistor TRT, and increases the layout pitch of the bit line BL. Therefore, in order to suppress the decrease in layout efficiency and the increase in cost, it is preferable to narrow the layout pitch of the bit line BL and make the memory cell MC and cell capacitor CCAP elongated in the X direction.

[0016] Although not shown in the figure, memories such as DRAMs have sense amplifiers that amplify data read from memory cells MC to bit lines BL. Narrowing the layout pitch of the bit lines BL requires narrowing the layout pitch of the sense amplifiers as well. However, for example, because sense amplifiers have multiple transistors, it may be difficult to layout them in a long, narrow area.

[0017] Furthermore, as shown in Figure 1, when arranging the cell capacitors CCAP that are elongated in the X direction, the layout pitch of the word lines WL becomes large. This results in areas with high and low element density within the chip, resulting in an unbalanced layout. This unbalanced layout can lead to wasted area in many places.

[0018] 2 is a block diagram showing an example of the layout of a semiconductor device SEM0 such as a DRAM, etc. For example, the semiconductor device SEM0 has cell arrays ARYa and ARYb arranged side by side in the X direction, and a sense amplifier S / A arranged between the cell arrays ARYa and ARYb.

[0019] A row decoder RDECa that selects the word line WLa is arranged at one end of the cell array ARYa in the Y direction, and a column decoder CDEC(1 / 2) that connects the bit line BLa to the sense amplifier S / A is arranged at the sense amplifier S / A side of the cell array ARYa. A row decoder RDECb that selects the word line WLb is arranged at one end of the cell array ARYb in the Y direction, and a column decoder CDEC(2 / 2) that connects the bit line BLb to the sense amplifier S / A is arranged at the sense amplifier S / A side of the cell array ARYb.

[0020] For example, when the row decoder RDECa selects the word line WLa, the row decoder RDECb selects the dummy word line DWLb. Each sense amplifier S / A reads data by differentially amplifying a voltage corresponding to the logical value of data read from the memory cell MC to the bit line BLa and a reference voltage appearing on the bit line BLb. For example, the value of the reference voltage is set between the voltage value of data with a logical value of 1 read from the memory cell MC and the voltage value of data with a logical value of 0 read from the memory cell MC, and is set to, for example, the precharge voltage of the bit line.

[0021] On the other hand, when the row decoder RDECb selects the word line WLb, the row decoder RDECa selects the dummy word line DWLa connected to the dummy memory cell. Each sense amplifier S / A reads data by differentially amplifying a voltage corresponding to the logical value of data read from the memory cell MC to the bit line BLb and a reference voltage appearing on the bit line BLa.

[0022] The column decoders CDEC(1 / 2) and CDEC(2 / 2) control the on / off of column switches (not shown) and select bit lines BLa and BLb with the same address in the cell arrays ARYa and ARYb on both sides in the X direction. Although the column decoders CDEC(1 / 2) and CDEC(2 / 2) are physically separate, they operate as a single unit and are therefore referred to as (1 / 2) and (2 / 2). Because the circuit configurations and layouts of the cell arrays ARYa and ARYb are similar, the following description will mainly focus on the cell array ARYa.

[0023] As shown in FIG. 1, each memory cell MC has a cell capacitor CCAP elongated in the X direction, and is connected to a bit line BLa extending in the X direction and a word line WLa extending in the Y direction. Each bit line BLa is connected to memory cells MC aligned in the X direction. Each word line WLa is connected to memory cells MC aligned in the Y direction. In addition, in the cell array ARYa, a dummy word line DWLa connected to dummy memory cells (not shown) is arranged on the opposite side of the sense amplifier S / A.

[0024] The layout pitch of the word lines WLa is made relatively large to match the size of the memory cells MC in the X direction, and the layout pitch of the bit lines BLa is made relatively small to match the size of the memory cells MC in the Y direction. This makes the cell array ARYa a rectangle with a large size in the X direction. The same is true for the cell array ARYb.

[0025] The size of the sense amplifiers S / A in the Y direction is reduced to match the layout pitch of the bit lines BLa and BLb. Depending on the layout pitch of the bit lines BLa and BLb, the layout of the sense amplifiers S / A may become difficult. One method for alleviating the layout pitch in the Y direction is to alternately shift the sense amplifiers S / As arranged in the Y direction in the X direction, but this tends to result in the unbalanced layout described above. For example, there is a risk that the layout pattern of the sense amplifiers S / A will be finer than the layout patterns of the other circuit elements.

[0026] In the layout of the semiconductor device according to the present invention shown in Figures 3 and subsequent figures, by changing the arrangement of the cell arrays ARYa and ARYb, it is possible to increase the layout pitch of the sense amplifiers S / A without changing the layout pitch of the bit lines BL and the layout pitch of the word lines WL.

[0027] 3 is a block diagram showing an example of a layout of a semiconductor device according to a first embodiment of the present invention. The same elements as those in FIG. 2 are denoted by the same reference numerals, and detailed description thereof will be omitted. The semiconductor device SEM1 shown in FIG. 3 is, for example, a DRAM chip. The semiconductor device SEM1 has cell arrays ARYa and ARYb arranged in the Y direction, and a sense amplifier S / A arranged between the cell arrays ARYa and ARYb.

[0028] Each of the cell arrays ARYa and ARYb has memory cells MC arranged in a matrix. The memory cells MC of the cell array ARYa are arranged at the intersections of the bit lines BL1a and word lines WLa, and the memory cells MC of the cell array ARYb are arranged at the intersections of the bit lines BL1b and word lines WLb. Like the memory cells MC shown in FIG. 1, the memory cells MC have cell capacitors CCAPs that are elongated in the X direction. Although not particularly limited, the ratio Y:X of the size in the Y direction to the size in the X direction of each of the cell arrays ARYa and ARYb may be approximately 1:20 at most.

[0029] A row decoder RDECa that selects a word line WLa is arranged on the opposite side of the cell array ARYa from the sense amplifier S / A, and a column decoder CDEC(1 / 2) is arranged on the sense amplifier S / A side of the cell array ARYa. A row decoder RDECb that selects a word line WLb is arranged on the opposite side of the cell array ARYb from the sense amplifier S / A, and a column decoder CDEC(2 / 2) is arranged on the sense amplifier S / A side of the cell array ARYb. The word lines WLa, WLb are arranged at intervals in the X direction and extend in the Y direction.

[0030] The operations of the row decoders RDECa and RDECb and the column decoders CDEC(1 / 2) and CDEC(2 / 2) are the same as those described in Fig. 2. The column decoders CDEC(1 / 2) and CDEC(2 / 2) may be arranged together as a common column decoder.

[0031] The cell array ARYa has a first-level bit line BL1a extending in the X direction and connected to memory cells MC aligned in the X direction, and a second-level bit line BL2a connected to the bit line BL1a via a bit line contact BLCNT, extending in the Y direction, and connected to the sense amplifier S / A. For example, the bit line BL2a is formed on the bit line BL1a using multi-layer wiring technology, and can be formed at any layout pitch in the X direction.

[0032] The cell array ARYb has a first-level bit line BL1b extending in the X direction and connected to memory cells MC aligned in the X direction, and a second-level bit line BL2b connected to the bit line BL1b via a bit line contact BLCNT, extending in the Y direction, and connected to the sense amplifier S / A. For example, the bit line BL2b is formed on the bit line BL1b using multi-layer wiring technology, and can be formed at any layout pitch in the X direction.

[0033] The word lines WLa and WLb are formed between the memory cells MC and the bit lines BL1a and BL1b. The bit lines BL1a and BL1b are an example of first bit lines spaced apart in the Y direction. The bit line BL2a is an example of a second bit line, and the bit line BL2b is an example of a third bit line.

[0034] The arrangement direction of the bit lines BL2a and BL2b is the longitudinal direction of the memory cells MC. Therefore, the layout pitch of the bit lines BL2a and BL2b in the X direction can be set to any layout pitch without depending on the layout pitch of the bit lines BL1a and BL1b. This allows the layout pitch of the sense amplifiers S / A connected to the bit lines BL2a and BL2b in the X direction to be set to any layout pitch without depending on the layout pitch of the bit lines BL1a and BL1b.

[0035] That is, by connecting the bit lines BL1a and BL1b extending in the X direction to the sense amplifiers S / A via the bit lines BL1b and BL2b extending in the Y direction, the arrangement direction of the sense amplifiers S / A can be rotated by 90 degrees with respect to that shown in Figure 2 so as to be aligned with the longitudinal direction of the memory cells MC, thereby providing more leeway in the layout design. As a result, the layout pitch of the sense amplifiers S / A aligned in the X direction can be appropriately set in accordance with the layout size of the sense amplifiers S / A.

[0036] In order to make the load capacitance uniform, the bit lines BL2a and BL2b are extended farther from the sense amplifier S / A than the bit line contact BLCNT, and their lengths are made uniform, which makes it possible to make the sensitivity of the sense amplifier S / A uniform regardless of the position of the bit line contact BLCNT.

[0037] The sense amplifiers S / A are arranged in the longitudinal direction of the cell arrays ARYa and ARYb (the X direction, which is the longitudinal direction of the memory cells MC), and the layout pitch of the sense amplifiers S / A does not depend on the layout pitch of the word lines WLa and WLb. For this reason, there may be empty spaces between the cell arrays ARYa and ARYb where no sense amplifiers S / A are formed.

[0038] For example, in the free space, it is possible to arrange a drive circuit (power supply circuit) for the sense amplifiers S / A, a control circuit CNTL such as a data input / output circuit, etc. This makes it possible to prevent the occurrence of wasted space where no circuit elements are arranged when arranging the sense amplifiers S / A in the longitudinal direction of the cell arrays ARYa and ARYb, and to prevent a decrease in the layout efficiency of the semiconductor device SEM1.

[0039] As described above, in the first embodiment, the bit lines BL1a and BL1b extending in the X direction are connected to the sense amplifiers S / A via the bit lines BL1b and BL2b extending in the Y direction, thereby allowing the sense amplifiers S / A to be arranged in the longitudinal direction of the memory cells MC. As a result, when the cell capacitors CCAP of the memory cells MC are formed elongated in the X direction, the layout design of the sense amplifiers S / A can be given some leeway, and the layout pitch of the sense amplifiers S / A arranged in the X direction can be appropriately set according to the layout size of the sense amplifiers S / A. In other words, even when the layout pitch of the bit lines BL1a and BL1b connected to the memory cells MC is small, the layout pitch of the sense amplifiers S / A can be relaxed, improving the ease of layout.

[0040] When a space is generated between the cell arrays ARYa and ARYb due to the layout of the sense amplifiers S / A that is independent of the layout pitch of the word lines WLa and WLb, the control circuit CNTL, etc. can be arranged in the space. This makes it possible to prevent the occurrence of wasted space where no circuit elements are arranged when arranging the sense amplifiers S / A in the longitudinal direction of the cell arrays ARYa and ARYb, and to prevent a decrease in the layout efficiency of the semiconductor device SEM1.

[0041] Fig. 4 is an exploded perspective view showing an example of a layout of a semiconductor device according to a second embodiment of the present invention. Fig. 5 is a perspective view showing an enlarged view of an area A in Fig. 4. The same elements as those in Fig. 3 are given the same reference numerals, and detailed description thereof will be omitted.

[0042] The semiconductor device SEM2 shown in FIG. 4 is formed by stacking, for example, a semiconductor substrate SS1 including a 3D-DRAM and a semiconductor substrate SS2 including peripheral circuits for controlling the 3D-DRAM. For example, the semiconductor substrates SS1 and SS2 are bonded together using an adhesive or the like, and then electrically connected by through electrodes such as TSVs. For example, the semiconductor substrates SS1 and SS2 are connected to each other using a bumpless TSV process described in Patent Document 1 or the like. The semiconductor substrate SS1 is an example of a first semiconductor substrate, and the semiconductor substrate SS2 is an example of a second semiconductor substrate.

[0043] The semiconductor substrates SS1 and SS2 are formed as wafers and then bonded together. The wafer-state semiconductor substrates SS1 and SS2 are then electrically connected by TSVs and then cut out into individual semiconductor devices SEM2. An outline of a manufacturing method for the semiconductor device SEM2 is shown in FIG. 7. Here, a method of connecting wafers or chips using a metal wiring process is exemplified, but a method called hybrid bonding described in Non-Patent Document 2 and the like is also applicable. The semiconductor substrates SS1 and SS2 may be stacked in the reverse order to that shown in FIG. 4.

[0044] The semiconductor substrate SS1 has cell arrays ARYa and ARYb each including a plurality of memory cells MC (Figure 5) arranged in a matrix and word lines WLa and WLb connected to the memory cells MC arranged in the Y direction, and a row decoder RDEC arranged between the cell arrays ARYa and ARYb in a planar view.

[0045] By adopting a structure in which semiconductor substrates SS1 and SS2 are bonded together, the sense amplifiers S / A and data input / output circuits DIO, etc., which are arranged on semiconductor substrate SS2, can be laid out freely in relation to the memory cells MC and row decoders RDEC arranged on semiconductor substrate SS1.

[0046] On the other hand, it is not possible to use a single semiconductor substrate to place the sense amplifier S / A including transistors on the cell arrays ARYa and ARYb including transistors and the row decoder RDEC. For this reason, when using a single semiconductor substrate, the sense amplifier S / A must be placed to avoid the positions where the cell arrays ARYa and ARYb and the row decoder RDEC are formed.

[0047] The semiconductor substrate SS1 has a plurality of memory layers ML (FIG. 5) each including a cell array ARYa, ARYb. That is, the memory layers ML each including memory cells MC with a planar structure called a planar type are stacked vertically on the semiconductor substrate SS1. The semiconductor substrate SS1 is an example of a first layer including the cell arrays ARYa, ARYb. In the planar type memory cells MC, the cell capacitors CCAP are formed in an elongated shape extending horizontally to obtain the required capacitance. As a result, as shown in FIG. 4, the layout pitch of the word lines WLa (or WLb) can be increased. Note that in FIG. 4, the dummy word lines DWL shown in FIG. 3 are omitted.

[0048] Each memory layer ML has cell arrays (corresponding to cell arrays ARYa and ARYb in FIG. 3) arranged on both sides of the row decoder RDEC in the Y direction in a plan view. That is, each memory layer ML has a configuration in which bit lines BL2a and BL2b are removed from the cell arrays ARYa and ARYb in FIG. 3. In each memory layer ML, the row decoder RDEC is provided in common to the cell arrays on both sides in the Y direction. Hereinafter, the cell arrays arranged on both sides in the Y direction in each memory layer ML will also be referred to as cell arrays ARYa and ARYb.

[0049] The semiconductor substrate SS1 has a plurality of segment bit lines SEGBLa, SEGBLb extending in the Z direction and penetrating through a plurality of memory layers ML. As shown in FIG. 5, the segment bit line SEGBLa is connected to the data input / output nodes ND of memory cells MC arranged at the same position in a planar view in the cell array ARYa of the plurality of memory layers. Although not shown, the segment bit line SEGBLb is connected to the data input / output nodes ND of memory cells MC arranged at the same position in a planar view in the cell array ARYb of the plurality of memory layers. The segment bit lines SEGBLa, SEGBLb are an example of a fourth bit line.

[0050] Here, the data input / output node ND indicates the node on the opposite side of the cell capacitor CCAP from the source / drain nodes of the transfer transistor TRT in Figure 1. The segment bit lines SEGBLa and SEGBLb are formed at positions corresponding to the bit line contacts BLCNT in Figure 1. One end of the segment bit lines SEGBLa and SEGBLb aligned in the X direction is connected to the bit lines BL1a and BL1b extending in the X direction, respectively.

[0051] The semiconductor substrate SS2 has a data input / output circuit DIO including multiple sense amplifiers S / A, column decoders CDEC(1 / 2), CDEC(2 / 2), multiple bit lines BL2a, BL2b, and a write / read latch circuit WRLT. For example, the write / read latch circuit WRLT has a write circuit that outputs data to be written into the memory cells MC to the sense amplifiers S / A, and a read latch circuit that latches read data output from the sense amplifiers S / A. An example of the write / read latch circuit WRLT is shown in FIG. 11. The semiconductor substrate SS2 is an example of a second hierarchical level including the sense amplifiers S / A and the bit lines BL2a, BL2b.

[0052] The sense amplifier S / A is disposed at a position facing the row decoder RDEC on the semiconductor substrate SS1. The column decoders CDEC(1 / 2) and CDEC(2 / 2) are disposed on both sides of the sense amplifier S / A in the Y direction, as in FIG. 3. The column decoders CDEC(1 / 2) and CDEC(2 / 2) may be disposed together as a common column decoder.

[0053] The bit lines BL2a and BL2b are spaced apart in the X direction and extend in the Y direction, similar to Fig. 3. As in Fig. 3, the layout pitch of the bit lines BL2a and BL2b can be the same as the layout pitch of the sense amplifiers S / A. Therefore, the layout pitch of the bit lines BL2a and BL2b can be made much larger than the layout pitch of the bit lines BL1a and BL1b.

[0054] Each bit line BL1a of the semiconductor substrate SS1 is connected to one of the bit lines BL2a of the semiconductor substrate SS2 via a through electrode such as a TSV, etc. Although not shown, each bit line BL1b of the semiconductor substrate SS1 is connected to one of the bit lines BL2b of the semiconductor substrate SS2 via a through electrode such as a TSV.

[0055] The double circles added to the bit lines BL1a and BL2a indicate the connection positions of the TSVs. The TSV that interconnects the bit lines BL1a and BL2a is an example of a first via, one end of which is connected to the bit line BL1a and the other end of which is connected to the bit line BL2a, and the TSV that interconnects the bit lines BL1b and BL2b is an example of a second via, one end of which is connected to the bit line BL1b and the other end of which is connected to the bit line BL2b. Note that in Figure 4 and the following figures, only some of the TSVs and their connection positions are shown to avoid cluttering the diagrams.

[0056] 4, the sense amplifiers S / A can be arranged in a position that overlaps the memory cells and row decoders RDEC in a plan view, which allows the sizes of the semiconductor substrates SS1 and SS2 to be reduced compared to when they are not overlapped. Also, by increasing the layout pitch of the bit lines BL2a and BL2b and using bumpless TSVs, the bit lines BL2a and BL2b can be connected to the bit lines BL1a and BL1b, respectively, even when the layout pitch of the bit lines BL1a and BL1b in the Y direction is small.

[0057] The diameter of a bumpless TSV is on the order of a few microns. This can be further reduced with technological advances. In contrast, a TSV structure using bumps requires a size of around 30 to 50 microns, which means the minimum pitch is large and it can be difficult to connect the bit lines BL1a and BL2a. Furthermore, compared to bumpless TSVs, a TSV structure using bumps has larger parasitic capacitance between the bit lines BL1a and BL2a and between the bit lines BL1b and BL2b, resulting in higher power consumption during memory operation.

[0058] Fig. 6 is a partial perspective view showing an overview of a 3D-DRAM formed on the semiconductor substrate SS1 of Fig. 4. Fig. 6 shows a main part of a cell array ARYa, but by replacing the symbol "a" at the end with "b", it becomes a diagram showing a main part of a cell array ARYb. In each memory layer ML, word lines WLa are formed extending in the Y direction at intervals in the X direction.

[0059] The cell capacitor CCAP of the memory cell MC is connected to the segment bit line SEGBLa via a transfer transistor TRT whose gate is connected to the word line WLa. Although not limited to this, the word line WLa has a double-gate structure, and each memory cell MC has a pair of transfer transistors TRT corresponding to the double gate. The segment bit lines SEGBLa arranged in the Y direction are assigned different data numbers.

[0060] 6, the segment bit line SEGBLa located in the center in the X direction is connected to a pair of memory cells MC adjacent to each other on both sides in the X direction in plan view, but in reality, the segment bit lines SEGBLa other than the segment bit lines SEGBLa at both ends in the X direction may be connected to a pair of memory cells MC. Note that the segment bit line SEGBLa may also be connected to a memory cell MC adjacent to each other on one side in the X direction in plan view.

[0061] When data is read from a memory cell MC, one of a pair of word lines WLa adjacent to the segment bit line SEGBLa in one of the multiple memory layers MLa is driven to a high level. Then, charge is read from the cell capacitor CCAP of the memory cell MC connected to the driven word line WLa to the segment bit line SEGBLa. By sharing the segment bit line SEGBLa between a pair of memory cells MC in each memory layer ML, the number of segment bit lines SEGBLa can be reduced, and an increase in the layout size of the cell array ARYa can be suppressed.

[0062] The transistor switch unit TR-SW has a select transistor SELT that connects the segment bit line SEGBLa to the bit line BL1a. The gate of the select transistor SELT is connected to a bit line select signal line BLSEL. The bit line select signal line BLSEL is wired for each group of segment bit lines SEGBLa aligned in the Y direction. The bit lines BL1a are connected via TSVs to sense amplifiers S / A (S / A0-S / A3) (not shown) that are each assigned a different data number.

[0063] When data is read from the memory cells MC, one of the groups of segment bit lines SEGBLa is connected to one of the bit lines BL1a. The other groups of segment bit lines SEGBLa are not connected to the bit line BL1a. Therefore, when data is read from the memory cells MC, one of the memory cells MC in the memory layer ML selected by the word line WLa can be selectively connected to the bit line BL1a via one group of segment bit lines SEGBLa.

[0064] This allows the capacitance of the bit line (SEGBLa+BL1a) connected to the sense amplifier S / A during read access to be reduced compared to when the bit line BL1a is also connected to the segment bit line SEGBLa that is not used for data read. As a result, the amount of signal read from the memory cell MC to the bit line BL1a can be relatively increased, improving the data read margin by the sense amplifier S / A. In addition, the data amplification speed by the sense amplifier S / A is increased, thereby shortening the read access time. Furthermore, since the bit line capacitance can be reduced, the power consumption for refresh can be reduced.

[0065] In practice, the structure of FIG. 6 is repeatedly arranged in the Y direction, and, for example, 128 bit lines BL1a are arranged and connected to 128 sense amplifiers S / A, respectively. When data is read, data is read from the 128 memory cells MC to the 128 bit lines BL1 via the segment bit lines SEGBLa, and then amplified by the 128 sense amplifiers S / A via the 128 TSVs. Of the 128 data amplified by the sense amplifiers S / A, for example, 64 data selected by column select switches CSW (not shown) are output from 64 data input / output terminals. The 128 data amplified by the sense amplifiers S / A are then written back to the memory cells MC.

[0066] Alternatively, the column selection switches CSW may be omitted and the data amplified by the 128 sense amplifiers S / A may be output from the 128 data input / output terminals. The number of bit lines BL1a and the number of sense amplifiers S / A may be, for example, 1024, 2048, or 4096.

[0067] On the other hand, in a data write operation, first, data is read from 128 memory cells MC to 128 bit lines BL1a and amplified by 128 sense amplifiers S / A. After this, 64 of the 128 data amplified by the sense amplifiers S / A are rewritten with data received at the data input / output terminals, and the 128 data including the rewritten data are written back to the memory cells MC.

[0068] Fig. 7 is a flow diagram showing an example of a manufacturing method of the semiconductor device SEM2 of Fig. 4. The semiconductor device SEM2 is manufactured using semiconductor substrates SS1 and SS2 in wafer form. Although Fig. 7 shows elements of the cell array ARYa, the cell array ARYb is also manufactured simultaneously with the cell array ARYa by the same steps as Fig. 7.

[0069] 7(a), an insulating layer INS1 is formed on a semiconductor substrate SS1 on which, for example, a 3D-DRAM, a clock circuit, a power supply circuit, etc. (not shown) are formed using a known manufacturing method. Then, after the surface of the insulating layer INS1 is planarized, a bit line BL1a is formed.

[0070] 7(b), an insulating layer INS2 is formed to cover the bit line BL1a, and then an opening is formed to expose the bit line BL1a. Note that the bit line BL1a that is not exposed in the cross section shown in FIG. 7(b) is exposed in another cross section in the front-to-back direction of the paper.

[0071] 7(c), a metal material such as copper is formed on the surface by sputtering or the like, and then patterned by photolithography to form an electrode EL connected to the bit line BL1a. Next, an insulating layer INS3 is formed to cover the electrode EL.

[0072] Next, in FIG. 7(d), the insulating layer INS3 is polished until the electrode EL is exposed, and then an adhesive ADH is applied to the semiconductor substrate SS1. A semiconductor substrate SS2, on which a sense amplifier S / A and a data input / output circuit are formed, is prepared in advance and polished to a thickness of approximately 5 μm using known techniques. An insulating layer INS4 is formed on the semiconductor substrate SS2. In practice, to ensure mechanical strength, the semiconductor substrate SS2 is polished by temporarily bonding a support wafer. The support wafer is removed after bonding the semiconductor substrate SS2 to the semiconductor substrate SS1.

[0073] 7(e), the semiconductor substrates SS1 and SS2 are bonded together with the adhesive ADH. Next, in FIG. 7(f), the semiconductor substrate SS2 is opened together with the insulating layer INS4 toward the electrode EL of the semiconductor substrate SS1, forming an opening that exposes the electrode EL.

[0074] 7(g), a metal film such as copper is formed on the surface by sputtering or the like, and the opening is filled with an electrode EL to form a TSV, and then an insulating layer INS5 is formed on the surface. Next, in FIG. 7(h), the insulating layer INS5 is polished until the electrode EL is exposed.

[0075] 7(i), a metal film for forming bit line BL2a is formed on the surface by sputtering or the like, and then patterned by photolithography to form bit line BL2a connected to bit line BL1 via TSV. A known multilayer wiring process is then performed to complete a wafer on which multiple semiconductor devices SEM2 are mounted. A protective film is then formed covering the surface of the wafer, and a dicing process is performed to separate the semiconductor devices SEM2, completing the semiconductor devices SEM2.

[0076] As described above, the second embodiment can also achieve the same effects as the first embodiment. For example, even when the layout pitch of the bit lines BL1a and BL1b connected to the memory cells MC is small, the layout pitch of the sense amplifiers S / A can be relaxed, thereby improving the ease of layout.

[0077] Furthermore, in the second embodiment, the semiconductor substrate SEM2 is formed by stacking the semiconductor substrate SS1 including the cell arrays ARYa and ARYb and the semiconductor substrate SS2 including the bit lines BL2a and BL2b and the sense amplifiers S / A. This allows the sense amplifiers S / A to be arranged at positions overlapping the memory cells MC and the row decoders RDEC in a plan view, and the sizes of the semiconductor substrates SS1 and SS2 can be reduced compared to when they are not overlapped.

[0078] By increasing the layout pitch of the bit lines BL2a and BL2b and using bumpless TSVs, the bit lines BL2a and BL2b can be connected to the bit lines BL1a and BL1b, respectively, even when the layout pitch of the bit lines BL1a and BL1b in the Y direction is small.

[0079] By forming a 3D-DRAM having a plurality of memory layers ML each including a planar type memory cell MC on a semiconductor substrate SS1, the memory integration degree of the semiconductor device MEM2 can be improved, and the capacity of the semiconductor device MEM2 can be increased.

[0080] FIG. 8 is a plan view showing an example of the layout of a semiconductor device SEM3 according to a third embodiment of the present invention. FIG. 9 is an exploded perspective view showing the semiconductor device SEM3 of FIG. 8. Elements similar to those in FIG. 3 or 4 are given the same reference numerals, and detailed description thereof will be omitted. The semiconductor device MEM3 is formed by stacking semiconductor substrates SS1 and SS2. Note that the semiconductor substrates SS1 and SS2 may be stacked in the reverse order to that in FIG. 9.

[0081] 8 shows a layout in which the semiconductor substrates SS1 and SS2 of FIG. 9 are overlapped in a plan view. For example, memory cells MC, word lines WLa, WLb, bit lines BL1a, BL2b, and a row decoder RDEC are arranged on the semiconductor substrate SS1. Sense amplifiers S / A, bit lines BL2a, BL2b, and a column decoder CDEC common to the cell arrays ARYa and ARYb are arranged on the semiconductor substrate SS2. Note that the dummy word lines DWL shown in FIG. 3 are omitted in FIG. 8.

[0082] In Figure 8, the TSVs at the connection points of bit lines BL1a and BL2a, indicated by double circles, and the TSVs at the connection points of bit lines BL1b and BL2b are arranged in a zigzag pattern so as to be offset in the Y direction in a plan view, and bit lines BL2a and BL2b are arranged so as not to protrude from the connection points to either side in the Y direction. That is, each bit line BL2a has one end connected to the sense amplifier S / A and the other end connected to bit line BL1a via a TSV. Each bit line BL2b has one end connected to the sense amplifier S / A and the other end connected to bit line BL1b via a TSV. The lengths of bit lines BL2a and BL2b are set to be equal to each other.

[0083] The sense amplifiers S / A are arranged in a zigzag pattern, shifted in accordance with the direction in which the connection points are shifted. The row decoder RDEC, which can be arranged in a position overlapping the sense amplifiers S / A in a plan view, is arranged between the cell arrays ARYa and ARYb.

[0084] This allows the lengths of the bit lines BL2a and BL2b connected to each of the zigzag-arranged sense amplifiers S / A to be equal to each other, thereby minimizing the parasitic capacitance of the bit lines BL2a and BL2b connected to each sense amplifier S / A. As a result, the data amplification time by the sense amplifiers S / A can be shortened compared to the semiconductor device SEM1 in FIG. 3 and the semiconductor device SEM2 in FIG. 4.

[0085] The semiconductor substrate SS2 has column switches (not shown) arranged near the sense amplifiers S / A. Column selection lines that drive the column switches are wired from the column decoders CDEC to the column switches. By using a common column decoder CDEC, the column decoders CDEC can be arranged at a position away from the sense amplifiers S / A, and the column decoders CDEC can be laid out without being affected by the sense amplifiers S / A arranged in a zigzag pattern.

[0086] In contrast, when the column decoders CDEC(1 / 2) and CDEC(2 / 2) are arranged adjacent to both sides of the sense amplifier S / A in the Y direction as shown in Figure 4, the shapes of the column decoders CDEC(1 / 2) and CDEC(2 / 2) must be changed to match the misalignment of the sense amplifier S / A, which may result in wasted area for the circuit layout.

[0087] Fig. 10 is a plan view showing an example of a circuit layout of the semiconductor substrate SS2 of Fig. 8. The bit lines BL2a and BL2b connected to each sense amplifier S / A are connected to a common data bus CDB common to the sense amplifiers S / A via column switches CSW (transistors), and are connected to a data input / output circuit DIO including a write / read latch circuit WRLT via the common data bus CDB.

[0088] Since the common data bus CDB corresponds to one data input / output terminal, the eight sense amplifiers S / A shown in Figure 10 amplify data assigned the same data number. The column decoder CDEC outputs eight column selection signals CLSEL that respectively control the on / off of pairs of column switches CSW connected to the sense amplifiers S / A. The column switches CSW operate by receiving the column selection signals CLSEL at their gates.

[0089] As in the above-described embodiment, the sense amplifiers S / A can be arranged with ample space in the X direction, and the layout pitch is large. Furthermore, the TSVs are arranged in a zigzag pattern to match the positions of the sense amplifiers S / A. This allows the layout pitch of the TSVs to be larger than the layout pitch of the bit lines BL2a and BL2b, improving the ease of TSV layout.

[0090] As shown in Fig. 9, the bit lines BL1a and BL1b of the semiconductor substrate SS1 and the bit lines BL2a and BL2b of the semiconductor substrate SS1 are connected by bumpless TSVs. For example, as explained in Fig. 7, the TSVs are formed by penetrating the semiconductor substrate SS2 (wafer) that has been polished to a thickness of about 5 µm, making it difficult to achieve minute dimensions at the bit line level.

[0091] For example, the diameter of a TSV depends on the thickness of the wafer where it is opened, and when the wafer thickness is about 5 μm, it is at least about 1 to 2 μm, which is larger than the width of the bit line. However, in this embodiment, by arranging the TSVs in a zigzag pattern, it is possible to prevent adjacent TSVs from contacting each other even when the diameter of the TSV is larger than the width of the bit lines BL2a and BL2b.

[0092] As described above, the third embodiment can also achieve the same effects as the first and second embodiments. For example, even when the layout pitch of the bit lines BL1a and BL1b connected to the memory cells MC is small, the layout pitch of the sense amplifiers S / A can be relaxed, thereby improving the ease of layout.

[0093] By stacking a semiconductor substrate SS1 including cell arrays ARYa and ARYb and a semiconductor substrate SS2 including bit lines BL2a and BL2b and a sense amplifier S / A, the sense amplifier S / A can be positioned so as to overlap the memory cells MC and row decoder RDEC in a planar view.

[0094] By increasing the layout pitch of the bit lines BL2a and BL2b and using bumpless TSVs, the bit lines BL2a and BL2b can be connected to the bit lines BL1a and BL1b, respectively, even when the layout pitch of the bit lines BL1a and BL1b in the Y direction is small.

[0095] By forming a 3D-DRAM having a plurality of memory layers ML each including a planar type memory cell MC on a semiconductor substrate SS1, the memory integration degree of the semiconductor device MEM2 can be improved, and the capacity of the semiconductor device MEM2 can be increased.

[0096] Furthermore, in the third embodiment, by shifting the TSVs to match the sense amplifiers S / A that are arranged shifted in the Y direction, the layout pitch of the TSVs can be made larger than the layout pitch of the bit lines BL2a and BL2b, thereby improving the ease of layout of the TSVs.

[0097] When the sense amplifiers S / A are arranged in a zigzag pattern, the parasitic capacitance of the bit lines BL2a and BL2b connected to each sense amplifier S / A can be minimized by making the lengths of the bit lines BL2a and BL2b connected to each sense amplifier S / A equal, thereby shortening the time it takes for the sense amplifiers S / A to amplify data.

[0098] By using a common column decoder CDEC, the column decoder CDEC can be placed at a position away from the sense amplifiers S / A, which allows the column decoder CDEC to be laid out without being affected by the sense amplifiers S / A that are arranged in a zigzag pattern, thereby preventing waste in the circuit layout area.

[0099] 11 is a diagram showing an example of the layout of a semiconductor device SEM4 according to a fourth embodiment of the present invention. Elements similar to those in FIG. 9 are given the same reference numerals, and detailed descriptions thereof will be omitted. The semiconductor device SEM4 has semiconductor substrates SS1, SS2, and SS3 stacked in this order. Note that the semiconductor substrates SS1, SS2, and SS3 may be stacked in the reverse order to that shown in FIG. 11.

[0100] The semiconductor substrate SS1 has memory cells MC, word lines WLa, WLb, bit lines BL1a, BL2b, and a row decoder RDEC, similar to that shown in Fig. 9. The connection specifications of the TSVs connecting the semiconductor substrates SS1 and SS2 are similar to those shown in Fig. 9. Note that the dummy word lines DWL shown in Fig. 3 are omitted in Fig. 11.

[0101] The semiconductor substrate SS2 does not include the column decoder CDEC of Figure 9, and a pair of adjacent sense amplifiers S / A are commonly connected to complementary input / output nodes. The complementary input / output nodes are connected to the semiconductor substrate SS3 via a pair of bumpless TSVs. The TSVs, one end of which is connected to the write / read latch circuit WRLT and the other end of which is connected to the sense amplifiers S / A, are an example of third vias.

[0102] For example, in a pair of sense amplifiers S / A, one of a pair of input / output nodes connected to bit line BL2a is connected to the semiconductor substrate SS3 via a TSV corresponding to one of the complementary data lines DQ, / DQ, and in a pair of sense amplifiers S / A, the other of the pair of input / output nodes connected to bit line BL2b is connected to the semiconductor substrate SS3 via a TSV corresponding to the other of the complementary data lines DQ, / DQ.

[0103] In FIG. 11, a data number is assigned to each pair of sense amplifiers S / A, so the common data bus CDB in FIG. 10 is not used. Although the TSVs appear long in the figure, their actual length is only a few μm. Therefore, compared to the bus configuration of FIG. 10, which has the common data bus CDB extending in a zigzag pattern in the X direction of the semiconductor substrate SS2, the load capacitance connected to the sense amplifiers S / A can be reduced, allowing the sense amplifiers S / A to operate at high speed. A method of selectively connecting one of a pair of sense amplifiers S / A to the semiconductor substrate SS3 will be explained in FIG. 12.

[0104] The semiconductor substrate SS3 has a data input / output circuit DIO including a write / read latch circuit WRLT corresponding to a pair of sense amplifiers S / A. The semiconductor substrate SS3 is an example of a third semiconductor substrate. The write / read latch circuit WRLT is formed for each data input / output terminal (not shown). Therefore, for example, the number of sense amplifiers S / A, the number of bit line pairs BL2a, BL2b, and the number of bit line pairs BL1a, BL2b provided in the semiconductor device SEM5 is twice the number of data input / output terminals.

[0105] The left side of Figure 11 shows an example of one of a pair of sense amplifiers S / A and a circuit connected to the sense amplifier S / A. The sense amplifier S / A has a latch circuit including a pair of CMOS inverters, and a p-channel transistor and an n-channel transistor that control the connection of the latch circuit to a power line and a ground line, respectively. The gate of the p-channel transistor receives a sense amplifier enable signal / SAEN that is set to a low level when the sense amplifier S / A is operating. The gate of the n-channel transistor receives a sense amplifier enable signal SAEN that is set to a high level when the sense amplifier S / A is operating. The sense amplifier S / A also has bit line isolators ISO arranged between it and bit lines BL2a and BL2b.

[0106] As shown on the left side of Fig. 11, the write / read latch circuit WRLT has a pair of write circuits WR1 and WR2 whose outputs are connected to the data lines DQ and / DQ, respectively, and a read latch RLT whose complementary inputs are connected to the data lines DQ and / DQ via a pair of CMOS transmission gates TG. Note that Fig. 11 shows typical circuit examples of the sense amplifier S / A and the write / read latch circuit WRLT, but circuits other than those shown may also be used.

[0107] 12 is a plan view showing an example of a circuit layout of the semiconductor substrate SS2 of FIG. 11. Elements similar to those in FIG. 10 are assigned the same reference numerals, and detailed description thereof will be omitted. In FIG. 12, the common data bus CDB shown in FIG. 10 is not used, and one and the other of the complementary input / output nodes of a pair of sense amplifiers S / A are connected to each other via a column switch CSW. Furthermore, the pair of sense amplifiers S / A are connected to any of four data line pairs (DQ0, / DQ0), (DQ1, / DQ1), (DQ2, / DQ2), and (DQ3, / DQ3) via the column switch CSW. Hereinafter, when the data line pairs are described without distinction, they will also be referred to as data line pairs DQ and / DQ.

[0108] The semiconductor substrate SS2 also has a data input / output control circuit DIOCNT that controls the gate of the column switch CSW to connect one of the pair of sense amplifiers S / A to the data line pair DQ, / DQ. During a data read or write operation, the data input / output control circuit DIOCNT exclusively outputs a column selection signal CLSEL0 corresponding to one of the pair of sense amplifiers S / A and a column selection signal CLSEL1 corresponding to the other of the pair of sense amplifiers S / A. In this way, the data input / output control circuit DIOCNT functions as a column decoder that selects multiple sense amplifiers S / A.

[0109] Note that one, four, or eight sense amplifiers S / A may be connected to each of the data line pairs DQ, / DQ via the column switches CSW. For example, assume that the semiconductor device SEM4 has 4096 sense amplifiers S / A. When one sense amplifier S / A is connected to each data line pair DQ, / DQ, the semiconductor device SEM4 can input and output 4096-bit data signals in parallel to the data input / output terminals. In other words, the number of data line pairs DQ, / DQ is equal to the number of bits of the external data terminals.

[0110] When two sense amplifiers S / A are selectively connected to each data line pair DQ, / DQ, the semiconductor device SEM4 can input and output 2048-bit data signals in parallel. When four sense amplifiers S / A are selectively connected to each data line pair DQ, / DQ, the semiconductor device SEM4 can input and output 1024-bit data signals in parallel. In this way, the semiconductor device SEM4 can operate as a high-bandwidth memory.

[0111] Furthermore, the more sense amplifiers S / A connected to each data line pair DQ, / DQ, the fewer TSVs connecting the semiconductor substrates SS2, SS3 can be, and the larger the layout pitch of the TSVs can be. For example, the number of sense amplifiers S / A connected to each data line pair DQ, / DQ is determined according to the bandwidth of input / output data (i.e., performance) and the applicable manufacturing process (i.e., the minimum layout pitch of the TSVs).

[0112] As described above, the fourth embodiment can also achieve the same effects as the first to third embodiments. Furthermore, in the fourth embodiment, the common data bus CDB is not used, and one of the pair of sense amplifiers S / A is connected to the data terminals DQ, / DQ of the write / read latch circuit WRLT of the semiconductor substrate SS3 via TSVs. Furthermore, bumpless TSVs are used for the TSVs. This allows the load capacitance connected to the sense amplifiers S / A to be smaller than when the common data bus CDB is used, and allows the sense amplifiers S / A to operate at high speed.

[0113] 13 is an exploded perspective view showing an example of a layout of a semiconductor device SEM5 according to a fifth embodiment of the present invention. The same elements as those in FIG. 11 are denoted by the same reference numerals, and detailed description thereof will be omitted. Note that in FIG. 13, the dummy word lines DWL shown in FIG. 3 are omitted.

[0114] The semiconductor device SEM5 differs from the semiconductor device SEM4 shown in Fig. 11 in that the sense amplifiers S / A and the write-read latch circuits WRLT are each arranged in a row along the X direction. Note that the semiconductor substrates SS1, SS2, and SS3 may be stacked in the reverse order to that shown in Fig. 13.

[0115] Since the write-read latch circuits WRLT can be arranged in a row, the write-read latch circuits WRLT can be easily connected to other circuits formed on the semiconductor substrate SS3. For example, when a plurality of arithmetic units are formed on the semiconductor substrate SS3 and the write-read latch circuits WRLT are connected to the arithmetic units, the routing of data lines can be simplified.

[0116] Furthermore, compared to when the sense amplifiers S / A and the write / read latch circuits WRLT are arranged in a zigzag pattern, the lengths of the data lines DQ and / DQ in the semiconductor substrates SS2 and SS3 can be shortened, and the load capacitance and wiring resistance of the data lines DQ and / DQ can be reduced. Therefore, the speed of the read operation and the write operation of the semiconductor device SEM5 can be made higher than that of the semiconductor device SEM4.

[0117] As described above, the fifth embodiment can also achieve the same effects as the first to fourth embodiments. Furthermore, in the fifth embodiment, the write / read latch circuits WRLT can be arranged in a row, which makes it easy to connect the write / read latch circuits WRLT to other circuits formed on the semiconductor substrate SS3, and facilitates the routing of data lines. Furthermore, the lengths of the data lines DQ and / DQ in the semiconductor substrates SS2 and SS3 can be shortened, which reduces the load capacitance and wiring resistance of the data lines DQ and / DQ. As a result, the speed of the read operation and write operation of the semiconductor device SEM5 can be increased.

[0118] 14 is an exploded perspective view showing an example of a layout of a semiconductor device SEM6 according to a sixth embodiment of the present invention. The same elements as those in FIG. 4 are denoted by the same reference numerals, and detailed description thereof will be omitted. Note that in FIG. 14, the dummy word lines DWL shown in FIG. 3 are omitted.

[0119] 4 in that bit lines BL2a and BL2b are formed on a semiconductor substrate SS1 using a metal wiring layer. Bit line BL2a is connected to bit line BL1a through a via VIA, and bit line BL2b is connected to bit line BL1b through a via VIA. Bit lines BL2a and BL2b are also connected to complementary input / output nodes of a sense amplifier S / A formed on a semiconductor substrate SS2 through bumpless TSVs.

[0120] As described above, the sixth embodiment can also achieve the same effects as the first to fifth embodiments. Furthermore, in the sixth embodiment, by forming the bit lines BL2a and BL2b on the semiconductor substrate SS1 using a metal wiring layer, the semiconductor device SEM6 can be formed using two semiconductor substrates SS1 and SS2, and the cost of the semiconductor device MEM6 can be reduced compared to when three semiconductor substrates SS1, SS2, and SS3 are used.

[0121] 15 is an exploded perspective view showing an example of a layout of a semiconductor device SEM7 according to the seventh embodiment of the present invention. Elements similar to those in FIG. 14 are given the same reference numerals, and detailed descriptions thereof will be omitted. Note that in FIG. 15, the dummy word lines DWL shown in FIG. 3 are omitted.

[0122] In the semiconductor device SEM7, the semiconductor substrate SS1 has memory cells MC (not shown), word lines WLa, WLb, bit lines BL1a, BL1b, BL2a, BL2, row decoders RDECa, RDECb, and sense amplifiers S / A. The semiconductor substrate SS1 functions as a memory chip by decoding addresses, storing data in memory cells, and reading data stored in the memory cells. The semiconductor substrate SS2 has a data input / output circuit DIO including a write / read latch circuit WRLT connected to the sense amplifiers S / A via bumpless TSVs, and functions as a logic chip.

[0123] 14, the semiconductor device SEM7 has a pair of adjacent sense amplifiers S / As commonly connected to complementary input / output nodes, and the complementary input / output nodes are connected to the semiconductor substrate SS2 via a pair of bumpless TSVs. For example, if the semiconductor device SEM7 has 4096 sense amplifiers S / As, the semiconductor device SEM7 can input and output 2048-bit data signals in parallel to the data input / output terminals.

[0124] 16 is a plan view showing an example of a circuit layout of the semiconductor substrate SS1 of FIG. 15. Elements similar to those in FIG. 12 are assigned the same reference numerals, and detailed description thereof will be omitted. FIG. 16 shows the bit lines BL2a, BL2b, sense amplifiers S / A, column switches CSW, and data input / output control circuits DIOCNT, and does not show the word lines WLa, WLb, and bit lines BL1a, BL1b. The semiconductor substrate SS1 shown in FIG. 16 is similar to the semiconductor substrate SS2 shown in FIG. 12, except that vias VIA are arranged instead of the TSVs connecting the bit lines BL1a, BL2a and the TSVs connecting the bit lines BL1b, BL2b in FIG. 12, and the sense amplifiers S / A are arranged in a row in the X direction.

[0125] As described above, the seventh embodiment can also achieve the same effects as the first to sixth embodiments. For example, the semiconductor device SEM7 can be formed using two semiconductor substrates SS1 and SS2, and the cost of the semiconductor device MEM7 can be reduced compared to when three semiconductor substrates SS1, SS2, and SS3 are used.

[0126] Although the present invention has been described above based on the embodiments, the present invention is not limited to the requirements shown in the above embodiments. These requirements can be changed without departing from the spirit of the present invention, and can be appropriately determined depending on the application form. [Explanation of symbols]

[0127] ADH Adhesive ARYa, ARYb cell array BL, BL1, BL2, BLa, BLb bit lines BL1a, BL1b, BL2a, BL2b bit lines BLCNT bit line contact BLSEL Bit line selection signal line CCAP Cell Capacitor CDB Common Data Bus CDEC Column Decoder CNTL control circuit CLSEL, CLSEL0, CLSEL1 Column selection signals CSW Column Switch DIO Data input / output circuit DIOCNT Data input / output control circuit DQ0, / DQ0, DQ1, / DQ1 data lines DQ2, / DQ2, DQ3, / DQ3 data lines DWLa, DWLb dummy word lines EL electrode INS1, INS2, INS3, INS4, INS5 insulation layers ISO Bit Line Isolator MC memory cell ML Memory Layer ND Data Input / Output Node RDEC, RDECa, RDECb row decoder S / A Sense amplifier SELT Select transistor SEGBLa, SEGBLb segment bit lines SEM0, SEM1, SEM2, SEM3 semiconductor device SEM4, SEM5, SEM6, SEM7 semiconductor device SS1, SS2, SS3 Semiconductor substrate TR-SW transistor switch section TRT Transfer Transistor VIA WL, WLa, WLb word lines WRLT Write / Read Latch Circuit

Claims

1. a first cell array and a second cell array each including a plurality of word lines spaced apart in a first direction and extending in a second direction intersecting the first direction, a plurality of first bit lines spaced apart in the second direction and extending in the first direction, and a plurality of memory cells respectively disposed at intersections of the word lines and the first bit lines, and arranged along the second direction; a plurality of sense amplifiers arranged along the first direction in a portion where the first cell array and the second cell array face each other in a plan view; a plurality of second bit lines arranged at intervals in the first direction, extending in the second direction, and connecting any one of the plurality of first bit lines of the first cell array to any one of the plurality of sense amplifiers; a plurality of third bit lines arranged at intervals in the first direction, extending in the second direction, and connecting any one of the plurality of first bit lines of the second cell array to any one of the plurality of sense amplifiers; A semiconductor device characterized by:

2. Each of the plurality of memory cells has a cell capacitor for storing data, and a transfer transistor disposed between the cell capacitor and the first bit line, the gate of the transfer transistor being connected to the word line; The cell capacitor has a shape in which the length in the first direction is longer than the length in the second direction, and is disposed between a pair of the word lines adjacent to each other in the first direction in a plan view.

2. The semiconductor device according to claim 1, wherein:

3. a first layer including the first cell array and the second cell array; a second tier including the sense amplifier, the second bit line, and the third bit line, and arranged opposite to the first tier; a first via connecting the first bit line and the second bit line of the first cell array to each other; a second via connecting the first bit line and the third bit line of the second cell array to each other; 2. The semiconductor device according to claim 1, wherein:

4. a first semiconductor substrate including the first layer; a second semiconductor substrate including the second layer, one end and the other end of the first via are connected to the first bit line and the second bit line of the first cell array without a bump therebetween; One end and the other end of the second via are connected to the first bit line and the third bit line of the second cell array without using a bump.

4. The semiconductor device according to claim 3, wherein:

5. the plurality of sense amplifiers arranged along the first direction are arranged with a shift in the second direction; each of the plurality of second bit lines has one end connected to the sense amplifier and the other end connected to the first bit line of the first cell array; each of the plurality of third bit lines has one end connected to the sense amplifier and the other end connected to the first bit line of the second cell array; The second bit line and the third bit line have the same length.

5. The semiconductor device according to claim 4, wherein:

6. a third semiconductor substrate including a data input / output circuit; a third via connecting the data input / output circuit to the sense amplifier; 5. The semiconductor device according to claim 4, wherein:

7. One end and the other end of the third via are connected to the data input / output circuit and the sense amplifier, respectively, without passing through a bump.

7. The semiconductor device according to claim 6, wherein:

8. the first semiconductor substrate has a row decoder that selects the word line to be driven based on an address signal; the row decoder is disposed in a region of the second semiconductor substrate facing the sense amplifier in a plan view; 5. The semiconductor device according to claim 4, wherein:

9. a first semiconductor substrate including the first cell array, the second cell array, the plurality of second bit lines, and the plurality of third bit lines; a second semiconductor substrate including the sense amplifier and disposed opposite the first semiconductor substrate; vias connecting the second bit lines and the third bit lines to the sense amplifiers, respectively; 2. The semiconductor device according to claim 1, wherein:

10. a first semiconductor substrate including the first cell array, the second cell array, the plurality of sense amplifiers, the plurality of second bit lines, and the plurality of third bit lines; a second semiconductor substrate including a data input / output circuit; a via connecting the data input / output circuit to the sense amplifier; 2. The semiconductor device according to claim 1, wherein:

11. a control circuit disposed in an area where the plurality of sense amplifiers are not formed in the opposing portion between the first cell array and the second cell array, the control circuit controlling reading and writing of data from and to the memory cells; 11. The semiconductor device according to claim 1, wherein:

12. The first semiconductor substrate is a plurality of memory layers stacked on top of one another, each memory layer including the first cell array and the second cell array; a fourth bit line formed through the plurality of memory layers and commonly connected to the first bit lines of the plurality of memory layers; 11. The semiconductor device according to claim 4, wherein:

13. a pair of column switches connecting the second bit line and the third bit line connected to each of the plurality of sense amplifiers to complementary data lines, respectively; a column decoder common to the first cell array and the second cell array for controlling the on / off of the pair of column switches; 11. The semiconductor device according to claim 4, wherein:

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