Printed circuit board

Abstract

To provide a printed circuit board capable of preventing occurrence of a crack due to a thermal shock even when a through via is formed in a core layer including an inorganic material such as a glass substrate.SOLUTION: A printed circuit board includes: a first insulating layer 111; a through via 135 having one or more gaps G1, G2 penetrating at least a part between an upper surface and a lower surface of the first insulating layer and separating at least part of one or more of a side surface of an upper end part and a side surface of a lower end part from the first insulating layer; and a second insulating layer 112 disposed on the first insulating layer, covering at least part of one or more of the upper end part and the lower end part of the through via, and filling at least a part of each of one or more gaps.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The present invention relates to printed circuit boards. [Background technology]

[0002] Recently, increasing the performance of package substrates has led to demands for larger area, higher layer count, and finer design. Meanwhile, copper clad laminate (CCL) is typically used as the core substrate in package substrates. However, CCL's low modulus and high thermal expansion coefficient make it prone to warpage and limit the feasibility of achieving finer circuitry. Therefore, new materials, such as inorganic core substrates, are needed that can suppress warpage with their high modulus and low thermal expansion coefficient and have smooth surfaces that facilitate the realization of finer circuitry. However, in core substrates containing inorganic materials, defects can occur at the top and bottom entrances during the formation of through vias, which can potentially become the initiation points for cracks after commercialization. Summary of the Invention [Problem to be solved by the invention]

[0003] One of the various objects of the present invention is to provide a printed circuit board that can prevent cracks from occurring due to thermal shock even when a through via is formed in a core layer containing an inorganic material such as a glass substrate. [Means for solving the problem]

[0004] One of the solutions proposed through the present invention is to provide a printed circuit board having a structure that may be advantageous in terms of stress against thermal shock by forming one or more gaps, which are separated spaces between the through via and the core layer, on the side of the upper end and / or the side of the lower end of the through via and filling these with an insulating material.

[0005] For example, one example of a printed circuit board may include a first insulating layer, a through via that penetrates at least a portion between the upper and lower surfaces of the first insulating layer and has one or more gaps that separate at least a portion of one or more of the side surfaces of the upper end and the lower end from the first insulating layer, respectively, and a second insulating layer that is arranged on the first insulating layer, covers at least a portion of one or more of the upper end and the lower end of the through via, and fills at least a portion of each of the one or more gaps.

[0006] For example, one example of a printed circuit board may include a glass substrate, a through hole penetrating between the upper and lower surfaces of the glass substrate, a metal via filling at least a portion of the through hole, one or more gaps respectively arranged between a side surface of the upper end of the metal via and a wall surface of the through hole, and between a side surface of the lower end of the metal via and a wall surface of the through hole, and an insulating layer arranged on the glass substrate and filling at least a portion of each of the one or more gaps. [Effects of the Invention]

[0007] One of the various effects of the present invention is that it provides a printed circuit board that can prevent cracks from occurring due to thermal shock even when a through via is formed in a core layer containing an inorganic material such as a glass substrate. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a block diagram illustrating an example of an electronic device system. [Figure 2] FIG. 1 is a perspective view schematically illustrating an example of an electronic device. [Figure 3] FIG. 1 is a cross-sectional view schematically illustrating an example of a printed circuit board. [Figure 4] 4 is an enlarged cross-sectional view schematically illustrating an area A of the printed circuit board of FIG. 3. FIG. [Figure 5a] 5A to 5C are plan views schematically showing various examples of cross sections taken along line II' of region A of the printed circuit board of FIG. 4. [Figure 5b]5A to 5C are plan views schematically showing various examples of cross sections taken along line II' of region A of the printed circuit board of FIG. 4. [Figure 6a] 4A to 4C are cross-sectional views schematically illustrating an example of manufacturing steps for the printed circuit board of FIG. 3. [Figure 6b] 4A to 4C are cross-sectional views schematically illustrating an example of manufacturing steps for the printed circuit board of FIG. 3. [Figure 6c] 4A to 4C are cross-sectional views schematically illustrating an example of manufacturing steps for the printed circuit board of FIG. 3. [Figure 6d] 4A to 4C are cross-sectional views schematically illustrating an example of manufacturing steps for the printed circuit board of FIG. 3. [Figure 6e] 4A to 4C are cross-sectional views schematically illustrating an example of manufacturing steps for the printed circuit board of FIG. 3. [Figure 6f] 4A to 4C are cross-sectional views schematically illustrating an example of manufacturing steps for the printed circuit board of FIG. 3. [Figure 6g] 4A to 4C are cross-sectional views schematically illustrating an example of manufacturing steps for the printed circuit board of FIG. 3. [Figure 6h] 4A to 4C are cross-sectional views schematically illustrating an example of manufacturing steps for the printed circuit board of FIG. 3. [Figure 6i] 4A to 4C are cross-sectional views schematically illustrating an example of manufacturing steps for the printed circuit board of FIG. 3. [Figure 7] FIG. 10 is a cross-sectional view schematically illustrating another example of a printed circuit board. [Figure 8] FIG. 10 is a cross-sectional view schematically illustrating yet another example of a printed circuit board. DETAILED DESCRIPTION OF THE INVENTION

[0009] The present invention will now be described with reference to the accompanying drawings, in which the shapes and sizes of elements may be exaggerated or reduced for clarity.

[0010] electronic equipment FIG. 1 is a block diagram illustrating an example of an electronic device system.

[0011] Referring to the drawing, an electronic device 1000 houses a main board 1010. Chip-related components 1020, network-related components 1030, and other components 1040 are physically and / or electrically connected to the main board 1010. These components are also connected to other electronic components described below to form various signal lines 1090.

[0012] Examples of chip-related components 1020 include, but are not limited to, memory chips such as volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), and flash memory; application processor chips such as central processors (e.g., CPU), graphics processors (e.g., GPU), digital signal processors, encryption processors, microprocessors, and microcontrollers; and logic chips such as analog-to-digital converters and ASICs (application-specific ICs). It goes without saying that the chip-related components 1020 may include other types of chip-related electronic components. It goes without saying that these chip-related components 1020 may be combined with one another. The chip-related components 1020 may be in the form of a package including the above-mentioned chips and electronic components.

[0013] The network-related components 1030 may include, but are not limited to, Wi-Fi (e.g., IEEE 802.11 family), WiMAX (e.g., IEEE 802.16 family), IEEE 802.20, LTE (long term evolution), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPS, GPRS, CDMA, TDMA, DECT, Bluetooth, 3G, 4G, 5G, and any other wireless and wired protocols designated as such, as well as any of a number of other different wireless or wired standards and protocols. It should be understood that the network-related components 1030 may also be combined with the chip-related components 1020.

[0014] The other components 1040 include high-frequency inductors, ferrite inductors, power inductors, ferrite beads, LTCC (low temperature co-firing ceramics), EMI (electromagnetic interference) filters, MLCC (multi-layer ceramic capacitors), etc. However, the other components are not limited to these, and may also include passive elements in the form of chip components used for various other applications. It goes without saying that the other components 1040 may be combined with the chip-related components 1020 and / or the network-related components 1030.

[0015] Depending on the type of electronic device 1000, the electronic device 1000 may include other electronic components that may or may not be physically and / or electrically coupled to the main board 1010. Examples of the other electronic components include, but are not limited to, a camera module 1050, an antenna module 1060, a display 1070, and a battery 1080. These may also include, but are not limited to, an audio codec, a video codec, a power amplifier, a compass, an accelerometer, a gyroscope, a speaker, a mass storage device (e.g., a hard disk drive), a compact disk (CD), a digital versatile disk (DVD), etc. Needless to say, other electronic components used for various purposes may also be included depending on the type of electronic device 1000.

[0016] The electronic device 1000 may be a smartphone, a personal digital assistant, a digital video camera, a digital still camera, a network system, a computer, a monitor, a tablet, a laptop, a netbook, a television, a video game, a smart watch, an automobile, etc. However, the electronic device 1000 is not limited to these, and it goes without saying that the electronic device 1000 may be any other electronic device that processes data.

[0017] FIG. 2 is a perspective view schematically illustrating an example of an electronic device.

[0018] Referring to the drawings, the electronic device may be, for example, a smartphone 1100. The smartphone 1100 houses a motherboard 1110, to which various components 1120 are physically and / or electrically connected. The smartphone 1100 also houses other components, such as a camera module 1130 and / or a speaker 1140, which may or may not be physically and / or electrically connected to the motherboard 1110. Some of the components 1120 may be the above-mentioned chip-related components, such as, but not limited to, a component package 1121. The component package 1121 may be in the form of a printed circuit board on which electronic components, including active and / or passive components, are surface-mounted. Alternatively, the component package 1121 may be in the form of a printed circuit board in which active and / or passive components are embedded. It goes without saying that the electronic device is not necessarily limited to the smartphone 1100, but may be other electronic devices as described above.

[0019] printed circuit board FIG. 3 is a cross-sectional view that schematically shows an example of a printed circuit board, and FIG. 4 is an enlarged cross-sectional view that schematically shows region A of the printed circuit board of FIG.

[0020] Referring to the drawings, a printed circuit board 100A according to one example may include a first insulating layer 111, a through via 135 that penetrates at least a portion between the upper and lower surfaces of the first insulating layer 111 and has one or more gaps G1, G2 that respectively separate at least a portion of a side surface of the upper end and / or a side surface of the lower end from the first insulating layer 111, and a second insulating layer 112 that is disposed on the first insulating layer 111, covers at least a portion of the upper end and / or a lower end of the through via 135, and fills at least a portion of each of the one or more gaps G1, G2. For example, the second insulating layer 112 is disposed on the upper and lower surfaces of the first insulating layer 111, and may cover at least a portion of each of the upper end and lower end of the through via 135 and may fill at least a portion of each of the one or more first gaps G1 formed on a side surface of the upper end of the through via 135 and one or more second gaps G2 formed on a side surface of the lower end of the through via 135. The upper end of the through via 135 may include a portion of the through via 135 below the upper surface of the through via 135. The lower end of the through via 135 may include another portion of the through via 135 above the lower surface of the through via 135.

[0021] As described above, in the printed circuit board 100A according to one example, one or more gaps G1, G2, which are spaces between the first insulating layer 111 and the through via 135, are formed on the side surfaces of the upper end and / or lower end of the through via 135 that penetrates the first insulating layer 111, and at least a portion of each of these one or more gaps G1, G2 may be filled with the second insulating layer 112. Therefore, even if the first insulating layer 111 includes an inorganic material such as a glass substrate as a core layer, it may have a structure that is advantageous against thermal shock from the viewpoint of stress. Therefore, it is possible to prevent cracks from occurring due to thermal shock.

[0022] For example, when a through hole is formed in a glass substrate, and then filled with copper (Cu) fill plating to form a TGV (Through Glass Via), and an insulating layer is laminated on top of it, and then reflow is performed at room temperature up to about 260°C, comparing the compressive stresses applied to the inlet portions of the upper and lower ends of the TGV, when a gap is formed and then filled with insulating material, the compressive stress may be significantly lower than when a gap is not formed. More specifically, compared to a TGV simply filled with copper (Cu) without any gaps (Experimental Example 1), when gaps were formed on the sides of the top and bottom of a TGV filled with copper (Cu) and then filled with ABF (Ajinomoto Build-up Film) (Experimental Example 2), and when gaps were formed on the sides of the top and bottom of a TGV filled with copper (Cu) and then filled with PPG (Prepreg) (Experimental Example 3), the compressive stress was improved to a level of approximately 1:0.02:0.11 (Experimental Example 1:Experimental Example 2:Experimental Example 3), respectively. Therefore, the structure in which gaps are formed and then filled with insulating material can suppress cracks caused by stress due to thermal shock.

[0023] Meanwhile, the upper surface and / or the lower surface of the first insulating layer 111 may have a step with respect to the upper surface and / or the lower surface of the through via 135, respectively. For example, the upper surface of the first insulating layer 111 may be disposed above the upper surface of the through via 135, and the lower surface of the first insulating layer 111 may be disposed below the lower surface of the through via 135. For example, the upper surface and the lower surface of the through via 135 may be recessed inside the through via 135 with respect to the upper surface and the lower surface of the first insulating layer 111, respectively. At least a portion of this recessed space may also be filled with the second insulating layer 112. Therefore, a structure more advantageous in terms of thermal shock may be obtained. Furthermore, the reliability of the through via 135 may be further improved.

[0024] The first insulating layer 111 may include an inorganic insulating material. For example, the first insulating layer 111 may include a glass substrate. For example, the first insulating layer 111 may include plate glass. However, the first insulating layer 111 is not limited thereto, and other materials may be used as long as they can form the one or more gaps G1 and G2. In contrast, the second insulating layer 112 may include an organic insulating material. Filling the one or more gaps G1 and G2 with such an organic insulating material may be more advantageous in terms of stress. The second insulating layer 112 may include, but is not limited to, PPG (Prepreg) or ABF (Ajinomoto Build-up Film), and may include other organic insulating materials.

[0025] Meanwhile, the through via 135 may be a metal via 135 filling at least a portion of a through hole h penetrating between the upper and lower surfaces of the first insulating layer 111. One or more first gaps G1 may be formed between the side of the upper end of the metal via 135 and the wall surface of the through hole h, and one or more second gaps G2 may be formed between the side of the lower end of the metal via 135 and the wall surface of the through hole h. The metal via 135 may include a seed layer m1 disposed on a portion of the wall surface of the through hole h and a metal layer m2 filling at least a portion of the through hole h. At least a portion of the one or more first and second gaps G1, G2 may be disposed on another portion of the wall surface of the through hole h, for example, between a portion of the wall surface of the through hole h where the seed layer m1 is not formed and the side surface of the metal layer m2. In some regions where the one or more first and second gaps G1, G2 are formed, a portion of the seed layer m1 may remain on the side surface of the metal layer m2, separated from the wall surface of the through hole h. In this way, the metal via 135 can be formed by forming a seed layer in the through hole h and then performing fill plating. Then, when a portion of the seed layer and fill plating layer is removed by a polishing process, one or more first and second gaps G1 and G2 can be formed. At this time, the above-mentioned recess space, for example, a dishing or dimple, can also be formed. Based on this structure, a structure advantageous in terms of thermal stress can be realized.

[0026] On the other hand, the through via 135 may have a maximum width at each of the upper and lower ends in cross section that is wider than the minimum width at the center between the upper and lower ends. For example, a through hole h at least partially filled with the through via 135 may have a roughly hourglass shape. Therefore, the through via 135 may have a structure that roughly corresponds to this. Such a structure may be more advantageous in terms of stress distribution.

[0027] Furthermore, the printed circuit board 100A according to an example may further include a frame 118 having a through hole H. At least a portion of the first insulating layer 111 may be disposed within the through hole H of the frame 118. The second insulating layer 112 may cover at least a portion of the frame 118 and fill at least a portion of the through hole H. The frame 118 may be used as a jig during the process, which may be more advantageous in controlling warpage during the process. Furthermore, a large-area frame 118 may have multiple through holes H formed therein, which may allow multiple printed circuit boards 100A to be manufactured through the same process and then cut separately, thereby increasing productivity.

[0028] Meanwhile, the printed circuit board 100A according to an example may further include a first wiring layer 121 disposed on the upper surface of the second insulating layer 112, a second wiring layer 122 disposed on the lower surface of the second insulating layer 112, a first connection via 131 penetrating at least a portion of the second insulating layer 112 and connecting at least a portion of the first wiring layer 121 to an upper surface of a through via 135, and a second connection via 132 penetrating at least another portion of the second insulating layer 112 and connecting at least a portion of the second wiring layer 122 to a lower surface of the through via 135. The first and second connection vias 131 and 132 may be directly connected to the upper and lower surfaces of the through via 135, respectively. The first and second connection vias 131 and 132 may have tapered shapes in opposite directions in cross section. With this structure, the second insulating layer 112 can more easily cover the upper and / or lower ends of the through via 135 and fill one or more gaps G1 and G2. Therefore, a structure that is advantageous for a stress structure can be more easily realized.

[0029] Furthermore, the printed circuit board 100A according to one example includes a third insulating layer 113 disposed on the upper surface of the second insulating layer 112 and covering at least a portion of the first wiring layer 121, a fourth insulating layer 114 disposed on the lower surface of the second insulating layer 112 and covering at least a portion of the second wiring layer 122, a third wiring layer 123 disposed on the upper surface of the third insulating layer 113, a fourth wiring layer 124 disposed on the lower surface of the fourth insulating layer 114, and a fourth wiring layer 124 that penetrates at least a portion of the third insulating layer 113 and interconnects at least a portion of the first and third wiring layers 121 and 123. The printed circuit board 100A may further include a third connection via 133 connecting the second and fourth wiring layers 122 and 124 to each other, a fourth connection via 134 penetrating at least a portion of the fourth insulating layer 114 and connecting at least a portion of the second and fourth wiring layers 122 and 124 to each other, a first resist layer 115 disposed on the upper surface of the third insulating layer 113 and having a first opening o1 exposing at least a portion of the third wiring layer 123, and a second resist layer 116 disposed on the lower surface of the fourth insulating layer 114 and having a second opening o2 exposing at least a portion of the fourth wiring layer 124. The third and fourth connection vias 133 and 134 may have tapered shapes in opposite directions in cross section. For example, the printed circuit board 100A according to one example may have a multilayer printed circuit board structure. Therefore, it may be used as an FCB (Flip-Chip Board), a BGA (Ball Grid Array), an interposer substrate, a package substrate, etc. However, the present invention is not limited thereto and may be applied to various other types of substrates.

[0030] The components of the printed circuit board 100A according to an example will be described in more detail below with reference to the drawings.

[0031] The first insulating layer 111 may include a glass substrate. The glass substrate may include glass, which is an amorphous solid. Examples of glass include pure silicon dioxide (approximately 100% SiO), soda-lime glass, borosilicate glass, and aluminosilicate glass. However, without limitation, alternative glass materials, such as fluoride glass, phosphate glass, and chalcogenide glass, may also be used. Other additives may be added to form glass with specific physical properties. Such additives may include calcium carbonate (e.g., lime) and sodium carbonate (e.g., soda), as well as magnesium, calcium, manganese, aluminum, lead, boron, iron, chromium, potassium, sulfur, and antimony, as well as carbonates and / or oxides of these and other elements. The glass substrate may be distinguished from organic insulating materials, such as glass fiber (glass cloth, glass fabric), such as copper clad laminate (CCL) and prepreg (PPG). For example, the first insulating layer 111 may be made of a glass substrate. However, the first insulating layer 111 is not limited to this material, and other materials may be used as long as they are capable of forming one or more gaps G1 and G2. For example, a silicon substrate or a ceramic substrate may also be used as the material of the first insulating layer 111.

[0032] The second to fourth insulating layers 112, 113, and 114 and the first and second resist layers 115 and 116 may each include an organic insulating material. The organic insulating material may include a thermosetting resin such as an epoxy resin, a thermoplastic resin such as a polyimide, or a resin together with an inorganic filler, an organic filler, and / or glass fiber (glass fiber, glass cloth, or glass fabric). For example, the organic insulating material may be, but is not limited to, PPG (Prepreg), ABF (Ajinomoto Build-up Film), PID (Photo Imageable Dielectric), or SR (Solder Resist). If necessary, the second to fourth insulating layers 112, 113, and 114 and the first and second resist layers 115 and 116 may each be composed of multiple layers. The first and second resist layers 115 and 116 may have first and second openings o1 and o2, respectively, and the first and second openings o1 and o2 may each be multiple. The pad patterns of the third and fourth wiring layers 123 and 124 exposed through the first and second openings o1 and o2 may be in the form of SMD (Solder Mask Defined) and / or NSMD (Non Solder Mask Defined).

[0033] The frame 118 may include various materials. For example, it may include an organic insulating material such as CCL (Copper Clad Laminate). Alternatively, it may include an inorganic insulating material such as silicon or ceramic. Alternatively, it may include a metal such as copper (Cu), but is not limited thereto. The frame 118 may have a through portion H. The through portion H may penetrate between the upper and lower surfaces of the frame 118. The through portion H may have a shape corresponding to the first insulating layer 111. If necessary, the through portion H may be formed in the form of a blind cavity. The through portion H may continuously surround the side surface of the first insulating layer 111. For example, the through portion H may have a substantially rectangular shape in a plan view. If necessary, the frame 118 may be composed of multiple units, and the number of multiple units may not be particularly limited.

[0034] Each of the first to fourth wiring layers 121, 122, 123, and 124 may include a metal. The metal may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof. Preferably, the metal may include copper (Cu), but is not limited to this. Each of the first to fourth wiring layers 121, 122, 123, and 124 may perform various functions according to the design. For example, they may include signal patterns, power patterns, ground patterns, etc. These patterns may each have various forms, such as lines, planes, and pads. Each of the first to fourth wiring layers 121, 122, 123, and 124 may include a seed layer and a plating layer. The seed layer may be formed by electroless plating (or chemical copper), or may be formed by a sputtering process if necessary. Alternatively, both may be used. The plating layer may be formed by electrolytic plating (or electrolytic copper). When the second to fourth insulating layers 112, 113, 114 are each made up of a plurality of layers, the first to fourth wiring layers 121, 122, 123, 124 may be made up of a plurality of layers corresponding to this. The first to fourth wiring layers 121, 122, 123, 124 may protrude above the second to fourth insulating layers 122, 123, 124, respectively, or may be embedded in the second to fourth insulating layers 112, 113, 114, respectively.

[0035] The first to fourth connection vias 131, 132, 133, and 134 may each include a metal. The metal may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof. Preferably, the metal may include copper (Cu), but is not limited to this. The first to fourth connection vias 131, 132, 133, and 134 may each perform various functions depending on the design. For example, they may include signal vias, power vias, and ground vias. The first to fourth connection vias 131, 132, 133, and 134 may each include a filled via in which a via hole is filled with metal, or a conformal via in which a metal is disposed along the wall surface of a via hole. The first to fourth connection vias 131, 132, 133, and 134 may each have a tapered shape in cross section. For example, the first and third connection vias 131, 133 may each have a wider upper end width than the lower end width on the cross section, and the second and fourth connection vias 132, 134 may each have a wider lower end width than the upper end width on the cross section. The first to fourth connection vias 131, 132, 133, 134 may similarly include the seed layer and plating layer included in the first to fourth wiring layers 121, 122, 123, 124, respectively. There may be a plurality of first to fourth connection vias 131, 132, 133, 134, respectively.

[0036] The through via 135 may include a metal. The metal may include, but is not limited to, copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof. Preferably, the metal may include, but is not limited to, copper (Cu). The through via 135 may include a metal via 135 filling at least a portion of the through hole h. The metal via 135 may perform various functions depending on the design. For example, the metal via 135 may include a signal via, a power via, a ground via, etc. One or more first gaps G1 may be formed between the side of the upper end of the metal via 135 and the wall surface of the through hole h, and one or more second gaps G2 may be formed between the side of the lower end of the metal via 135 and the wall surface of the through hole h. The metal via 135 may include a seed layer m1 disposed on a portion of the wall surface of the through hole h and a metal layer m2 filling at least a portion of the through hole h. One or more first and second gap portions G1, G2 may be disposed between another portion of the through hole h, for example, a portion where the seed layer m1 is not formed, and a side surface of the metal layer m2. For example, the metal via 135 may be formed by forming a seed layer in the through hole h and then performing fill plating. Then, when a portion of the seed layer and the fill plating layer is removed by a polishing process, one or more first and second gap portions G1, G2 may be formed. In addition, the above-mentioned recess space, for example, a dishing or a dimple, may be formed. The number of metal vias 135 may be multiple.

[0037] 5a and 5b are plan views each schematically showing various examples of a cross section taken along line II' of region A of the printed circuit board in FIG.

[0038] Referring to FIG. 5a, the one or more first gaps G1 may be plural. For example, the one or more first gaps G1 may include a first gap G1-1 and a first gap G1-2, which may be spaced apart. The first and second gaps G1-1 and G1-2 may have different sizes, e.g., different widths and depths. The first gap G1 may include more gaps than those shown in the figure. The above description can be applied substantially similarly to the second gap G2. In this way, by forming gaps of various sizes at various positions and filling them with insulating material, design flexibility can be increased and a structure advantageous for thermal shock can be achieved.

[0039] 5b, one or more first gaps G1 may have a single continuous structure. For example, one or more first gaps G1 may include a single first-third gap G1-3 that continuously surrounds the side of the upper end of the through via 135. The above description can be applied substantially similarly to the second gap G2. In this way, by forming the gaps wider and more continuously, a structure that is more advantageous in terms of thermal shock can be realized.

[0040] 6a to 6i are cross-sectional views schematically illustrating an example of a process for manufacturing the printed circuit board of FIG.

[0041] Referring to FIG. 6a, a first insulating layer 111 may be prepared. As described above, the first insulating layer 111 may be a glass substrate such as a glass plate, but is not limited to this. Next, through holes h may be formed through the first insulating layer 111. Depending on the material of the first insulating layer 111, the through holes h may be formed by a chemical method or a mechanical method. For example, etching, blasting, laser, plasma, etc. may be used.

[0042] 6b, a seed layer m1 can be formed on the wall surface of the through hole h and on the upper and lower surfaces of the first insulating layer 111. The seed layer m1 can be formed by electroless plating (or chemical copper plating), but is not limited to this. If necessary, the seed layer m1 may be formed in multiple layers.

[0043] Referring to FIG. 6c, a metal layer m2 may be formed on the seed layer m1. The metal layer m2 may be formed by fill plating. Fill plating may be, but is not limited to, electrolytic plating (or electroplating). The metal layer m2 may fill the through hole h and may also be formed on the upper and lower surfaces of the first insulating layer 111.

[0044] 6d, at least a portion of the seed layer m1 and the metal layer m2 disposed on the upper and lower surfaces of the first insulating layer 111 may be removed. Furthermore, a through via 135 and one or more first and second gap portions G1 and G2 may be formed. For example, the seed layer m1 and the metal layer m2 formed on the surface of the first insulating layer 111 may be removed using a polishing process such as CMP (Chemical Mechanical Planarization) to form the through via 135. At this time, the through via 135 may be removed more than the first insulating layer 111 at the entrance portions of the upper and / or lower ends of the through via 135, thereby forming one or more first and / or second gap portions G1 and G2. Furthermore, the upper and / or lower surfaces of the through via 135 may be recessed inward as a whole, thereby forming dishing or dimples.

[0045] 6e, a frame 118 having a through portion H can be prepared. In addition, a first insulating layer 111 having a through via 135 formed therein can be disposed in the through portion H of the frame 118 using tape 119. The frame 118 can be used as a jig. There can be a plurality of through portions H, and a first insulating layer 111 having a through via 135 formed therein can be disposed in each of the through portions H.

[0046] 6f, a second insulating layer 112-1 may be laminated on the frame 118 and the first insulating layer 111. At this time, one or more first gaps G1 may be filled with the second insulating layer 112-1.

[0047] 6g, the tape 119 can be removed. Also, the second insulating layer 112-2 can be laminated below the frame 118 and the first insulating layer 111. At this time, one or more second gaps G2 can be filled with the second insulating layer 112-2. Meanwhile, after hardening, the second insulating layer 112 can be formed by integrating the second insulating layer 112 with the second insulating layer 112-1 and the second insulating layer 112-2.

[0048] 6h, first and second wiring layers 121, 122 and first and second connection vias 131, 132 can be formed in the second insulating layer 112. For example, after via holes are formed at required positions in the second insulating layer 112 using a laser drill or the like, circuit processes such as tenting (TT), AP (Additive Process), SAP (Semi Additive Process), MSAP (Modified Semi Additive Process), etc. can be performed to form the first and second wiring layers 121, 122 and the first and second connection vias 131, 132.

[0049] Referring to FIG. 6i, a build-up process can be further performed. For example, third and fourth insulating layers 113 and 114 can be laminated on the upper and lower sides of the second insulating layer 112, respectively. Furthermore, third and fourth wiring layers 123 and 124 and third and fourth connection vias 133 and 134 can be formed in the third and fourth insulating layers 113 and 114, respectively, using the via hole forming process and circuit process described above. Next, first and second resist layers 115 and 116 can be formed on the third and fourth insulating layers 113 and 114, respectively, and first and second openings o1 and o2 can be formed using a photolithography process, laser processing, or the like. Through this series of processes, the printed circuit board 100A according to one example can be manufactured.

[0050] The rest of the description may be substantially the same as that of the printed circuit board 100A according to the above-described example, and therefore a duplicated description will be omitted.

[0051] FIG. 7 is a cross-sectional view schematically showing another example of a printed circuit board.

[0052] Referring to the drawings, another example of a printed circuit board 100B may further include, in the printed circuit board 100A according to the above-described example, a first electrical connecting metal 151 disposed on the first opening o1 of the first resist layer 115 and connected to at least a portion of the exposed third wiring layer 123, and a second electrical connecting metal 152 disposed on the second opening o2 of the second resist layer 116 and connected to at least a portion of the exposed fourth wiring layer 124.

[0053] The first and second electrical connection metals 151 and 152 can connect the printed circuit board 100B to other substrates or electronic components. The first and second electrical connection metals 151 and 152 may each be formed of a conductive material, such as solder, but this is merely an example and the material is not limited thereto. The first and second electrical connection metals 151 and 152 may each be a land, a ball, a pin, or the like. The first and second electrical connection metals 151 and 152 may each be formed in a multi-layer or single layer. If formed in a multi-layer, they may include copper pillars and solder formed on the copper pillars. If formed in a single layer, they may include, but are not limited to, tin-silver solder or copper. The first and second electrical connection metals 151 and 152 may each be a plurality of metals.

[0054] The rest of the description may be substantially the same as that of the printed circuit board 100A according to the above-described example, and therefore a duplicated description will be omitted.

[0055] FIG. 8 is a cross-sectional view schematically showing yet another example of a printed circuit board.

[0056] Referring to the drawings, a printed circuit board 100C according to another example may further include a first under bump metal 161 arranged between at least a portion of the exposed third wiring layer 123 and the first electrical connecting metal 151, and a second under bump metal 162 arranged between at least a portion of the exposed fourth wiring layer 124 and the second electrical connecting metal 152, in the printed circuit board 100B according to the other example described above.

[0057] The first and second under-bump metals 161 and 162 can improve the connection reliability of the first and second electrical connection metals 151 and 152. The first and second under-bump metals 161 and 162 can each include a metal. The metal can include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof. Preferably, the metal can include copper (Cu), but is not limited to this. The first and second under-bump metals 161 and 162 can each include a seed layer and a plating layer. The seed layer can be formed by electroless plating (or chemical copper), or can be formed by a sputtering process if necessary. Alternatively, both can be used. The plating layer can be formed by electrolytic plating (or electrolytic copper). The first and second under-bump metals 161 and 162 can each include a via portion and a pad portion, but are not limited thereto, and each can also include only a via portion. For example, the first and second under-bump metals 161 and 162 may have a structure in which vias protrude above the first and second resist layers 115 and 116, respectively, without pads. The first and second under-bump metals 161 and 162 may each be plural.

[0058] The rest of the description may be substantially the same as that of the printed circuit board 100A according to the example and the printed circuit board 100B according to the other example, and therefore a duplicated description will be omitted.

[0059] In the present invention, the term "cover" can refer to not only completely covering but also at least partially covering, and can refer to not only directly covering but also indirectly covering. Furthermore, the term "fill" can refer not only to completely filling but also to at least partially filling, and can also refer to almost completely filling. For example, it can refer to the presence of some voids or gaps. Furthermore, the term "surround" can refer not only to completely surrounding but also to partially surrounding and almost surrounding. Furthermore, the term "expose" can refer not only to completely exposing but also to partially exposing, and "exposing" can refer to exposing a structure from being buried. For example, exposing a pad through an opening means exposing the pad from the resist layer, and a surface treatment layer or the like can be further disposed on the exposed pad.

[0060] In the present invention, "disposed in a through-hole or a penetrating portion" refers not only to a case where an object is completely disposed in the through-hole or a penetrating portion, but also to a case where a part of the object protrudes upward or downward in a cross section. For example, a case where the object is disposed in the through-hole or a penetrating portion in a plan view can be judged in a broader sense.

[0061] In the present invention, "substantially" can be determined taking into account process errors, positional deviations, measurement errors, and the like that occur in the manufacturing process. For example, "substantially perpendicular" can include not only a completely perpendicular case but also a nearly perpendicular case. Furthermore, "substantially coplanar" can include not only a completely coplanar case but also a nearly coplanar case.

[0062] In the present invention, the term "same insulating material" does not only mean the completely same insulating material, but also means the same type of insulating material. Therefore, although the compositions of the insulating materials are substantially the same, the specific composition ratios may differ slightly.

[0063] In the present invention, the term "cross section" can refer to the cross-sectional shape of an object cut vertically or the cross-sectional shape of an object when viewed from the side, and the term "planar" can refer to the planar shape of an object cut horizontally or the planar shape of an object when viewed from the top or bottom.

[0064] In the present invention, for convenience, terms such as "lower side, bottom part, lower surface" are used to mean the downward direction based on the cross section of the drawing, and terms such as "upper side, top part, upper surface" are used to mean the opposite direction. However, these are definitions of directions for convenience of explanation, and it goes without saying that the scope of the claims is not particularly limited by such directional descriptions, and the concepts of up / down can be changed at any time.

[0065] In the present invention, the term "connected" refers not only to direct connection but also to indirect connection via an adhesive layer or the like. Furthermore, the term "electrically connected" refers to both physical connection and non-physical connection. Furthermore, expressions such as "first" and "second" are used to distinguish one component from another and do not limit the order and / or importance of the components. In some cases, a first component may be called a second component, and similarly, a second component may be called a first component, without departing from the scope of the right.

[0066] In the present invention, "thickness, width, length, depth, line width, spacing, pitch, separation distance, surface roughness," etc. can be measured using a scanning microscope, optical microscope, etc., based on a cross section obtained by polishing or cutting a printed circuit board. The cut section can be a vertical or horizontal section, and each value can be measured based on the required cut section. For example, the width of the upper and / or lower ends of a via can be measured on a cross section cut along the central axis of the via. In this case, if the value is not constant, the value can be determined by averaging values ​​measured at any five points.

[0067] The term "one example" used in the present invention does not mean the same embodiment as another example, but is provided to emphasize and describe each example's unique features. However, the example presented above does not exclude the example being realized in combination with features of another example. For example, even if a feature described in a particular example is not described in another example, it can be understood as a description related to the other example unless there is a description in the other example that contradicts or contradicts that feature.

[0068] The terms used in the present invention are merely used to describe an example and are not intended to limit the present invention. In this case, singular expressions include plural expressions unless the context clearly indicates a different meaning. [Explanation of symbols]

[0069] 1000:Electronic equipment 1010: Main board 1020: Chip related parts 1030: Network related parts 1040:Other parts 1050: Camera 1060: Antenna 1070: Display 1080: Battery 1090: Signal line 1100: Smartphone 1110: Motherboard 1120: Parts 1121: Parts package 1130: Camera module 1140:Speaker 100A, 100B, 100C: Printed circuit board 111: Insulating layer (glass substrate) 112, 113, 114: Insulating layer (build-up layer) 115, 116: resist layer 118: Frame 119: Tape 121, 122, 123, 124: Wiring layer 131, 132, 133, 134: Connection vias 135:Through via (metallic via) 151, 152: Electrically connected metal 161, 162: Under bump metal H: Penetration part h:Through hole G1, G2, G1-1, G1-2, G1-3: Gap area m1: seed layer m2: metal layer o1, o2: opening

Claims

1. a frame having a penetration; a glass substrate at least a portion of which is disposed within the through-hole; a first insulating layer including a first insulating portion covering at least a portion of each of an upper surface of the frame and an upper surface of the glass substrate, a second insulating portion covering at least a portion of each of a lower surface of the frame and a lower surface of the glass substrate, and a third insulating portion filling at least a portion of the space between the frame and the glass substrate in the through-hole; a through via that penetrates at least a portion between the upper surface and the lower surface of the glass substrate; a first connection via that penetrates at least a portion of the first insulating portion and is directly connected to an upper surface of the through via; a second connection via that penetrates at least a portion of the second insulating portion and is directly connected to a lower surface of the through via.

2. The printed circuit board according to claim 1 , wherein the first to third insulating portions are integrated with each other without any boundaries.

3. The printed circuit board of claim 1 , wherein the third insulating portion has an interface between an upper surface and a lower surface of the frame.

4. The printed circuit board of claim 1 , wherein the thickness between the upper and lower surfaces of the glass substrate is greater than the thickness between the upper and lower surfaces of the through via.

5. an upper surface of the glass substrate is disposed above an upper surface of the through via; The printed circuit board according to claim 4 , wherein a lower surface of the glass substrate is located lower than a lower surface of the through via.

6. The through via may further include one or more gaps separating at least a portion of a side surface of an upper end or a side surface of a lower end of the through via from the glass substrate, The printed circuit board of claim 4 , wherein the first insulating layer fills at least a portion of each of the one or more gaps.

7. The glass substrate further includes a through hole extending between the upper surface and the lower surface thereof, the through via includes a seed layer disposed on a wall surface of the through hole, and a metal layer disposed on the seed layer and filling at least a portion of the through hole; The printed circuit board of claim 1 , wherein the seed layer comprises multiple layers.

8. The printed circuit board of claim 7, wherein the plurality of layers includes an electroless plating layer.

9. The seed layer includes an electroless plating layer, The printed circuit board of claim 7 , wherein the metal layer comprises an electrolytically plated layer.

10. the through via has a substantially hourglass shape in cross section; the first connection via has a substantially tapered side surface in which the width of an upper end is wider than the width of a lower end in cross section; The printed circuit board according to claim 1 , wherein the second connection via has a substantially tapered side surface with a lower end wider than an upper end in cross section.

11. a first wiring layer disposed on an upper surface of the first insulating portion and directly connected to the first connection via; The printed circuit board according to claim 1 , further comprising: a second wiring layer disposed on the lower surface of the second insulating portion and directly connected to the second connection via.

12. 12. The printed circuit board of claim 11, wherein there is no wiring layer in direct contact with the top or bottom surface of the glass substrate.

13. a second insulating layer disposed on an upper surface of the first insulating portion and covering at least a portion of the first wiring layer; a third insulating layer disposed on a lower surface of the second insulating portion and covering at least a portion of the second wiring layer; a third wiring layer disposed on an upper surface of the second insulating layer; a fourth wiring layer disposed on the lower surface of the third insulating layer; a third connection via that penetrates at least a portion of the second insulating layer and connects at least a portion of the first and third wiring layers to each other; a fourth connection via that penetrates at least a portion of the third insulating layer and connects at least a portion of the second and fourth wiring layers to each other, the third connection via has a substantially tapered side surface in which the width of an upper end is wider than the width of a lower end in cross section; The printed circuit board according to claim 11 , wherein the fourth connection via has a substantially tapered side surface with a lower end wider than an upper end in cross section.

14. a first solder resist layer disposed on an upper surface of the second insulating layer and having a first opening exposing at least a portion of the third wiring layer; The printed circuit board according to claim 13 , further comprising: a second solder resist layer disposed on the lower surface of the third insulating layer and having a second opening that exposes at least a portion of the fourth wiring layer.

15. the frame is embedded outside the first insulating layer; The printed circuit board of claim 1 , wherein an outer surface of the frame is exposed from an outer surface of the first insulating layer.

16. 16. The printed circuit board of claim 15, wherein the exposed outer surface of the frame and the outer surface of the first insulating layer are substantially coplanar with one another.

17. forming a through via in a glass substrate, the through via penetrating at least a portion of the glass substrate between an upper surface and a lower surface; disposing at least a portion of the glass substrate within a frame having a through-hole; forming a first insulating layer including a first insulating portion covering at least a portion of each of an upper surface of the frame and an upper surface of the glass substrate, a second insulating portion covering at least a portion of each of a lower surface of the frame and an lower surface of the glass substrate, and a third insulating portion filling at least a portion of a space between the frame and the glass substrate in the through-hole; forming a first connection via that penetrates at least a portion of the first insulating portion and is directly connected to an upper surface of the through via; and forming a second connection via that penetrates at least a portion of the second insulating portion and is directly connected to a lower surface of the through via.

18. The step of forming the through via comprises: forming a through hole penetrating between an upper surface and a lower surface of the glass substrate; forming a seed layer on the wall surfaces of the through-holes and on the upper and lower surfaces of the glass substrate; forming a metal layer on the seed layer and filling at least a portion of the through hole with the metal layer; and removing at least a portion of each of the seed layer and the metal layer disposed on an upper surface and a lower surface of the glass substrate; The method of claim 17 , wherein the seed layer comprises multiple layers.

19. removing at least a portion of each of the seed layer and the metal layer, an upper surface of the metal layer is formed below an upper surface of the glass substrate; The method for manufacturing a printed circuit board according to claim 18 , wherein the lower surface of the metal layer is formed above the lower surface of the glass substrate.

20. removing at least a portion of each of the seed layer and the metal layer, one or more gaps are formed to separate at least a portion of one or more of a side surface of an upper end portion and a side surface of a lower end portion of the metal layer from the glass substrate within the through hole; In the step of forming the first insulating layer, The method of claim 18 , wherein the first insulating layer fills at least a portion of each of the one or more gaps.

21. The step of disposing at least a portion of the glass substrate in the through-hole includes: attaching tape to the underside of the frame; and The method for manufacturing a printed circuit board according to claim 17, further comprising the step of attaching the glass substrate to an upper surface of the tape exposed through the through-hole.

22. The step of forming the first insulating layer includes: laminating a first insulating layer on the frame and the glass substrate; removing the tape; and 22. The method of claim 21, further comprising laminating a first insulating layer and a second insulating layer on the underside of the frame and the glass substrate.

23. In the step of forming the first insulating layer, The method of claim 22, wherein the first insulating layer including the first to third insulating portions is formed by integrating the first-1 and first-2 insulating layers with each other.

24. In the step of forming the first insulating layer, 23. The method for manufacturing a printed circuit board according to claim 22, wherein an interface between the first-first and first-second insulating layers is formed between the upper and lower surfaces of the frame.

25. forming a first wiring layer on an upper surface of the first insulating layer, the first wiring layer being directly connected to the first connection via; The method of claim 17 , further comprising: forming a second wiring layer on the lower surface of the second insulating layer, the second wiring layer being directly connected to the second connection via.

26. The method for manufacturing a printed circuit board according to claim 25, wherein no wiring layer is formed in direct contact with the upper or lower surface of the glass substrate.

27. forming a second insulating layer on an upper surface of the first insulating portion to cover at least a portion of the first wiring layer; forming a third insulating layer on a lower surface of the second insulating portion to cover at least a portion of the second wiring layer; forming a third connection via that penetrates at least a portion of the second insulating layer and is connected to the first wiring layer; forming a fourth connection via that penetrates at least a portion of the third insulating layer and is connected to the second wiring layer; forming a third wiring layer connected to the third connection via on an upper surface of the second insulating layer; The method of claim 25, further comprising forming a fourth wiring layer connected to the fourth connection via on the lower surface of the third insulating layer.

28. forming a first solder resist layer on an upper surface of the second insulating layer, the first solder resist layer having a first opening exposing at least a portion of the third wiring layer; 28. The method of claim 27, further comprising: forming a second solder resist layer on the lower surface of the third insulating layer, the second solder resist layer having a second opening that exposes at least a portion of the fourth wiring layer.

29. the frame is embedded outside the first insulating layer; The method for manufacturing a printed circuit board according to claim 17 , wherein the outer surface of the frame is exposed from the outer surface of the first insulating layer.

30. 30. The method of claim 29, wherein the exposed outer surface of the frame and the outer surface of the first insulating layer are substantially coplanar with one another.

31. A glass substrate; an insulating layer covering at least a portion of each of the upper and lower surfaces of the glass substrate; a through hole penetrating between the upper surface and the lower surface of the glass substrate; a through via disposed within the through hole; the through via includes a plurality of seed layers disposed on a wall surface of the through hole, and a metal layer disposed on the plurality of seed layers and filling at least a portion of the through hole; the plurality of seed layers include electroless plating layers; The printed circuit board, wherein the metal layer includes an electrolytic plating layer.

32. A first connection via that penetrates at least a portion of the insulating layer on the upper surface of the glass substrate and is directly connected to an upper surface of the through via; 32. The printed circuit board of claim 31, further comprising: a second connection via that penetrates at least a portion of the insulating layer on the lower surface of the glass substrate and is directly connected to a lower surface of the through via.

33. A first wiring layer disposed on an upper surface of the insulating layer and directly connected to the first connection via; The printed circuit board of claim 32 , further comprising: a second wiring layer disposed on the lower surface of the insulating layer and directly connected to the second connection via.

34. The through via has an upper surface recessed below an upper surface of the glass substrate; a lower surface of the through via is recessed below a lower surface of the glass substrate; 32. The printed circuit board of claim 31, wherein the insulating layer fills at least a portion of the through hole on top and bottom surfaces of the through via, respectively.

35. A first gap portion that separates at least a portion of a side surface of the upper end of the through via from the glass substrate; a second gap portion that separates at least a portion of a side surface of the lower end of the through via from the glass substrate, 35. The printed circuit board of claim 34, wherein the insulating layer fills at least a portion of each of the first and second gaps.

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