Semiconductor device

Abstract

To provide a semiconductor device in which a reverse recovery characteristic of a body diode can be improved.SOLUTION: An SJ-MOSFET includes a parallel pn layer 2 in which a drift layer includes an n-type column region 3 and a p-type column region 4. In an active region 21 of a semiconductor substrate 30, a plurality of MOS cells 9 are provided adjacent to each other by holding some cells of SBD 50 by Schottky junction between a conductive film 52 and the n-type column region 3. The conductive film 52 is selectively provided between a source electrode 14 and the semiconductor substrate 30. At a depth position right below a p-type base region 5 inside the parallel pn layer 2 across the entire range of the active region 21, a low carrier lifetime region 41 is provided. At a border between the active region 21 and an edge terminal region 22 and a part right below an outer periphery of a gate pad 15, across the entire range in the depth direction inside the parallel pn layer 2, a low carrier lifetime region 42 is provided.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device. [Background technology]

[0002] Conventionally, the drift layer is - In a normal MOSFET configured only with a type region, or in an SJ-MOSFET with a super junction (SJ) structure in which the drift layer is a parallel pn layer of an n-type column region and a p-type column region, there are known structures that aim to reduce the size and improve the reverse recovery characteristics by incorporating a Schottky barrier diode (SBD) in the same semiconductor substrate as the MOSFET or by locally shortening the carrier lifetime in the semiconductor substrate (see, for example, Patent Documents 1 to 5 listed below). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2022-164914 [Patent Document 2] Japanese Patent Publication No. 2021-027138 [Patent Document 3] Patent No. 6732359 [Patent Document 4] Japanese Patent Application Laid-Open No. 2009-054961 [Patent Document 5] Japanese Patent Application Laid-Open No. 2015-018913 Summary of the Invention [Problem to be solved by the invention]

[0004] However, in conventional SJ-MOSFETs, the reverse recovery characteristics of the parasitic pn junction diode (body diode) become hard recovery, which adversely affects the switching characteristics of the SJ-MOSFET and the operation of peripheral components electrically connected to the SJ-MOSFET.

[0005] SUMMARY OF THE INVENTION In order to solve the above-mentioned problems associated with the prior art, an object of the present invention is to provide a semiconductor device capable of improving the reverse recovery characteristics of the body diode. [Means for solving the problem]

[0006] In order to solve the above-mentioned problems and achieve the object of the present invention, a semiconductor device according to the present invention has the following features: A semiconductor substrate is provided with an active region and a termination region surrounding the periphery of the active region. A parallel pn layer is provided within the semiconductor substrate in the active region, in which first conductivity type column regions and second conductivity type column regions are alternately and repeatedly arranged adjacent to each other in a first direction parallel to the front surface of the semiconductor substrate. A first semiconductor region of a second conductivity type is selectively provided within the semiconductor substrate in contact with the parallel pn layer. A second semiconductor region of a first conductivity type is selectively provided on the front surface of the semiconductor substrate in contact with the first semiconductor region. A gate insulating film is selectively provided on the front surface of the semiconductor substrate in the active region.

[0007] A gate electrode is provided in the active region at a position of the gate insulating film facing the semiconductor substrate. A first electrode is provided on the front surface of the semiconductor substrate and in contact with the second semiconductor region. A second electrode is provided on the back surface of the semiconductor substrate. A conductive film is selectively provided between the front surface of the semiconductor substrate and the first electrode in contact with the first electrode and the first conductivity type column region. A Schottky barrier diode is provided by a Schottky junction between the conductive film and the first conductivity type column region. A first low carrier lifetime region, into which a first carrier lifetime killer is introduced, is provided within the parallel pn layer throughout the active region at a depth directly below the first semiconductor region.

[0008] According to the above-described invention, it is possible to make the change in reverse recovery current of the parasitic pn junction diode (body diode) formed inside the semiconductor substrate by the insulated gate structure more gradual, and also to make the effective (apparent) reverse recovery current of the body diode smaller. [Effects of the Invention]

[0009] The semiconductor device according to the present invention has the effect of improving the reverse recovery characteristics of the body diode. [Brief explanation of the drawings]

[0010] [Figure 1] 1 is a plan view showing a layout of the semiconductor device according to the first embodiment as viewed from the front surface side of the semiconductor substrate. [Figure 2] 2 is an enlarged plan view showing a part of the active region of FIG. 1. FIG. [Figure 3] 3 is a cross-sectional view showing a cross-sectional structure taken along line AA' in FIG. 2. [Figure 4] 10 is an enlarged plan view showing a layout of a part of an active region of a semiconductor device according to a second embodiment, as viewed from the front surface side of a semiconductor substrate. FIG. [Figure 5] 5 is a cross-sectional view showing the cross-sectional structure taken along the line BB' in FIG. 4. [Figure 6] 5 is a cross-sectional view showing a cross-sectional structure taken along line CC' in FIG. 4. [Figure 7] FIG. 11 is a plan view showing a layout of a part of an active region of a semiconductor device according to a third embodiment, as viewed from the front surface side of a semiconductor substrate. [Figure 8] 8 is a cross-sectional view showing a cross-sectional structure taken along the line D1-D1' in FIG. 7. [Figure 9] 8 is a cross-sectional view showing the cross-sectional structure taken along the line D2-D2' in FIG. 7. [Figure 10] 8 is a cross-sectional view showing a cross-sectional structure taken along line EE' in FIG. 7. [Figure 11] FIG. 10 is a cross-sectional view showing the structure of a semiconductor device according to a fourth embodiment. [Figure 12]FIG. 10 is a cross-sectional view showing another example of the structure of the semiconductor device according to the fourth embodiment. [Figure 13] FIG. 10 is a cross-sectional view showing another example of the structure of the semiconductor device according to the fourth embodiment. [Figure 14] FIG. 11 is a plan view showing a layout of a part of an active region of a semiconductor device according to a fifth embodiment, as viewed from the front surface side of a semiconductor substrate. [Figure 15A] 15 is a cross-sectional view showing the cross-sectional structure taken along the cutting line F1-F1' in FIG. 14. [Figure 15B] 15 is a cross-sectional view showing the cross-sectional structure taken along the line F2-F2' in FIG. 14. [Figure 16] 15 is a cross-sectional view showing the cross-sectional structure taken along the line GG' in FIG. 14. [Figure 17] 15 is a cross-sectional view showing a cross-sectional structure taken along the line HH' in FIG. 14. [Figure 18] FIG. 13 is a plan view showing the layout of the semiconductor device according to the sixth embodiment as viewed from the front surface side of the semiconductor substrate. [Figure 19] FIG. 13 is a plan view showing another example of the layout of the semiconductor device according to the sixth embodiment, as viewed from the front surface side of the semiconductor substrate. [Figure 20] 19 is a cross-sectional view showing the cross-sectional structure taken along line II' in FIG. 18. [Figure 21] 19 is a cross-sectional view showing the cross-sectional structure taken along the line JJ' in FIG. 18. [Figure 22] 19 is a cross-sectional view showing the cross-sectional structure taken along the line KK' in FIG. 18. [Figure 23] 19 is a cross-sectional view showing another example of the cross-sectional structure taken along line II' in FIG. 18. [Figure 24] 19 is a cross-sectional view showing another example of the cross-sectional structure taken along the line JJ' in FIG. 18. FIG. [Figure 25] 19 is a cross-sectional view showing another example of the cross-sectional structure taken along the line KK' in FIG. 18. [Figure 26] 19 is a cross-sectional view showing the cross-sectional structure taken along the line LL' in FIG. 18. [Figure 27] 19 is a cross-sectional view showing the cross-sectional structure taken along the line MM' in FIG. 18. [Figure 28] 19 is a cross-sectional view showing the cross-sectional structure taken along the line NN′ in FIG. 18. [Figure 29] 19 is a cross-sectional view showing another example of the cross-sectional structure taken along the line LL' in FIG. 18. FIG. [Figure 30] 19 is a cross-sectional view showing another example of the cross-sectional structure taken along the line MM′ in FIG. 18. FIG. [Figure 31] 19 is a cross-sectional view showing a cross-sectional structure of another example taken along the line NN′ in FIG. 18. FIG. [Figure 32] FIG. 13 is a cross-sectional view showing the structure of a semiconductor device according to an eighth embodiment. [Figure 33] FIG. 13 is a cross-sectional view showing another example of the structure of the semiconductor device according to the eighth embodiment. [Figure 34] FIG. 10 is a plan view showing the layout of the semiconductor device of the reference example as viewed from the front surface side of the semiconductor substrate. [Figure 35] 30 is a cross-sectional view showing the cross-sectional structure taken along the line AA-AA' in FIG. 29. DETAILED DESCRIPTION OF THE INVENTION

[0011] Preferred embodiments of a semiconductor device according to the present invention will be described in detail below with reference to the accompanying drawings. In this specification and the accompanying drawings, layers and regions prefixed with n or p indicate that electrons or holes are the majority carriers, respectively. The symbols (+ and -) attached to n or p indicate that the impurity concentration is higher or lower than that of layers or regions not prefixed with that symbol. In the following description of the embodiments and the accompanying drawings, similar components are designated by the same symbols, and redundant explanations will be omitted.

[0012] (Reference example) The following describes the problems with the semiconductor device of the reference example. Fig. 34 is a plan view showing the layout of the semiconductor device of the reference example as seen from the front surface side of the semiconductor substrate. Fig. 35 is a cross-sectional view showing the cross-sectional structure along the cutting line AA-AA' in Fig. 34. The semiconductor device 210 of the reference example shown in Figs. 34 and 35 is a MOSFET (Metal Oxide Semiconductor Field Effect Transistor: a MOS type field effect transistor with an insulated gate consisting of a three-layer structure of metal-oxide film-semiconductor) with a super junction (SJ) structure in which a drift layer is a parallel pn layer 202 in an active region 221 of a semiconductor substrate (semiconductor chip) 230 using silicon carbide (SiC) as a semiconductor material.

[0013] The active region 221 has a substantially rectangular planar shape and is disposed approximately in the center of the semiconductor substrate 230. In the active region 221, a plurality of cells (functional units of an element) 209 of the same MOSFET structure (here, a planar gate structure: an insulated gate structure) are disposed adjacent to each other in a first direction X parallel to the front surface of the semiconductor substrate 230. The plurality of cells 209 extend in a stripe pattern in a second direction Y parallel to the front surface of the semiconductor substrate 230 and perpendicular to the first direction X. In the active region 221, a source pad (source electrode 214: not shown in FIG. 29 ) and a gate pad 215 are disposed on the front surface of the semiconductor substrate 230. The edge termination region 222 is a region between the active region 221 and the chip edge (the edge of the semiconductor substrate 230) and surrounds the periphery of the active region 221.

[0014] The parallel pn layer 202 is formed by alternately and repeatedly arranging n-type column regions 203 and p-type column regions 204 adjacent to each other in the first direction X. The n-type column regions 203 and p-type column regions 204 extend linearly in the second direction Y. The cell 209 includes a p-type base region 205, an n + type source region 206, p ++ The gate electrode 212 is made up of a contact region 207, a JFET (Junction FET) region 208, a gate insulating film 211, and a gate electrode 212, and extends linearly in the second direction Y. The source electrode 214 is formed in a contact hole of the interlayer insulating film 213 by an n-type contact region 207, a JFET (Junction FET) region 208, a gate insulating film 211, and a gate electrode 212. + type source region 206 and p++ The n-type contact region 207 is in contact with the back surface of the semiconductor substrate 230. ++ A type drain region 201 and a drain electrode 216 are provided.

[0015] In the semiconductor device 210 of this reference example, when a positive voltage relative to the source electrode 214 is applied to the drain electrode 216 and the voltage applied to the gate electrode 212 is less than the gate threshold voltage, the p-type base region 205 and the p-type column region 204 and the p-type column region 203 are reverse-biased, so the SJ-MOSFET remains off. A depletion layer extends vertically (toward the source electrode 214 and the drain electrode 216) from the p-n junction between the p-type base region 205 and the n-type column region 203, and also horizontally from the p-n junction between the p-type column region 204 and the n-type column region 203 toward the outside (toward the chip edge). The amount by which this depletion layer extends outward in the edge termination region 222 ensures a predetermined withstand voltage based on the breakdown field strength of the semiconductor material (here, SiC) and the depletion layer width.

[0016] Furthermore, the semiconductor device 210 of the reference example incorporates only a parasitic pn junction diode (body diode) formed by the pn junction between the p-type base region 205 and the p-type column region 204 and the n-type column region 203. During the period when the SJ-MOSFET transitions from on to off, the body diode conducts, and electrons and holes are injected into and stored in the p-type column region 204 and the n-type column region 203 of the parallel pn layer 202, respectively. When the SJ-MOSFET transitions from this state to a turned-off state (reverse recovery state of the body diode), the carriers (electrons and holes) in the parallel pn layer 202 are discharged to the drain electrode 216 and the source electrode 214, and a current (reverse recovery current of the body diode) flows in the reverse direction through the pn junction between the p-type base region 205 and the n-type column region 203, causing the carriers to decrease in the parallel pn layer 202.

[0017] While the carriers in the parallel pn layer 202 decrease, they are discharged to the drain electrode 216 and the source electrode 214, causing a depletion layer to expand vertically from the pn junction between the p-type base region 205 and the n-type column region 203, increasing the reverse voltage across the pn junction. The reverse voltage across the pn junction between the p-type column region 204 and the n-type column region 203 also increases, promoting carrier recombination near the pn junction between the p-type column region 204 and the n-type column region 203, resulting in the carriers disappearing from the parallel pn layer 202 in a short period of time. This phenomenon manifests itself in the switching operation of the SJ-MOSFET as a steep change in the reverse recovery current of the body diode of the SJ-MOSFET. The number of carriers disappearing per unit time from the parallel pn layer 202 varies depending on the design of the parallel pn layer 202.

[0018] Generally, the larger the pn junction area between the p-type column region 204 and the n-type column region 203, the greater the number of carriers accumulated in the parallel pn layer 202 when the SJ-MOSFET is on, which results in a larger peak value (maximum current value) of the reverse recovery current of the body diode, and the larger the time rate of change (rate of decrease) di / dt from the peak value, which results in a steeper change in the reverse recovery current of the body diode (hard recovery).On the other hand, the smaller the pn junction area between the p-type column region 204 and the n-type column region 203, the fewer the number of carriers accumulated in the parallel pn layer 202 when the SJ-MOSFET is on, which results in a smaller peak value of the reverse recovery current of the body diode, and the smaller the time rate of change di / dt from the peak value, which results in a gradual change in the reverse recovery current of the body diode (soft recovery).

[0019] A steep change in the reverse recovery current of the body diode adversely affects the switching characteristics of the SJ-MOSFET and the operation of peripheral components electrically connected to the SJ-MOSFET. On the other hand, reducing the pn junction area between the p-type column region 204 and the n-type column region 203 makes the change in the reverse recovery current of the body diode more gradual, but reduces the effect of the parallel pn layer 202 in reducing the on-resistance. Furthermore, in switching applications of inverter circuits connected to inductive loads, the reverse recovery current of the body diode of the SJ-MOSFET is consumed by the inductive load of the inverter circuit. Therefore, a large peak value of the reverse recovery current of the body diode of the SJ-MOSFET increases switching loss. Therefore, one problem to be solved in this embodiment is, for example, improving the reverse recovery characteristics of the body diode.

[0020] Furthermore, SJ-MOSFETs are generally not designed for bidirectional conduction (both forward and reverse bias of the body diode). For example, when an SJ-MOSFET is used for switching an inverter circuit connected to an inductive load, it is not possible to maintain a withstand voltage against reverse conduction of the reflux current (forward conduction of the body diode of the SJ-MOSFET) that flows during the dead time period of the inverter operation. This requires a diode to block reverse conduction of the reflux current as a separate component, and the increased number of separate components increases the cost of the product (semiconductor circuit device). Therefore, one problem to be solved in this embodiment is, for example, cost reduction by reducing the number of separate components in a product equipped with an SJ-MOSFET.

[0021] (Embodiment 1) The structure of a semiconductor device according to a first embodiment will be described. FIG. 1 is a plan view showing the layout of the semiconductor device according to the first embodiment as viewed from the front surface side of a semiconductor substrate. In FIG. 1, MOS cells 9 and SBD cells of an SBD 50 are indicated by solid lines extending in a stripe shape in the horizontal direction and labeled only with the reference numeral 9. FIG. 2 is an enlarged plan view showing a portion of the active region of FIG. 1. FIG. 2 shows the layout of a p-type region 51 of one SBD cell of an SBD 50. In FIG. 2, the interface between an n-type column region 3 and a p-type column region 4 is indicated by a fine dashed line, and the end of a gate electrode 12 is indicated by a coarse dashed line (the same applies to FIG. 4). FIG. 3 is a cross-sectional view showing the cross-sectional structure along the line A-A' in FIG. 2.

[0022] 1 to 3, a semiconductor device 10 according to a first embodiment is an SJ-MOSFET with a super junction (SJ) structure. The SBD 50 is embedded in an active region 21 of a semiconductor substrate (semiconductor chip) 30 made of SiC as a semiconductor material, in the form of a flat plate parallel to the front surface of the semiconductor substrate 30, and the drift layer is a parallel pn layer 2. The active region 21 has a substantially rectangular planar shape and is located approximately at the center of the semiconductor substrate 30. In the center of the active region 21, a plurality of cells (hereinafter referred to as MOS cells) 9 having the same structure as the MOSFET (here, a planar gate structure) are arranged adjacent to each other in a first direction X parallel to the front surface of the semiconductor substrate 30, with the SBD 50 cells (hereinafter referred to as SBD cells) partially sandwiched between them. The MOS cells 9 and the SBD cells extend in a stripe pattern in a second direction Y parallel to the front surface of the semiconductor substrate 30 and perpendicular to the first direction X.

[0023] On the front surface of the semiconductor substrate 30, a source pad (source electrode 14; not shown in FIG. 1) is provided in the center of the active region 21, and a gate pad 15 and gate runners (not shown) are provided in an outer peripheral portion 21b (see FIGS. 19 to 24) surrounding the periphery of the central portion of the active region 21. The source pad has substantially the same planar shape as the central portion of the active region 21 and covers substantially the entire central portion of the active region 21. The source pad may have a substantially rectangular planar shape, for example, with a portion recessed toward the chip center (the center of the semiconductor substrate 30) so as to surround three sides of the substantially rectangular gate pad 15. Gate electrodes 12 (see FIG. 3) of all MOS cells 9 are electrically connected to the gate pad 15 via gate runners.

[0024] The active region 21 is formed over the entire area thereof directly below the p-type base region 5 (n ++ 3, a low carrier lifetime region (first low carrier lifetime region) 41 is provided at a depth position of the n-type drain region 1 side (see FIG. 3). A low carrier lifetime region (second low carrier lifetime region) 42 (shown by an x ​​mark) is preferably provided so as to surround the periphery of the active region 21, closer to the edge end than the end of the p-type base region 5. The low carrier lifetime region 42 is preferably further provided so as to surround the periphery of the gate pad 15. The low carrier lifetime region 42 extends from the front surface of the semiconductor substrate 30 in the depth direction Z to the n-type drain region 1 side. ++ The n-type drain region is preferably ++ It may terminate within the drain region 1 or on the back surface of the semiconductor substrate 30 .

[0025] The low carrier lifetime regions 41 and 42 are regions in which the lifetime of minority carriers (holes) is relatively shortened by introducing carrier lifetime killers (crystal defects that serve as trapping centers for minority carriers: first and second carrier lifetime killers), and at least the low carrier lifetime region 41 is provided. The carrier lifetime of the semiconductor substrate 30 is shortest in the low carrier lifetime regions 41 and 42. The low carrier lifetime regions 41 and 42 have the function of limiting the current path (hole current path) during reverse recovery of the parasitic pn junction diode (body diode) formed by the pn junction (see FIG. 3 ) between the p-type base region 5 and the p-type column region 4 and the n-type column region 3 of the SJ-MOSFET to the active region 21.

[0026] Edge termination region 22 is a region between active region 21 and the chip edge (edge ​​of semiconductor substrate 30) and surrounds active region 21 in a substantially rectangular shape. Edge termination region 22 is a region closer to the chip edge than the edge of p-type base region 5. Edge termination region 22 functions to maintain a breakdown voltage by mitigating the electric field on the front surface side of semiconductor substrate 30. The breakdown voltage is the limit voltage at which the drain-source voltage does not increase further even if the drain-source current increases due to avalanche breakdown at the pn junction. A predetermined breakdown voltage structure, such as a junction termination extension (JTE) structure or a field limiting ring (FLR) structure, is disposed in edge termination region 22. The detailed structure of edge termination region 22 will be described later.

[0027] As shown in FIG. 3, the semiconductor substrate 30 is made of SiC. ++ The semiconductor substrate 30 is formed by epitaxially growing an epitaxial layer 32 containing a parallel pn layer 2 on the front surface of a starting substrate 31. The main surface of the semiconductor substrate 30 facing the epitaxial layer 32 is the front surface, and the n ++ The main surface on the mold starting substrate 31 side is referred to as the back surface. ++ The starting substrate 31 is n ++The parallel pn layer 2 is formed by alternately and repeatedly arranging n-type column regions (first conductivity type column regions) 3 and p-type column regions 4 (second conductivity type column regions) adjacent to each other in the first direction X. The n-type column regions 3 and p-type column regions 4 are n ++ The n-type column region 3 and the p-type column region 4 are in contact with the n-type drain region 1. Each n-type column region 3 and each p-type column region 4 extends linearly in the second direction Y and in the depth direction Z, forming a quadrangular pillar shape.

[0028] Both the n-type column regions 3 and the p-type column regions 4 have a striped pattern in both plan and cross-sectional views. That is, both the n-type column regions 3 and the p-type column regions 4 are arranged in the short direction (first direction X) at predetermined repeat pitches P1 and P2, and may extend linearly with approximately the same widths Wn and Wp in the long direction (second direction Y), and may also extend linearly with approximately the same widths Wn and Wp in the depth direction Z. The n-type column regions 3 and the p-type column regions 4 may terminate in the edge termination region 22 in the long direction.

[0029] It is sufficient that the charge balance between the adjacent n-type column region 3 and p-type column region 4 is roughly equal, and the widths Wn and Wp and impurity concentrations of the n-type column region 3 and p-type column region 4 may be different from each other. "Equal charge balance" means that the amount of one impurity, expressed as the product of the carrier concentration (number of activated impurities per unit volume) of the n-type column region 3 and the width Wn, and the amount of the other impurity, expressed as the product of the carrier concentration of the p-type column region 4 and the width Wp, are roughly the same ("roughly the same" means that the amount of one impurity is in the range of 95% to 105% of the amount of the other impurity), and the amounts of charge are balanced between the adjacent n-type column region 3 and p-type column region 4. "Roughly the same impurity concentration (carrier concentration)" and "roughly the same width" mean that the impurity concentration and width are the same within the range including tolerances due to process variations.

[0030] In the active region 21, a p-type base region (first semiconductor region) 5, an n-type base region (first semiconductor region) 6, and an n-type base region (n-type semiconductor region) 7 are provided between the front surface of the semiconductor substrate 30 and the parallel pn layer 2. +p-type source region (second semiconductor region) 6 ++ The p-type contact region 7 and the JFET region 8 are selectively provided. + Type source region 6 and p ++ The p-type contact region 7 is a diffusion region formed by ion implantation and thermal diffusion in the surface region of the epitaxial layer 32 (the portion on the front surface side of the semiconductor substrate 30). The p-type base region 5 is provided between the front surface of the semiconductor substrate 30 and the p-type column region 4, and has a lower surface (n ++ The p-type base region 5 is in contact with the p-type column region 4 at its end (surface on the n-type drain region 1 side) in the first direction X. The p-type base region 5 is wider in the first direction X than the p-type column region 4, and is in contact with the n-type column region 3 at both ends (side surfaces) in the first direction X.

[0031] n + Type source region 6 and p ++ The n-type contact regions 7 are selectively provided between the front surface of the semiconductor substrate 30 and the p-type base region 5, are surrounded by the p-type base region 5, and are exposed to contact holes 13a, which will be described later. + The source region 6 is p ++ The contact region 7 is located closer to the gate electrode 12 than the contact region 7. ++ The p-type contact region 7 may not be provided. ++ Instead of the n-type contact region 7, the p-type base region 5 reaches the front surface of the semiconductor substrate 30 and is exposed in the contact hole 13a. The JFET region 8 is formed by a portion of the n-type column region 3 that extends to reach the front surface of the semiconductor substrate 30 and is adjacent to the p-type base region 5 in the first direction X.

[0032] The gate electrode 12 is provided on the front surface of the semiconductor substrate 30 via a gate insulating film 11. The gate electrode 12 is connected to the n-type base region 5 via the gate insulating film 11. +The gate electrode 12 covers the entire surface of the JFET region 8 via the gate insulating film 11, and faces the n-type column region 3 in the depth direction Z via the JFET region 8. The p-type base region 5 and the n-type base region 6 are disposed between the centers of the adjacent gate electrodes 12 and extend linearly in the second direction Y. + Type source region 6, p ++ The contact region 7, the JFET region 8, the gate insulating film 11, and the gate electrode 12 constitute one MOS cell 9 of the planar gate structure of the MOSFET.

[0033] The MOS cells 9 are regularly arranged, partially sandwiching the SBD cells (cells of the SBD 50). Specifically, for every one or more MOS cells 9 arranged in the first direction X (two or more arranged adjacently), one SBD cell of the SBD 50 is arranged adjacent to the MOS cell 9. All the cells (MOS cells 9 and SBD cells) are arranged in a stripe pattern extending in the second direction Y. In FIG. 2, a region where one or more MOS cells 9 are arranged (two or more arranged adjacently) is illustrated as a "MOS region," and a region where one SBD cell is arranged is illustrated as an "SBD region" (the same applies to FIGS. 4, 7, and 13). In FIG. 3, MOS cells 9 are arranged adjacent to each other, and an SBD cell is arranged adjacent to the MOS cell 9. One SBD cell and the SBD region have the same planar shape. The repetition pitch of the SBD cells is set appropriately as long as a predetermined current capacity of the SJ-MOSFET can be obtained within a predetermined chip size.

[0034] The SBD 50 is a Schottky barrier diode that utilizes the rectification of a Schottky barrier formed at the junction between the n-type column region 3 that reaches the front surface of the semiconductor substrate 30 and a conductive film 52 that contacts the n-type column region 3 on the front surface of the semiconductor substrate 30. The SBD 50 is connected in parallel to the body diode of the SJ-MOSFET. The SBD 50 extends linearly in the second direction Y along the n-type column region 3. One SBD cell of the SBD 50 is formed between the centers of adjacent gate electrodes 12 across the Schottky junction between the conductive film 52 and the n-type column region 3. The SBD cell (i.e., within the SBD region) has an n+ There is no p type source region 6. ++ A mold contact region 7 may be provided.

[0035] That is, the p-type base region 5, n-type + One SBD cell (i.e., one SBD region) of the SBD 50 is configured by forming a Schottky junction between the conductive film 52 and the n-type column region 3 instead of the p-type source region 6, JFET region 8, gate insulating film 11, and gate electrode 12. The SBD 50 is disposed between adjacent p-type base regions 5. The SBD 50 may have a Junction Barrier Schottky (JBS) structure that combines a Schottky junction between the conductive film 52 and the n-type column region 3 and a pn junction between the p-type region 51 (the hatched portion in the checkered pattern: the third semiconductor region) and the n-type column region 3.

[0036] A plurality of p-type regions 51 (three in this example) are selectively provided between the front surface of the semiconductor substrate 30 and the n-type column region 3 that constitutes the SBD 50. The plurality of p-type regions 51 extend in stripes in the second direction Y between adjacent p-type base regions 5. Of these plurality of p-type regions 51, the p-type region 51 closest to the p-type base region 5 is the p-type region 51 closest to the p-type base region 5 (or further p ++ The p-type regions 51 may be in contact with the n-type contact region 3. The n-type column regions 3 directly below extend between the adjacent p-type regions 51 and are exposed together with the p-type regions 51 through contact holes 13b (described later). The number, width, spacing, and impurity concentration of the p-type regions 51 constituting the JBS structure of the SBD cell are set appropriately according to the impurity concentration of the n-type column regions 3.

[0037] The p-type region 51 is a diffusion region formed in the surface region of the epitaxial layer 32 by ion implantation and thermal diffusion. The p-type region 51 may be formed simultaneously with the p-type base region 5, for example, and may have approximately the same depth and impurity concentration as the p-type base region 5. The ion implantation for forming the p-type base region 5 and the ion implantation for forming the p-type region 51 may be performed separately in this order (or the reverse order is also possible). As long as the p-type region 51 promotes depletion in the surface region of the n-type column region 3 during reverse recovery of the body diode of the SJ-MOSFET, the impurity concentration of the p-type region 51 may be higher than the impurity concentration of the p-type base region 5, and the depth of the p-type region 51 may be shallower than the depth of the p-type base region 5.

[0038] The p-type region 51 has the function of alleviating the electric field applied to the SBD 50 by depleting the body diode of the SJ-MOSFET (or by depleting the surface region of the n-type column region 3, or both) during reverse recovery. Furthermore, during reverse recovery of the body diode of the SJ-MOSFET, the p-type region 51 promotes depletion of the surface region of the n-type column region 3 that constitutes the SBD 50. This reduces the number of minority carriers (holes) in the n-type column region 3 that constitutes the SBD 50 and suppresses carrier recombination near the pn junction between the p-type column region 4 and the n-type column region 3, resulting in a gradual change in the reverse recovery current of the body diode of the SJ-MOSFET (soft recovery).

[0039] The conductive film 52 is provided in the contact hole 13b on the front surface of the semiconductor substrate 30 in a linear shape extending in the second direction Y, and covers the n-type column region 3 and the p-type region 51 that constitute the SBD cell. When the MOS cell 9 is an n-channel type, molybdenum (Mo) may be used as the metal material of the conductive film 52. The conductive film 52 may also function as a barrier metal that prevents atomic diffusion and mutual reaction between the source electrode 14 and the semiconductor substrate 30. When the conductive film 52 functions as a barrier metal, it may be provided in the entire area between the semiconductor substrate 30 and the interlayer insulating film 13 and the source electrode 14 in the active region 21. An example of a metal material that functions as a barrier metal is titanium (Ti).

[0040] The low carrier lifetime region 41 is provided throughout the active region 21 at a depth directly below the p-type base region 5, and is adjacent to the p-type base region 5, the JFET region 8, and the SBD 50 in the depth direction Z. The low carrier lifetime region 41 has the function of promoting the recombination of carriers (electrons and holes) during reverse recovery of the body diode of the SJ-MOSFET, thereby reducing the effective (apparent) reverse recovery current of the body diode. The low carrier lifetime region 41 is provided in the semiconductor substrate 30 by introducing protons (H + It is formed by irradiation with light ions such as argon (Au) and helium (He).

[0041] The presence of the low carrier lifetime region 41 in the n-type column region 3 directly below the SBD 50 reduces the resistance of the n-type column region 3, making it easier for a forward current to flow through the SBD 50. However, it is presumed that by appropriately setting the dose of light ion irradiation for forming the low carrier lifetime region 41, the operation of the SJ-MOSFET will not be adversely affected. For example, the dose of light ion irradiation for forming the low carrier lifetime region 41 is set to 1×10 11 / cm 2 More than 1×10 13 / cm 2 The acceleration voltage is preferably set to about 100 keV or more and 2 MeV or less, and the irradiation is preferably performed from the front or back surface of the semiconductor substrate 30.

[0042] The interlayer insulating film 13 is provided on the entire front surface of the semiconductor substrate 30 and covers the gate electrode 12. The interlayer insulating film 13 is provided with a contact hole 13a for each MOS cell 9, and a contact hole 13b for each SBD cell of the SBD 50. The contact holes 13a and 13b extend in a stripe shape in the second direction Y. The source electrode (first electrode) 14 is provided on the interlayer insulating film 13 so as to fill the contact holes 13a and 13b. The source electrode 14 is provided with an n-type electrode in the contact hole 13a. + Type source region 6 and p ++ The source electrode 14 is in ohmic contact with the p-type contact region 7. The source electrode 14 is in contact with the conductive film 52 through the contact hole 13b. The source electrode 14 is in ohmic contact with the p-type base region 5 and the p-type ++ The back surface (n ++ A drain electrode 16 (second electrode) is provided on the entire back surface of the starting mold substrate 31.

[0043] Although not particularly limited, for example, if the semiconductor device 10 (SJ-MOSFET) according to the first embodiment has a breakdown voltage of 3.3 kV, the dimensions and impurity concentrations of each part will be as follows: The repeat pitches P1 and P2 of the n-type column regions 3 and p-type column regions 4 are approximately 1.0 μm or more and 5.0 μm or less, and may be, for example, approximately 3.0 μm. The impurity concentrations of the n-type column regions 3, p-type column regions 4, p-type base regions 5, and p-type regions 51 are all 1.0×10 16 / cm 3 n + The impurity concentration of the source region 6 is 1.0×10 17 / cm 3 n ++ type drain region 1 and p ++ The impurity concentration of the contact region 7 is 1.0×10 18 / cm 3 Over 1.0 x 10 19 / cm 3 It is about the following.

[0044] Next, the operation of the semiconductor device 10 (SJ-MOSFET) according to the first embodiment will be described. When a voltage equal to or greater than the gate threshold voltage is applied to the gate electrode 12 while a positive voltage with respect to the source electrode 14 is applied to the drain electrode 16, the n + A channel (n-type inversion layer) is formed in the region between the n-type source region 6 and the JFET region 8. ++ The n-type drain region 1 is connected to the n-type column region 3 through the channel. + A drift current (main current) flows toward the type source region 6, and the SJ-MOSFET turns on.

[0045] On the other hand, when a voltage positive with respect to the source electrode 14 is applied to the drain electrode 16 and the voltage applied to the gate electrode 12 is less than the gate threshold voltage, the p-type base region 5 and the p-type column region 4 and the p-type column region 3 are reverse biased, so the SJ-MOSFET remains in the off state. A depletion layer spreads vertically (toward the source electrode 14 and the drain electrode 16) from the p-n junction between the p-type base region 5 and the n-type column region 3, and also spreads horizontally from the p-n junction between the p-type column region 4 and the n-type column region 3.

[0046] The depletion layer extends laterally by half the width Wn of the n-type column region 3, so that the drift layer is depleted by the thickness of the parallel pn layer 2, ensuring a predetermined breakdown voltage of the active region 21. - Compared to a conventional MOSFET consisting only of a silicon-type region, the depletion layer does not need to extend as much, allowing for a higher impurity concentration in the drift layer and lowering the on-resistance. Furthermore, the depletion layer extends laterally outward (toward the chip edge) within edge termination region 22, ensuring a predetermined breakdown voltage for edge termination region 22 based on the breakdown field strength of the semiconductor material.

[0047] Furthermore, when the body diode of the SJ-MOSFET is forward biased, the SBD 50 conducts forward current earlier than the body diode at a voltage lower than the threshold voltage of the body diode of the SJ-MOSFET. +The parasitic npn bipolar transistor (body diode) formed by the type-source region 6 does not operate. Therefore, for example, the withstand voltage can be maintained against reverse conduction of the reflux current (forward conduction of the body diode) that flows during the dead time period in inverter operation.

[0048] Then, during the period when the SJ-MOSFET transitions from on to off, the body diode of the SJ-MOSFET becomes conductive, and electrons and holes are injected into and stored in the p-type column region 4 and the n-type column region 3. When the SJ-MOSFET turns off from this state (reverse recovery state of the body diode), the carriers (electrons and holes) in the parallel pn layer 2 are discharged to the drain electrode 16 and the source electrode 14, and a current (reverse recovery current of the body diode) flows in the reverse direction through the pn junction between the p-type base region 5 and the n-type column region 3.

[0049] As the reverse recovery current flows, the carriers in the parallel pn layer 2 decrease, while as the carriers in the parallel pn layer 2 are discharged to the drain electrode 16 and the source electrode 14, a depletion layer expands vertically from the pn junction between the p-type base region 5 and the n-type column region 3, and the reverse voltage applied to the pn junction increases. The reverse voltage applied to the pn junction between the p-type column region 4 and the n-type column region 3 also increases, promoting the recombination of carriers near the pn junction between the p-type column region 4 and the n-type column region 3, and causing carriers to disappear from the parallel pn layer 2 in a short period of time.

[0050] During reverse recovery of the body diode of this SJ-MOSFET, the SBD 50, which is partially disposed in the active region 21 and connected in parallel to the MOS cell 9, is also reverse biased, and the surface region of the n-type column region 3 that constitutes the SBD 50 is depleted. This reduces the number of minority carriers in the n-type column region 3 that constitutes the SBD 50, which is essentially equivalent to reducing the junction area between the p-type column region 4 and the n-type column region 3. This makes it possible to moderate the change in the reverse recovery current of the body diode of the SJ-MOSFET.

[0051] Because there is no need to reduce the junction area between the p-type column region 4 and the n-type column region 3, the reverse recovery characteristics of the body diode of the SJ-MOSFET can be made soft, while maintaining the on-resistance reduction effect of the parallel pn layer 2. Furthermore, because the number of minority carriers in the n-type column region 3 that constitutes the SBD 50 is reduced, the peak value of the reverse recovery current of the body diode of the SJ-MOSFET is reduced, making it possible to reduce switching losses in switching applications of inverter circuits connected to inductive loads.

[0052] As described above, according to the first embodiment, the SJ-MOSFET has a drift layer that is a parallel pn layer made up of an n-type column region and a p-type column region. The parallel pn layer provides a high breakdown voltage, and the impurity concentration of the drift layer can be increased to achieve a low on-resistance. Furthermore, according to the first embodiment, an SBD is incorporated into the active region using a Schottky junction between a conductive film and an n-type column region. When the body diode of the SJ-MOSFET is forward biased, the SBD conducts forward current faster than the body diode of the SJ-MOSFET. This allows the SBD to maintain a breakdown voltage against reverse conduction of a reflux current that flows during a dead time period during inverter operation, for example. Furthermore, incorporating the SBD on the same semiconductor substrate as the SJ-MOSFET reduces the number of individual components in a product incorporating the SJ-MOSFET, thereby reducing costs.

[0053] Furthermore, according to the first embodiment, the SBD built into the active region by a Schottky junction between a conductive film and an n-type column region can moderate the change in the reverse recovery current of the body diode of the SJ-MOSFET while maintaining the on-resistance reduction effect of the parallel pn layer. Furthermore, the provision of a low-carrier lifetime region at a depth directly below the p-type base region throughout the active region can reduce the effective (apparent) reverse recovery current of the body diode of the SJ-MOSFET. This further moderates the change in the reverse recovery current of the body diode of the SJ-MOSFET. Furthermore, the peak value of the reverse recovery current of the body diode of the SJ-MOSFET is reduced, thereby reducing switching losses in switching applications of inverter circuits connected to inductive loads. Therefore, the reverse recovery characteristics of the body diode can be improved.

[0054] (Embodiment 2) The structure of a semiconductor device according to a second embodiment will be described. FIG. 4 is a plan view showing the layout of a part of the active region of the semiconductor device according to the second embodiment as viewed from the front surface side of the semiconductor substrate. The overall layout of a semiconductor device 60 according to the second embodiment as viewed from the front surface side of the semiconductor substrate 30 is the same as that shown in FIG. 1. FIG. 4 is an enlarged view of a part of the active region 21 of FIG. 1, showing the layout of a p-type region 61 (hatched portion in a checkerboard pattern) of one SBD cell of an SBD 63. FIGS. 5 and 6 are cross-sectional views taken along the cutting lines B-B' and CC of FIG. 4, respectively. 1 is a cross-sectional view showing the cross-sectional structure at '.

[0055] 4 to 6, the semiconductor device 60 according to the second embodiment is different from the semiconductor device 10 according to the first embodiment (see FIGS. 2 and 3) in the layout of the multiple p-type regions 61 that constitute the JBS structure of the SBD cell of the SBD 63. The SBD cell of the SBD 63 is a diode with a JBS structure that combines a Schottky junction between a conductive film 62 and an n-type column region 3 and a pn junction between a p-type region 61 and an n-type column region 3. Like the SBD cell of the SBD 50 according to the first embodiment, the SBD cell of the SBD 63 is disposed between adjacent p-type base regions 5 and extends in a stripe shape in the second direction Y together with the MOS cell 9.

[0056] A plurality of p-type regions 61 are provided between adjacent p-type base regions 5, scattered in the second direction Y. Each p-type region 61 has a width substantially the same as the interval between adjacent p-type base regions 5, and is spaced apart from the p-type base regions 5 (or further p ++ The n-type column region 3 extends between the p-type regions 61 adjacent to each other in the second direction Y and is exposed to the contact hole 13b together with the p-type regions 61. That is, the p-type regions 61 and the n-type column regions 3 are alternately and repeatedly arranged adjacent to each other in the second direction Y between the p-type base regions 5 adjacent to each other.

[0057] The width in the second direction Y, the repetition pitch in the second direction Y, and the impurity concentration of the p-type regions 61 are set appropriately depending on the impurity concentration of the n-type column regions 3. The width in the second direction Y and the repetition pitch of the p-type regions 61 are, for example, approximately 1.0 μm to 5.0 μm, and may be, for example, approximately 3.0 μm. The configuration of the conductive film 62 is similar to that of the conductive film 52 of the SBD 50 of the first embodiment. That is, the conductive film 62 is provided linearly extending in the second direction Y on the front surface of the semiconductor substrate 30 in the contact hole 13b of the interlayer insulating film 13, and covers the n-type column regions 3 and the p-type regions 61 that constitute the SBD cell.

[0058] As described above, according to the second embodiment, the same effects as those of the first embodiment can be obtained even when the layout of the p-type region constituting the JBS structure of the SBD arranged adjacent to the MOS cell is changed in various ways.

[0059] (Embodiment 3) The structure of a semiconductor device according to a third embodiment will be described. FIG. 7 is a plan view showing the layout of a part of the active region of a semiconductor device according to the third embodiment as viewed from the front surface side of the semiconductor substrate. Of the overall layout of a semiconductor device 70 according to the third embodiment as viewed from the front surface side of the semiconductor substrate 30, the layout other than the MOS cell 79 and the SBD cell of the SBD 66 is the same as that shown in FIG. 1. In FIG. 7, a plurality of p-type regions 64 constituting the JBS structure of the SBD cell of the SBD 66 are collectively shown as a single region (hatched area in a checkerboard pattern). FIGS. 8 to 10 show the cross sections along the cut lines D1-D1', D2-D2', and E-D1' in FIG. 7, respectively. FIG. 10 is a cross-sectional view showing the cross-sectional structure at E'.

[0060] The semiconductor device 70 according to the third embodiment shown in FIGS. 7 to 10 differs from the semiconductor device according to the first embodiment (see FIG. 2) in that the MOS cells 79 and the SBD cells of the SBD 66 are arranged in a matrix. Specifically, the MOS cells 79 and the SBD cells of the SBD 66 have substantially the same size and substantially rectangular planar shapes. The MOS cells 79 are arranged in a matrix, with the SBD cells of the SBD 66 sandwiched between them. That is, in both the first and second directions X and Y, for every one or more MOS cells 79 arranged (two or more arranged adjacently), one SBD cell of the SBD 66 is arranged adjacent to the MOS cell 79. The SBD cells of the SBD 66 are preferably regularly scattered. Alternatively, one MOS cell 79 and one SBD cell of the SBD 66 may be arranged alternately and repeatedly adjacently in both the first and second directions X and Y in a checkerboard pattern.

[0061] The MOS cell 79 has a p-type base region 75, n-type + Type source region 76, p ++The planar layout of the contact region 77 and the JFET region 78 (p ++ The p-type base region 75 of the MOS cell 79 and the n-type contact region 77 (not shown) are different from those of the MOS cell 9 of the first embodiment (see FIG. 2). + Type source region 76, p ++ The contact region 77, the JFET region 78, the gate insulating film 71, the gate electrode 72, and the contact hole 73a extend linearly in the second direction Y, being partially interrupted (separated) in the SBD region (a region where one SBD cell of the SBD 66 is arranged). + The p-type source region 76, the gate electrode 72, and the contact hole 73a terminate at a position away from the SBD region in the second direction Y. ++ The contact region 77) terminates at the periphery of the SBD region.

[0062] The SBD 66 is a diode that utilizes the rectification of a Schottky barrier formed at the junction between the n-type column region 3 that reaches the front surface of the semiconductor substrate 30 and a conductive film 65 that contacts the n-type column region 3 on the front surface of the semiconductor substrate 30. The SBD 66 may have a JBS structure that combines a Schottky junction between the conductive film 65 and the n-type column region 3 and a pn junction between the p-type region 64 and the n-type column region 3. A plurality of p-type regions 64 that make up the JBS structure of the SBD cell are arranged in a lattice pattern so as to form an overall cross-shaped planar shape. Specifically, a plurality of p-type regions 64 (hereinafter referred to as first p-type regions 64a) extending in stripes in the first direction X between p-type base regions 75 adjacent to each other in the first direction X, and a plurality of p-type regions 64 (hereinafter referred to as second p-type regions 64b) extending in stripes in the second direction Y between p-type base regions 75 adjacent to each other in the second direction Y are arranged to intersect in a cross shape.

[0063] The first p-type region 64a extends linearly in the first direction X between the front surface of the semiconductor substrate 30 and the parallel pn layer 2, alternately contacting the n-type column region 3 and the p-type column region 4. The n-type column region 3 and the p-type column region 4 directly below extend between adjacent first p-type regions 64a. The second p-type region 64b extends linearly in the second direction Y along the n-type column region 3 or the p-type column region 4 between the front surface of the semiconductor substrate 30 and the n-type column region 3 or the p-type column region 4. The n-type column region 3 or the p-type column region 4, or the junction surface between the n-type column region 3 and the p-type column region 4, extends between adjacent second p-type regions 64b. The p-type region 64 is + The p-type region 64 is arranged apart from the p-type source region 76 in the first direction X. ++ The contact area 77 is in contact with the die contact area 77.

[0064] The interlayer insulating film 73 is provided over the entire front surface of the semiconductor substrate 30 and covers the gate electrode 72. The interlayer insulating film 73 is provided with a contact hole 73a for each MOS cell 79 and a contact hole 73b for each SBD cell of the SBD 66. The contact holes 73a and 73b in the interlayer insulating film 73 have a generally rectangular planar shape with an opening area smaller than the surface area of ​​the MOS cell 79 and the SBD cell of the SBD 66, respectively. The contact holes 73a and 73b are arranged in a matrix such that the interlayer insulating film 73 remains in a lattice pattern. The conductive film 65 is provided over the entire front surface of the semiconductor substrate 30 in the contact hole 73b. The conductive film 65 covers the p-type regions 64 and the n-type column regions 3 and p-type column regions 4 between adjacent p-type regions 64.

[0065] The JBS structure of the SBD 63 (see FIG. 4) of the semiconductor device 60 of the second embodiment may be applied to the SBD 66 of the semiconductor device 70 of the third embodiment, so that the first and second p-type regions 64 a and 64 b of the SBD 66 are scattered in the first and second directions X and Y, respectively.

[0066] As described above, according to the third embodiment, even when the cells are arranged in a matrix, it is possible to obtain the same effects as those of the first embodiment.

[0067] (Fourth embodiment) The structure of a semiconductor device according to a fourth embodiment will be described. FIG. 11 is a cross-sectional view showing the structure of the semiconductor device according to the fourth embodiment. FIG. 12 is a cross-sectional view showing another example of the structure of the semiconductor device according to the fourth embodiment. The overall layout of a semiconductor device 80 according to the fourth embodiment, viewed from the front surface side of the semiconductor substrate 30, is the same as that of FIG. 1, except that reference numeral 9 is replaced with reference numeral 89. The semiconductor device 80 according to the fourth embodiment shown in FIGS. 11 and 12 is obtained by applying a trench gate structure to the semiconductor device according to the first embodiment (see FIG. 3). The MOS cell 89 is obtained by applying a trench gate structure (insulated gate structure) to the MOS cell 9 of the first embodiment.

[0068] Specifically, in the fourth embodiment, the MOS cells 89 are arranged adjacent to each other in the first direction X, with the SBD cell of the SBD 50 partially sandwiched therebetween, similar to the MOS cells 9 in the first embodiment, and extend in a stripe shape in the second direction Y. The MOS cells 89 are formed by a p-type base region 81, an n + type source region 82, p ++ The p-type base region 81, the n-type contact region 83, the trench 84, the gate insulating film 85, and the gate electrode 86 form a trench gate structure. The area between the centers of the adjacent gate electrodes 86 forms one MOS cell 89. + type source region 82 and p ++ The contact regions 83 are selectively provided between the front surface of the semiconductor substrate 30 and the parallel pn layer 2, respectively.

[0069] p-type base region 81, n + type source region 82 and p ++ The p-type contact region 83 is a diffusion region formed by ion implantation and thermal diffusion in the surface region of the epitaxial layer 32. The p-type base region 81 is provided throughout the MOS region (a region in which one or more MOS cells 89 are arranged (adjacent to each other when two or more cells are arranged)).+ type source region 82 and p ++ The n-type contact region 83 is selectively provided between the front surface of the semiconductor substrate 30 and the p-type base region 81. The trench 84 is + The trench 84 penetrates the p-type source region 82 and the p-type base region 81 and reaches the n-type column region 3. A gate electrode 86 is provided inside the trench 84 with a gate insulating film 85 interposed therebetween.

[0070] The interlayer insulating film 87 is provided over the entire front surface of the semiconductor substrate 30 and covers the gate electrode 86. The interlayer insulating film 87 is provided with a contact hole 87a for each MOS cell 89, and a contact hole 87b for each SBD cell of the SBD 50. The contact holes 87a and 87b extend in a stripe pattern in the second direction Y. A barrier metal 88 is provided over the entire front surface of the semiconductor substrate 30 within the contact holes 87a and 87b. The barrier metal 88 is made of a metal capable of forming ohmic contact with the semiconductor substrate 30. The barrier metal 88 may have a stacked structure of two or more layers. The barrier metal 88 in the contact hole 87b constitutes the conductive film 52 of the SBD 50.

[0071] Between the front surface of the semiconductor substrate 30 and the parallel pn layer 2, a p-type base region 81, an n + Instead of the n-type source region 82, trench 84, gate insulating film 85, and gate electrode 86, a Schottky junction is formed between the conductive film 52 and the n-type column region 3, thereby forming one SBD cell (i.e., one SBD region) of the SBD 50. The SBD 50 is selectively disposed between adjacent p-type base regions 81. The configuration of the SBD 50 is the same as that of the first embodiment. The p-type region 51 of the SBD 50 contacts the p-type base region 81, as in the first embodiment. The n-type region 51 is disposed within the SBD cell (SBD region). + There is no p-type source region 82. ++A contact region 83 may be provided. The p-type regions 51 constituting the JBS structure of the SBD cell may be formed simultaneously with the p-type base region 81. The p-type regions 51 may be formed to approximately the same depth as the p-type base region 81 and may have approximately the same impurity concentration.

[0072] Of the multiple p-type regions 51 constituting the JBS structure of the SBD cell, one or more p-type regions 51 may be arranged to overlap the p-type base region 81 of the SBD cell (i.e., within the SBD region) (FIG. 12). In this case, the p-type region 51 overlapping the p-type base region 81 contacts the p-type column region 4. The impurity concentration of the p-type region 51 is set higher than the impurity concentration of the p-type base region 81. The SBD 50 of the semiconductor device 80 according to the fourth embodiment shown in FIG. 12 may be applied to the semiconductor devices 10, 60, and 70 according to the first to third embodiments (see FIGS. 1 to 10), and the p-type regions 51, 61, and 64 of the SBD cells of the SBDs 50, 63, and 66 according to the first to third embodiments may be arranged to overlap the p-type base regions 5 and 75 of the SBD cell.

[0073] 11, the semiconductor device 60 according to the second embodiment (see FIGS. 4 to 6) may be applied to the semiconductor device 80 according to the fourth embodiment, and the SBD 63 may be disposed instead of the SBD 50. Alternatively, the semiconductor device 70 according to the third embodiment (see FIG. 7) may be applied to the semiconductor device 80 according to the fourth embodiment, as shown in FIGS. 11 and 12, and the MOS cells 89 may be disposed in a matrix with the SBD cells of the SBD 66 of the third embodiment partially sandwiched between them. In this case, the p-type base regions 81, n + type source region 82, p ++ The mold contact region 83, the trench 84, the gate insulating film 85, the gate electrode 86, and the contact hole 87a may be linearly extended in the second direction Y with a partial break in the SBD region.

[0074] Another example of a semiconductor device 80 according to the fourth embodiment shown in FIG. 13 is a semiconductor device having an n-type base region 81. ++ p +The mold region 501 and the p are formed at the bottom of the trench 84 so as to cover the bottom surface of the trench 84. + and a mold region 502. + The p-type region 501 connects the p-type base region 81 and the p-type column region 4. At the bottom of the trench 84, + The trench 84 is provided with a p + It may terminate within the type region 502. + The mold region 502 has the function of reducing the electric field near the bottom of the trench 84. + The p-type region 502 is provided apart from the p-type base region 81 and faces the bottom surface of the trench 84 in the depth direction.

[0075] p + Type region 501 and p + The p-type region 502 may be formed at the same time and may have approximately the same impurity concentration. + Type region 501 and p + In the fourth embodiment, the low carrier lifetime region 41 is p + Type region 501 and p + Type area 502(p + Type region 501 and p + When the mold region 502 is not provided, the thickness of the trench 84 is n ++ The trench is provided at a depth on the drain region 1 side.

[0076] As described above, according to the fourth embodiment, even when a trench gate structure is applied, it is possible to obtain the same effects as those of the first embodiment.

[0077] (Embodiment 5) The structure of a semiconductor device according to a fifth embodiment will be described. FIG. 14 is a plan view showing the layout of a part of the active region of the semiconductor device according to the fifth embodiment as viewed from the front surface side of the semiconductor substrate. Of the overall layout of the semiconductor device 90 according to the fifth embodiment as viewed from the front surface side of the semiconductor substrate 30, the layout other than the MOS cell 109 and the SBD cell of the SBD 105 is the same as that shown in FIG. 1. In FIG. 13, multiple p-type regions 91 constituting the JBS structure of each SBD cell of the SBD 105 are collectively shown as one region (hatched area with a checkerboard pattern). FIGS. 15A, 15B, 16, and 17 show the cross sections along the cutting lines F1-F1' and F1' in FIG. 14, respectively. Cross-sectional views showing cross-sectional structures along the cut lines F2-F2', G-G', and H-H' is.

[0078] The semiconductor device 90 according to the fifth embodiment differs from the semiconductor device according to the fourth embodiment (see FIG. 11 ) in that the MOS cells 109 and the SBD cells of the SBD 105 are arranged in a matrix. Specifically, the MOS cells 109 and the SBD cells of the SBD 105 have substantially the same size and substantially rectangular planar shapes. The MOS cells 109 are arranged in a matrix, with the SBD cells of the SBD 105 sandwiched between them. That is, in both the first and second directions X and Y, for every one or more MOS cells 109 arranged (two or more, arranged adjacently), one SBD cell of the SBD 105 is arranged adjacent to the MOS cell 109. The SBD cells of the SBD 105 are preferably regularly scattered. Alternatively, one MOS cell 109 and one SBD cell of the SBD 105 may be arranged alternately and repeatedly adjacent to each other in both the first and second directions X and Y in a checkerboard pattern.

[0079] The MOS cell 109 has a planar layout of an n-type column region 93 and a p-type column region 94 of a parallel pn layer 92 that constitutes a drift layer, and a p-type base region 95 and n-type base region 96 that constitute a trench gate structure. + Type source region 96, p ++ The planar layout of the contact region 106, the trench 97, the gate insulating film 98, and the gate electrode 99 (p ++The parallel pn layer 92 differs from the MOS cell 89 of the fourth embodiment (see FIG. 1 where reference numeral 89 is used instead of reference numeral 9) in that the p-type contact region 94 is arranged in a matrix, and the n-type column regions 93 are arranged in a lattice surrounding the p-type column regions 94, as viewed from the front surface side of the semiconductor substrate 30. One MOS cell 109 is formed between the centers of adjacent gate electrodes 99. The MOS cells 109 are arranged in a matrix with the same layout as the p-type column regions 94.

[0080] The p-type base region 95 is provided in the MOS region over the entire area between the front surface of the semiconductor substrate 30 and the parallel pn layer 92. + type source region 96 and p ++ The n-type contact regions 106 are selectively provided between the front surface of the semiconductor substrate 30 and the p-type base region 95. + The source region 96 extends in a rectangular or U-shape along the trench 97. The trench 97 is formed in the MOS region so as to extend in the depth direction Z. + The trench 97 penetrates the n-type source region 96 and the p-type base region 95 to reach the n-type column region 93. The trench 97 is provided in a cross shape extending in the first and second directions X and Y along the n-type column region 93, with the center at the intersection of the lattice-like n-type column regions 93, or in a rectangular or ladder shape extending along the n-type column region 93 and surrounding the periphery of the p-type base region 95. A gate electrode 99 is provided inside the trench 97 with a gate insulating film 98 interposed therebetween.

[0081] The SBD 105 is a diode that utilizes the rectification of a Schottky barrier formed at the junction between an n-type column region 93 that reaches the front surface of the semiconductor substrate 30 and a conductive film 104 that contacts the n-type column region 93 on the front surface of the semiconductor substrate 30. One SBD cell of the SBD 105 is formed between the centers of gate electrodes 99 that are adjacent to each other in the first direction X (or the second direction Y) and sandwich a Schottky junction between the conductive film 104 and the n-type column region 93. The SBD 105 may have a JBS structure that combines a Schottky junction between the conductive film 104 and the n-type column region 93 and a pn junction between a p-type region 91 and the n-type column region 93. A plurality of p-type regions 91 that constitute the JBS structure of the SBD cell are arranged in a lattice pattern so as to form an overall cross-shaped planar shape.

[0082] Specifically, a plurality of p-type regions 91 (first p-type regions 91a) extending in stripes in the first direction X and a plurality of p-type regions 91 (second p-type regions 91b) extending in stripes in the second direction Y are arranged to intersect in a crisscross pattern. The first and second p-type regions 91a and 91b extend linearly along the n-type column regions 93 that extend linearly in the first and second directions X and Y, respectively. The width of the region in which the first and second p-type regions 91a and 91b are arranged may be wider than the width Wn of the n-type column regions 93. Between adjacent first p-type regions 91a and between adjacent second p-type regions 91b, the n-type column regions 93 or p-type column regions 94 extend directly below. The p-type regions 91 are n + The p-type region 91 is disposed apart from the p-type source region 96. ++ The p-type region 91 may contact a trench 97.

[0083] The interlayer insulating film 107 is provided over the entire front surface of the semiconductor substrate 30 and covers the gate electrode 99. The interlayer insulating film 107 is provided with a contact hole 107a for each MOS cell 109 and a contact hole 107b for each SBD cell of the SBD 105. The contact holes 107a and 107b in the interlayer insulating film 107 have a substantially rectangular planar shape with an opening area smaller than the surface area of ​​the MOS cell 109 and the SBD cell of the SBD 105, respectively. The contact holes 107a and 107b are arranged in a matrix such that the interlayer insulating film 107 remains in a lattice pattern. A barrier metal 108 is provided over the entire front surface of the semiconductor substrate 30 in the contact holes 107a and 107b. The configuration of the barrier metal 108 is the same as that of the barrier metal 88 of the fourth embodiment (see FIG. 11). The barrier metal 108 in the contact holes 107b forms a conductive film 104.

[0084] The JBS structure of the SBD 63 (see FIG. 4) of the semiconductor device 60 of the second embodiment may be applied to the SBD 105 of the semiconductor device 90 of the fifth embodiment, so that the first and second p-type regions 91a and 91b of the SBD 105 are scattered in the first and second directions X and Y, respectively.

[0085] As described above, according to the fifth embodiment, even when the cells are arranged in a matrix, it is possible to obtain the same effects as those of the fourth embodiment.

[0086] (Embodiment 6) As a structure of a semiconductor device according to a sixth embodiment, the structure of edge termination region 22 will be described. FIG. 18 is a plan view showing a layout of a semiconductor device according to the sixth embodiment as viewed from the front surface side of the semiconductor substrate. FIG. 19 is a plan view showing another example of a layout of a semiconductor device according to the sixth embodiment as viewed from the front surface side of the semiconductor substrate. FIGS. 18 and 19 show layouts of parallel pn layers 2 and 92 as viewed from the front surface side of semiconductor substrate 30 using semiconductor devices 80 and 90 (FIGS. 11 to 16) according to the fourth and fifth embodiments, respectively, as examples. FIGS. 18 and 19 each show layouts of trench 84 and gate polysilicon wiring layer 116 added to FIG. 1.

[0087] 20 to 22 are cross-sectional views showing cross-sectional structures taken along lines I-I', J-J', and K-K' in FIG. 18, respectively. FIGS. 23 to 25 are cross-sectional views showing other examples of cross-sectional structures taken along lines I-I', J-J', and K-K' in FIG. 18, respectively. The cross-sectional structures taken along lines I-I', J-J', and K-K' in FIG. 19 are obtained by replacing the reference numerals 2 to 4 in FIGS. 20 to 25 with reference numerals 92 to 94. Here, the semiconductor devices 80 and 90 according to the fourth and fifth embodiments will be described as examples, but the structure of the edge termination region 22 shown in FIGS. 20 to 25 can also be applied to the semiconductor devices 10, 60, and 70 (FIGS. 1 to 10) according to the first to third embodiments.

[0088] 18, 20 to 22, in the semiconductor device 80 according to the fourth embodiment, a plurality of MOS cells 89 are arranged adjacent to each other in a central portion 21a of the active region 21. The central portion 21a of the active region 21 is located closer to the chip center than the center of the gate electrode 86 closest to the chip end (the end of the semiconductor substrate 30) in a first direction X, which will be described later, and is located n + The drift layer in the peripheral portion 21b of the active region 21 is made up of a parallel pn layer 2 extending from the central portion 21a of the active region 21 and an n-type region 3a adjacent to the chip edge side of the parallel pn layer 2. The column region of the parallel pn layer 2 closest to the chip edge in the first direction X is a p-type column region 4.

[0089] The n-type region 3a is a region between the parallel pn layer 2 and the chip edge, and is exposed on the side surface of the chip edge. The n-type region 3a is in contact with the n-type column region 3 and the p-type column region 4, surrounds the periphery of the parallel pn layer 2, and connects all of the n-type column regions 3 to each other. In the peripheral portion 21b of the active region 21, a p-type base region 81 is provided between the front surface of the semiconductor substrate 30 and the parallel pn layer 2 and n-type region 3a. ++ The p type drain region 1 is located closest to the chip edge. +The p-type region 501 extends toward the chip edge. + The portion of p-type region 501 extending toward the chip edge side is called peripheral p-type region 111. Peripheral p-type region 111 contacts source electrode 14 at contact hole 87c in interlayer insulating film 87, and is fixed to the potential of source electrode 14.

[0090] The peripheral p-type region 111 functions to extract holes (minority carriers) accumulated in the n-type column region 3 of the edge termination region 22 to the source electrode 14 during reverse recovery of the body diode when forward current flows through the body diode of the SJ-MOSFET. + It may be the same as the mold region 501, or may be higher. For example, 1.0×10 17 / cm 3 A low carrier lifetime region 41 is provided adjacent to the peripheral p-type region 111 at a depth directly below the peripheral p-type region 111 over the entire peripheral portion 21b of the active region 21.

[0091] Contact hole 87c is provided in interlayer insulating film 87 in outer periphery 21b of active region 21 and surrounds central portion 21a of active region 21. A source contact between source electrode 14 and outer periphery p-type region 111 is formed in contact hole 87c. Forming a source contact between source electrode 14 and outer periphery p-type region 111 in outer periphery 21b of active region 21 makes it easier for holes accumulated in n-type column region 3 of edge termination region 22 to flow as reverse recovery current through outer periphery p-type region 111 during reverse recovery of the body diode of the SJ-MOSFET. Forming low carrier lifetime region 41 along the path of this hole current (reverse recovery current of the body diode) makes it easier for the hole current to flow into SBD 100, which will be described later.

[0092] A low carrier lifetime region 42 is provided inside n-type region 3a at the boundary between edge termination region 22 and active region 21, adjacent to the outer peripheral end of peripheral p-type region 111. Low carrier lifetime region 42 is formed in depth direction Z from the front surface of semiconductor substrate 30 to at least n-type region 3a and n-type region 3a. ++ The low carrier lifetime region 42 reaches the interface with the gate drain region 1. The low carrier lifetime region 42 is formed by the proton (H + The low carrier lifetime region 41 may be formed by irradiation of light ions such as argon (A) or helium (He). The light ion irradiation for forming the low carrier lifetime region 41 is performed with an irradiation dose of, for example, 1×10 11 / cm 2 More than 1×10 13 / cm 2 Preferably, irradiation is performed from the front or back surface of semiconductor substrate 30 at an acceleration voltage of about 100 keV to 2 MeV. Alternatively, low carrier lifetime region 42 may be formed using a metal mask with an electron beam to a depth that reaches from the front surface to the back surface of semiconductor substrate 30, and the electron beam irradiation dose is preferably, for example, about 20 kGy to 500 kGy. Low carrier lifetime region 42 has the function of suppressing the flow of reverse recovery current of the body diode of the SJ-MOSFET from active region 21 into edge termination region 22.

[0093] Furthermore, an SBD 100 is provided in the contact hole 87c at a position facing the p-type column region 4 in the depth direction Z. The SBD 100 is a diode that utilizes the rectification of a Schottky barrier formed at the junction between the conductive film 102 and the p-type region 101 (the hatched portion of the checkerboard pattern). The p-type region 101 is a diffusion region formed by ion implantation and thermal diffusion in the surface region of the epitaxial layer 32. A plurality of p-type regions 101 are provided in the depth direction Z at positions facing the p-type column region 4 closest to the chip end in the first direction X and the longitudinal ends of all the p-type column regions 4, to a depth that does not penetrate from the front surface of the semiconductor substrate 30 to the peripheral p-type region 111. The upper surfaces of the plurality of p-type regions 101 are in contact with the conductive film 102 and are surrounded by the peripheral p-type region 111. The peripheral p-type region 111 is interposed between adjacent p-type regions 101.

[0094] For example, the multiple p-type regions 101 may concentrically surround the periphery of the central portion 21a of the active region 21 so as to be partially discontinued in the depth direction Z at a position facing the n-type column region 3. The p-type region 101 may face, in the depth direction Z, the n-type column region 3 or the n-type region 3a adjacent to the p-type column region 4 facing it in the depth direction Z. By providing the SBD 100 in the contact hole 87c, holes accumulated in the n-type column region 3 of the edge termination region 22 are more likely to be extracted to the source electrode 14 during reverse recovery of the body diode. This reduces the number of minority carriers (holes) in the n-type column region 3 of the edge termination region 22, suppressing carrier recombination near the pn junction between the p-type column region 4 and the n-type column region 3 in the edge termination region 22, and resulting in a gradual change in the reverse recovery current of the body diode of the SJ-MOSFET (soft recovery).

[0095] An insulating layer 114 and an interlayer insulating film 87 are stacked in this order on the front surface of the semiconductor substrate 30 in the peripheral portion 21b of the active region 21 and the edge termination region 22. The insulating layer 114 is formed by stacking, in this order, a gate insulating film 85 extending from the central portion 21a of the active region 21 and a field oxide film. A gate polysilicon (poly-Si) wiring layer 116 is provided within the insulating layer 114 in the peripheral portion 21b of the active region 21. The gate polysilicon wiring layer 116 surrounds the periphery of the active region 21 in a substantially rectangular or U-shape. The gate electrodes 86 of all MOS cells 89 are connected to the gate polysilicon wiring layer 116. A gate metal wiring layer 117 contacts the gate polysilicon wiring layer 116 via a contact hole that penetrates the interlayer insulating film 87 and the insulating layer 114 in the depth direction Z. The gate metal wiring layer 117 surrounds the periphery of the active region 21 so as not to contact the source wiring layer (see FIG. 28). The gate metal wiring layer 117 is connected to the gate pad 15 (see FIG. 1). The gate polysilicon wiring layer 116 and the gate metal wiring layer 117 form a gate runner.

[0096] In edge termination region 22, between the front surface of semiconductor substrate 30 and n-type region 3a, an FLR structure is provided as a breakdown voltage structure on the chip edge side of low carrier lifetime region 42. The FLR structure is a floating p - In this structure, a plurality of FLRs 112, which are type regions, are concentrically arranged at a distance from each other around the active region 21. The FLR 112 closest to the center of the chip may be adjacent to the low carrier lifetime region 42. The impurity concentration of the FLRs 112 is, for example, 1.0×10 14 / cm 3 Over 1.0 x 10 15 / cm 3 For example, an FLR structure is provided in an opening in interlayer insulating film 87, and a plurality of contact holes exposing different FLRs 112 are provided in insulating layer 114 at the opening in interlayer insulating film 87. Field plates (FPs) 115, which are floating metal electrodes in contact with the FLRs 112, are provided in each contact hole in insulating layer 114. FPs 115 may extend from within the contact holes onto insulating layer 114.

[0097] At the outermost periphery of edge termination region 22, a p-type region is formed between the front surface of semiconductor substrate 30 and n-type region 3a, separated from the FLR structure. ++ A channel stopper region 113 is provided. ++ The channel stopper region 113 is exposed at the edge of the chip. ++ The channel stopper region 113 is provided along the outer periphery of the semiconductor substrate 30. ++ The impurity concentration of the channel stopper region 113 is, for example, 1.0×10 18 / cm 3 Over 1.0 x 10 19 / cm 3 It is about the same as below. ++ Instead of the n-type channel stopper region 113, ++A channel stopper region of a p-type may be provided. A channel stopper electrode 118 is provided on the front surface of the semiconductor substrate 30 at the outermost periphery of the edge termination region 22. The channel stopper electrode 118 is provided along the periphery of the semiconductor substrate 30. The channel stopper electrode 118 is connected to the p-type via a contact hole that penetrates the interlayer insulating film 87 and the insulating layer 114 in the depth direction Z. ++ The mold contacts the channel stopper region 113 .

[0098] 23 to 25, instead of the FLR structure, a JTE structure 121 may be provided as a breakdown voltage structure. The JTE structure 121 is a structure including a plurality of p - The p type region has a lower impurity concentration as it moves away from the center of the chip to the edge of the chip. - 23 to 25 show a structure in which a plurality of p-type regions concentrically arranged adjacent to the active region 21 are arranged so as to surround the periphery of the active region 21. - The type region is one p - The innermost end of the JTE structure 121 (the p - The p-type region 123 is in contact with the peripheral p-type region 111 and is fixed to the potential of the source electrode 14 via the peripheral p-type region 111. When the voltage-withstanding structure is a JTE structure 121, the depth position of the low carrier lifetime region 42 and the arrangement of the gate runners (gate polysilicon wiring layer 123 and gate metal wiring layer 124) differ from the structures shown in FIGS.

[0099] The low carrier lifetime region 42 extends from the interface between the JTE structure 121 and the n-type region 3 a to at least the n-type region 3 a and the n-type region 3 a. ++The gate metal wiring layer 124 extends to the interface with the gate-type drain region 1. No FP 115 is arranged, and the entire front surface of the semiconductor substrate 30 in the edge termination region 22 is covered with the insulating layer 122 and the interlayer insulating film 87. The configuration of the insulating layer 122 is similar to that of the insulating layer 114 in FIGS. 20 to 22. The gate polysilicon wiring layer 123 is provided with a width that extends from the outer periphery 21b of the active region 21 to the chip edge side of the JTE structure 121, and covers the entire periphery of the JTE structure 121 via the insulating layer 122. The gate metal wiring layer 124 extends from the outer periphery 21b of the JTE structure 121 in the depth direction Z, for example, to the outer periphery - At a position facing the mold region, the insulating layer 122 is connected to the gate polysilicon wiring layer 123 via a contact hole that penetrates the interlayer insulating film 87 and the insulating layer 122 in the depth direction Z.

[0100] 19, the outer periphery 21b of the active region 21 of the semiconductor device 90 according to the fifth embodiment is different from the semiconductor device 70 according to the fourth embodiment shown in FIG. 18 in the arrangement of the n-type column regions 93 and p-type column regions 94 of the parallel pn layer 92. Specifically, in the semiconductor device 90 according to the fifth embodiment, the n-type column regions 93 and the p-type column regions 94 are alternately and repeatedly arranged adjacent to each other around the entire outer periphery of the parallel pn layer 92 (the portion adjacent to the inner periphery of the n-type region 93a surrounding the periphery of the parallel pn layer 92). Therefore, SBDs 100 are provided in contact holes 87c of the interlayer insulating film 87 in the outer periphery 21b of the active region 21, scattered along the periphery of the parallel pn layer 92.

[0101] As described above, the sixth embodiment is applicable to the semiconductor devices according to the first to fifth embodiments.

[0102] (Embodiment 7) As the structure of the semiconductor device according to the seventh embodiment, the structure immediately below the gate pad 15 of the structure of the semiconductor device according to the sixth embodiment shown in Fig. 18 will be described. Figs. 26 to 28 are cross-sectional views showing the cross-sectional structures taken along the cutting lines L-L', M-M', and N-N' in Fig. 17, respectively. Here, the semiconductor device according to the sixth embodiment (i.e., the semiconductor device 80 according to the fourth embodiment shown in Figs. 11 to 13) will be described as an example, but the structure immediately below the gate pad 15 shown in Figs. 26 to 28 can also be applied to the semiconductor devices 10, 60, 70, and 90 according to the first to third and fifth embodiments (Figs. 1 to 10, 13 to 16, and 18).

[0103] 26 to 28, in the peripheral portion 21b of the active region 21, a gate pad 15 is provided on the front surface of the semiconductor substrate 30, with an insulating layer 114 and an interlayer insulating film 87 interposed therebetween. A gate polysilicon wiring layer 116 is provided directly below the gate pad 15, with the interlayer insulating film 87 interposed therebetween, so as to face the outer periphery of the gate pad 15 in the depth direction Z. The drift layer directly below the gate pad 15 may be formed of a parallel pn layer 2 or an n-type region 3a. The p-type base region 81 may not be provided directly below the gate pad 15, and the front surface of the semiconductor substrate 30 may coincide with the parallel pn layer 2 or the n-type region 3a. FIG. 27 is a cross-sectional view (M-M' cross section) of the p-type column region 4 of the semiconductor device according to the seventh embodiment shown in FIG. 18. In the semiconductor device according to the seventh embodiment, a p-type region 145 in contact with the front surface of the semiconductor substrate 30 and a JBS structure 144 formed by a conductive film 146 may be selectively provided within the semiconductor substrate 30 so as to surround the outer periphery of the gate pad 15.

[0104] A source wiring layer 17 is provided closer to the chip edge than the gate pad 15 and the gate metal wiring layer 117 (see FIGS. 21 and 22) (FIG. 28). The source wiring layer 17 contacts the peripheral p-type region 111 via a contact hole in the interlayer insulating film 87, and fixes the peripheral p-type region 111 to the potential of the source electrode 14. A low carrier lifetime region 41 is provided adjacent to the peripheral p-type region 111 at a depth directly below the peripheral p-type region 111 throughout the entire peripheral portion 21b of the active region 21.

[0105] A low carrier lifetime region 42 is provided inside the parallel pn layer 2 and inside the n-type region 3a, facing the outer periphery of the gate pad 15 in the depth direction Z. When the p-type base region 81 is not provided immediately below the gate pad 15, the low carrier lifetime region 42 may be provided immediately below the end of the p-type base region 81. The low carrier lifetime region 42 may be provided immediately below the end of the gate polysilicon wiring layer 116 arranged around the gate pad 15.

[0106] 29 to 31 show another example of the semiconductor device according to the seventh embodiment. The semiconductor device shown in FIGS. 29 to 31 differs from the semiconductor device shown in FIGS. 26 to 28 in that a p-type base region 81 is provided between the front surface of the semiconductor substrate 30, the parallel pn layer 2, and the n-type region 3a immediately below the gate pad 15, but the other structures are similar to those of the semiconductor device shown in FIGS. 26 to 28. The semiconductor device shown in FIGS. 29 to 31 selectively provides a p-type region 145 in contact with the front surface of the semiconductor substrate 30 and a JBS structure 144 formed by a conductive film 146, surrounding the outer periphery of the gate pad 15. Inside the JBS structure 144 to the gate pad 15, an n + type source region 82 and p ++ The mold contact region 83 may not be provided.

[0107] As described above, the seventh embodiment is applicable to the semiconductor devices according to the first to sixth embodiments.

[0108] (Embodiment 8) The structure of a semiconductor device according to the eighth embodiment will be described. FIG. 32 is a cross-sectional view showing the structure of the semiconductor device according to the eighth embodiment. FIG. 33 is a cross-sectional view showing another example of the structure of the semiconductor device according to the eighth embodiment. A semiconductor device 130 according to the eighth embodiment shown in FIG. 32 differs from the semiconductor device 10 according to the first embodiment (see FIG. 3) in that the low carrier lifetime region 41 is not provided directly below the SBD 50. By not providing the low carrier lifetime region 41 directly below the SBD 50, the SBD 50 has a low resistance, and a reverse recovery current easily flows through the SBD 50 during reverse recovery of the body diode of the SJ-MOSFET.

[0109] The semiconductor device 140 according to the eighth embodiment shown in FIG. 33 differs from the semiconductor device 130 according to the eighth embodiment shown in FIG. 32 in that the SBD 143 is formed by the conductive film 142, the n-type column region 3, and the n ++ The SBD 143 has an MPS (Merged pin / Schottky) structure that utilizes the rectification of a Schottky barrier formed between the n-type drain region 1 and the n-type base region 81. When the SBD 143 has an MPS structure, two p-type regions 141 are provided between adjacent p-type base regions 81, each in contact with one of the p-type base regions 81. An n-type column region 3 extends between the adjacent p-type regions 141 and reaches the front surface of the semiconductor substrate 30.

[0110] 32 or 33 according to the eighth embodiment may be applied to the semiconductor devices 60, 70, 80, and 90 according to the second to fifth embodiments, so that the low carrier lifetime region 41 is not provided directly below the SBDs 63, 66, 50, and 105 of the second to fifth embodiments, or the SBDs 63, 66, 50, and 105 of the second to fifth embodiments may have an MPS structure. Whether the SBDs 63, 66, 50, and 105 have a JBS structure or an MPS structure can be selected as appropriate depending on the cell pitch, the width Wn of the n-type column region 3, the impurity concentration of the p-type base region 81, and the like.

[0111] As described above, according to the eighth embodiment, the same effects as those of the first to sixth embodiments can be obtained.

[0112] The present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the present invention. For example, the present invention can also be applied to a Si semiconductor device using Si (silicon) as a semiconductor material, which has a breakdown voltage of approximately 600 V or less. Furthermore, although the first conductivity type is n-type and the second conductivity type is p-type in each embodiment, the present invention is equally valid even if the first conductivity type is p-type and the second conductivity type is n-type. [Industrial Applicability]

[0113] As described above, the semiconductor device according to the present invention is useful for power semiconductor devices used in power conversion devices and power supply devices for various industrial machines, and is particularly suitable for SJ-MOSFETs that use SiC as a semiconductor material, which has a high breakdown voltage (e.g., 3.3 kV or more) and a large chip size. [Explanation of symbols]

[0114] 1,201 n ++ Type drain region 2,92,202 parallel pn layers 3,93,203 n-type column region 3a,93a n-type region 4,94,204 p-type column region 5,75,81,95,205 p-type base region 6,76,82,96,206 n + Type Source Area 7,77,83,106,207 p ++ Mold contact area 8,78,208 JFET area 9,79,89,109 MOS cells 10,60,70,80,90,130,140,210 Semiconductor devices 11,71,85,98,211 Gate insulating film 12,72,86,99,212 gate electrode 13,73,87,107,213 Interlayer insulating film 13a, 13b, 73a, 73b, 87a, 87b, 87c, 107a, 107b Contact holes in interlayer insulating film 14,214 Source electrode 15,215 gate pads 16,216 Drain electrode 17 Source wiring layer 21,221 active area 21a Central part of the active region 21b Outer periphery of active region 22,222 Edge Termination Area 30,230 Semiconductor substrates 31n ++ Starting substrate 32 Epitaxial layer 41,42 Low carrier lifetime region 50,63,66,100,105,143,144 SBD 51,61,64,64a,64b,91,91a,91b,101,141,145 p-type region that constitutes the JBS structure of SBD 52,62,65,102,104,142,146 Conductive film of SBD 84,97 Trench 88,108 Barrier metal 111 Outer p-type region 113 pages ++ Type channel stopper region 114,122 Insulating layer 116,123 Gate polysilicon wiring layer 117,124 Gate metal wiring layer 118 Channel stopper electrode 121 JTE structure 209 cells (MOS cells) 501,502 p + type area P1 Repeat pitch of n-type column region P2 Repeat pitch of p-type column region Wn Width of n-type column region Wp Width of the p-type column region X: the first direction parallel to the front surface of the semiconductor substrate Y: A second direction parallel to the front surface of the semiconductor substrate and perpendicular to the first direction Z depth direction

Claims

1. an active region provided in a semiconductor substrate; a termination region surrounding the active region; a parallel pn layer formed in the active region within the semiconductor substrate, in which first conductivity type column regions and second conductivity type column regions are alternately and repeatedly arranged adjacent to each other in a first direction parallel to the front surface of the semiconductor substrate; a first semiconductor region of a second conductivity type selectively provided in contact with the parallel pn layer inside the semiconductor substrate; a second semiconductor region of a first conductivity type selectively provided on the front surface of the semiconductor substrate in contact with the first semiconductor region; a gate insulating film selectively provided on the front surface of the semiconductor substrate in the active region; a gate electrode provided in the active region at a position of the gate insulating film facing the semiconductor substrate; a first electrode provided on the front surface of the semiconductor substrate and in contact with the second semiconductor region; a second electrode provided on a rear surface of the semiconductor substrate; a conductive film selectively provided between the front surface of the semiconductor substrate and the first electrode, the conductive film being in contact with the first electrode and the first conductivity type column region; a Schottky barrier diode formed by a Schottky junction between the conductive film and the first conductivity type column region; a first low carrier lifetime region, into which a first carrier lifetime killer is introduced, the first low carrier lifetime region being provided within the parallel pn layer over the entire active region at a depth directly below the first semiconductor region; A semiconductor device comprising:

2. 2. The semiconductor device according to claim 1, further comprising: a second low carrier lifetime region, into which a second carrier lifetime killer is introduced, the second low carrier lifetime region being provided at the boundary between the active region and the termination region over the entire area from the top surface of the semiconductor substrate to a depth of the bottom surface of the parallel pn layer.

3. a gate pad provided on the front surface of the semiconductor substrate and spaced apart from the first electrode, the gate electrode being electrically connected to the gate electrode; 2. The semiconductor device according to claim 1, further comprising a second low carrier lifetime region, into which a second carrier lifetime killer is introduced, the second low carrier lifetime region being provided across the entire area from the front surface of the parallel pn layer to a depth of the lower surface of the parallel pn layer immediately below the outer periphery of the gate pad.

4. a third semiconductor region of a second conductivity type selectively provided between the conductive film and the first conductivity type column region in contact with the conductive film; 2. The semiconductor device according to claim 1, wherein the Schottky barrier diode has a JBS structure in which a Schottky junction between the conductive film and the first conductivity type column region and a pn junction between the third semiconductor region and the first conductivity type column region are mixed.

5. 5. The semiconductor device according to claim 4, wherein the bottom end of the third semiconductor region is at the same depth as the bottom surface of the first semiconductor region or is closer to the front surface of the semiconductor substrate than the bottom surface of the first semiconductor region.

6. 5. The semiconductor device according to claim 4, wherein the impurity concentration of the third semiconductor region is equal to or higher than the impurity concentration of the first semiconductor region.

7. a first conductivity type high concentration region having an impurity concentration higher than that of the first conductivity type column region, the first conductivity type high concentration region being provided in contact with the second electrode between the back surface of the semiconductor substrate and the parallel pn layer; 2. The semiconductor device according to claim 1, wherein the Schottky barrier diode has an MPS structure formed by Schottky junctions between the conductive film and the first conductivity type column region and the first conductivity type high concentration region.

8. 2. The semiconductor device according to claim 1, wherein a plurality of cells of an insulated gate structure constituted by the gate electrode, the gate insulating film, the first semiconductor region, and the second semiconductor region are arranged adjacent to each other in the first direction, partially sandwiching a cell of the Schottky barrier diode therebetween, and extend in a stripe pattern in a second direction that is parallel to a front surface of the semiconductor substrate and perpendicular to the first direction.

9. 2. The semiconductor device according to claim 1, wherein a plurality of cells of an insulated gate structure constituted by the gate electrode, the gate insulating film, the first semiconductor region, and the second semiconductor region are arranged in a matrix with the cells of the Schottky barrier diode partially sandwiched therebetween.

10. 2. The semiconductor device according to claim 1, wherein an insulated gate structure composed of the gate electrode, the gate insulating film, the first semiconductor region, and the second semiconductor region is a planar gate structure having the gate electrode extending along the front surface of the semiconductor substrate.

11. 2. The semiconductor device according to claim 1, wherein an insulated gate structure composed of the gate electrode, the gate insulating film, the first semiconductor region, and the second semiconductor region is a trench gate structure having the gate electrode extending in a depth direction from a front surface of the semiconductor substrate.

12. the first carrier lifetime killer is a proton or helium; The irradiation dose of the first carrier lifetime killer is 1×10 11 / cm 2 1x10 or more 13 / cm 2 2. The semiconductor device according to claim 1, wherein:

13. the second carrier lifetime killer is a proton or helium; The irradiation dose of the second carrier lifetime killer is 1×10 11 / cm 2 1x10 or more 13 / cm 2 4. The semiconductor device according to claim 2, wherein:

14. the second carrier lifetime killer is provided by electron beam irradiation, 4. The semiconductor device according to claim 2, wherein the dose of the second carrier lifetime killer is equal to or greater than 20 kGy and less than 500 kGy.

15. the first conductivity type is n-type, 2. The semiconductor device according to claim 1, wherein the conductive film is made of molybdenum.

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