COMPONENTS HAVING BILATER HERMETIC ATOMIC LAYER DEPOSITION COATINGS FOR SEMICONDUCTOR PROCESSING CHAMBERS - Patent application

Abstract

A component for use in a semiconductor processing chamber is provided. A metal or metal alloy component body has a process-facing surface. An intermediate aluminum oxide coating is disposed on the process-facing surface, the intermediate aluminum oxide coating being at least 99% pure by weight and having a porosity of less than 0.1% by volume, the intermediate aluminum oxide coating having a first thickness. A process-exposed layer is disposed on the intermediate aluminum oxide coating, the process-exposed layer comprising at least one of yttrium, hafnium, zirconium, lanthanum, magnesium, and a lanthanide, the process-exposed layer being at least 99% pure by weight, having a porosity of less than 0.1%, and having a second thickness, the second thickness being less than or equal to the first thickness.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims the benefit of priority to U.S. Application No. 63 / 420,859, filed October 31, 2022, the disclosure of which is incorporated herein by reference for all purposes. [Background technology]

[0002] The background description provided herein is intended to present the contents of the present disclosure generally. Work by the presently named inventors within the scope of what is described in this Background section, as well as aspects of the description that may not otherwise be considered prior art at the time of filing, are not admitted, expressly or impliedly, as prior art against the present disclosure.

[0003] In the formation of semiconductor devices, semiconductor processing chambers are used to process substrates. Some semiconductor processing chambers have component parts that are eroded during semiconductor processing. Coatings may be used to protect the component parts. Deposition of some coatings may occur at high temperatures that reduce the mechanical strength of the component parts. Summary of the Invention

[0004] To achieve the above, and in accordance with the objects of the present disclosure, a component for use in a semiconductor processing chamber is provided. A metal or metal alloy component body has a process-facing surface. An intermediate aluminum oxide coating is disposed on the process-facing surface, the intermediate aluminum oxide coating being at least 99% pure by weight and having a porosity of less than 0.1% by volume, the intermediate aluminum oxide coating having a first thickness. A process-exposed layer is disposed on the intermediate aluminum oxide coating, the process-exposed layer comprising at least one of yttrium, hafnium, zirconium, lanthanum, magnesium, and a lanthanide, the process-exposed layer being at least 99% pure by weight, having a porosity of less than 0.1%, and having a second thickness, the second thickness being less than or equal to the first thickness.

[0005] In another manifestation, a method is provided for fabricating a component for use in a semiconductor processing chamber. The component body is formed of a metal or metal alloy having a process-facing surface. An intermediate layer is deposited on the process-facing surface of the component body by atomic layer deposition at a first temperature, the intermediate layer having a first thickness. A process-exposed layer is deposited on the intermediate layer by atomic layer deposition at a second temperature higher than the first temperature, the process-exposed layer having a second thickness less than the first thickness.

[0006] These and other features of the present disclosure are described in more detail below in the detailed description and in conjunction with the following figures. [Brief explanation of the drawings]

[0007] The present disclosure is illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings in which like reference numerals refer to similar elements and in which:

[0008] [Figure 1] FIG. 1 is a high-level flow chart of one embodiment.

[0009] [Figure 2A] FIG. 2A is a schematic cross-sectional view of a portion of one embodiment. [Figure 2B] FIG. 2B is a schematic cross-sectional view of a portion of one embodiment.

[0010] [Figure 3] FIG. 3 is a schematic diagram of a semiconductor processing chamber that can be used in one embodiment.

[0011] In the drawings, like reference numerals may be used to denote like structural elements. It should also be understood that the depictions in the figures are schematic and not to scale. DETAILED DESCRIPTION OF THE INVENTION

[0012] The present disclosure will now be described in detail with reference to several preferred embodiments thereof, as illustrated in the accompanying drawings. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present disclosure. However, it will be apparent to one skilled in the art that the present disclosure may be practiced without some or all of these specific details. In other instances, well-known process steps and / or structures have not been described in detail in order to avoid unnecessarily obscuring the present disclosure.

[0013] Spray coating methods are used to deposit protective coatings on process-facing surfaces of semiconductor processing chamber components. These processes are relatively inexpensive, can produce coatings tens to thousands of microns thick, and are suitable for coatings with relatively complex three-dimensional topologies. However, such processes generate numerous defects and porosity. The overall effect of this processing technique is that the resulting coatings are porous, relatively rough after processing, and have localized domains (chemical reactions, stresses, and crystalline structures) that can lead to uncontrolled stresses and defects and reduced mechanical integrity. As a result, such spray coatings do not provide a sufficient hermetic seal.

[0014] Porosity can accelerate corrosive erosion or halogen conversion by plasma chemistries due to increased surface area and increased penetration depth from the surface, and / or can increase or trap redeposition of etching by-products during semiconductor processing, or a pre-coating step may be required during waferless cleaning to mitigate these deleterious properties. Rough surfaces can trap by-product adhesion, or large surface areas can be susceptible to extensive halogen conversion. Local domain structures and weak interfaces can be disrupted, leading to delamination from the coating body or preferential attack by the corrosive or plasma processing environment. All of these above effects can result in the release of nanometer- to micron-sized particles, ultimately affecting wafer etching performance.

[0015] Atomic layer deposition (ALD) techniques use multi-step deposition chemistry where each step reaches equilibrium, allowing for the formation of uniform, highly dense, and extremely high-quality molecularly smooth films regardless of substrate geometry. Most metal oxide and halide deposition processes require high temperatures (over 150 °C) to deposit aluminum oxide (Al2O3) or yttrium oxide (YO3), and over 300 °C for most other metal oxides; these temperatures detemper heat-treated aluminum. ALD processes also tend to be very slow and expensive due to precursor cycling and purging, as well as the cost of precursor chemicals. Some metal oxide coatings, such as Al2O3, can be performed relatively inexpensively due to low precursor costs, low substrate temperatures, high deposition efficiency through precursor reactions, and reduced steric hindrance. Metals with high atomic weights often require very expensive precursors, higher substrate temperatures, and can be highly porous due to steric hindrance, resulting in the deposition of fewer monolayers per chemical reaction pass. It should be noted that industrial processes are sometimes run in a mixed ALD / chemical vapor deposition (CVD) mode to increase throughput, at the expense of film quality and uniformity.

[0016] For ease of understanding, Figure 1 is a high-level flowchart of a process used in one embodiment. A component body is provided (step 104). The component body is a metal or metal alloy component body. For example, the component body may be formed from a hardened aluminum alloy, such as T6 grade 6061 aluminum. Figure 2A is a schematic cross-sectional view of a portion of a component body 204. The component body 204 has a process-facing surface 208. The process-facing surface 208 is located on the side of the component body 204 closest to the substrate being processed and / or the vacuum and / or plasma generated during semiconductor processing. In some embodiments, if the process-facing surface 208 does not have a protective coating, the process-facing surface 208 is exposed to the process plasma and / or vacuum.

[0017] An aluminum oxide coating or layer is deposited on the process-facing surface 208 by atomic layer deposition (step 108). The ALD of the intermediate aluminum oxide coating is performed at a first temperature to provide an intermediate layer having a first thickness. In some embodiments, the ALD process includes multiple cycles. In each cycle, in some embodiments, a precursor is deposited first. In some embodiments, the precursor is trimethylaluminum (Al(CH)). Next, a first purge is performed. In some embodiments, an N purge gas is flowed to purge any undeposited precursor. Next, a reactant is applied. In some embodiments, the reactant is water. The reactant oxidizes the aluminum, forming a monolayer of alumina (aluminum oxide). Next, a second purge is performed. In some embodiments, an N purge gas is flowed to purge any remaining reactant as a vapor. This cycle is repeated multiple times to form the ALD alumina coating. In some embodiments, the ALD process is plasma-less. In some embodiments, coatings may be applied to other surfaces of the component body 204 in addition to the process-facing surface 208. In some embodiments, the first temperature ranges from 100°C to 200°C. In some embodiments, the aluminum oxide coating has a thickness of 2 nm to 5 μm. In some embodiments, the aluminum oxide coating has a thickness of 30 nm to 1000 nm. In some embodiments, the ALD of the aluminum oxide coating is deposited on a native oxide layer on one or more surfaces of the component body 204.

[0018] A process-exposed layer is deposited on the aluminum oxide coating by atomic layer deposition (step 112). The ALD of the process-exposed layer is performed at a second temperature. In some embodiments, the process-exposed layer includes yttrium oxide (YO). In some embodiments, the ALD of the YO coating is performed by providing multiple cycles, each cycle depositing an yttrium layer using an yttrium precursor, such as tris(cyclopentadienyl)yttrium(III), and then oxidizing the yttrium layer, such as by providing water vapor. In some embodiments, the process-exposed layer includes at least one of magnesium, yttrium, hafnium, and a lanthanide. In some embodiments, the process-exposed layer includes at least one of YO, yttrium trifluoride (YF), yttrium oxyfluoride (YOF), magnesium fluoride (MgF), hafnium oxide (HfO), a lanthanide oxide, lanthanum fluoride, lanthanum oxide, and a lanthanide fluoride. In some embodiments, the ALD of the YO coating is performed at a temperature of 220°C. In some embodiments, the ALD deposition of the process-exposed layer is performed at a second temperature that is higher than the first temperature to provide a second thickness that is less than the first thickness. In some embodiments, the second temperature is in the range of 150°C to 400°C. In some embodiments, the second temperature is in the range of 200°C to 300°C. In some embodiments, the process-exposed layer has a thickness of 10 nm to 50 nm. In some embodiments, the process-exposed layer has a thickness of 10 nm to 200 nm. In some embodiments, the process-exposed layer has a thickness of 10 nm to 1,000 nm.

[0019] In some embodiments, the process-exposed layer comprises pyrochlore. Pyrochlore is a mineral having the general formula A2B2O7 or A2B2O6, where A and B are trivalent and tetravalent metal cations, respectively. In some embodiments, pyrochlore materials are crystalline, although their crystal structure and stoichiometry vary considerably. In some embodiments, there may be up to a 10% excess of cations in the A or B site. In some embodiments, the pyrochlore material is amorphous. In some embodiments, the pyrochlore material is a mixture of amorphous and crystalline materials. The crystalline material may be a single crystal material or a polycrystalline material. In some embodiments, the pyrochlore comprises at least one of zirconium and hafnium, and at least one of lanthanum (La), samarium (Sm), yttrium (Y), erbium (Er), cerium (Ce), gadolinium (Gd), ytterbium (Yb), and neodymium (Nd). In some embodiments, the pyrochlore comprises at least one of zirconium and hafnium, and at least one of La, Ce, and Gd. In some embodiments, the pyrochlore consists essentially of zirconium and La. In some embodiments, the pyrochlore is formed from materials that do not form volatile halides and are resistant to surface damage from ion bombardment.

[0020] In some embodiments, the process-exposed layer may be a mixed metal oxide other than pyrochlore. For example, in some embodiments, the process-exposed layer may include yttrium aluminum oxide, such as yttrium aluminum garnet (YAG), yttrium aluminum monoclinic (YAM), and yttrium aluminum perovskite (YAP). In some embodiments, the process-exposed layer includes at least one of magnesium, yttrium, hafnium, zirconium, lanthanum, and a lanthanide. In some embodiments, the process-exposed layer includes at least one of an oxide, fluoride, and oxyfluoride of at least one of yttrium, hafnium, zirconium, lanthanum, and a lanthanide.

[0021] 2B is a schematic cross-sectional view of a portion of component body 204 after an aluminum oxide coating 212 has been deposited by atomic layer deposition on process-facing surface 208 (step 108) and after a process-exposed layer 216 has been deposited by atomic layer deposition on aluminum oxide coating 212 (step 112). Aluminum oxide coating 212 has a first thickness that is greater than a second thickness, which is the thickness of process-exposed layer 216.

[0022] The component body 204 is loaded into a semiconductor processing chamber (step 116). The component body 204 is used to process the stack in the semiconductor processing chamber (step 120). In some embodiments, the semiconductor processing chamber is used to etch the stack. In some embodiments, multiple stacks are processed sequentially in the processing chamber.

[0023] In some embodiments, providing an aluminum oxide coating by ALD is less expensive than providing a process-exposed layer by ALD. By providing a thicker layer of aluminum oxide coating and then a thinner process-exposed layer, the protective performance of the component body 204 can be improved at a low cost. Additionally, in some embodiments, the first temperature used to deposit the aluminum oxide coating is lower than the second temperature used to deposit the process-exposed layer. In some embodiments, if the aluminum alloy component body 204 is maintained at the second temperature for an extended period of time, the aluminum alloy component body loses its mechanical strength. Additionally, if the component body 204 is T6 grade 6061 aluminum and maintained at the second temperature for an extended period of time, the component body loses its T6 grade. When the process-exposed layer is deposited to a thickness equal to the first thickness, the component body 204 is exposed to the second temperature for a time sufficient to cause the component body to lose its mechanical strength, its T6 grade, or both. By first applying an aluminum oxide coating to a first thickness at a first temperature, and then applying a thinner process-exposed layer to a second thickness at a second temperature higher than the first temperature, the component body 204 is exposed to the second temperature for a time short enough that the component body 204 does not lose its mechanical strength and / or T6 grade. Thus, in some embodiments, after the process-exposed layer is deposited, the component body 204 remains T6 grade 6061 aluminum. In some embodiments, the second temperature does not cause detempering or loss of mechanical strength of the component body 204. In some embodiments, the first temperature is less than 150°C and the second temperature is greater than 150°C. In some embodiments, the first temperature is less than 200°C and the second temperature is greater than 200°C.

[0024] Deposition of an aluminum oxide coating by atomic layer deposition provides a thin conformal layer. If the aluminum oxide coating is formed by anodization, ALD of the process-exposed layer may outgas the anodized aluminum coating, preventing ALD of the process-exposed layer. Additionally, in some embodiments, the ALD aluminum oxide coating is 99.9% pure by weight and has less than 0.1% porosity by volume. In some embodiments, the ALD aluminum oxide coating is 99% pure by weight and has less than 0.1% porosity by volume. Anodized aluminum oxide does not have such purity. In some embodiments, the ALD-formed process-exposed layer is 99% pure by weight and has less than 0.1% porosity by volume. In some embodiments, the ALD-formed process-exposed layer is 99.9% pure by weight and has less than 0.1% porosity by volume.

[0025] In some embodiments, the aluminum oxide coating provides a stress relief layer that reduces delamination of the process-exposed layer. Additionally, aluminum oxide coatings can be provided at a lower cost. Thicker ALD aluminum oxide coatings provide precursors with limited steric hindrance, minimizing or preventing pinhole defects. Additionally, while aluminum oxide coatings are not as etch-resistant as the process-exposed layer, they are less porous, thick enough to provide a hermetic seal, and have reasonable plasma resistance. In some embodiments, ALD of aluminum oxide can be deposited more quickly and at lower temperatures than some other ALD coatings. Even though deposition of the process-exposed layer occurs at approximately the same temperature as ALD of aluminum oxide, ALD of aluminum oxide is preferred due to its lower cost and faster speed. In some embodiments, yttria can be deposited up to 500 nm thick before there is a risk of thermal damage to the aluminum.

[0026] For ease of understanding, FIG. 3 schematically illustrates an example of a semiconductor processing chamber system 300 that can be used in one embodiment. The semiconductor processing chamber system 300 includes a plasma reactor 302 having a semiconductor processing chamber 304 therein. A plasma power supply 306, regulated by a power matching network 308, supplies power to a transformer-coupled plasma (TCP) coil 310 located near a dielectric-induced power window 312 to generate plasma 314 within the semiconductor processing chamber 304 by providing inductively coupled power. A pinnacle 372 extends from a chamber wall 376 of the semiconductor processing chamber 304 to the dielectric-induced power window 312, forming a pinnacle ring. The pinnacle 372 is angled relative to the chamber wall 376 and the dielectric-induced power window 312. For example, the interior angles between the pinnacle 372 and the chamber wall 376 and between the pinnacle 372 and the dielectric-induced power window 312 may each be greater than 90° and less than 180°. The pinnacle 372, as shown, provides an angled ring near the top of the semiconductor processing chamber 304. The pinnacle 372 is more commonly considered a chamber liner. The TCP coil (top power supply) 310 can be configured to generate a uniform diffusion profile within the semiconductor processing chamber 304. For example, the TCP coil 310 can be configured to generate a toroidal power distribution within the plasma 314. A dielectric induction power window 312 is provided to separate the TCP coil 310 from the semiconductor processing chamber 304 while allowing energy to pass from the TCP coil 310 to the semiconductor processing chamber 304. A wafer bias voltage power supply 316, regulated by a bias matching network 318, provides power to the electrode 320 to set the bias voltage when the stack is placed on the electrode 320. A process wafer 366 is placed on the electrode 320. A controller 324 controls the plasma power supply 306 and the wafer bias voltage power supply 316.

[0027] The plasma power supply 306 and wafer bias voltage power supply 316 can be configured to operate at a specific high frequency, such as 13.56 megahertz (MHz), 27 MHz, 2 MHz, 60 MHz, 400 kilohertz (KHz), 2.54 gigahertz (GHz), or a combination thereof. The plasma power supply 306 and wafer bias voltage power supply 316 can be appropriately sized to provide various ranges of power to achieve desired process performance. For example, in one embodiment, the plasma power supply 306 can provide a power range of 50 to 5,000 watts, and the wafer bias voltage power supply 316 can provide a bias voltage range of 20 to 2,000 volts (V). In addition, the TCP coil 310 and / or electrode 320 can be configured with two or more sub-coils or sub-electrodes. The sub-coils or sub-electrodes can be powered by a single power supply or by multiple power supplies.

[0028] As shown in FIG. 3 , the semiconductor processing chamber system 300 further includes a gas source / gas supply mechanism 330. The gas source 330 is fluidly connected to the semiconductor processing chamber 304 through a gas inlet, such as a gas injector 340. The gas injector 340 has at least one borehole 341 that allows gas to flow through the gas injector 340 and into the semiconductor processing chamber 304. The gas injector 340 may be located at any advantageous location within the semiconductor processing chamber 304 and may take any form for injecting gas. Preferably, however, the gas inlet may be configured to provide an “adjustable” gas injection profile. The adjustable gas injection profile allows for independent adjustment of the flow rate of each of the gases to multiple zones within the semiconductor processing chamber 304. More preferably, the gas injector is mounted to the dielectric-inductive power window 312. The gas injector may be mounted on, within, or form part of the power window. Process gases and by-products are removed from the semiconductor process chamber 304 via a pressure control valve 342 and a pump 344. The pressure control valve 342 and pump 344 also serve to maintain a specific pressure within the semiconductor processing chamber 304. The pressure control valve 342 is capable of maintaining a pressure of less than 1 torr during processing. An edge ring 360 is mounted around the top of the electrode 320. The gas source / gas delivery mechanism 330 is controlled by a controller 324. A Kiyo by Lam Research, Inc. of Fremont, California, can be used to practice one embodiment.

[0029] Various semiconductor processing chamber systems 300 can use various components having a component body 204, an aluminum oxide coating 212, and a process exposure layer 216. Such components include chamber liners, such as chamber pinnacles, and chamber walls. The component 200 can be used in other types of semiconductor processing chambers for etching, deposition, or other semiconductor processes. Examples of other types of semiconductor processing chambers in which the component 200 can be used are capacitively coupled semiconductor processing chambers and bevel semiconductor processing chambers. In some embodiments, the component can be part of a thermal atomic layer etch chamber. A thermal atomic layer etch chamber can use heat instead of plasma to facilitate the thermal etching process. In some embodiments, the process-facing surface can be a plasma-facing surface or a vacuum-facing surface, where vacuum is defined as a region of pressure less than 0.1 bar.

[0030] While the present disclosure has been described in terms of several preferred embodiments, there are alterations, modifications, substitutions, and various substitute equivalents that fall within the scope of the present disclosure. It should also be noted that there are many alternative ways of implementing the methods and apparatuses of the present disclosure. Therefore, it is intended that the following appended claims be interpreted as including all such alterations, modifications, substitutions, and various substitute equivalents that fall within the true spirit and scope of the present disclosure. As used herein, the phrase "A, B, or C" should be interpreted in a non-exclusive logical "OR" sense ("A or B or C") and not in the sense of "only one of A or B or C." Each step in a process may be optional and not required. Different embodiments may omit one or more steps or perform steps in a different order. Additionally, various embodiments may perform different steps simultaneously rather than sequentially.

Claims

1. 1. A component for use in a semiconductor processing chamber, comprising: a metal or metal alloy component body having a process-facing surface; an intermediate aluminum oxide coating on the process-facing surface, the intermediate aluminum oxide coating being at least 99% pure by weight, having a porosity of less than 0.1% by volume, and having a first thickness; a process-exposed layer on the intermediate aluminum oxide coating, the process-exposed layer comprising at least one of yttrium, hafnium, zirconium, lanthanum, magnesium, and a lanthanide, the process-exposed layer being at least 99% pure by weight, having a porosity of less than 0.1%, and having a second thickness, the second thickness being less than or equal to the first thickness; A component comprising:

2. 10. A component according to claim 1, A component wherein the component body is aluminum or an aluminum alloy.

3. Component according to claim 1, The process exposed layer is Y ２ O ３ , Y.F. ３ , YOF, HfO ２ , a lanthanide oxide, lanthanum oxide, lanthanum fluoride, yttrium aluminum oxide, magnesium fluoride, and at least one of a lanthanide fluoride.

4. Component according to claim 1, The component, wherein the first thickness is in the range of 30 nm to 1000 nm.

5. 10. A component according to claim 1, The second thickness is in the range of 10 nm to 1000 nm.

6. Component according to claim 1, A component wherein the component body is T6 grade 6061 aluminum.

7. Component according to claim 1, The component, wherein the process exposed layer comprises a mixed metal oxide comprising at least one of zirconium and hafnium, and at least one of lanthanum, samarium, yttrium, erbium, cerium, gadolinium, ytterbium, and neodymium.

8. Component according to claim 1, The component, wherein the process exposed layer comprises a mixed metal oxide comprising at least one of zirconium and hafnium, and at least one of lanthanum, cerium, and gadolinium.

9. Component according to claim 1, The process-exposed layer is made of MgF ２ , Y ２ O ３ , Y.F. ３ , HfO ２ and yttrium aluminum oxide.

10. 1. A method for fabricating a component for use in a semiconductor processing chamber, comprising: forming a metal or metal alloy component body having a process-facing surface; depositing an intermediate layer on the process-facing surface of the component body by atomic layer deposition at a first temperature, the intermediate layer having a first thickness; depositing a process-exposed layer on the intermediate layer by atomic layer deposition at a second temperature greater than the first temperature, the process-exposed layer having a second thickness less than the first thickness.

11. 11. The method of claim 10, The process-exposed layer is made of MgF ２ , Y ２ O ３ , Y.O.F., Y.F. ３ , HfO ２ , lanthanide oxide, lanthanum oxide, lanthanum fluoride, yttrium aluminum oxide, and at least one of lanthanide fluorides.

12. 11. The method of claim 10, The method wherein the intermediate layer is an aluminum oxide coating.

13. 11. The method of claim 10, The method, wherein the first thickness is in the range of 30 nm to 1000 nm.

14. 14. The method of claim 13, The method, wherein the second thickness is in the range of 10 nm to 1000 nm.

15. 11. The method of claim 10, The method wherein the component body is T6 grade 6061 aluminum.

16. 11. The method of claim 10, The method, wherein the first temperature is less than 200°C and the second temperature is greater than 200°C.

17. 11. The method of claim 10, further comprising: Mounting the component in a semiconductor processing chamber; Using said component in said semiconductor processing chamber A method comprising:

18. 11. The method of claim 10, The method, wherein the process exposed layer comprises a mixed metal oxide comprising at least one of zirconium and hafnium, and at least one of lanthanum, samarium, yttrium, erbium, cerium, gadolinium, ytterbium, and neodymium.

19. 11. The method of claim 10, The method, wherein the process exposed layer comprises a mixed metal oxide comprising at least one of zirconium and hafnium, and at least one of lanthanum, cerium, and gadolinium.

20. 11. The method of claim 10, The process exposed layer is Y ２ O ３ , Y.F. ３ , HfO ２ , MgF ２ and yttrium aluminum oxide.

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