Storage device

Abstract

To provide a storage device with high storage capacity and low consumption power.SOLUTION: A storage device includes a first layer and a second layer including the first layer. The first layer includes a circuit and the second layer includes a first memory cell. The circuit includes a bit line driver circuit that transmits a signal to the first memory cell, and / or a word line driver circuit. The first memory cell includes a first transistor, a second transistor, a conductor, and an MTJ element. The MTJ element includes a free layer. The free layer is electrically connected to the conductor, and a first terminal of the first transistor is electrically connected to the first terminal of the second transistor through the conductor. In addition, the free layer exists over the conductor. The circuit includes a transistor containing silicon in the channel formation region. In the channel formation region of each of the first transistor and the second transistor, metal oxide is included.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] One embodiment of the present invention relates to a storage device and an electronic device.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. The technical field of the invention disclosed in this specification relates to an object, an operating method, or a manufacturing method. Alternatively, one embodiment of the present invention relates to a process, a machine, manufacture, or a composition of matter. Therefore, more specific examples of the technical field of one embodiment of the present invention disclosed in this specification include semiconductor devices, display devices, liquid crystal display devices, light-emitting devices, power storage devices, imaging devices, memory devices, signal processing devices, sensors, processors, electronic devices, systems, driving methods thereof, manufacturing methods thereof, and inspection methods thereof. [Background technology]

[0003] In recent years, with the increase in the amount of data handled, there has been a demand for memory devices with larger storage capacities. In order to increase the storage capacity per unit area, it is effective to form memory cells by stacking them, as in 3D NAND type memory devices (see Patent Documents 1, 2, and 3). By stacking memory cells, the storage capacity per unit area can be increased according to the number of stacked memory cells. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] US Patent Application Publication No. 2011 / 0065270 [Patent Document 2] US Patent Application Publication No. 2016 / 0149004 [Patent Document 3] US Patent Application Publication No. 2013 / 0069052 Summary of the Invention [Problem to be solved by the invention]

[0005] Storage devices used in computer cache memories, main memories, and the like are required to have short access times, in other words, fast write and read speeds, for example. For example, the access times (sometimes called delay times or latencies) of SRAM (Static Random Access Memory) and DRAM (Dynamic Random Access Memory) are approximately several nanoseconds to several tens of nanoseconds, and therefore they are used as computer cache memories, main memories, and the like. However, because SRAM and DRAM are volatile memories, their power consumption can be high while data is being retained. Therefore, storage devices used in computer cache memories and main memories are required to have not only large storage capacities but also low power consumption.

[0006] An object of one embodiment of the present invention is to provide a storage device with low power consumption, or to provide a storage device with a large storage capacity.

[0007] Another object of one embodiment of the present invention is to provide a novel memory device or an electronic device including the memory device.

[0008] Note that the problems of one embodiment of the present invention are not limited to the problems listed above. The problems listed above do not preclude the existence of other problems. Note that the other problems are problems not mentioned in this section, which will be described below. Problems not mentioned in this section can be derived by a person skilled in the art from the description in the specification or drawings, and can be appropriately extracted from these descriptions. Note that one embodiment of the present invention solves at least one of the problems listed above and other problems. Note that one embodiment of the present invention does not necessarily solve all of the problems listed above and other problems. [Means for solving the problem]

[0009] (1) One embodiment of the present invention is a memory device having a first layer and a second layer overlapping the first layer. The first layer has a circuit, and the second layer has a first memory cell. The circuit has a bit line driver circuit and / or a word line driver circuit that transmits a signal to the first memory cell. The first memory cell has a first transistor, a second transistor, a conductor, and an MTJ element, and the MTJ element has a free layer. The free layer is electrically connected to the conductor, and a first terminal of the first transistor is electrically connected to a first terminal of the second transistor via the conductor. The circuit has transistors whose channel formation regions include silicon, and each of the first transistor and the second transistor includes a metal oxide in the channel formation region.

[0010] (2) Alternatively, one embodiment of the present invention is a memory device having a first layer and a second layer overlapping the first layer, and different from the configuration of (1) above. The first layer has a circuit, and the second layer has a first memory cell. The circuit has a bit line driver circuit and / or a word line driver circuit that transmits a signal to the first memory cell. The first memory cell has a first transistor, a second transistor, a conductor, and an MTJ element, and the MTJ element has a free layer and a fixed layer. The free layer is electrically connected to the conductor, a first terminal of the first transistor is electrically connected to a first terminal of the second transistor, a second terminal of the second transistor is electrically connected to the conductor, and the second terminal of the first transistor is electrically connected to the fixed layer. The fixed layer is located above the free layer. The circuit has transistors whose channel formation regions include silicon, and each of the first transistor and the second transistor includes a metal oxide in the channel formation region.

[0011] (3) Alternatively, in one aspect of the present invention, in the above-mentioned (1) or (2), the conductor preferably includes a metal material in which the spin Hall effect occurs when a current flows.

[0012] (4) Alternatively, in one embodiment of the present invention, in any one of the above (1) to (3), a third layer may be included. Note that the third layer preferably includes a second memory cell and is stacked on the second layer.

[0013] (5) Another embodiment of the present invention is an electronic device including the storage device according to any one of (1) to (4) above and a housing.

[0014] In this specification and the like, a semiconductor device is a device that utilizes semiconductor characteristics, and refers to a circuit including a semiconductor element (transistor, diode, photodiode, etc.), a device having such a circuit, etc. It also refers to any device that can function by utilizing semiconductor characteristics. For example, an integrated circuit, a chip including an integrated circuit, an electronic component in which a chip is housed in a package, etc. are examples of semiconductor devices. Furthermore, memory devices, display devices, light-emitting devices, lighting devices, electronic devices, etc. are themselves semiconductor devices and may include semiconductor devices.

[0015] Furthermore, when it is stated in this specification that X and Y are connected, it is understood that the following cases are disclosed in this specification: when X and Y are electrically connected, when X and Y are functionally connected, and when X and Y are directly connected. Therefore, it is not limited to a predetermined connection relationship, for example, a connection relationship shown in a figure or text, and it is understood that connections other than those shown in a figure or text are also disclosed in a figure or text. X and Y are understood to be objects (e.g., a device, an element, a circuit, wiring, an electrode, a terminal, a conductive film, a layer, etc.).

[0016] As an example of a case where X and Y are electrically connected, one or more elements (for example, a switch, a transistor, a capacitance element, an inductor, a resistance element, a diode, a display device, a light-emitting device, a load, etc.) that enable the electrical connection between X and Y can be connected between X and Y. The switch has a function of controlling on / off. In other words, the switch has a function of being in a conductive state (on state) or a non-conductive state (off state), and controls whether or not a current flows.

[0017] As an example of a case where X and Y are functionally connected, one or more circuits that enable the functional connection between X and Y (for example, logic circuits (inverters, NAND circuits, NOR circuits, etc.), signal conversion circuits (digital-analog conversion circuits, analog-digital conversion circuits, gamma correction circuits, etc.), potential level conversion circuits (power supply circuits (boosting circuits, step-down circuits, etc.), level shifter circuits that change the potential level of signals, etc.), voltage sources, current sources, switching circuits, amplifier circuits (circuits that can increase the signal amplitude or current amount, operational amplifiers, differential amplifier circuits, source follower circuits, buffer circuits, etc.), signal generation circuits, memory circuits, control circuits, etc.) can be connected between X and Y. As an example, even if another circuit is sandwiched between X and Y, if a signal output from X is transmitted to Y, X and Y are considered to be functionally connected.

[0018] When it is explicitly stated that X and Y are electrically connected, this includes the case where X and Y are electrically connected (i.e., the case where X and Y are connected with another element or circuit between them) and the case where X and Y are directly connected (i.e., the case where X and Y are connected without another element or circuit between them).

[0019] Furthermore, for example, it can be expressed as follows: "X, Y, and the source (or first terminal, etc.) and drain (or second terminal, etc.) of the transistor are electrically connected to each other, and are electrically connected in the order of X, the source (or first terminal, etc.) of the transistor, the drain (or second terminal, etc.) of the transistor, and Y." Or, it can be expressed as follows: "The source (or first terminal, etc.) of the transistor is electrically connected to X, and the drain (or second terminal, etc.) of the transistor is electrically connected to Y, and X, the source (or first terminal, etc.) of the transistor, the drain (or second terminal, etc.) of the transistor, and Y are electrically connected in this order." Or, it can be expressed as follows: "X is electrically connected to Y via the source (or first terminal, etc.) and drain (or second terminal, etc.) of the transistor, and X, the source (or first terminal, etc.) of the transistor, the drain (or second terminal, etc.) of the transistor, and Y are provided in this connection order." By using expressions similar to these examples to define the order of connections in a circuit configuration, the source (or first terminal, etc.) and drain (or second terminal, etc.) of a transistor can be distinguished and the technical scope can be determined. Note that these expressions are merely examples and are not limiting. Here, X and Y are assumed to be objects (e.g., devices, elements, circuits, wiring, electrodes, terminals, conductive films, layers, etc.).

[0020] Note that even when independent components are shown electrically connected in a circuit diagram, one component may have the functions of multiple components. For example, if part of a wiring also functions as an electrode, one conductive film has the functions of both wiring and an electrode. Therefore, the term "electrically connected" in this specification also includes such cases where one conductive film has the functions of multiple components.

[0021] Furthermore, in this specification and the like, a "resistance element" can be, for example, a circuit element, wiring, or the like having a resistance value higher than 0 Ω. Therefore, in this specification and the like, a "resistance element" is intended to include wiring having a resistance value, a transistor in which a current flows between the source and drain, a diode, a coil, and the like. Therefore, the term "resistance element" can be replaced with terms such as "resistance," "load," or "region having a resistance value," and conversely, the terms "resistance," "load," or "region having a resistance value" can be replaced with terms such as "resistance element." The resistance value can be, for example, preferably 1 mΩ or more and 10 Ω or less, more preferably 5 mΩ or more and 5 Ω or less, and even more preferably 10 mΩ or more and 1 Ω or less. Furthermore, for example, a resistance value of 1 Ω or more and 1×10 9 It may be set to Ω or less.

[0022] Furthermore, in this specification, a "capacitive element" can refer to, for example, a circuit element having a capacitance value higher than 0 F, a wiring region having a capacitance value, a parasitic capacitance, a gate capacitance of a transistor, etc. Therefore, in this specification, terms such as "capacitive element," "parasitic capacitance," and "gate capacitance" can be replaced with terms such as "capacitance," and conversely, the term "capacitance" can be replaced with terms such as "capacitive element," "parasitic capacitance," and "gate capacitance." Furthermore, the term "pair of electrodes" in "capacitance" can be replaced with "pair of conductors," "pair of conductive regions," "pair of regions," etc. The value of the capacitance can be, for example, 0.05 fF or more and 10 pF or less. It may also be, for example, 1 pF or more and 10 μF or less.

[0023] In this specification, a transistor has three terminals called a gate, a source, and a drain. The gate is a control terminal that controls the conduction state of the transistor. The two terminals that function as a source or a drain are input / output terminals of the transistor. One of the two input / output terminals serves as a source and the other as a drain depending on the conductivity type (n-channel or p-channel) of the transistor and the level of the potential applied to the three terminals of the transistor. Therefore, in this specification, the terms source and drain are interchangeable. In addition, in this specification, when describing the connection relationship of a transistor, the terms "one of the source or drain" (or first electrode or first terminal) and "the other of the source or drain" (or second electrode or second terminal) are used. Note that, depending on the structure of a transistor, a backgate may be included in addition to the three terminals described above. In this case, in this specification, one of the gate or backgate of the transistor may be referred to as a first gate, and the other of the gate or backgate of the transistor may be referred to as a second gate. Furthermore, for the same transistor, the terms "gate" and "backgate" may be interchangeable. Furthermore, when a transistor has three or more gates, the gates may be referred to as a first gate, a second gate, a third gate, and so on in this specification and the like.

[0024] Furthermore, even when a single circuit element is shown on a circuit diagram, the circuit element may comprise multiple circuit elements. For example, when a circuit diagram shows one resistor, this includes two or more resistors electrically connected in series. For example, when a circuit diagram shows one capacitor, this includes two or more capacitors electrically connected in parallel. For example, when a circuit diagram shows one transistor, this includes two or more transistors electrically connected in series, with the gates of the respective transistors electrically connected to each other. Similarly, when a circuit diagram shows one switch, this includes two or more transistors electrically connected in series, with the gates of the respective transistors electrically connected to each other.

[0025] Furthermore, in this specification and the like, a node can be referred to as a terminal, a wiring, an electrode, a conductive layer, a conductor, an impurity region, etc. depending on the circuit configuration, device structure, etc. Furthermore, a terminal, a wiring, etc. can be referred to as a node.

[0026] Furthermore, in this specification and the like, the terms "voltage" and "potential" can be interchanged as appropriate. "Voltage" refers to the potential difference from a reference potential. For example, if the reference potential is the ground potential (earth potential), then "voltage" can be interchanged with "potential." Note that ground potential does not necessarily mean 0 V. Furthermore, potential is relative, and as the reference potential changes, the potential applied to wiring, the potential applied to a circuit, etc., the potential output from a circuit, etc. also changes.

[0027] Furthermore, in this specification, the terms "high-level potential" and "low-level potential" do not refer to specific potentials. For example, when two wirings are both described as "functioning as wirings that supply a high-level potential," the high-level potentials provided by both wirings do not have to be equal to each other. Similarly, when two wirings are both described as "functioning as wirings that supply a low-level potential," the low-level potentials provided by both wirings do not have to be equal to each other.

[0028] "Current" refers to the phenomenon of charge transfer (electrical conduction). For example, a statement that "electrical conduction of a positively charged body is occurring" can be rephrased as "electrical conduction of a negatively charged body is occurring in the opposite direction." Therefore, in this specification, unless otherwise specified, "current" refers to the phenomenon of charge transfer (electrical conduction) associated with the movement of carriers. The carriers referred to here include electrons, holes, anions, cations, complex ions, etc., and the carriers differ depending on the system through which the current flows (e.g., semiconductor, metal, electrolyte, vacuum, etc.). Furthermore, the "direction of current" in wiring, etc., refers to the direction in which positively charged carriers move and is expressed as a positive current amount. In other words, the direction in which negatively charged carriers move is opposite to the direction of current flow and is expressed as a negative current amount. Therefore, in this specification, etc., unless otherwise specified regarding the positive or negative sign of the current (or the direction of current), a statement such as "current flows from element A to element B" can be rephrased as "current flows from element B to element A," etc. Furthermore, statements such as "current is input to element A" can be rephrased as "current is output from element A" or the like.

[0029] Furthermore, in this specification, the ordinal numbers "first," "second," and "third" are used to avoid confusion between components. Therefore, they do not limit the number of components. Furthermore, they do not limit the order of the components. For example, a component referred to as "first" in one embodiment of this specification may be a component referred to as "second" in another embodiment or in the claims. Furthermore, for example, a component referred to as "first" in one embodiment of this specification may be omitted in another embodiment or in the claims.

[0030] Furthermore, in this specification, terms indicating position, such as "above" and "below," may be used for convenience in describing the positional relationship between components with reference to the drawings. Furthermore, the positional relationship between components changes as appropriate depending on the direction in which each component is depicted. Therefore, the terms are not limited to those used in the specification, and can be rephrased appropriately depending on the situation. For example, the expression "insulator located on the upper surface of a conductor" can be rephrased as "insulator located on the lower surface of a conductor" by rotating the orientation of the drawing 180 degrees.

[0031] Furthermore, terms such as "above" and "below" do not limit the positional relationship of components to being directly above or below and in direct contact with each other. For example, the expression "electrode B on insulating layer A" does not require that electrode B be formed on insulating layer A in direct contact with it, and does not exclude the inclusion of other components between insulating layer A and electrode B.

[0032] Furthermore, in this specification and the like, terms such as "film" and "layer" can be interchanged depending on the situation. For example, the term "conductive layer" may be interchanged with the term "conductive film." Or, for example, the term "insulating film" may be interchanged with the term "insulating layer." Or, in some cases or depending on the situation, terms such as "film" and "layer" may not be used and may be interchanged with other terms. For example, the terms "conductive layer" or "conductive film" may be interchanged with the term "conductor." Or, for example, the terms "insulating layer" and "insulating film" may be interchanged with the term "insulator."

[0033] Furthermore, in this specification and the like, terms such as "electrode," "wiring," and "terminal" do not functionally limit these components. For example, an "electrode" may be used as part of a "wiring," and vice versa. Furthermore, the terms "electrode" and / or "wiring" include cases where multiple "electrodes" and / or "wirings" are integrally formed. Furthermore, for example, a "terminal" may be used as part of a "wiring" and / or "electrode," and vice versa. Furthermore, the term "terminal" includes cases where multiple "electrodes," "wirings," "terminals," etc. are integrally formed. Therefore, for example, an "electrode" can be part of a "wiring" or "terminal," and a "terminal" can be part of a "wiring" or "electrode." Furthermore, terms such as "electrode," "wiring," and "terminal" may be replaced with terms such as "region" in some cases.

[0034] Furthermore, in this specification and the like, terms such as "wiring," "signal line," and "power line" may be interchangeable depending on the circumstances. For example, the term "wiring" may be changed to the term "signal line." For example, the term "wiring" may be changed to the term "power line." Vice versa, terms such as "signal line" and "power line" may be changed to the term "wiring." A term such as "power line" may be changed to the term "signal line." Vice versa, terms such as "signal line" may be changed to the term "power line." Furthermore, the term "potential" applied to a wiring may be changed to the term "signal" depending on the circumstances. Vice versa, terms such as "signal" may be changed to the term "potential."

[0035] In this specification and the like, the term "impurities" in semiconductors refers to, for example, elements other than the main components constituting the semiconductor layer. For example, an element with a concentration of less than 0.1 atomic % is an impurity. The presence of impurities can cause, for example, an increase in the defect level density of the semiconductor, a decrease in carrier mobility, and a decrease in crystallinity. When the semiconductor is an oxide semiconductor, impurities that change the semiconductor characteristics include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and transition metals other than the main components, particularly, for example, hydrogen (also contained in water), lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen. Specifically, when the semiconductor is a silicon layer, impurities that change the semiconductor characteristics include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 15 elements excluding hydrogen, and oxygen.

[0036] In this specification and the like, a switch refers to a device that has the function of being in a conductive state (on state) or a non-conductive state (off state) and controlling whether or not a current flows. Alternatively, a switch refers to a device that has the function of selecting and switching a path through which a current flows. As an example, an electrical switch, a mechanical switch, or the like can be used. In other words, the switch is not limited to a specific one as long as it can control a current.

[0037] Examples of electrical switches include transistors (e.g., bipolar transistors, MOS transistors, etc.), diodes (e.g., PN diodes, PIN diodes, Schottky diodes, MIM (Metal Insulator Metal) diodes, MIS (Metal Insulator Semiconductor) diodes, diode-connected transistors, etc.), and logic circuits combining these. When a transistor is used as a switch, the "conductive state" of the transistor refers to a state in which the source electrode and drain electrode of the transistor can be considered to be electrically short-circuited. The "non-conductive state" of the transistor refers to a state in which the source electrode and drain electrode of the transistor can be considered to be electrically disconnected. When a transistor is operated simply as a switch, the polarity (conductivity type) of the transistor is not particularly limited.

[0038] An example of a mechanical switch is a switch that uses MEMS (microelectromechanical systems) technology. This switch has a mechanically movable electrode, and the movement of the electrode controls whether the switch is conductive or non-conductive.

[0039] In this specification, "parallel" refers to a state in which two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, it also includes cases where the angle is -5° or more and 5° or less. Furthermore, "substantially parallel" or "roughly parallel" refers to a state in which two straight lines are arranged at an angle of -30° or more and 30° or less. Furthermore, "perpendicular" refers to a state in which two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, it also includes cases where the angle is 85° or more and 95° or less. Furthermore, "substantially perpendicular" or "approximately perpendicular" refers to a state in which two straight lines are arranged at an angle of 60° or more and 120° or less. [Effects of the Invention]

[0040] According to one embodiment of the present invention, a storage device with low power consumption or a storage device with large storage capacity can be provided.

[0041] According to one embodiment of the present invention, a novel memory device or the like can be provided. Alternatively, according to one embodiment of the present invention, an electronic device including the memory device can be provided.

[0042] The effects of one embodiment of the present invention are not limited to the effects listed above. The effects listed above do not preclude the existence of other effects. The other effects are described below and are not mentioned in this section. Effects not mentioned in this section can be derived by a person skilled in the art from the description in the specification or drawings, and can be extracted as appropriate from these descriptions. One embodiment of the present invention has at least one of the effects listed above and other effects. Therefore, one embodiment of the present invention may not have the effects listed above in some cases. [Brief explanation of the drawings]

[0043] [Figure 1] 1A and 1B are block diagrams showing examples of the configuration of a storage device. [Figure 2] FIG. 2 is a block diagram showing an example of the configuration of a storage device. [Figure 3]3A to 3D are circuit diagrams showing examples of the configuration of a memory cell. [Figure 4] FIG. 4 is a schematic diagram illustrating an example of the configuration of a memory element included in a memory cell. [Figure 5] 5A and 5B are block diagrams showing examples of the configuration of a storage device. [Figure 6] 6A to 6C are circuit diagrams showing examples of the configuration of a memory cell. [Figure 7] FIG. 7 is a cross-sectional view showing a configuration example of a storage device. [Figure 8] 8A to 8C are cross-sectional views showing examples of the structure of a transistor. [Figure 9] FIG. 9 is a schematic cross-sectional view showing a configuration example of a storage device. [Figure 10] FIG. 10 is a cross-sectional view showing a configuration example of a storage device. [Figure 11] FIG. 11A is a diagram illustrating the classification of IGZO crystal structures, FIG. 11B is a diagram illustrating the XRD spectrum of crystalline IGZO, and FIG. 11C is a diagram illustrating the electron microbeam diffraction pattern of crystalline IGZO. [Figure 12] FIG. 12A is a perspective view showing an example of a semiconductor wafer, FIG. 12B is a perspective view showing an example of a chip, and FIGS. 12C and 12D are perspective views showing an example of an electronic component. [Figure 13] FIG. 13 is a block diagram illustrating the CPU. [Figure 14] 14A to 14J are perspective views or schematic diagrams illustrating an example of a product. [Figure 15] 15A to 15E are perspective views or schematic diagrams for explaining an example of a product. DETAILED DESCRIPTION OF THE INVENTION

[0044] In this specification and the like, a metal oxide refers to an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as oxide semiconductors or simply as OSs), and the like. For example, when a metal oxide is used in the active layer of a transistor, the metal oxide may be referred to as an oxide semiconductor. That is, when a metal oxide can form a channel formation region of a transistor having at least one of an amplifying function, a rectifying function, and a switching function, the metal oxide can be referred to as a metal oxide semiconductor. Furthermore, an OS transistor can be rephrased as a transistor having a metal oxide or an oxide semiconductor.

[0045] In this specification and the like, nitrogen-containing metal oxides may also be collectively referred to as metal oxides. Nitrogen-containing metal oxides may also be referred to as metal oxynitrides.

[0046] In this specification and the like, the configurations shown in each embodiment can be combined as appropriate with the configurations shown in other embodiments to form one aspect of the present invention. In addition, when multiple configuration examples are shown in one embodiment, the configuration examples can be combined as appropriate with each other.

[0047] In addition, the content (or even part of the content) described in one embodiment can be applied, combined, or replaced with at least one of another content (or even part of the content) described in that embodiment and another content (or even part of the content) described in one or more other embodiments.

[0048] The contents described in the embodiments refer to the contents described in each embodiment using various figures or the contents described using text in the specification.

[0049] Furthermore, a figure (or even a part thereof) described in one embodiment can be combined with another part of that figure, another figure (or even a part thereof) described in that embodiment, and at least one figure (or even a part thereof) described in one or more other embodiments to form even more figures.

[0050] The embodiments described in this specification will be described with reference to the drawings. However, it will be readily understood by those skilled in the art that the embodiments can be implemented in many different ways, and that various changes in form and details can be made without departing from the spirit and scope of the invention. Therefore, the present invention should not be interpreted as being limited to the description of the embodiments. Note that in the configuration of the invention of the embodiments, the same reference numerals are used in different drawings for the same parts or parts having similar functions, and repeated description thereof may be omitted. Also, in perspective views and the like, the description of some components may be omitted to ensure clarity of the drawings.

[0051] In this specification, when the same symbol is used for multiple elements, and particularly when it is necessary to distinguish between them, an identification symbol such as “_1”, “[n]”, or “[m,n]” may be added to the symbol.

[0052] In addition, in the drawings of this specification, the size, layer thickness, or region may be exaggerated for clarity. Therefore, the drawings are not necessarily limited to the scale. Note that the drawings are schematic illustrations of ideal examples, and are not limited to the shapes or values ​​shown in the drawings. For example, variations in signals, voltages, or currents due to noise, or variations in signals, voltages, or currents due to timing differences may be included.

[0053] (Embodiment 1) In this embodiment, a memory device according to one embodiment of the present invention will be described.

[0054] <Storage device configuration example> 2 shows the configuration of a memory device of one embodiment of the present invention. The memory device MDV includes a peripheral circuit PHL and a memory cell array MCA. The peripheral circuit PHL includes a row decoder 2621, a word line driver circuit 2622, a bit line driver circuit 2630, an output circuit 2640, and a control logic circuit 2660.

[0055] The bit line driver circuit 2630 includes a column decoder 2631, a precharge circuit 2632, a sense amplifier 2633, and a write circuit 2634. The precharge circuit 2632 has a function of precharging wiring (not shown in FIG. 2) electrically connected to a memory cell MC (described later) to a predetermined potential. The sense amplifier 2633 has a function of acquiring a potential (or current) read from the memory cell MC as a data signal and amplifying the data signal. The amplified data signal is output to the outside of the memory device MDV via an output circuit 2640 as a digital data signal RDATA.

[0056] Furthermore, the memory device MDV is supplied with a low power supply voltage (VSS), a high power supply voltage (VDD) for the peripheral circuit PHL, and a power supply voltage (VIL) for the memory cell array MCA from the outside as power supply voltages.

[0057] Furthermore, control signals (CE, WE, RE), an address signal ADDR, and a data signal WDATA are input to the memory device MDV from the outside. The address signal ADDR is input to a row decoder 2621 and a column decoder 2631, and the data signal WDATA is input to a write circuit 2634.

[0058] The control logic circuit 2660 processes external input signals (CE, WE, RE) to generate control signals for the row decoder 2621 and column decoder 2631. CE is a chip enable signal, WE is a write enable signal, and RE is a read enable signal. The signals processed by the control logic circuit 2660 are not limited to these, and other control signals may be input as necessary.

[0059] It should be noted that the above-mentioned circuits and signals can be appropriately selected or omitted as required.

[0060] Note that the configuration example of this embodiment is not limited to the configuration in Fig. 2. For example, the configuration may be changed as appropriate, such as providing all or part of the peripheral circuit PHL in a layer below the memory cell array MCA.

[0061] Specifically, for example, as shown in FIG. 1A, the memory device MDV may have a configuration in which the peripheral circuit PHL is provided in a lower layer and the memory cell array MCA is provided above the peripheral circuit PHL.

[0062] In the memory device MDV of Fig. 1A, the memory cell array MCA has, as an example, m × n memory cells MC. In the memory cell array MCA, the memory cells MC are arranged in a matrix of m rows and n columns. Note that Fig. 1A shows only memory cells MC[1,1], memory cells MC[m,1], memory cells MC[1,n], and memory cells MC[m,n] from among the multiple memory cells MC.

[0063] 1A, the peripheral circuit PHL includes a circuit WD, a circuit BD, a circuit SD, a circuit CLC, and a circuit OPC. The peripheral circuit PHL does not necessarily have to include all of the circuits WD, BD, SD, CLC, and OPC, but may include one or more circuits selected from the circuits WD, BD, SD, CLC, and OPC.

[0064] For example, the circuit WD may be a circuit corresponding to the word line driver circuit 2622 in Figure 2. For example, the circuit WD is electrically connected to the wirings WL[1] to WL[m]. The circuit WD transmits selection signals to a plurality of memory cells MC included in the memory cell array MCA via the wirings WL[1] to WL[m].

[0065] Note that, although FIG. 1A shows an example in which one wiring WL[1] to one wiring WL[m] are provided for each row of the memory cell array MCA, multiple wirings may be provided for one row of the memory cell array MCA.

[0066] 2. The circuit BD may be, for example, a circuit corresponding to the bit line driver circuit 2630 in FIG. 2. The circuit BD is electrically connected to the wirings BL[1] to BL[n]. The circuit BD functions as a circuit for transmitting a write signal to the memory cells MC included in the memory cell array MCA via the wirings BL[1] to BL[n]. The circuit BD also functions as a circuit for applying a predetermined voltage or current to the memory cells MC included in the memory cell array MCA via the wirings BL[1] to BL[n] during reading.

[0067] 1A shows an example in which one wiring BL[1] to one wiring BL[n] is provided for each column of the memory cell array MCA, but multiple wirings may be provided for one column of the memory cell array MCA. For example, a wiring for transmitting a write signal and a wiring for transmitting a read signal may be provided for one column of the memory cell array MCA.

[0068] For example, the circuit SD can be a voltage generating circuit for applying a predetermined voltage to a plurality of memory cells MC in the memory cell array MCA. For example, the circuit SD is electrically connected to the wirings SL[1] to SL[m]. Note that the memory device MDV in FIG. 1A may not include the circuit SD and may instead be configured to directly receive the power supply voltage (VIL) for the memory cell array MCA shown in FIG. 2.

[0069] Note that although FIG. 1A shows an example in which one wiring SL[1] to one wiring SL[m] are provided for each column of the memory cell array MCA, multiple wirings may be provided for one column of the memory cell array MCA.

[0070] As an example, the circuit CLC can be a circuit equivalent to the control logic circuit 2660 in FIG.

[0071] As an example, the circuit OPC can be a circuit equivalent to the output circuit 2640 in FIG.

[0072] In the configuration example of the memory device MDV in FIG. 1A, the peripheral circuit PHL can be formed, for example, on a semiconductor substrate. That is, the circuits WD, BD, SD, OPC, and CLC can be formed on the semiconductor substrate. Furthermore, by using a substrate made of silicon, for example, as the semiconductor substrate, transistors including silicon in their channel formation regions (hereinafter referred to as Si transistors) can be formed on the substrate. Therefore, Si transistors can be used as the transistors included in the peripheral circuit PHL.

[0073] The semiconductor substrate may be, for example, a substrate made of germanium. The peripheral circuit PHL may be formed on a compound semiconductor substrate, such as a substrate made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide. The peripheral circuit PHL may be formed on a semiconductor substrate having an insulator region therein, such as an SOI (Silicon On Insulator) substrate.

[0074] The peripheral circuit PHL can be formed on, for example, an insulating substrate. Examples of such insulating substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconia substrates (e.g., yttria-stabilized zirconia substrates), and resin substrates. The peripheral circuit PHL can be formed on, for example, a conductive substrate. Examples of such conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. However, unlike semiconductor substrates, insulating and conductive substrates cannot form channel formation regions in the substrate itself, and therefore, transistors cannot be formed directly on insulating and conductive substrates. Therefore, to form transistors on an insulating or conductive substrate, a separate semiconductor film must be provided above the insulating or conductive substrate.

[0075] 1A, the memory cell array MCA can be provided above the peripheral circuit PHL by, for example, forming the memory cell array MCA by a semiconductor process. In particular, since OS transistors can be formed by a semiconductor process, the memory cell array MCA can be provided above the semiconductor substrate and the peripheral circuit PHL by using OS transistors as the transistors included in the memory cell array MCA.

[0076] 1A shows a configuration in which one memory cell array MCA is provided above the peripheral circuit PHL, but the memory device of one embodiment of the present invention is not limited to this. For example, the memory device of one embodiment of the present invention may have multiple stacked memory cell arrays MCA above the peripheral circuit PHL. FIG. 1B shows a configuration of a memory device in which memory cell arrays MCA[1] to MCA[p] (p is an integer of 2 or more) are stacked above the peripheral circuit PHL.

[0077] <<Memory cell configuration example 1>> Fig. 3A shows an example of a memory cell that can be included in the memory device MDV. The memory cell MC shown in Fig. 3A can be said to be an example of SOT-MRAM (Spin Orbit Torque-Magnetoresistive Random Access Memory), which is a three-terminal memory element.

[0078] The memory cell MC includes, for example, a transistor M1, a transistor M2, and a resistance change device MD.

[0079] For example, OS transistors can be used as the transistors M1 and M2. The channel formation region of an OS transistor is preferably an oxide containing at least one of indium, gallium, and zinc. Alternatively, an oxide containing at least one of indium, an element M (e.g., aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, etc.) and zinc may be used instead of the oxide. The OS transistor preferably has the structure of the transistor described in Embodiment 2.

[0080] 3A includes a back gate, the memory device of one embodiment of the present invention is not limited thereto. For example, the transistors M1 and M2 in FIG. 3A may have a structure without a back gate, that is, a single-gate transistor. Some of the transistors may have a back gate, and other transistors may have a structure without a back gate.

[0081] Furthermore, it is preferable that the sizes (e.g., channel length, channel width, transistor configuration, etc.) of the transistors M1 and M2 are equal to each other. By making the transistor sizes equal to each other, the electrical characteristics of each transistor can be made approximately equal. Therefore, by making the sizes of the transistors M1 and M2 equal to each other, the transistors M1 and M2 can perform approximately the same operation under the same conditions. Here, the same conditions refer to, for example, the input potentials to the sources, drains, gates, etc. of the transistors M1 and M2.

[0082] Unless otherwise specified, each of the transistors M1 and M2 may operate as a switching element. That is, the gate voltage, source voltage, and drain voltage of each of the above-described transistors may be within a voltage range in which they operate as a switching element. Furthermore, each of the transistors M1 and M2 may operate in a linear region or a saturation region when in an on state.

[0083] The above-described modifications to the structure, operation, etc. of the transistors are not limited to the transistors M1 and M2. For example, modifications may be made to the structure, operation, etc. of transistors described elsewhere in the specification or illustrated in other drawings.

[0084] The resistance change device MD has an MTJ (magnetic tunnel junction) element ME. The resistance change device MD also has terminals IT1, IT2, and OT. Details of the resistance change device MD will be described later.

[0085] A first terminal of the transistor M1 is electrically connected to a terminal IT1 of the resistance change device MD, a second terminal of the transistor M1 is electrically connected to a wiring BL1, and a gate of the transistor M1 is electrically connected to a wiring WL. A first terminal of the transistor M2 is electrically connected to a terminal IT2 of the resistance change device MD, a second terminal of the transistor M2 is electrically connected to a wiring BL2, and a gate of the transistor M2 is electrically connected to the wiring WL. A terminal OT of the resistance change device MD is electrically connected to a wiring RBL.

[0086] The wiring BL1 and the wiring BL2 function as, for example, write bit lines for the memory cells MC or wirings that apply a constant voltage.

[0087] The wiring WL functions as a word line for the memory cells MC, for example.

[0088] The wiring RBL functions as a read bit line for the memory cell MC, for example.

[0089] In FIG. 3A , the back gates of the transistors M1 and / or M2 are illustrated. Although the connection configuration of the back gates is not shown, the electrical connection of the back gates can be determined during the design stage. For example, in a transistor having a back gate, the gate and back gate may be electrically connected to increase the on-state current of the transistor. That is, for example, the gate and back gate of the transistor M1 may be electrically connected, or the gate and back gate of the transistor M2 may be electrically connected. Furthermore, in a transistor having a back gate, for example, a wiring may be provided to electrically connect the back gate of the transistor to an external circuit or the like, and a potential may be applied to the back gate of the transistor from the external circuit or the like to change the threshold voltage of the transistor or reduce the off-state current of the transistor. Specifically, the memory cell MC may have the configuration shown in FIG. 3B . The memory cell MC in FIG. 3B has a configuration in which a wiring BGE is electrically connected to the back gates of the transistors M1 and M2 included in the memory cell MC in FIG. 3A. By applying a predetermined potential to the wiring BGE, the threshold voltages of the transistors M1 and M2 can be changed.

[0090] Next, the resistance change device MD will be described.

[0091] Fig. 4 is a block diagram showing an example of a resistance change device MD. The resistance change device MD in Fig. 4 has a layer RL, a layer TIS, a layer FL, and a layer CA. The layers RL, TIS, and FL are included in the MTJ element ME.

[0092] The layer CA has, for example, a conductive film. The terminals IT1 and IT2 are electrically connected via the film. Therefore, when a voltage is applied between the terminals IT1 and IT2, a current flows between the terminals IT1 and IT2. The layer CA is sometimes called a channel layer.

[0093] Furthermore, the film is made of a material that generates the spin Hall effect when a current is passed between terminals IT1 and IT2. The spin Hall effect is a phenomenon in which a spin current is generated in a direction approximately perpendicular to the direction of current flow. Specifically, when a current flows in a two-dimensional plane such as a thin film, electrons with different spin directions are polarized on the top and bottom surfaces of the thin film, respectively, thereby generating a spin current in a direction approximately perpendicular to the thin film. Therefore, when a current flows between terminals IT1 and IT2, the layer CA can generate a spin current in a direction approximately perpendicular to the layer CA.

[0094] The layer CA preferably contains a metal material that generates the spin Hall effect. Specifically, it is preferable to use a transition metal with a strong spin-orbit interaction as the metal material. Examples of such transition metals include tungsten, platinum, and tantalum. The layer CA may also contain a topological insulator that generates the spin Hall effect instead of a metal material. In this case, an alloy of bismuth and antimony, an alloy of bismuth and selenium, or the like may be used.

[0095] The layer FL functions as a free layer in the MTJ element ME. The layer FL has a ferromagnetic material, and the ferromagnetic material allows the layer FL to assume a state in which its magnetic moment is parallel or antiparallel to the magnetization direction of the layer RL, which will be described later.

[0096] The ferromagnetic material contained in the layer FL is preferably a material whose magnetization is reversed by a small spin current, and is preferably a material whose magnetization is not easily reversed by thermal energy.

[0097] The ferromagnetic material may be, for example, an alloy of one or more of iron, cobalt, and nickel. For example, an alloy of cobalt, iron, and boron may be used. Other examples include an alloy of manganese and gallium, and an alloy of manganese and germanium.

[0098] The magnetic moment of the layer FL is subjected to a spin torque due to the spin current generated in the layer CA. The direction of the magnetic moment of the layer FL is reversed, for example, when the spin torque exceeds a threshold value. In other words, the magnetization direction of the layer FL can be changed by passing a current through the layer CA (between terminal IT1 and terminal IT2). This operation allows information to be recorded in the MTJ element ME.

[0099] The layer TIS functions as a layer having a tunnel insulator in the MTJ element ME. When a voltage is applied between the layer FL and the layer RL (terminal OT), a tunnel current can flow through the layer TIS due to the tunnel magnetoresistance effect. At this time, the electrical resistance value of the layer TIS changes depending on the direction of the magnetic moment of the layer FL. Specifically, the electrical resistance value of the layer TIS changes depending on whether the magnetization directions of the layers FL and RL are parallel or antiparallel.

[0100] The tunnel insulator may be, for example, magnesium oxide, aluminum oxide, etc. In particular, it is preferable to use crystalline magnesium oxide as the tunnel insulator.

[0101] The layer RL functions as a fixed layer in the MTJ element ME. The layer RL includes a ferromagnetic material. Unlike the ferromagnetic material of the layer FL, the magnetization direction of the ferromagnetic material of the layer RL is fixed.

[0102] The ferromagnetic material contained in the layer RL may be, for example, a material that can be used for the ferromagnetic material contained in the layer FL.

[0103] It is preferable that the ferromagnetic material and the tunnel insulator contained in the MTJ element ME are combined so as to increase the magnetoresistance ratio (MR ratio) of the MTJ element ME.

[0104] Here, an example of a method for writing information to and reading information from the memory cell MC of FIG. 3A will be described.

[0105] When writing information to the memory cell MC, a high-level potential is applied to the wiring WL to turn on the transistors M1 and M2. Next, a first potential is applied from the wiring BL1 to the terminal IT1 via the transistor M1, and a second potential is applied from the wiring BL2 to the terminal IT2 via the transistor M2. As a result, a current corresponding to the potential difference between the first and second potentials flows between the terminals IT1 and IT2 in the resistance change device MD. As a result, a current flows through the layer CA of the MTJ element ME, generating a spin current in the layer CA, which determines the magnetization direction of the ferromagnetic material in the layer FL. The first potential may be higher or lower than the second potential. Furthermore, the potential applied by the wiring RBL is preferably within a range in which no current flows between the terminal IT1 and the terminal OT and / or between the terminal IT2 and the terminal OT.

[0106] When reading information from the memory cell MC, a high-level potential is applied to the wiring WL to turn on the transistors M1 and M2. Next, a predetermined voltage is applied to each of the terminals IT1, IT2, and OT so that current flows between the terminal IT1 and the terminal OT and / or between the terminal IT2 and the terminal OT. The electrical resistance of the MTJ element ME changes depending on whether the magnetization directions of the layers RL and FL are parallel or antiparallel, and therefore the amount of tunnel current flowing through the layer TIS of the MTJ element ME also changes. The information recorded in the MTJ element ME can be read by measuring the amount of current flowing between the MTJ element ME and the terminal OT. Alternatively, the information recorded in the MTJ element ME can be read by applying a predetermined potential to each of the terminals IT1 and IT2, passing a constant current between the MTJ element ME and the terminal OT, and measuring the potential at the terminal OT.

[0107] [Peripheral circuit configuration example 1] Next, Fig. 5A shows a configuration example in which the memory cell MC of Fig. 3A is applied to the memory device MDV of Fig. 1A. Note that in Fig. 5A, each component is illustrated on a plane for ease of viewing, but the memory cell array MCA is assumed to be provided above the peripheral circuit PHL, as in the memory device MDV of Fig. 1A.

[0108] Note that, in the storage device MDV of FIG. 5A, explanations of portions that overlap with the contents of the storage device MDV of FIG. 1A will be omitted.

[0109] In the memory device MDV of Fig. 5A, the peripheral circuit PHL has a circuit WD, a circuit BD, and a circuit RBD. For the circuit WD and the circuit BD, please refer to the description of the memory device MDV of Fig. 1A.

[0110] For example, the circuit RBD is electrically connected to the wirings RBL[1] to RBL[m]. The circuit RBD also functions as a circuit for receiving read data from the memory cells MC included in the memory cell array MCA via the wirings RBL[1] to RBL[m]. That is, the circuit RBD can be, for example, a circuit corresponding to the sense amplifier 2633 in the memory device MDV in FIG. 2. Therefore, the circuit RBD may be included in the circuit BD corresponding to the bit line driver circuit 2630.

[0111] 1A, the circuit BD is electrically connected to the wirings BL1[1] to BL1[n] and the wirings BL2[1] to BL2[n]. That is, the wirings BL1 and BL2 are provided for each column of the memory cell array MCA.

[0112] In this case, the circuit BD preferably inputs different voltages (or currents) to the wirings BL1 and BL2 when writing data to the memory cell MC and when reading data from the memory cell MC.

[0113] Note that the configuration example in which the memory cell MC of Fig. 3A is applied to the memory device MDV of Fig. 1A is not limited to the configuration of the memory device MDV of Fig. 5 A. The circuit configuration of the memory device MDV of Fig. 5A may be changed depending on the situation.

[0114] <<Memory cell configuration example 2>> Fig. 3C shows an example of a memory cell that can be provided in the memory device MDV, which is different from Fig. 3A. Note that the memory cell MC shown in Fig. 3C can also be said to be an example of an SOT-MRAM.

[0115] The memory cell MC includes, for example, a transistor M3, a transistor M4, and a resistance change device MD.

[0116] For example, OS transistors can be applied to the transistors M3 and M4, similar to the transistors M1 and M2. The resistance change device MD has the MTJ element ME of FIG. 4, similar to the resistance change device MD of FIG. 3A.

[0117] A first terminal of the transistor M3 is electrically connected to the terminal IT2 of the resistance change device MD, a second terminal of the transistor M3 is electrically connected to the wiring SL, and a gate of the transistor M3 is electrically connected to the wiring WLa. A first terminal of the transistor M4 is electrically connected to the terminal OT of the resistance change device MD, a second terminal of the transistor M4 is electrically connected to the wiring SL, and a gate of the transistor M4 is electrically connected to the wiring WLb. A terminal IT1 of the resistance change device MD is electrically connected to the wiring BL.

[0118] The wiring BL functions as, for example, a bit line for the memory cell MC or a wiring that applies a constant voltage.

[0119] The wiring SL functions as, for example, a wiring that applies a constant voltage.

[0120] The wiring WLa functions as, for example, a write word line and a read word line for the memory cells MC.

[0121] The line WLb functions as a read word line for the memory cell MC, for example.

[0122] Next, an example of a method for writing and reading information in the memory cell MC of Fig. 3C will be described. Note that, as an example, a low-level potential is applied to the wiring SL.

[0123] When writing information to the memory cell MC, a high-level potential is applied to the wiring WLa to turn on the transistor M3, and a low-level potential is applied to the wiring WLb to turn off the transistor M4. Next, a third potential higher than the low-level potential is applied from the wiring BL to the terminal IT1. This causes a current corresponding to the potential difference between the third potential and the low-level potential to flow between the terminal IT1 and the terminal IT2 in the resistance change device MD. This causes a current to flow in the layer CA of the MTJ element ME, generating a spin current in the layer CA. This spin current determines the magnetization direction of the ferromagnetic material in the layer FL.

[0124] When reading information from the memory cell MC, a high-level potential is applied to the line WLa to turn on transistor M3, and a high-level potential is applied to the line WLb to turn on transistor M4. Next, a fourth potential higher than the low-level potential and lower than the third potential is applied from the line BL to terminal IT1, causing current to flow between terminal IT1 and terminal IT2 and / or between terminal IT1 and terminal OT. The electrical resistance of the MTJ element ME changes depending on whether the magnetization directions of the layers RL and FL are parallel or antiparallel, and therefore the amount of tunnel current flowing through the layer TIS of the MTJ element ME also changes. In other words, the information recorded in the MTJ element ME can be read by measuring the amount of current flowing through the MTJ element ME and terminal IT1. Alternatively, the information recorded in the MTJ element ME can be read by applying a predetermined potential to the line SL, passing a constant current from the line BL to terminal IT1 of the MTJ element ME, and measuring the potential at terminal IT1.

[0125] 3C may have a configuration in which the back gates of the transistors M3 and M4 are electrically connected to the wiring BGE, as in FIG. 3B. Specifically, the memory cell MC may have a configuration as shown in FIG. 3D. By applying a predetermined potential to the wiring BGE, the threshold voltages of the transistors M3 and M4 can be changed.

[0126] [Peripheral circuit configuration example 2] Next, Fig. 5B shows a configuration example in which the memory cell MC of Fig. 3C is applied to the memory device MDV of Fig. 1A. Note that in Fig. 5B, each component is illustrated on a plane for ease of viewing, but the memory cell array MCA is assumed to be provided above the peripheral circuit PHL as in the memory device MDV of Fig. 1A, as in Fig. 5A.

[0127] Note that, in the storage device MDV of FIG. 5B, the description of the portions that overlap with the contents of the storage device MDV of FIG. 1A will be omitted.

[0128] In the memory device MDV of Fig. 5B, the peripheral circuit PHL has a circuit WD, a circuit BD, and a circuit SD. For the circuit WD, the circuit BD, and the circuit SD, please refer to the description of the memory device MDV of Fig. 1A.

[0129] The memory device MDV in Fig. 5B differs from the memory device MDV in Fig. 1A in that the wirings SL[1] to SL[n] are arranged in the column direction instead of the row direction. Thus, in the memory device MDV, there is no particular limitation on the direction in which the wirings extend.

[0130] The circuit WD is electrically connected to the wirings WLa[1] to WLa[m] and the wirings WLb[1] to WLb[m] as the wirings WL[1] to WL[m] in the memory device MDV in Fig. 1A. That is, the wirings WLa and WLb are provided for each row of the memory cell array MCA.

[0131] In this case, the circuit WD is preferably configured to input different voltages to the wirings WLa and WLb when writing data to the memory cell MC and when reading data from the memory cell MC.

[0132] Note that the configuration example in which the memory cell MC of Fig. 3C is applied to the memory device MDV of Fig. 1A is not limited to the configuration of the memory device MDV of Fig. 5B. The circuit configuration of the memory device MDV of Fig. 5B may be changed depending on the situation.

[0133] <<Memory cell configuration example 3>> Fig. 6A shows an example of a memory cell that can be included in the memory device MDV. The memory cell shown in Fig. 6A can be said to be an example of STT-MRAM (Spin Transfer Torque-Magnetoresistive Random Access Memory).

[0134] The memory cell MC includes a transistor M10 and the above-described MTJ element ME.

[0135] The transistor M10 can be, for example, an OS transistor, similar to the transistors M1 and M2.

[0136] Similar to the MTJ element shown in Figure 4, the MTJ element ME has a layer FL having a free layer, a layer TIS having a tunnel insulator, and a layer RL having a fixed layer, with the layer FL and the layer RL overlapping each other via the layer TIS.

[0137] A first terminal of the transistor M10 is electrically connected to a layer RL of the MTJ element ME, a second terminal of the transistor M10 is electrically connected to a wiring SL, and a gate of the transistor M10 is electrically connected to a wiring WL. A layer FL of the MTJ element ME is electrically connected to a wiring BL.

[0138] For example, the wiring BL functions as a write bit line or a read bit line for the memory cell MC.

[0139] The wiring WL functions as a word line for the memory cells MC, for example.

[0140] For example, the wiring SL functions as a wiring that applies a constant voltage. The constant voltage can be, for example, a low-level potential.

[0141] Here, an example of a method for writing information to and reading information from the memory cell MC of FIG. 6A will be described.

[0142] When writing information to the memory cell MC, a high-level potential is applied to the line WL to turn on the transistor M10. This establishes a conductive state between the layer RL and the line SL. Depending on the voltage conditions between the lines BL and SL, a tunnel current is generated in the layer TIS, causing a current to flow between the lines BL and SL. At this time, the magnetization direction of the layer FL can be changed by flowing a large amount of electrons with spins aligned in a certain direction into the layer FL. This allows information to be recorded in the MTJ element ME.

[0143] When reading information from the memory cell MC, a high-level potential is applied to the line WL to turn on the transistor M10. This establishes a conductive state between the layer RL and the line SL. When a constant voltage is applied to the line BL, the amount of current flowing through the MTJ element ME depends on whether the magnetization directions of the layers RL and FL are parallel or antiparallel. Specifically, for example, the amount of current when the magnetization directions of the layers RL and FL are parallel is greater than the amount of current when the magnetization directions of the layers RL and FL are antiparallel. In other words, by measuring the amount of current flowing through the MTJ element ME, the information recorded in the MTJ element ME can be read.

[0144] 6A can record information by passing electrons whose spins are aligned in a certain direction through the MTJ element ME to change the magnetization direction of the layer FL. However, the configuration of the memory cell MC provided in the memory device of one embodiment of the present invention is not limited to this. For example, a wiring having a function of generating a magnetic field may be provided near the MTJ element ME. In this configuration, information can be written to the MTJ element ME by generating a magnetic field from the wiring to change the magnetization direction of the layer FL of the MTJ element ME.

[0145] <<Memory cell configuration example 4>> Fig. 6B shows an example of a memory cell that can be included in the memory device MDV. The memory cell shown in Fig. 6B can be said to be an example of a ReRAM (Resistive Random Access Memory).

[0146] The memory cell MC includes a transistor M10 and a resistance change element RM.

[0147] The transistor M10 can be, for example, an OS transistor, similar to the transistors M1 and M2.

[0148] As shown in Fig. 6B, the memory cell MC in Fig. 6B has a configuration in which the MTJ element ME of the memory cell MC in Fig. 6A is replaced with a resistance change element RM. Note that in the memory cell MC in Fig. 6B, a first terminal of the resistance change element RM is electrically connected to a first terminal of the transistor M10, and a second terminal of the resistance change element RM is electrically connected to a wiring BL.

[0149] For example, the wiring BL functions as a write bit line or a read bit line for the memory cell MC.

[0150] The wiring WL functions as a word line for the memory cells MC, for example.

[0151] The wiring SL functions as, for example, a wiring that applies a constant voltage, which may be, for example, a reference potential.

[0152] Here, an example of a method for writing information to and reading information from the memory cell MC of FIG. 6B will be described.

[0153] When writing information to the memory cell MC, a high-level potential is applied to the wiring WL to turn on the transistor M10. This establishes electrical continuity between the wiring BL and the wiring SL. Furthermore, by applying a pulse voltage higher than the reference potential (positive pulse voltage) or a pulse voltage lower than the reference potential (negative pulse voltage) to the wiring BL, the pulse voltage is input to the second terminal of the resistance change element RM. At this time, the electrical resistance of the resistance change element RM changes depending on whether the voltage applied to the second terminal of the resistance change element RM is a positive pulse voltage or a negative pulse voltage. This allows information to be recorded in the resistance change element RM of the memory cell MC.

[0154] When reading information from the memory cell MC, a high-level potential is applied to the line WL to turn on the transistor M10. This establishes electrical continuity between the line BL and the line SL. When a constant voltage greater than the negative pulse voltage and less than the positive pulse voltage is applied to the line BL, the amount of current flowing through the resistance change element RM is determined by the electrical resistance value of the resistance change element RM. In other words, by measuring the amount of current flowing through the resistance change element RM, the information recorded in the resistance change element RM can be read.

[0155] <<Memory Cell Configuration Example 5>> Fig. 6C shows an example of a memory cell that can be included in the memory device MDV. The memory cell shown in Fig. 6C can be said to be an example of a phase change memory (sometimes referred to as PCM, PRAM, etc.).

[0156] The memory cell MC includes a transistor M10 and a phase change memory cell PCM1.

[0157] The transistor M10 can be, for example, an OS transistor, similar to the transistors M1 and M2.

[0158] The phase change memory PCM1 has, for example, an electrode TE, a phase change layer CHL, and an electrode BE, and the electrode TE, the phase change layer CHL, and the electrode BE are electrically connected in this order.

[0159] Furthermore, for example, chalcogenide glass can be applied to the phase change layer CHL. Note that in the present embodiment, the phase change layer CHL will be described as being made of chalcogenide glass.

[0160] It is preferable that the electrode TE and the electrode BE have different contact areas with the phase-change layer CHL. For example, in FIG. 6C, the contact area between the electrode TE and the phase-change layer CHL is illustrated as being larger than the contact area between the electrode BE and the phase-change layer CHL. By reducing the contact area between the electrode BE and the phase-change layer CHL, heat can be applied locally to the phase-change layer CHL, making it easier for a phase change to occur in the phase-change layer CHL near the electrode BE than in the phase-change layer CHL near the electrode TE.

[0161] 6C, the memory cell MC in FIG. 6C has a configuration in which the MTJ element ME of the memory cell MC in FIG. 6A is replaced with a phase-change memory PCM1. Note that in the memory cell MC in FIG. 6C, the electrode BE of the phase-change memory PCM1 is electrically connected to the first terminal of the transistor M10, and the electrode TE of the phase-change memory PCM1 is electrically connected to the wiring BL.

[0162] For example, the wiring BL functions as a write bit line or a read bit line for the memory cell MC.

[0163] The wiring WL functions as a word line for the memory cells MC, for example.

[0164] For example, the wiring SL functions as a wiring that applies a constant voltage. The constant voltage can be, for example, a low-level potential.

[0165] Here, an example of a method for writing information to and reading information from the memory cell MC of FIG. 6C will be described.

[0166] When writing information to the memory cell MC, a high-level potential is applied to the wiring WL to turn on the transistor M10. This establishes electrical continuity between the wiring BL and the wiring SL. Furthermore, when the chalcogenide glass of the phase-change layer CHL is in, for example, an amorphous state, applying a high-level potential from the wiring BL (specifically, applying a high voltage between the electrodes TE and BE) increases the amount of current flowing through the phase-change memory PCM1. This causes impact ionization within the chalcogenide glass, increasing the number of carriers and rapidly reducing the electrical resistance of the chalcogenide glass. This increases the current flow through the chalcogenide glass, generating Joule heat in the chalcogenide glass and raising its temperature. This melts the chalcogenide glass. Subsequently, by controlling the voltage from the wiring BL to maintain the temperature of the chalcogenide glass within its crystallization temperature range, the chalcogenide glass can transition to a polycrystalline state. After the chalcogenide glass is made polycrystalline, even if the voltage supply from the wiring BL and the wiring SL is stopped, the chalcogenide glass can maintain the polycrystalline state.

[0167] In addition, the temperature of the chalcogenide glass can be raised by Joule heat to melt the chalcogenide glass, and then the voltage supply from the wiring BL and wiring SL can be stopped to rapidly cool the chalcogenide glass, thereby transitioning the chalcogenide glass to an amorphous state.

[0168] The memory cell MC can record information in the phase change memory PCM1 by changing the phase of the chalcogenide glass contained in the phase change layer CHL.

[0169] When reading information from the memory cell MC, a high-level potential is applied to the line WL, turning on the transistor M10. This establishes electrical continuity between the line BL and the line SL. When a voltage lower than that used during writing is applied to the line BL, the amount of current flowing between the electrodes TE and BE of the phase-change memory PCM1 depends on whether the chalcogenide glass of the phase-change layer CHL is in an amorphous or polycrystalline state. Specifically, for example, when the chalcogenide glass is in an amorphous state, the amount of current is small, and when the chalcogenide glass is in a polycrystalline state, the amount of current is large. In other words, by measuring the amount of current flowing through the phase-change memory PCM1, the information recorded in the phase-change memory PCM1 can be read.

[0170] A memory cell having a memory element such as an MTJ element ME, a resistive change element RM, or a phase-change memory PCM1 functions as a nonvolatile memory, thereby reducing the power required to retain data. Therefore, by applying the above-described configuration to a memory device, a memory device with low power consumption can be provided. Furthermore, by using OS transistors or the like as the transistors of the memory cell, the memory cell array can be fabricated using a semiconductor process, allowing the memory cell array to be stacked above the peripheral circuitry. By stacking multiple memory cell arrays, a memory device with a large storage capacity can be provided.

[0171] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0172] (Embodiment 2) In this embodiment, an example of a cross-sectional structure of the memory device described in the above embodiment will be described.

[0173] 7 is a cross-sectional view schematically illustrating an example of the configuration of the memory device MDV of FIG. 1B. Specifically, the memory device MDV illustrated in FIG. 7 includes a layer SIL and layers OSL[1] to OSL[p] (where p is an integer equal to or greater than 1) provided above the layer SIL. The layer SIL includes, for example, the peripheral circuit PHL described in the first embodiment. Each of the layers OSL[1] to OSL[p] includes, for example, the memory cell array MCA described in the first embodiment.

[0174] As an example, the layer SIL includes a transistor 300, and each of the layers OSL[1] to OSL[p] includes a transistor 500A, a transistor 500B, and a memory element 400. In particular, in this specification and the like, one or both of the transistor 500A and the transistor 500B may be referred to as the transistor 500.

[0175] 8A shows a cross-sectional view of the transistor 500 in the channel length direction, FIG. 8B shows a cross-sectional view of the transistor 500 in the channel width direction, and FIG. 8C shows a cross-sectional view of the transistor 300 in the channel width direction. Note that the transistors shown in each of FIGS. 8A to 8C may have partially different shapes from the transistor shown in FIG. 7 for the purpose of explanation.

[0176] Each of the layers OSL[ 1 ] to OSL[p] has a memory cell 600 , and the memory cell 600 includes a transistor 500A, a transistor 500B, and a memory element 400 .

[0177] 7, the memory cell 600 has a configuration similar to that of the memory cell MC in FIG. 3A. Specifically, the transistor 500A corresponds to one of the transistor M1 and the transistor M2, the transistor 500B corresponds to the other of the transistor M1 and the transistor M2, and the memory element 400 corresponds to the resistance change device MD. Therefore, in the memory device MDV in FIG. 7, the first terminal of the transistor 500A is electrically connected to the first terminal of the transistor 500B and the first terminal of the memory element 400.

[0178] 3A can be, for example, a conductor 450 electrically connected to one second terminal of the transistor 500A or the transistor 500B. The other wiring BL1 or the wiring BL2 in FIG. 3A can be, for example, a conductor 450 electrically connected to the other second terminal of the transistor 500A or the transistor 500B. The conductor 450 will be described later.

[0179] 3A can be, for example, a conductor 560 corresponding to the gates of the transistors 500A and 500B. The wiring RBL in FIG. 3A can be, for example, a conductor 460 electrically connected to the second terminal of the memory element 400. The conductor 460 will be described later.

[0180] The transistor 500 is a transistor (OS transistor) having a metal oxide in a channel formation region. The transistor 500 has a small off-state current and a field-effect mobility that does not change easily even at high temperatures. By using the transistor 500 as a transistor included in, for example, the above-described memory device, a memory device whose operating capability is not easily degraded even at high temperatures can be realized.

[0181] The peripheral circuit PHL included in the layer SIL has, for example, circuits WD, BD, SD, CLC, OPC, etc., similar to the configuration of the memory device MDV in Fig. 1B. Therefore, the transistor 300 can be a transistor included in the circuits WD, BD, RBD, SD, CLC, OPC, etc.

[0182] The transistor 300 includes a conductor 316, an isolation layer 312, an insulator 315, a semiconductor region 313 made of part of a substrate 310, and low-resistance regions 314a and 314b that function as source and drain regions.

[0183] For example, a semiconductor substrate can be used as the substrate 310. As described above, examples of the semiconductor substrate include a substrate made of silicon and a substrate made of germanium. Alternatively, for example, a compound semiconductor substrate can be used as the substrate 310. As described above, examples of the compound semiconductor substrate include a substrate made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, gallium oxide, and the like.

[0184] 8C , the transistor 300 has a top surface and side surfaces in the channel width direction of a semiconductor region 313 covered with a conductor 316 via an insulator 315. By forming the transistor 300 as a fin type in this way, the effective channel width is increased, thereby improving the on-state characteristics of the transistor 300. Furthermore, the contribution of the electric field of the gate electrode can be increased, thereby improving the off-state characteristics of the transistor 300.

[0185] The transistor 300 may be either a p-channel type or an n-channel type.

[0186] The region where the channel of the semiconductor region 313 is formed, the region nearby, the low-resistance region 314a that serves as the source region or the drain region, and the low-resistance region 314b preferably contain a semiconductor such as a silicon-based semiconductor, and preferably contain single-crystal silicon. Alternatively, they may be formed of a material containing Ge (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), GaAlAs (gallium aluminum arsenide), GaN (gallium nitride), or the like. A configuration using silicon in which the effective mass is controlled by applying stress to the crystal lattice and changing the lattice spacing may also be used. Alternatively, the transistor 300 may be a HEMT (High Electron Mobility Transistor) by using GaAs and GaAlAs, or the like.

[0187] The low resistance region 314a and the low resistance region 314b contain, in addition to the semiconductor material applied to the semiconductor region 313, an element that imparts n-type conductivity, such as arsenic or phosphorus, or an element that imparts p-type conductivity, such as boron.

[0188] The conductor 316 functioning as the gate electrode can be made of a conductive material such as a semiconductor material, metal material, alloy material, or metal oxide material, such as silicon containing an element that imparts n-type conductivity, such as arsenic or phosphorus, or an element that imparts p-type conductivity, such as boron.

[0189] Since the work function is determined by the material of the conductor, the threshold voltage of the transistor can be adjusted by selecting the material of the conductor. Specifically, it is preferable to use a material such as titanium nitride or tantalum nitride as the conductor. Furthermore, in order to achieve both conductivity and embeddability, it is preferable to use a metal material such as tungsten or aluminum as the conductor in a stacked structure, and tungsten is particularly preferable in terms of heat resistance.

[0190] The element isolation layer 312 is provided to isolate a plurality of transistors formed on the substrate 310. The element isolation layer 312 can be formed by, for example, a local oxidation of silicon (LOCOS) method, a shallow trench isolation (STI) method, a mesa isolation method, or the like.

[0191] 7 and 8C is an example, and the structure of the transistor 300 is not limited thereto, and an appropriate transistor may be used depending on the circuit configuration, driving method, etc. For example, the transistor 300 shown in FIGS.

[0192] In the transistor 300 shown in FIG. 7, an insulator 320, an insulator 322, an insulator 324, and an insulator 326 are stacked in this order from the substrate 310 side.

[0193] The insulators 320, 322, 324, and 326 can be formed using, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, or the like.

[0194] In this specification, silicon oxynitride refers to a material whose composition contains more oxygen than nitrogen, silicon nitride oxide refers to a material whose composition contains more nitrogen than oxygen, aluminum oxynitride refers to a material whose composition contains more oxygen than nitrogen, and aluminum nitride oxide refers to a material whose composition contains more nitrogen than oxygen.

[0195] The insulator 322 may function as a planarizing film that flattens steps caused by the insulator 320 and the transistor 300 covered by the insulator 322. For example, the top surface of the insulator 322 may be planarized by a planarization process using a chemical mechanical polishing (CMP) method or the like to improve the flatness.

[0196] The insulator 324 is preferably a film having a barrier property that prevents impurities such as water and hydrogen from diffusing from the substrate 310 or the transistor 300 to a region where the transistor 500 is provided.

[0197] An example of a film having a barrier property against hydrogen is silicon nitride formed by a CVD method. Here, diffusion of hydrogen into a semiconductor element having an oxide semiconductor, such as the transistor 500, may degrade the characteristics of the semiconductor element. Therefore, it is preferable to use a film that suppresses hydrogen diffusion between the transistor 500 and the transistor 300. Specifically, the film that suppresses hydrogen diffusion is a film that releases a small amount of hydrogen.

[0198] The amount of desorption of hydrogen can be analyzed using, for example, thermal desorption spectroscopy (TDS). For example, the amount of desorption of hydrogen from the insulator 324 is calculated as 10×10 per area of ​​the insulator 324 when the surface temperature of the film is in the range of 50° C. to 500° C. in TDS analysis. 15 atoms / cm 2 Less than or equal to 5 x 10 15 atoms / cm 2 The following is fine.

[0199] It is preferable that the insulator 326 has a lower dielectric constant than the insulator 324. For example, the relative dielectric constant of the insulator 326 is preferably less than 4, and more preferably less than 3. Furthermore, for example, the relative dielectric constant of the insulator 326 is preferably 0.7 times or less, and more preferably 0.6 times or less, the relative dielectric constant of the insulator 324. By using a material with a low dielectric constant as the interlayer film, the parasitic capacitance that occurs between wirings can be reduced.

[0200] Furthermore, conductors 328, 330, and the like are embedded in insulators 320, 322, 324, and 326. Note that conductors 328 and 330 function as plugs or wiring. Furthermore, for conductors that function as plugs or wiring, the same reference numeral may be used to refer to multiple structures. Furthermore, in this specification and the like, the wiring and the plug connecting to the wiring may be integrated. In other words, there are cases where a portion of a conductor functions as wiring, and cases where a portion of a conductor functions as a plug.

[0201] The materials for each plug and wiring (conductor 328, conductor 330, etc.) can be a conductive material such as a metal material, an alloy material, a metal nitride material, or a metal oxide material, and can be used in a single layer or a stacked layer. It is preferable to use a high-melting-point material such as tungsten or molybdenum that has both heat resistance and conductivity, and tungsten is preferred. Alternatively, it is preferable to form the wiring from a low-resistance conductive material such as aluminum or copper. Using a low-resistance conductive material can reduce the wiring resistance.

[0202] A wiring layer may be provided over the insulator 326 and the conductor 330. For example, in FIG. 7 , the insulator 350, the insulator 352, and the insulator 354 are stacked in this order over the insulator 326 and the conductor 330. The conductor 356 is formed in the insulator 350, the insulator 352, and the insulator 354. For example, the conductor 356 functions as a plug or wiring connected to the transistor 300. Note that the conductor 356 can be formed using a material similar to that of the conductor 328 and the conductor 330.

[0203] Note that, for example, the insulator 350 is preferably an insulator having barrier properties against impurities such as water and hydrogen, similar to the insulator 324. Similarly to the insulator 326, the insulators 352 and 354 are preferably made of an insulator having a relatively low dielectric constant in order to reduce parasitic capacitance between wirings. The conductor 356 preferably includes a conductor having barrier properties against water, hydrogen, and the like. In particular, a conductor having barrier properties against hydrogen is formed in the opening of the insulator 350 having barrier properties against hydrogen. With this structure, the transistor 300 and the transistor 500 can be separated by a barrier layer, thereby suppressing diffusion of hydrogen from the transistor 300 to the transistor 500.

[0204] Note that, for example, tantalum nitride or the like is preferably used as the conductor having a barrier property against hydrogen. Stacking tantalum nitride and highly conductive tungsten can suppress diffusion of hydrogen from the transistor 300 while maintaining the conductivity of the wiring. In this case, a structure in which the tantalum nitride layer having a barrier property against hydrogen is in contact with the insulator 350 having a barrier property against hydrogen is preferable.

[0205] Furthermore, on the insulator 354 and the conductor 356, an insulator 360, an insulator 362, and an insulator 364 are stacked in this order.

[0206] The insulator 360 is preferably an insulator having barrier properties against impurities such as water and hydrogen, similar to the insulator 324. Therefore, the insulator 360 can be made of, for example, a material that can be used for the insulator 324.

[0207] The insulators 362 and 364 function as an interlayer insulating film and a planarizing film. As the insulators 362 and 364, it is preferable to use an insulator that has a barrier property against impurities such as water and hydrogen, similar to the insulator 324. Therefore, the insulator 362 and / or the insulator 364 can be made of a material that can be used for the insulator 324.

[0208] Openings are formed in the insulators 360, 362, and 364 in regions that overlap with part of the conductor 356, and the conductor 366 is provided to fill the openings. The conductor 366 is also formed over the insulator 362. For example, the conductor 366 functions as a plug or a wiring connected to the transistor 300. Note that the conductor 366 can be formed using a material similar to that of the conductors 328 and 330.

[0209] An insulator 510, an insulator 512, an insulator 513, an insulator 514, and an insulator 516 are stacked in this order over the insulator 364 and the conductor 366. Any of the insulator 510, the insulator 512, the insulator 513, the insulator 514, and the insulator 516 is preferably made using a substance that has a barrier property against oxygen and / or hydrogen.

[0210] For example, the insulator 510 and the insulator 514 are preferably formed using a film having a barrier property that prevents impurities such as water and hydrogen from diffusing from the substrate 310 or the like to a region where the transistor 500 is provided. Therefore, a material similar to that of the insulator 324 or the like can be used.

[0211] An example of a film having a barrier property against hydrogen is silicon nitride formed by a CVD method. Here, hydrogen diffusion into a semiconductor element having an oxide semiconductor, such as the transistor 500, may degrade the characteristics of the semiconductor element. Therefore, it is preferable to use a film that suppresses hydrogen diffusion between the transistor 500 and the substrate 310. Specifically, the film that suppresses hydrogen diffusion is a film that releases a small amount of hydrogen.

[0212] As a film having a barrier property against hydrogen, for example, the insulators 510 and 514 are preferably made of a metal oxide such as aluminum oxide, hafnium oxide, or tantalum oxide.

[0213] In particular, aluminum oxide has a high blocking effect of preventing the permeation of both oxygen and impurities such as hydrogen and moisture, which can cause fluctuations in the electrical characteristics of a transistor. Therefore, aluminum oxide can prevent impurities such as hydrogen and moisture from entering the transistor 500 during and after the transistor manufacturing process. Furthermore, aluminum oxide can suppress the release of oxygen from the oxide that constitutes the transistor 500. Therefore, aluminum oxide is suitable for use as a protective film for the transistor 500.

[0214] For example, the insulator 513 is preferably a film having a barrier property that prevents diffusion of impurities such as water and hydrogen, similar to the insulators 510 and 514. In particular, in FIG. 7, the insulator 513 functions as a film that seals the transistor 500 together with the insulator 576 described later. For this reason, the insulator 513 is preferably made of a material that can be used for the insulator 576. The insulator 513 may also be made of a material that can be used for the insulator 510 or the insulator 514.

[0215] For example, the insulator 512 and the insulator 516 can be formed using a material similar to that of the insulator 320 or the insulator 326. By using a material with a relatively low dielectric constant for these insulators, parasitic capacitance between wirings can be reduced. For example, silicon oxide, silicon oxynitride, or the like can be used for the insulators 512 and 516.

[0216] A conductor 518, a conductor constituting the transistor 500 (for example, the conductor 503 shown in FIGS. 8A and 8B), and the like are embedded in the insulators 510, 512, 513, 514, and 516. The conductor 518 functions as a plug or wiring that connects a conductor 450, a conductor 460, the transistor 300, and the like, which will be described later. The conductor 518 can be formed using, for example, a material similar to that of the conductor 328 and the conductor 330.

[0217] In particular, the conductor 518 in the region in contact with the insulator 510 and the insulator 514 is preferably a conductor that has a barrier property against oxygen, hydrogen, and water. With this structure, the transistor 300 and the transistor 500 can be separated by a layer that has a barrier property against oxygen, hydrogen, and water, and diffusion of hydrogen from the transistor 300 to the transistor 500 can be suppressed.

[0218] Above the insulator 516 is the transistor 500 .

[0219] As shown in Figures 8A and 8B, the transistor 500 includes a conductor 503 arranged so as to be embedded in the insulator 514 and the insulator 516, an insulator 520 arranged on the insulator 516 and the conductor 503, an insulator 522 arranged on the insulator 520, an insulator 524 arranged on the insulator 522, an oxide 530a arranged on the insulator 524, an oxide 530b arranged on the oxide 530a, conductors 542a and 542b arranged apart from each other on the oxide 530b, an insulator 580 arranged on the conductors 542a and 542b and having an opening formed therein overlapping with the conductors 542a and 542b, an oxide 530c arranged on the bottom and side surfaces of the opening, an insulator 550 arranged on the surface on which the oxide 530c is formed, and a conductor 560 arranged on the surface on which the insulator 550 is formed. In this specification and the like, the conductor 542a and the conductor 542b are collectively referred to as the conductor 542.

[0220] 8A and 8B, it is preferable that an insulator 544 be disposed between the oxide 530a, the oxide 530b, the conductor 542a, and the conductor 542b and the insulator 580. It is preferable that the conductor 560 include a conductor 560a provided inside the insulator 550 and a conductor 560b provided so as to be embedded inside the conductor 560a. It is preferable that an insulator 574 be disposed on the insulator 580, the conductor 560, and the insulator 550, as shown in FIGS.

[0221] In the following, the oxide 530a, the oxide 530b, and the oxide 530c may be collectively referred to as the oxide 530.

[0222] Although the transistor 500 has a three-layer structure of oxides 530a, 530b, and 530c in and around a channel formation region, one embodiment of the present invention is not limited to this structure. For example, the transistor may have a single layer of oxide 530b, a two-layer structure of oxides 530b and 530a, a two-layer structure of oxides 530b and 530c, or a stacked structure of four or more layers. Although the transistor 500 has a two-layer structure, one embodiment of the present invention is not limited to this structure. For example, the conductor 560 may have a single-layer structure or a stacked structure of three or more layers. The transistor 500 illustrated in FIGS. 7, 8A, and 8B is merely an example, and the transistor is not limited to this structure. An appropriate transistor may be used depending on the circuit configuration, driving method, and the like.

[0223] Here, the conductor 560 functions as the gate electrode of the transistor, and the conductors 542a and 542b function as the source and drain electrodes, respectively. As described above, the conductor 560 is formed so as to be embedded in the opening of the insulator 580 and in the region sandwiched between the conductors 542a and 542b. The arrangements of the conductors 560, 542a, and 542b are selected in a self-aligned manner with respect to the opening of the insulator 580. That is, in the transistor 500, the gate electrode can be positioned between the source and drain electrodes in a self-aligned manner. Therefore, the conductor 560 can be formed without providing an alignment margin, thereby reducing the area occupied by the transistor 500. This allows for miniaturization and high integration of memory devices.

[0224] Furthermore, since the conductor 560 is formed in a self-aligned manner in the region between the conductor 542a and the conductor 542b, the conductor 560 does not have a region that overlaps with the conductor 542a or the conductor 542b. This reduces the parasitic capacitance formed between the conductor 560 and the conductor 542a and between the conductor 560 and the conductor 542b. This improves the switching speed of the transistor 500 and provides high frequency characteristics.

[0225] The conductor 560 may function as a first gate (also referred to as a top gate) electrode. The conductor 503 may function as a second gate (also referred to as a bottom gate) electrode. In this case, the threshold voltage of the transistor 500 can be controlled by changing the potential applied to the conductor 503 independently of the potential applied to the conductor 560. In particular, applying a negative potential to the conductor 503 can increase the threshold voltage of the transistor 500 and reduce the off-state current. Therefore, applying a negative potential to the conductor 503 can reduce the drain current when the potential applied to the conductor 560 is 0 V compared to not applying a negative potential to the conductor 503.

[0226] The conductor 503 is arranged to overlap the oxide 530 and the conductor 560. In this way, when a potential is applied to the conductor 560 and the conductor 503, the electric field generated from the conductor 560 and the electric field generated from the conductor 503 are connected, and the channel formation region formed in the oxide 530 can be covered. In this specification and the like, a transistor structure in which the channel formation region is electrically surrounded by the electric fields of the first gate electrode and the second gate electrode is called a surrounded channel (S-channel) structure.

[0227] The conductor 503 has a structure similar to that of the conductor 518, in which the conductor 503a is formed in contact with the inner walls of the openings of the insulators 514 and 516, and the conductor 503b is formed further inward. Note that although the transistor 500 has a structure in which the conductor 503a and the conductor 503b are stacked, one embodiment of the present invention is not limited to this. For example, the conductor 503 may have a single layer structure or a stacked structure of three or more layers.

[0228] Here, the conductor 503a is preferably made of a conductive material that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, and copper atoms (the impurities are less likely to permeate). Alternatively, it is preferably made of a conductive material that has the function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.) (the oxygen is less likely to permeate). In this specification, the function of suppressing the diffusion of impurities or oxygen refers to the function of suppressing the diffusion of any one or all of the impurities and oxygen.

[0229] For example, the conductor 503a has a function of suppressing the diffusion of oxygen, so that the conductor 503b can be prevented from being oxidized and its conductivity from decreasing.

[0230] Furthermore, when the conductor 503 also functions as a wiring, it is preferable that the conductor 503b be made of a highly conductive material containing tungsten, copper, or aluminum as a main component. Furthermore, when the conductivity of the wiring can be maintained at a high level, the conductor 503a is not necessarily provided. While the conductor 503b is illustrated as a single layer, it may have a multilayer structure, for example, a multilayer structure of titanium or titanium nitride and the above-mentioned conductive material.

[0231] The insulators 520, 522, and 524 function as a second gate insulating film.

[0232] Here, the insulator 524 in contact with the oxide 530 preferably contains more oxygen than the oxygen required for the stoichiometric composition. In other words, the insulator 524 preferably has an excess oxygen region. By providing an insulator containing such excess oxygen in contact with the oxide 530, oxygen vacancies in the oxide 530 can be reduced, improving the reliability of the transistor 500. Note that in this specification and elsewhere, oxygen vacancies in a metal oxide are referred to as V O This is sometimes called oxygen vacancy.

[0233] A transistor using a metal oxide has impurities or oxygen vacancies (V O ) may cause fluctuations in electrical characteristics and reduce reliability. O ) hydrogen near the oxygen vacancy (V O ) with hydrogen (hereafter referred to as V O H.) and generate electrons that serve as carriers. Therefore, if oxygen vacancies are present in the region where a channel is formed in the oxide semiconductor, the transistor is likely to have normally-on characteristics (a channel exists and current flows through the transistor even when no voltage is applied to the gate electrode). Therefore, in the region where a channel is formed in the oxide semiconductor, impurities, oxygen vacancies, and V O It is preferable that H is reduced as much as possible. In other words, it is preferable that the region in the oxide semiconductor where a channel is formed has a reduced carrier concentration and is i-type (intrinsic) or substantially i-type.

[0234] Specifically, it is preferable to use an oxide material from which a portion of oxygen is released by heating as an insulator having an excess oxygen region. The oxide material from which oxygen is released by heating is an oxide material from which the amount of released oxygen converted to oxygen atoms is 1.0 × 10 in TDS (Thermal Desorption Spectroscopy) analysis. 18 atoms / cm 3 or more, preferably 1.0 × 10 19 atoms / cm 3More preferably, 2.0 × 10 19 atoms / cm 3 or more, or 3.0 x 10 20 atoms / cm 3 The oxide film is one having the above properties. The surface temperature of the film during the TDS analysis is preferably in the range of 100°C or higher and 700°C or lower, or 100°C or higher and 400°C or lower.

[0235] Alternatively, the oxide 530 may be brought into contact with the insulator having the excess oxygen region and subjected to one or more of heat treatment, microwave treatment, and RF treatment. By performing such treatment, water or hydrogen in the oxide 530 can be removed. For example, a reaction occurs in the oxide 530 that breaks the VOH bond, in other words, "V O H→V O +H" reaction occurs, resulting in dehydrogenation. Some of the generated hydrogen may combine with oxygen to form HO and be removed from the oxide 530 or the insulator near the oxide 530. Some of the hydrogen may also be diffused or captured (also called gettered) in the conductor 542a and the conductor 542b.

[0236] The microwave treatment is preferably performed using, for example, an apparatus having a power source for generating high-density plasma or an apparatus having a power source for applying RF to the substrate side. For example, high-density oxygen radicals can be generated by using an oxygen-containing gas and high-density plasma, and the oxygen radicals generated by the high-density plasma can be efficiently introduced into the oxide 530 or an insulator near the oxide 530 by applying RF to the substrate side. The microwave treatment is performed at a pressure of 133 Pa or higher, preferably 200 Pa or higher, and more preferably 400 Pa or higher. The gases introduced into the microwave treatment apparatus may be, for example, oxygen and argon, with an oxygen flow ratio (O2 / (O2+Ar)) of 50% or less, preferably 10% to 30%.

[0237] During the manufacturing process of the transistor 500, heat treatment is preferably performed with the surface of the oxide 530 exposed. The heat treatment may be performed, for example, at a temperature of 100° C. to 450° C., more preferably 350° C. to 400° C. Note that the heat treatment is performed in a nitrogen gas or inert gas atmosphere, or an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more. For example, the heat treatment is preferably performed in an oxygen atmosphere. This supplies oxygen to the oxide 530, thereby eliminating oxygen vacancies (V O ) can be reduced. The heat treatment may be performed under reduced pressure. Alternatively, the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas after the heat treatment in a nitrogen gas or inert gas atmosphere to compensate for the desorbed oxygen. Alternatively, the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas, and then the heat treatment may be performed in a nitrogen gas or inert gas atmosphere.

[0238] By subjecting the oxide 530 to oxygen addition treatment, oxygen vacancies in the oxide 530 are repaired by the supplied oxygen. In other words, O Furthermore, the reaction of the hydrogen remaining in the oxide 530 with the supplied oxygen can be removed as HO (dehydration). As a result, the hydrogen remaining in the oxide 530 recombines with the oxygen vacancies to form V O The formation of H can be suppressed.

[0239] When the insulator 524 has an excess oxygen region, the insulator 522 preferably has a function of suppressing the diffusion of oxygen (for example, oxygen atoms, oxygen molecules, etc.) (preferably making the oxygen less permeable).

[0240] The insulator 522 preferably has a function of suppressing diffusion of oxygen, impurities, and the like, which prevents oxygen contained in the oxide 530 from diffusing toward the insulator 520. Furthermore, reaction of the conductor 503 with oxygen contained in the insulator 524 and the oxide 530 can be suppressed.

[0241] The insulator 522 is preferably a single-layer or multi-layer insulator containing a high-k material, such as aluminum oxide, hafnium oxide, oxide containing aluminum and hafnium (hafnium aluminate), tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO3), or (Ba,Sr)TiO3 (BST). As transistors become smaller and more highly integrated, thinner gate insulating films can cause problems such as leakage current. Using a high-k material for the insulator that functions as the gate insulating film makes it possible to reduce the gate potential during transistor operation while maintaining the physical film thickness.

[0242] In particular, an insulator containing an oxide of one or both of aluminum and hafnium, which is an insulating material that has the function of suppressing the diffusion of impurities and oxygen (i.e., is difficult for oxygen to permeate), is preferably used. As an insulator containing an oxide of one or both of aluminum and hafnium, aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate) is preferably used. When the insulator 522 is formed using such a material, the insulator 522 functions as a layer that suppresses oxygen release from the oxide 530 and the intrusion of impurities such as hydrogen into the oxide 530 from the periphery of the transistor 500.

[0243] Alternatively, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to these insulators. Alternatively, these insulators may be nitrided. Silicon oxide, silicon oxynitride, or silicon nitride may be stacked on the above insulators.

[0244] Furthermore, it is preferable that the insulator 520 is thermally stable. For example, silicon oxide and silicon oxynitride are suitable because they are thermally stable. Furthermore, by combining a high-k insulator with silicon oxide or silicon oxynitride, it is possible to obtain the insulator 520 having a thermally stable layered structure with a high dielectric constant.

[0245] 8A and 8B, the second gate insulating film has a three-layer stack structure including the insulators 520, 522, and 524. However, the second gate insulating film may have a single-layer, two-layer, or four or more-layer stack structure. In this case, the second gate insulating film is not limited to a stack structure made of the same material, and may have a stack structure made of different materials.

[0246] In the transistor 500, a metal oxide functioning as an oxide semiconductor is preferably used for the oxide 530 including the channel formation region. For example, a metal oxide such as In-M-Zn oxide (wherein the element M is one or more elements selected from aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, etc.) may be used for the oxide 530. In particular, the In-M-Zn oxide that can be used for the oxide 530 is preferably a C-Axis Aligned Crystalline Oxide Semiconductor (CAAC-OS) or a Cloud-Aligned Composite Oxide Semiconductor (CAC-OS). Alternatively, an In-Ga oxide, an In-Zn oxide, an In oxide, or the like may be used for the oxide 530.

[0247] Furthermore, it is preferable to use a metal oxide with a low carrier concentration for the transistor 500. To lower the carrier concentration of a metal oxide, the impurity concentration in the metal oxide should be lowered to lower the density of defect states. In this specification and the like, a low impurity concentration and a low density of defect states are referred to as high-purity intrinsic or substantially high-purity intrinsic. Examples of impurities in metal oxides include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, and silicon.

[0248] In particular, hydrogen contained in the metal oxide reacts with oxygen that bonds with the metal atom to form water, which can cause oxygen vacancies in the metal oxide. When hydrogen enters an oxygen vacancy in the oxide 530, the oxygen vacancy and hydrogen bond to form V. O May form H. V O H functions as a donor and may generate electrons as carriers. Furthermore, some of the hydrogen may bond with oxygen, which is bonded to a metal atom, to generate electrons as carriers. Therefore, a transistor using a metal oxide containing a large amount of hydrogen is likely to have normally-on characteristics. Furthermore, since hydrogen in a metal oxide is easily moved by stresses such as heat and an electric field, the reliability of the transistor may be reduced if the metal oxide contains a large amount of hydrogen. In one embodiment of the present invention, V in the oxide 530 O It is preferable to reduce H as much as possible to obtain high-purity intrinsic or substantially high-purity intrinsic V. O To obtain metal oxides with sufficiently reduced H, it is important to remove impurities such as water and hydrogen from the metal oxide (sometimes referred to as dehydration or dehydrogenation treatment), and to supply oxygen to the metal oxide to compensate for oxygen deficiencies (sometimes referred to as oxygen addition treatment). O By using a metal oxide in which impurities such as H are sufficiently reduced for the channel formation region of a transistor, stable electrical characteristics can be achieved.

[0249] Defects in which hydrogen has entered oxygen vacancies can function as donors in metal oxides. However, it is difficult to quantitatively evaluate such defects. Therefore, metal oxides are sometimes evaluated using carrier concentration rather than donor concentration. Therefore, in this specification and the like, the carrier concentration assuming a state in which no electric field is applied may be used as a parameter of metal oxides, rather than donor concentration. In other words, the "carrier concentration" described in this specification and the like may sometimes be rephrased as "donor concentration."

[0250] Therefore, when a metal oxide is used for the oxide 530, it is preferable that the hydrogen in the metal oxide is reduced as much as possible. Specifically, in the metal oxide, the hydrogen concentration obtained by secondary ion mass spectrometry (SIMS) is set to 1×10 20 atoms / cm 3 Less than 1 x 10 19 atoms / cm 3 less than 5 × 10 18 atoms / cm 3 less than 1×10 18 atoms / cm 3 By using a metal oxide in which impurities such as hydrogen are sufficiently reduced for a channel formation region of a transistor, stable electrical characteristics can be obtained.

[0251] When a metal oxide is used for the oxide 530, the metal oxide has a wide band gap and is an intrinsic (also referred to as I-type) or substantially intrinsic semiconductor. The carrier concentration of the metal oxide in the channel formation region is 1×10 18 cm -3 Preferably, it is less than 1 x 10 17 cm -3 More preferably, it is less than 1×10 16 cm -3 More preferably, it is less than 1×10 13 cm -3 More preferably, it is less than 1×10 12 cm -3The lower limit of the carrier concentration of the metal oxide in the channel formation region is not particularly limited, but is preferably, for example, 1×10 -9 cm -3 It can be said that:

[0252] Furthermore, when a metal oxide is used for the oxide 530, contact between the conductors 542a and 542b and the oxide 530 may cause oxygen in the oxide 530 to diffuse into the conductors 542a and 542b, resulting in the oxidation of the conductors 542a and 542b. The oxidation of the conductors 542a and 542b is likely to result in a decrease in the conductivity of the conductors 542a and 542b. The diffusion of oxygen in the oxide 530 to the conductors 542a and 542b can be rephrased as the conductors 542a and 542b absorbing the oxygen in the oxide 530.

[0253] Furthermore, oxygen in the oxide 530 diffuses into the conductor 542a and the conductor 542b, which may form a heterogeneous layer between the conductor 542a and the oxide 530b and between the conductor 542b and the oxide 530b. Since the heterogeneous layer contains more oxygen than the conductor 542a and the conductor 542b, it is presumed that the heterogeneous layer has insulating properties. In this case, the three-layer structure of the conductor 542a or the conductor 542b, the heterogeneous layer, and the oxide 530b can be regarded as a three-layer structure consisting of a metal, an insulator, and a semiconductor, and may be referred to as a metal-insulator-semiconductor (MIS) structure or a diode junction structure based on the MIS structure.

[0254] Note that the above-mentioned different layer is not limited to being formed between the conductor 542a and the conductor 542b and the oxide 530b, and for example, the different layer may be formed between the conductor 542a and the conductor 542b and the oxide 530c.

[0255] The metal oxide that functions as a channel formation region in the oxide 530 preferably has a band gap of 2 eV or more, preferably 2.5 eV or more. By using a metal oxide with a wide band gap, the off-state current of the transistor can be reduced.

[0256] The oxide 530 has the oxide 530a below the oxide 530b, which can prevent impurities from diffusing from structures formed below the oxide 530a to the oxide 530b. Also, the oxide 530 has the oxide 530c on the oxide 530b, which can prevent impurities from diffusing from structures formed above the oxide 530c to the oxide 530b.

[0257] The oxide 530 preferably has a stacked structure made up of multiple oxide layers with different atomic ratios of the metal atoms. Specifically, the atomic ratio of the element M among the constituent elements in the metal oxide used for the oxide 530a is preferably greater than the atomic ratio of the element M among the constituent elements in the metal oxide used for the oxide 530b. The atomic ratio of the element M to In in the metal oxide used for the oxide 530a is preferably greater than the atomic ratio of the element M to In in the metal oxide used for the oxide 530b. The atomic ratio of In to M in the metal oxide used for the oxide 530b is preferably greater than the atomic ratio of In to M in the metal oxide used for the oxide 530a. The oxide 530c can be made up of the same metal oxide as that used for the oxide 530a or the oxide 530b.

[0258] Specifically, oxide 530a may be a metal oxide having an atomic ratio of In, Ga, and Zn of In:Ga:Zn=1:3:4 or 1:1:0.5. Oxide 530b may be a metal oxide having an atomic ratio of In, Ga, and Zn of In:Ga:Zn=4:2:3 or 1:1:1. Oxide 530c may be a metal oxide having an atomic ratio of In, Ga, and Zn of In:Ga:Zn=1:3:4 and an atomic ratio of Ga to Zn of Ga:Zn=2:1 or Ga:Zn=2:5. Specific examples of the oxide 530c having a layered structure include layered structures in which the atomic ratios of In, Ga, and Zn are In:Ga:Zn=4:2:3 and In:Ga:Zn=1:3:4, layered structures in which the atomic ratios of Ga and Zn are Ga:Zn=2:1 and In:Ga:Zn=4:2:3, layered structures in which the atomic ratios of Ga and Zn are Ga:Zn=2:5 and In:Ga:Zn=4:2:3, and layered structures in which gallium oxide and In, Ga, and Zn are In:Ga:Zn=4:2:3.

[0259] Furthermore, for example, when the atomic ratio of In to element M in the metal oxide used for oxide 530a is smaller than the atomic ratio of In to element M in the metal oxide used for oxide 530b, an In-Ga-Zn oxide having a composition in which the atomic ratio of In to Ga to Zn is In:Ga:Zn=5:1:6 or thereabouts, In:Ga:Zn=5:1:3 or thereabouts, or In:Ga:Zn=10:1:3 or thereabouts, can be used as oxide 530b.

[0260] In addition to the compositions described above, oxide 530b may be made of a metal oxide having a composition of In:Zn=2:1, a composition of In:Zn=5:1, a composition of In:Zn=10:1, or a composition close to any one of these.

[0261] It is preferable to combine these oxides 530a, 530b, and 530c so that the atomic ratios satisfy the above relationship. For example, it is preferable that oxides 530a and 530c are metal oxides having a composition of In:Ga:Zn=1:3:4 or a composition close to that, and oxide 530b is a metal oxide having a composition of In:Ga:Zn=4:2:3 to 4.1 or a composition close to that. Note that the above compositions refer to the atomic ratios in the oxide formed on the substrate or in the sputtering target. Furthermore, increasing the In ratio in the composition of oxide 530b is preferable because it can increase the on-state current or field-effect mobility of the transistor.

[0262] The conduction band minimum energy of the oxide 530a and the oxide 530c is preferably higher than that of the oxide 530b. In other words, the electron affinity of the oxide 530a and the oxide 530c is preferably smaller than that of the oxide 530b.

[0263] Here, the energy level of the conduction band minimum changes gradually at the junction between the oxides 530a, 530b, and 530c. In other words, the energy level of the conduction band minimum at the junction between the oxides 530a, 530b, and 530c changes continuously or forms a continuous junction. To achieve this, it is preferable to reduce the defect level density of the mixed layers formed at the interface between the oxides 530a and 530b and at the interface between the oxides 530b and 530c.

[0264] Specifically, when the oxide 530a and the oxide 530b, and the oxide 530b and the oxide 530c have a common element (main component) other than oxygen, a mixed layer with a low density of defect states can be formed. For example, when the oxide 530b is an In-Ga-Zn oxide, the oxide 530a and the oxide 530c may be made of an In-Ga-Zn oxide, a Ga-Zn oxide, or a gallium oxide.

[0265] In this case, the oxide 530b serves as the main carrier path. By configuring the oxide 530a and the oxide 530c as described above, the defect state density at the interface between the oxide 530a and the oxide 530b and at the interface between the oxide 530b and the oxide 530c can be reduced. As a result, the influence of interface scattering on carrier conduction is reduced, and the transistor 500 can obtain a high on-state current.

[0266] Conductors 542a and 542b, which function as a source electrode and a drain electrode, are provided on oxide 530b. Conductors 542a and 542b are preferably made of a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, and lanthanum, or an alloy containing any of the above metal elements or an alloy combining any of the above metal elements. For example, tantalum nitride, titanium nitride, tungsten, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, or an oxide containing lanthanum and nickel is preferably used. In addition, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are preferred because they are conductive materials that are resistant to oxidation or materials that maintain conductivity even when absorbing oxygen. Furthermore, metal nitride films such as tantalum nitride are preferred because they have barrier properties against hydrogen or oxygen.

[0267] 8A and 8B, the conductor 542a and the conductor 542b are shown as single-layer structures, but they may also have a stacked structure of two or more layers. For example, a tantalum nitride film and a tungsten film may be stacked. Alternatively, a titanium film and an aluminum film may be stacked. Alternatively, a two-layer structure in which an aluminum film is stacked on a tungsten film, a two-layer structure in which a copper film is stacked on a copper-magnesium-aluminum alloy film, a two-layer structure in which a copper film is stacked on a titanium film, or a two-layer structure in which a copper film is stacked on a tungsten film may be used.

[0268] Further, there are three-layer structures in which a titanium film or titanium nitride film is laminated on the titanium film or titanium nitride film, an aluminum film or copper film is laminated on the titanium film or titanium nitride film, and a titanium film or titanium nitride film is further formed thereon, a three-layer structure in which a molybdenum film or molybdenum nitride film is laminated on the molybdenum film or molybdenum nitride film, an aluminum film or copper film is laminated on the molybdenum film or molybdenum nitride film, and a molybdenum film or molybdenum nitride film is further formed thereon, etc. Note that a transparent conductive material containing indium oxide, tin oxide, or zinc oxide may also be used.

[0269] 8A , regions 543a and 543b may be formed as low-resistance regions at and near the interfaces of the oxide 530 with the conductors 542a and 542b. In this case, the region 543a functions as one of a source region and a drain region, and the region 543b functions as the other of the source region and the drain region. A channel formation region is formed in the region between the regions 543a and 543b.

[0270] Providing the conductor 542a (conductor 542b) so as to be in contact with the oxide 530 may reduce the oxygen concentration in the region 543a (region 543b). Also, a metal compound layer containing the metal contained in the conductor 542a (conductor 542b) and components of the oxide 530 may be formed in the region 543a (region 543b). In such a case, the carrier concentration in the region 543a (region 543b) increases, and the region 543a (region 543b) becomes a low-resistance region.

[0271] The insulator 544 is provided to cover the conductors 542a and 542b and suppresses oxidation of the conductors 542a and 542b. In this case, the insulator 544 may be provided to cover the side surfaces of the oxide 530 and the insulator 524 and to be in contact with the insulator 522.

[0272] The insulator 544 can be a metal oxide containing one or more elements selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, neodymium, lanthanum, magnesium, etc. Alternatively, the insulator 544 can be silicon nitride oxide, silicon nitride, or the like.

[0273] In particular, it is preferable to use, as the insulator 544, an insulator containing an oxide of either or both of aluminum and hafnium, such as aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate). In particular, hafnium aluminate has higher heat resistance than a hafnium oxide film. Therefore, it is preferable because it is less likely to crystallize during heat treatment in a later process. Note that the insulator 544 is not an essential component if the conductors 542a and 542b are made of oxidation-resistant materials or if their conductivity does not decrease significantly even when they absorb oxygen. The insulator 544 may be designed appropriately depending on the desired transistor characteristics.

[0274] The insulator 544 can prevent impurities such as water and hydrogen contained in the insulator 580 from diffusing into the oxide 530b. The insulator 544 can also prevent the conductor 560 from being oxidized by excess oxygen contained in the insulator 580.

[0275] The insulator 550 functions as a first gate insulating film. The insulator 550 is preferably disposed in contact with the inside (top surface and side surface) of the oxide 530c. The insulator 550 is preferably formed using an insulator that contains excess oxygen and releases oxygen by heating, similar to the insulator 524 described above.

[0276] Specifically, silicon oxide having excess oxygen, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, and silicon oxide having vacancies can be used. In particular, silicon oxide and silicon oxynitride are preferable because they are stable against heat.

[0277] By providing the insulator 550, which releases oxygen upon heating, in contact with the top surface of the oxide 530c, oxygen can be effectively supplied from the insulator 550 to the channel formation region of the oxide 530b through the oxide 530c. Similar to the insulator 524, the concentration of impurities such as water or hydrogen in the insulator 550 is preferably reduced. The thickness of the insulator 550 is preferably 1 nm to 20 nm.

[0278] Furthermore, a metal oxide may be provided between the insulator 550 and the conductor 560 to efficiently supply excess oxygen contained in the insulator 550 to the oxide 530. The metal oxide preferably suppresses oxygen diffusion from the insulator 550 to the conductor 560. By providing a metal oxide that suppresses oxygen diffusion, the diffusion of excess oxygen from the insulator 550 to the conductor 560 is suppressed. In other words, a decrease in the amount of excess oxygen supplied to the oxide 530 can be suppressed. Furthermore, oxidation of the conductor 560 due to excess oxygen can be suppressed. As the metal oxide, a material that can be used for the insulator 544 may be used.

[0279] The insulator 550 may have a stacked structure, similar to the second gate insulating film. As transistors become smaller and more highly integrated, thinner gate insulating films can cause problems such as leakage current. Therefore, by using a stacked structure of a high-k material and a thermally stable material for the insulator that functions as the gate insulating film, it becomes possible to reduce the gate potential during transistor operation while maintaining the physical film thickness. Furthermore, a stacked structure that is thermally stable and has a high dielectric constant can be achieved.

[0280] The conductor 560 functioning as the first gate electrode is shown as a two-layer structure in FIGS. 8A and 8B, but may be a single-layer structure or a stacked structure of three or more layers.

[0281] The conductor 560a is preferably made of a conductive material that suppresses the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (e.g., NO, NO, and the like), and copper atoms. Alternatively, a conductive material that suppresses the diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, and the like) is preferably used. The conductor 560a has the function of suppressing the diffusion of oxygen, which can suppress the oxidation of the conductor 560b due to oxygen contained in the insulator 550 and a decrease in conductivity. Examples of conductive materials that suppress the diffusion of oxygen include tantalum, tantalum nitride, ruthenium, and ruthenium oxide. Alternatively, the conductor 560a can be made of an oxide semiconductor that can be used for the oxide 530. In this case, the conductor 560b can be formed by sputtering to reduce the electrical resistance of the conductor 560a, thereby making it a conductor. This can be referred to as an OC (Oxide Conductor) electrode.

[0282] The conductor 560b is preferably made of a conductive material containing tungsten, copper, or aluminum as a main component. Since the conductor 560b also functions as wiring, it is preferable to use a conductor with high conductivity. For example, a conductive material containing tungsten, copper, or aluminum as a main component can be used. The conductor 560b may have a layered structure, such as a layered structure of titanium or titanium nitride and the above conductive material.

[0283] The insulator 580 is provided over the conductor 542a and the conductor 542b with the insulator 544 interposed therebetween. The insulator 580 preferably has an excess oxygen region. For example, the insulator 580 preferably includes silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide doped with fluorine, silicon oxide doped with carbon, silicon oxide doped with carbon and nitrogen, silicon oxide having voids, or a resin. Silicon oxide and silicon oxynitride are particularly preferred because they are thermally stable. Silicon oxide and silicon oxide having voids are particularly preferred because they allow for easy formation of excess oxygen regions in a later step.

[0284] The insulator 580 preferably has an excess oxygen region. By providing the insulator 580, from which oxygen is released by heating, in contact with the oxide 530c, oxygen in the insulator 580 can be efficiently supplied to the oxide 530 through the oxide 530c. Note that the concentration of impurities such as water or hydrogen in the insulator 580 is preferably reduced.

[0285] The opening of the insulator 580 is formed to overlap the region between the conductor 542a and the conductor 542b, so that the conductor 560 is formed to be embedded in the opening of the insulator 580 and the region sandwiched between the conductor 542a and the conductor 542b.

[0286] When miniaturizing memory devices, it is necessary to shorten the gate length, but it is also necessary to prevent the conductivity of the conductor 560 from decreasing. If the film thickness of the conductor 560 is increased for this purpose, the conductor 560 may have a shape with a high aspect ratio. In this embodiment, the conductor 560 is provided so as to be embedded in the opening of the insulator 580. Therefore, even if the conductor 560 has a shape with a high aspect ratio, the conductor 560 can be formed without collapsing during the process.

[0287] The insulator 574 is preferably provided in contact with the top surface of the insulator 580, the top surface of the conductor 560, and the top surface of the insulator 550. By forming the insulator 574 by a sputtering method, excess oxygen regions can be provided in the insulator 550 and the insulator 580. This allows oxygen to be supplied from the excess oxygen regions into the oxide 530.

[0288] For example, the insulator 574 can be a metal oxide containing one or more elements selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, magnesium, and the like.

[0289] In particular, aluminum oxide has high barrier properties and can suppress the diffusion of hydrogen and nitrogen even when it is a thin film with a thickness of 0.5 nm to 3.0 nm. Therefore, aluminum oxide formed by sputtering can function as both an oxygen source and a barrier film against impurities such as hydrogen.

[0290] Parts of the insulators 574, 580, 544, 522, 520, 516, and 514 are removed to form openings that surround the transistor 500 and expose the insulator 513, thereby forming an insulator 576 with high barrier properties against hydrogen or water. Therefore, the side surfaces of the insulators 574, 580, 544, 522, 520, 516, and 514 are in contact with the insulator 576. This prevents moisture and hydrogen from entering the transistor 500 from the outside.

[0291] As described above, the insulators 513 and 576 preferably have a high function of suppressing diffusion of hydrogen (for example, at least one of a hydrogen atom, a hydrogen molecule, and the like) or water molecules. For example, silicon nitride or silicon nitride oxide, which are materials with high hydrogen barrier properties, are preferably used for the insulators 513 and 576. This can suppress diffusion of hydrogen and the like into the oxide 530, thereby suppressing deterioration in the characteristics of the transistor 500. Therefore, the reliability of the memory device of one embodiment of the present invention can be improved.

[0292] An insulator 581 functioning as an interlayer film or a planarizing film is preferably provided over the insulator 576. Like the insulator 524, the insulator 581 preferably has a low concentration of impurities such as water or hydrogen.

[0293] Furthermore, an insulator 552 is provided on the side surfaces of openings formed in insulators 581, 576, 574, 580, and 544. Then, conductors 540a and 540b are provided so as to contact the side surfaces of insulator 552 and the bottom surfaces of the openings. Note that in FIG. 8A , conductors 540a and 540b are provided opposite each other with conductor 560 interposed therebetween.

[0294] The insulator 552 is provided in contact with, for example, the insulator 581, the insulator 576, the insulator 574, the insulator 580, and the insulator 544. The insulator 552 preferably has a function of suppressing diffusion of hydrogen or water molecules. For example, the insulator 552 is preferably formed using an insulator with high hydrogen barrier properties, such as silicon nitride, aluminum oxide, or silicon nitride oxide. Silicon nitride is particularly suitable for use as the insulator 552 because it has high hydrogen barrier properties. Using a material with high hydrogen barrier properties for the insulator 552 can suppress diffusion of impurities such as water or hydrogen from the insulator 580 or the like to the oxide 530 through the conductors 540a and 540b. Furthermore, oxygen contained in the insulator 580 can be suppressed from being absorbed by the conductors 540a and 540b. Thus, the reliability of the memory device of one embodiment of the present invention can be improved.

[0295] The conductor 540a and the conductor 540b can be formed using, for example, the same material as the conductor 328, the conductor 330, the conductor 503, etc. In particular, it is preferable that each of the conductors 540a and 540b has a stacked structure of two or more layers, in which the first layer in contact with the insulator 552 is formed of a conductive material that has a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, and copper atoms (the impurities are less likely to permeate), and the second and subsequent layers are formed of a conductive material with high conductivity that contains tungsten, copper, aluminum, or the like as a main component.

[0296] 7, an insulator 582 is provided over an insulator 581. The insulator 582 is preferably made of a substance that has a barrier property against oxygen and / or hydrogen. Therefore, the insulator 582 can be made of a material similar to that of the insulator 514. For example, the insulator 582 is preferably made of a metal oxide such as aluminum oxide, hafnium oxide, or tantalum oxide.

[0297] In particular, aluminum oxide has a high blocking effect of preventing the permeation of both oxygen and impurities such as hydrogen and moisture, which can cause fluctuations in the electrical characteristics of a transistor. Therefore, aluminum oxide can prevent impurities such as hydrogen and moisture from entering the transistor 500 during and after the transistor manufacturing process. Furthermore, aluminum oxide can suppress the release of oxygen from the oxide that constitutes the transistor 500. Therefore, aluminum oxide is suitable for use as a protective film for the transistor 500.

[0298] An insulator 586 is provided over the insulator 582. The insulator 586 can be formed using a material similar to that of the insulator 320. By using a material with a relatively low dielectric constant for these insulators, parasitic capacitance between wirings can be reduced. For example, a silicon oxide film, a silicon oxynitride film, or the like can be used as the insulator 586.

[0299] 7 and 8A, conductors 540a, 540b, 546, etc. are embedded in insulators 520, 522, 524, 544, 580, 574, 576, 581, 582, and 586. Note that as conductor 546, for example, a material that can be used for conductors 540a and 540b can be used.

[0300] The conductor 540a, the conductor 540b, and the conductor 546 function as plugs or wirings that connect the transistor 500, the transistor 300, and the conductors 450 and 460 described later. The conductors 540a and 540b can be formed using the same material as the conductors 328 and 330. In particular, in FIG. 7, the conductor 546 is formed so as to be in contact with the conductor 518.

[0301] The conductor 450 may be provided over the conductor 540a, the conductor 540b, the conductor 546, and the insulator 586. The conductor 450 functions as a wiring that connects the conductor 460, the transistor 300, the transistor 500, and the like, which will be described later. In particular, in FIG. 7, the conductor 450 is formed so as to be in contact with the conductor 540a, the conductor 540b, the conductor 546, and the like.

[0302] For example, a metal film containing an element selected from molybdenum, titanium, tantalum, tungsten, aluminum, copper, chromium, neodymium, and scandium, or a metal nitride film containing any of the above elements (tantalum nitride film, titanium nitride film, molybdenum nitride film, tungsten nitride film), etc. can be used for the conductor 450. Alternatively, a conductive material such as indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, or indium tin oxide added with silicon oxide can also be used.

[0303] 7, the conductor 450 has a single-layer structure, but is not limited to this structure and may have a stacked structure of two or more layers. For example, a conductor having a barrier property and a conductor having high adhesion to the conductor having high conductivity may be formed between a conductor having a barrier property and a conductor having high conductivity.

[0304] Next, a description will be given of the configuration of the memory element 400. In this configuration example, the memory element 400 is an MTJ element ME included in the resistance change device MD of the memory cell MC in FIGS. 3A and 3B.

[0305] The memory element 400 is provided in a partial region on the conductor 450. The memory element 400 has a conductor 401, an insulator 402, a conductor 403, and a conductor 404, and the conductor 401, the insulator 402, the conductor 403, and the conductor 404 are stacked in this order in the region.

[0306] The conductor 401 is a free layer in the memory element 400 and corresponds to the layer FL of the MTJ element ME in FIG. 4. The insulator 402 is a tunnel insulator in the memory element 400 and corresponds to the layer TIS of the MTJ element ME in FIG. 4. The conductor 403 is a fixed layer in the MTJ element ME and corresponds to the layer RL of the MTJ element ME in FIG. 4. Therefore, for materials that can be applied to the conductor 401, the insulator 402, and the conductor 403, please refer to the description of the MTJ element ME in FIG. 4.

[0307] The conductor 404 is provided as a hard mask for forming the conductor 401, the insulator 402, and the conductor 403. Therefore, for the conductor 404, for example, a material that can be applied to the conductor 328, the conductor 330, and the like can be used.

[0308] The insulator 452 is provided to cover the insulator 586, the conductor 450, the conductor 401, the insulator 402, the conductor 403, and the conductor 404.

[0309] As the insulator 452, for example, like the insulator 324, a film having a barrier property that prevents impurities such as water and hydrogen from diffusing into a region where the transistor 500 is provided is preferably used. That is, as the insulator 452, a material that can be used for the insulator 324 is preferably used.

[0310] An insulator 454 is provided over the insulator 452. The insulator 454 functions as a planarizing film that flattens steps formed by the conductor 450, the memory element 400, the insulator 452, and the like. The insulator 454 can be formed, for example, by forming an insulator to be the insulator 454 over the insulator 452 and then performing planarization treatment by a chemical mechanical polishing (CMP) method or the like until the conductor 404 is exposed.

[0311] An insulator 456 is provided over the insulator 454 , the insulator 452 , and the conductor 404 .

[0312] For the insulators 454 and 456, it is preferable to use, for example, an insulator with a relatively low relative dielectric constant, similar to the insulator 326. In other words, it is preferable to use, for the insulators 454 and 456, a material that can be used for the insulator 326.

[0313] A conductor 457 is embedded in the insulator 456. A conductor 458 is embedded in the insulators 452, 454, and 456. The conductors 457 and 458 function as plugs or wiring. A plurality of conductors that function as plugs or wiring may be collectively denoted by the same reference numeral. In this specification and the like, a wiring and a plug connected to the wiring may be integral. That is, there are cases where a part of a conductor functions as a wiring and cases where a part of a conductor functions as a plug.

[0314] A conductor 460 is provided over the insulator 456, the conductor 457, and the conductor 458. The conductor 460 can be, for example, a wiring electrically connected to the memory element 400. Specifically, the conductor 460 can be the wiring RBL shown in the memory cell MC in FIG.

[0315] For the conductor 460, for example, a material that can be used for the conductor 450 can be used.

[0316] An insulator 459 is provided on the insulator 456. In some cases, the insulator 459 may also be provided on the conductor 457 and / or the conductor 458. The insulator 459 functions, for example, as an insulator for separating wirings. Note that in the memory device MDV of FIG. 7, the insulator 459 is made flush with the conductor 460 by a planarization process such as chemical mechanical polishing (CMP).

[0317] The insulator 459 is preferably made of an insulator having a relatively low relative dielectric constant, similar to the insulator 326. In other words, the insulator 459 is preferably made of a material that can be used for the insulator 326.

[0318] In addition, an insulator 462 is provided over the conductor 460 and the insulator 459.

[0319] For example, it is preferable to use a film having a barrier property that prevents impurities such as water and hydrogen from diffusing between the upper and lower OSL layers as the insulator 462. Therefore, it is preferable to use an insulator having a barrier property against impurities such as water and hydrogen as the insulator 462, similar to the insulator 324, for example.

[0320] Moreover, layers OSL[2] (not shown) to OSL[p] are provided above the insulator 462, and the layers OSL[2] to OSL[p] can be fabricated using the same process as the layer OSL[1]. Therefore, the insulator 462 may be formed using the same material as the insulator 510. Furthermore, by fabricating the layers OSL[2] to OSL[p] using the same process as the layer OSL[1], it is possible to stack, for example, each of the memory cell arrays MCA of the layers OSL[2] to OSL[p] above the memory cell array MCA included in the layer OSL[1]. In other words, it is possible to stack each of the memory cells 600 of the layers OSL[2] to OSL[p] above the memory cell 600 included in the layer OSL[1]. The configuration example of the memory device MDV shown in FIG. 7 can be applied to the memory device MDV of FIG. 1B.

[0321] Note that although FIG. 7 shows a configuration example of the memory device MDV in which the memory cell 600 is the memory cell MC in FIG. 3A, one embodiment of the present invention is not limited to this.

[0322] For example, the memory device MDV may be configured with the memory cell MC of Fig. 3C as the memory cell 600. Fig. 9 shows the configuration of the memory device MDV with the memory cell MC of Fig. 3C as the memory cell 600.

[0323] Specifically, in the memory device MDV of FIG. 9, the transistor 500A corresponds to the transistor M4 of FIG. 3C, the transistor 500B corresponds to the transistor M3, and the memory element 400 corresponds to the resistance change device MD.

[0324] In the memory device MDV of FIG. 9 , the transistors 500A and 500B are formed to share the insulator 524, the oxide 530a, the oxide 530b, and either the conductor 542a or the conductor 542b. The insulator 580 and the conductor 542 have two openings that reach the oxide 530, and each opening contains an oxide 530c, an insulator 550, and a conductor 560. This allows the first terminal of the transistor 500A and the first terminal of the transistor 500B to share either the conductor 542a or the conductor 542b. Furthermore, the area in which the transistors 500A and 500B are formed can be smaller than the area in which the transistors 500A and 500B are formed separately. This allows the area required to form the memory cell 600 to be reduced, thereby reducing the area per bit, or the bit density.

[0325] In the memory device MDV of Figure 9, the first terminal of transistor 500A is electrically connected to the first terminal of transistor 500B, the second terminal of transistor 500B is electrically connected to the first terminal of memory element 400, and the second terminal of memory element 400 is electrically connected to the second terminal of transistor 500A.

[0326] 3C can be, for example, a conductor 450 electrically connected to the first terminal of the transistor 500A and the first terminal of the transistor 500B. The wiring BL in FIG. 3C can be, for example, a conductor 450 electrically connected between the second terminal of the transistor 500B and the memory element 400.

[0327] 3C can be, for example, the conductor 560 corresponding to the gate of the transistor 500B. The wiring WLb in FIG. 3C can be, for example, the conductor 560 corresponding to the gate of the transistor 500A.

[0328] Also, for example, the memory device MDV may be configured with the memory cell MC of Figures 6A to 6C as the memory cell 600. Figure 10 shows the configuration of the memory device MDV with the memory cell MC of Figures 6A to 6C as the memory cell 600.

[0329] 10, the transistor 500A corresponds to the transistor M10 in FIGS. 6A to 6C, and the memory element 400 corresponds to the MTJ element in FIG. 6A, the resistance change element RM in FIG. 6B, the phase change memory PCM1 in FIG. 6C, etc. Therefore, in the memory device MDV in FIG. 10, a first terminal of the transistor 500A is electrically connected to a first terminal of the memory element 400.

[0330] 6A to 6C can be, for example, a conductor 450 electrically connected to the second terminal of the transistor 500A. The wiring BL in FIGS. 6A to 6C can be, for example, a conductor 460 electrically connected to the second terminal of the memory element 400. The wiring WL in FIGS. 6A to 6C can be, for example, a conductor 560 electrically connected to the gate of the transistor 500A.

[0331] 6A to 6C. Therefore, in the memory device MDV in FIG. 10, the location where the memory element 400 is formed is indicated by vertically hatched stripes. Also, in FIG. 10, an insulator 452 is provided on the side surface of the memory element 400, but depending on the configuration of the memory element 400, the insulator 452 may not be provided on the side surface of the memory element 400.

[0332] By applying the above configuration to a storage device, it is possible to provide a storage device with low power consumption, a storage device with a large storage capacity, or a novel storage device.

[0333] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0334] (Embodiment 3) In this embodiment, a metal oxide (hereinafter also referred to as an oxide semiconductor) that can be used for the OS transistor described in the above embodiment will be described.

[0335] The metal oxide preferably contains at least indium or zinc. It is particularly preferable that it contains indium and zinc. It is also preferable that it contains aluminum, gallium, yttrium, tin, or the like in addition to these. It may also contain one or more elements selected from boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, cobalt, and the like.

[0336] <Classification of crystal structures> First, classification of crystal structures in oxide semiconductors will be described with reference to Fig. 11A. Fig. 11A is a diagram illustrating classification of crystal structures of oxide semiconductors, typically IGZO (a metal oxide containing In, Ga, and Zn).

[0337] As shown in FIG. 11A, oxide semiconductors are broadly classified into "amorphous," "crystalline," and "crystal." "Amorphous" includes completely amorphous. "Crystalline" includes c-axis-aligned crystalline (CAAC), nanocrystalline (nc), and cloud-aligned composite (CAC) (excluding single crystal and polycrystal). "Crystalline" excludes single crystal, polycrystal, and completely amorphous. "Crystalline" includes single crystal and polycrystal.

[0338] The structure within the bold frame in Figure 11A is an intermediate state between "amorphous" and "crystal" and belongs to a new boundary region (new crystalline phase). In other words, this structure can be said to be completely different from the energetically unstable "amorphous" and "crystal."

[0339] The crystalline structure of a film or substrate can be evaluated using X-ray diffraction (XRD) spectroscopy. Figure 11B shows the XRD spectrum obtained by GIXD (Grazing-Incidence XRD) measurement of a CAAC-IGZO film classified as "Crystalline" (the vertical axis represents intensity in arbitrary units (au)). The GIXD method is also known as the thin-film method or the Seemann-Bohlin method. Hereinafter, the XRD spectrum obtained by GIXD measurement shown in Figure 11B may be simply referred to as the XRD spectrum. The composition of the CAAC-IGZO film shown in Figure 11B is approximately In:Ga:Zn = 4:2:3 [atomic ratio]. The thickness of the CAAC-IGZO film shown in Figure 11B is 500 nm.

[0340] As shown in Figure 11B, a clear peak indicating crystallinity is detected in the XRD spectrum of the CAAC-IGZO film. Specifically, a peak indicating c-axis orientation is detected near 2θ = 31° in the XRD spectrum of the CAAC-IGZO film. As shown in Figure 11B, the peak near 2θ = 31° is asymmetrical with respect to the angle at which the peak intensity is detected.

[0341] The crystalline structure of a film or substrate can be evaluated by the diffraction pattern (also called the nanobeam electron diffraction pattern) observed by nanobeam electron diffraction (NBED). The diffraction pattern of the CAAC-IGZO film is shown in Figure 11C. Figure 11C shows a diffraction pattern observed by NBED, in which an electron beam is incident parallel to the substrate. The composition of the CAAC-IGZO film shown in Figure 11C is approximately In:Ga:Zn = 4:2:3 [atomic ratio]. In the nanobeam electron diffraction method, electron diffraction is performed using a probe diameter of 1 nm.

[0342] As shown in Figure 11C, multiple spots indicating c-axis orientation are observed in the diffraction pattern of the CAAC-IGZO film.

[0343] <<Structure of oxide semiconductor>> Note that oxide semiconductors may be classified differently from those shown in FIG. 11A when focusing on their crystal structures. For example, oxide semiconductors are divided into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. Examples of non-single-crystal oxide semiconductors include the above-mentioned CAAC-OS and nc-OS. Non-single-crystal oxide semiconductors include polycrystalline oxide semiconductors, amorphous-like oxide semiconductors (a-like OSs), amorphous oxide semiconductors, and the like.

[0344] Here, the above-mentioned CAAC-OS, nc-OS, and a-like OS will be described in detail.

[0345] [CAAC-OS] CAAC-OS is an oxide semiconductor having multiple crystalline regions, each with its c-axis aligned in a specific direction. The specific direction can be the thickness direction of the CAAC-OS film, the normal direction to the surface on which the CAAC-OS film is formed, or the normal direction to the surface of the CAAC-OS film. A crystalline region is a region with periodic atomic arrangement. If the atomic arrangement is considered as a lattice arrangement, a crystalline region can also be a region with a uniform lattice arrangement. Furthermore, CAAC-OS has a region where multiple crystalline regions are connected in the ab-plane direction, and the region may have distortion. Note that distortion refers to a location where the lattice arrangement changes between a region with a uniform lattice arrangement and a region with a different uniform lattice arrangement in the region where multiple crystalline regions are connected. In other words, CAAC-OS is an oxide semiconductor with a c-axis aligned but no clear orientation in the ab-plane direction.

[0346] Each of the multiple crystalline regions is composed of one or more minute crystals (crystals with a maximum diameter of less than 10 nm). When a crystalline region is composed of one minute crystal, the maximum diameter of the crystalline region is less than 10 nm. When a crystalline region is composed of many minute crystals, the size of the crystalline region may be several tens of nm.

[0347] In an In-M-Zn oxide (wherein M is one or more elements selected from aluminum, gallium, yttrium, tin, titanium, etc.), the CAAC-OS tends to have a layered crystal structure (also referred to as a layered structure) in which a layer containing indium (In) and oxygen (hereinafter referred to as an In layer) and a layer containing M, zinc (Zn), and oxygen (hereinafter referred to as an (M, Zn) layer) are stacked. Note that indium and the element M are mutually substituted. Therefore, the (M, Zn) layer may contain indium. The In layer may contain M. The In layer may contain Zn. The layered structure is observed as a lattice image in a high-resolution TEM image, for example.

[0348] When the CAAC-OS film is subjected to structural analysis using, for example, an XRD apparatus, a peak indicating c-axis orientation is detected at or near 2θ=31° in out-of-plane XRD measurement using θ / 2θ scan. Note that the position of the peak indicating c-axis orientation (2θ value) may vary depending on the type and composition of the metallic elements constituting the CAAC-OS.

[0349] Furthermore, for example, in the electron diffraction pattern of the CAAC-OS film, multiple bright spots are observed, and the spots are observed at positions that are point-symmetric with respect to the spot of the incident electron beam that has passed through the sample (also called the direct spot).

[0350] When the crystalline region is observed from the specific direction, the lattice arrangement within the crystalline region is basically a hexagonal lattice, but the unit cell is not necessarily a regular hexagon and may be non-regular hexagonal. Furthermore, the distortion may have a pentagonal, heptagonal, or other lattice arrangement. In the CAAC-OS, no clear grain boundaries are observed even near the distortion. This indicates that the formation of grain boundaries is suppressed by the distortion of the lattice arrangement. This is thought to be because the CAAC-OS can tolerate distortion due to the lack of close-packed oxygen atom arrangement in the ab-plane direction and the change in interatomic bond distance caused by metal atom substitution.

[0351] A crystal structure with clear grain boundaries is called polycrystalline. Grain boundaries act as recombination centers, trapping carriers and potentially causing a decrease in the on-state current and field-effect mobility of a transistor. Therefore, CAAC-OS, which lacks clear grain boundaries, is one of the crystalline oxides with a crystal structure suitable for use in the semiconductor layer of a transistor. Zn is preferred for use in CAAC-OS. For example, In-Zn oxide and In-Ga-Zn oxide are suitable because they can suppress the generation of grain boundaries more effectively than In oxide.

[0352] CAAC-OS is an oxide semiconductor with high crystallinity and no clear crystal grain boundaries. Therefore, it can be said that the CAAC-OS is less susceptible to a decrease in electron mobility due to crystal grain boundaries. Furthermore, since the crystallinity of an oxide semiconductor can be reduced by the inclusion of impurities or the formation of defects, the CAAC-OS can also be said to be an oxide semiconductor with few impurities and defects (such as oxygen vacancies). Therefore, oxide semiconductors with CAAC-OS have stable physical properties. Therefore, oxide semiconductors with CAAC-OS are heat-resistant and highly reliable. Furthermore, the CAAC-OS is stable even under high temperatures (so-called thermal budget) during the manufacturing process. Therefore, using a CAAC-OS for an OS transistor can increase the flexibility of the manufacturing process.

[0353] [nc-OS] The nc-OS has periodic atomic arrangement in a microscopic region (e.g., a region of 1 nm to 10 nm, particularly a region of 1 nm to 3 nm). In other words, the nc-OS has microcrystals. Note that the size of the microcrystals is, for example, 1 nm to 10 nm, particularly 1 nm to 3 nm, and therefore the microcrystals are also called nanocrystals. Furthermore, the nc-OS exhibits no regularity in the crystal orientation between different nanocrystals. Therefore, no orientation is observed throughout the film. Therefore, depending on the analytical method, the nc-OS may be indistinguishable from an a-like OS and an amorphous oxide semiconductor. For example, when a structural analysis of an nc-OS film is performed using an XRD apparatus, no peaks indicating crystallinity are detected in out-of-plane XRD measurements using θ / 2θ scanning. Furthermore, when an nc-OS film is subjected to electron diffraction (also known as selected-area electron diffraction) using an electron beam with a probe diameter larger than that of nanocrystals (e.g., 50 nm or larger), a halo-like diffraction pattern is observed. On the other hand, when electron diffraction (also called nanobeam electron diffraction) is performed on an nc-OS film using an electron beam with a probe diameter close to or smaller than the size of the nanocrystals (for example, 1 nm to 30 nm), an electron diffraction pattern can be obtained in which multiple spots are observed within a ring-shaped region centered on the direct spot.

[0354] [a-like OS] The a-like OS is an oxide semiconductor having a structure between the nc-OS and the amorphous oxide semiconductor. The a-like OS has a pore or low-density region. That is, the a-like OS has lower crystallinity than the nc-OS and CAAC-OS. Furthermore, the a-like OS has a higher hydrogen concentration in the film than the nc-OS and CAAC-OS.

[0355] <<Oxide semiconductor structure>> Next, the above-mentioned CAC-OS will be described in detail, which relates to the material composition.

[0356] [CAC-OS] CAC-OS is a material structure in which elements constituting a metal oxide are unevenly distributed in a size range of 0.5 nm to 10 nm, preferably 1 nm to 3 nm, or a similar size range. Hereinafter, a metal oxide in which one or more metal elements are unevenly distributed and the regions containing the metal elements are mixed in a size range of 0.5 nm to 10 nm, preferably 1 nm to 3 nm, or a similar size range, is also referred to as a mosaic or patch state.

[0357] Furthermore, CAC-OS has a mosaic structure in which the material is separated into first and second regions, and the first regions are distributed throughout the film (hereinafter also referred to as a cloud structure). That is, CAC-OS is a composite metal oxide having a structure in which the first and second regions are mixed.

[0358] Here, the atomic ratios of In, Ga, and Zn to the metal elements constituting the CAC-OS in the In-Ga-Zn oxide are denoted as [In], [Ga], and [Zn], respectively. For example, in the CAC-OS in the In-Ga-Zn oxide, the first region is a region where [In] is larger than [In] in the composition of the CAC-OS film. The second region is a region where [Ga] is larger than [Ga] in the composition of the CAC-OS film. Alternatively, for example, the first region is a region where [In] is larger than [In] in the second region and [Ga] is smaller than [Ga] in the second region. The second region is a region where [Ga] is larger than [Ga] in the first region and [In] is smaller than [In] in the first region.

[0359] Specifically, the first region is a region whose main component is indium oxide, indium zinc oxide, or the like. The second region is a region whose main component is gallium oxide, gallium zinc oxide, or the like. In other words, the first region can be rephrased as a region whose main component is In. The second region can be rephrased as a region whose main component is Ga.

[0360] It should be noted that there are cases where a clear boundary between the first region and the second region cannot be observed.

[0361] For example, in the case of CAC-OS in In-Ga-Zn oxide, EDX mapping obtained using EDX (Energy Dispersive X-ray spectroscopy) confirms that the CAC-OS has a structure in which a region mainly composed of In (first region) and a region mainly composed of Ga (second region) are unevenly distributed and mixed.

[0362] When CAC-OS is used in a transistor, the conductivity due to the first region and the insulating property due to the second region act in a complementary manner, thereby providing the CAC-OS with a switching function (the ability to turn on and off). In other words, CAC-OS has a conductive function in part of the material and an insulating function in part of the material, and the material as a whole functions as a semiconductor. By separating the conductive function from the insulating function, both functions can be maximized. Therefore, by using CAC-OS in a transistor, a high on-current (I on ), high field-effect mobility (μ), and good switching behavior can be achieved.

[0363] Oxide semiconductors have a variety of structures, each with different characteristics. The oxide semiconductor of one embodiment of the present invention may include two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, an a-like OS, a CAC-OS, an nc-OS, and a CAAC-OS.

[0364] <Transistors containing oxide semiconductors> Next, a case where the oxide semiconductor is used in a transistor will be described.

[0365] By using the oxide semiconductor for a transistor, a transistor with high field-effect mobility and high reliability can be realized.

[0366] For the transistor, an oxide semiconductor with a low carrier concentration is preferably used. For example, the carrier concentration of the oxide semiconductor is 1×10 17 cm -3 Less than 1 × 10 15 cm -3 or less, more preferably 1 × 10 13 cm -3 Less than or equal to 1×10 11 cm -3 or less, more preferably 1 × 10 10 cm -3 Less than 1 x 10 -9 cm -3 The above is the case. Note that in order to reduce the carrier concentration of an oxide semiconductor film, the impurity concentration in the oxide semiconductor film may be reduced to reduce the density of defect states. In this specification and the like, a semiconductor having a low impurity concentration and a low density of defect states is referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor. Note that an oxide semiconductor having a low carrier concentration may also be referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor.

[0367] Furthermore, a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has a low density of defect states, and therefore the density of trap states may also be low.

[0368] Furthermore, charges trapped in the trap states of an oxide semiconductor take a long time to dissipate and may behave like fixed charges. Therefore, a transistor in which a channel formation region is formed in an oxide semiconductor with a high density of trap states may have unstable electrical characteristics.

[0369] Therefore, in order to stabilize the electrical characteristics of a transistor, it is effective to reduce the impurity concentration in the oxide semiconductor. Furthermore, in order to reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in the adjacent film. Examples of impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, and silicon.

[0370] <Impurities> Here, the influence of each impurity in an oxide semiconductor will be described.

[0371] When an oxide semiconductor contains silicon or carbon, which is one of the Group 14 elements, defect levels are formed in the oxide semiconductor. Therefore, the concentration of silicon or carbon in the oxide semiconductor and the concentration of silicon or carbon near the interface with the oxide semiconductor (concentration obtained by secondary ion mass spectrometry (SIMS)) are calculated to be 2×10 18 atoms / cm 3 Less than or equal to 2 x 10 17 atoms / cm 3 The following applies.

[0372] Furthermore, when an oxide semiconductor contains an alkali metal or alkaline earth metal, defect levels may be formed and carriers may be generated. Therefore, a transistor using an oxide semiconductor containing an alkali metal or alkaline earth metal is likely to have normally-on characteristics. For this reason, when the concentration of the alkali metal or alkaline earth metal in the oxide semiconductor obtained by SIMS is 1×10 18 atoms / cm 3 Less than or equal to 2 x 10 16 atoms / cm 3 Do the following:

[0373] Furthermore, when nitrogen is contained in an oxide semiconductor, electrons serving as carriers are generated, the carrier concentration increases, and the semiconductor is likely to become n-type. As a result, a transistor using an oxide semiconductor containing nitrogen as a semiconductor tends to have normally-on characteristics. Alternatively, when nitrogen is contained in an oxide semiconductor, trap states may be formed. As a result, the electrical characteristics of the transistor may become unstable. For this reason, the nitrogen concentration in the oxide semiconductor obtained by SIMS is set to 5×10 19 atoms / cm 3 Less than 5 x 10 18 atoms / cm 3 Less than or equal to 1×10 18 atoms / cm 3 Less than 5 × 10, more preferably 17 atoms / cm 3 Do the following:

[0374] Furthermore, hydrogen contained in an oxide semiconductor may react with oxygen bonded to a metal atom to form water, which may form an oxygen vacancy. When hydrogen enters the oxygen vacancy, electrons serving as carriers may be generated. Furthermore, some of the hydrogen may bond with oxygen bonded to a metal atom to generate electrons serving as carriers. Therefore, a transistor using an oxide semiconductor containing hydrogen is likely to have normally-on characteristics. For this reason, it is preferable to reduce the amount of hydrogen in the oxide semiconductor as much as possible. Specifically, the hydrogen concentration in an oxide semiconductor measured by SIMS is 1×10 20 atoms / cm 3 Less than 1 x 10 19 atoms / cm 3 less than 5 × 10 18 atoms / cm 3 less than 1×10 18 atoms / cm 3 Make it less than.

[0375] When an oxide semiconductor with sufficiently reduced impurities is used for a channel formation region of a transistor, stable electrical characteristics can be obtained.

[0376] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0377] (Fourth embodiment) This embodiment mode will describe an example of a semiconductor wafer on which the memory device or the like shown in the above embodiment mode is formed, and an example of an electronic component in which the memory device is incorporated.

[0378] <Semiconductor wafer> First, an example of a semiconductor wafer on which a memory device or the like is formed will be described with reference to FIG. 12A.

[0379] 12A includes a wafer 4801 and a plurality of circuit portions 4802 provided on the upper surface of the wafer 4801. Note that on the upper surface of the wafer 4801, a portion where the circuit portions 4802 are not present is a spacing 4803, which is a region for dicing.

[0380] The semiconductor wafer 4800 can be manufactured by forming a plurality of circuit portions 4802 on the surface of the wafer 4801 in a previous process. After that, the surface of the wafer 4801 opposite to the surface on which the plurality of circuit portions 4802 are formed may be ground to thin the wafer 4801. This process reduces warping of the wafer 4801 and allows for miniaturization of the component.

[0381] The next step is the dicing process. Dicing is performed along scribe lines SCL1 and SCL2 (sometimes called dicing lines or cutting lines) indicated by dashed lines. To facilitate the dicing process, spacing 4803 is preferably arranged so that multiple scribe lines SCL1 are parallel to each other, multiple scribe lines SCL2 are parallel to each other, and scribe lines SCL1 and SCL2 are perpendicular to each other.

[0382] By performing a dicing process, chips 4800a as shown in FIG. 12B can be cut out from semiconductor wafer 4800. Chip 4800a has wafer 4801a, circuit portion 4802, and spacing 4803a. It is preferable to make spacing 4803a as small as possible. In this case, it is sufficient that the width of spacing 4803 between adjacent circuit portions 4802 is approximately the same length as the cutting margin of scribe line SCL1 or the cutting margin of scribe line SCL2.

[0383] Note that the shape of the element substrate of one embodiment of the present invention is not limited to the shape of the semiconductor wafer 4800 illustrated in Figure 12A. For example, the semiconductor wafer may have a rectangular shape. The shape of the element substrate can be changed as appropriate depending on the manufacturing process and the device for manufacturing the element.

[0384] <Electronic components> FIG. 12C shows a perspective view of electronic component 4700 and a substrate (mounting substrate 4704) on which electronic component 4700 is mounted. Electronic component 4700 shown in FIG. 12C has chip 4800a in mold 4711. Note that chip 4800a shown in FIG. 12C has a configuration in which circuit unit 4802 is stacked. In other words, the memory device described in the above embodiment can be used as circuit unit 4802. FIG. 12C omits a portion to show the interior of electronic component 4700. Electronic component 4700 has lands 4712 on the outside of mold 4711. Lands 4712 are electrically connected to electrode pads 4713, and electrode pads 4713 are electrically connected to chip 4800a by wires 4714. Electronic component 4700 is mounted on, for example, a printed circuit board 4702. A plurality of such electronic components are combined and electrically connected on a printed circuit board 4702 to complete a mounting board 4704 .

[0385] 12D shows a perspective view of electronic component 4730. Electronic component 4730 is an example of a SiP (System in Package) or MCM (Multi Chip Module). Electronic component 4730 has an interposer 4731 provided on a package substrate 4732 (printed circuit board), and a semiconductor device 4735 and multiple semiconductor devices 4710 provided on interposer 4731.

[0386] The electronic component 4730 includes a semiconductor device 4710. The semiconductor device 4710 can be, for example, the memory device or high bandwidth memory (HBM) described in the above embodiment. The semiconductor device 4735 can be an integrated circuit (semiconductor device) such as a CPU, a GPU, an FPGA, or a memory device.

[0387] A ceramic substrate, a plastic substrate, a glass epoxy substrate, or the like can be used for the package substrate 4732. A silicon interposer, a resin interposer, or the like can be used for the interposer 4731.

[0388] The interposer 4731 has multiple wirings and functions to electrically connect multiple integrated circuits with different terminal pitches. The multiple wirings are provided in a single layer or multiple layers. The interposer 4731 also functions to electrically connect the integrated circuits provided on the interposer 4731 to electrodes provided on the package substrate 4732. For these reasons, the interposer is sometimes called a "rewiring substrate" or "intermediate substrate." In some cases, through electrodes are provided in the interposer 4731, and the integrated circuits and the package substrate 4732 are electrically connected using the through electrodes. In addition, in a silicon interposer, TSVs (Through Silicon Vias) can also be used as through electrodes.

[0389] It is preferable to use a silicon interposer as the interposer 4731. Since a silicon interposer does not require an active element, it can be manufactured at a lower cost than an integrated circuit. On the other hand, since the wiring of a silicon interposer can be formed using a semiconductor process, it is easy to form fine wiring that is difficult to form with a resin interposer.

[0390] HBM requires many interconnects to achieve a wide memory bandwidth. Therefore, the interposer that implements HBM requires fine and high-density interconnects. Therefore, it is preferable to use a silicon interposer for implementing HBM.

[0391] Furthermore, SiP, MCM, etc. that use silicon interposers are less likely to experience a decrease in reliability due to differences in the expansion coefficient between the integrated circuit and the interposer. Furthermore, because the silicon interposer has a highly flat surface, poor connections between the integrated circuit mounted on the silicon interposer and the silicon interposer are less likely to occur. Silicon interposers are particularly preferable for 2.5D packages (2.5-dimensional packaging), which place multiple integrated circuits side-by-side on an interposer.

[0392] A heat sink (heat sink) may be provided overlapping the electronic component 4730. When a heat sink is provided, it is preferable to align the height of an integrated circuit provided on the interposer 4731. For example, in the electronic component 4730 shown in this embodiment, it is preferable to align the height of the semiconductor device 4710 and the height of the semiconductor device 4735.

[0393] Electrodes 4733 may be provided on the bottom of package substrate 4732 in order to mount electronic component 4730 on another substrate. Fig. 12D shows an example in which electrodes 4733 are formed with solder balls. By providing solder balls in a matrix on the bottom of package substrate 4732, BGA (Ball Grid Array) mounting can be achieved. Electrodes 4733 may also be formed with conductive pins. By providing conductive pins in a matrix on the bottom of package substrate 4732, PGA (Pin Grid Array) mounting can be achieved.

[0394] The electronic component 4730 can be mounted on other substrates using various mounting methods, including but not limited to BGA and PGA, such as a staggered pin grid array (SPGA), a land grid array (LGA), a quad flat package (QFP), a quad flat J-leaded package (QFJ), or a quad flat non-leaded package (QFN).

[0395] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0396] (Embodiment 5) In this embodiment, a CPU that can include the storage device of the above embodiment will be described.

[0397] FIG. 13 is a block diagram showing an example of the configuration of a CPU that partially uses the storage device described in the above embodiments.

[0398] The CPU shown in FIG. 13 includes an ALU 1191 (Arithmetic logic unit, arithmetic circuit), an ALU controller 1192, an instruction decoder 1193, an interrupt controller 1194, a timing controller 1195, a register 1196, a register controller 1197, a bus interface 1198 (Bus I / F), a rewritable ROM 1199, and a ROM interface 1189 (ROM I / F) on a substrate 1190. The substrate 1190 may be a semiconductor substrate, an SOI substrate, a glass substrate, or the like. The ROM 1199 and the ROM interface 1189 may be provided on separate chips. Of course, the CPU shown in FIG. 13 is merely an example of a simplified configuration, and actual CPUs have a wide variety of configurations depending on their applications. For example, a configuration including the CPU or arithmetic circuit shown in FIG. 13 may be considered as one core, and a configuration including multiple such cores, each operating in parallel, such as a GPU, may be used. The number of bits that the CPU can handle in its internal arithmetic circuit, data bus, etc. can be, for example, 8 bits, 16 bits, 32 bits, 64 bits, etc.

[0399] An instruction input to the CPU via the bus interface 1198 is input to the instruction decoder 1193 , decoded, and then input to the ALU controller 1192 , interrupt controller 1194 , register controller 1197 , and timing controller 1195 .

[0400] The ALU controller 1192, interrupt controller 1194, register controller 1197, and timing controller 1195 perform various controls based on the decoded instructions. Specifically, the ALU controller 1192 generates signals for controlling the operation of the ALU 1191. Furthermore, the interrupt controller 1194 processes interrupt requests from external input / output devices, peripheral circuits, etc., based on their priority and mask status while the CPU is executing a program. The register controller 1197 generates addresses for the register 1196, and reads and writes data from and to the register 1196 depending on the CPU state.

[0401] Furthermore, the timing controller 1195 generates signals that control the timing of the operations of the ALU 1191, ALU controller 1192, instruction decoder 1193, interrupt controller 1194, and register controller 1197. For example, the timing controller 1195 includes an internal clock generation unit that generates an internal clock signal based on a reference clock signal, and supplies the internal clock signal to the various circuits described above.

[0402] 13, memory cells are provided in a register 1196. The register 1196 may include, for example, the storage device described in the above embodiments.

[0403] 13, the register controller 1197 selects the holding operation in the register 1196 in accordance with an instruction from the ALU 1191. That is, it selects whether to hold data in a memory cell of the register 1196 using a flip-flop or a capacitive element. If holding data in a flip-flop is selected, a power supply voltage is supplied to the memory cell in the register 1196. If holding data in a capacitive element is selected, the data is rewritten to the capacitive element, and the supply of power supply voltage to the memory cell in the register 1196 can be stopped.

[0404] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0405] (Embodiment 6) In this embodiment, an example of an electronic device including the memory device described in the above embodiment will be described. Note that Figures 14A to 14J and 15A to 15E illustrate how an electronic component 4700 including the memory device is included in each electronic device.

[0406] [mobile phone] 14A is a mobile phone (smartphone), which is one type of information terminal. The information terminal 5500 has a housing 5510 and a display unit 5511. As input interfaces, a touch panel is provided on the display unit 5511 and buttons are provided on the housing 5510.

[0407] The information terminal 5500 can store temporary files (such as caches when using a web browser) generated when an application is executed by applying the storage device described in the above embodiment.

[0408] [Wearable devices] 14B illustrates an information terminal 5900, which is an example of a wearable terminal. The information terminal 5900 includes a housing 5901, a display unit 5902, operation buttons 5903, an operator 5904, a band 5905, and the like.

[0409] Like the information terminal 5500 described above, the wearable terminal can store temporary files generated when an application is executed by applying the storage device described in the above embodiment.

[0410] [Information terminal] 14C also shows a desktop information terminal 5300. The desktop information terminal 5300 has a main body 5301 of the information terminal, a display 5302, and a keyboard 5303.

[0411] The desktop information terminal 5300, like the information terminal 5500 described above, can store temporary files generated when an application is executed by applying the storage device described in the above embodiment.

[0412] 14A to 14C are taken as examples of electronic devices, but information terminals other than smartphones, wearable terminals, and desktop information terminals can also be applied. Examples of information terminals other than smartphones, wearable terminals, and desktop information terminals include PDAs (Personal Digital Assistants), notebook information terminals, and workstations.

[0413] [electric appliances] 14D also illustrates, as an example of an electrical appliance, an electric refrigerator-freezer 5800. The electric refrigerator-freezer 5800 includes a housing 5801, a refrigerator door 5802, a freezer door 5803, and the like.

[0414] By applying the storage device described in the above embodiment to electric refrigerator-freezer 5800, electric refrigerator-freezer 5800 can be used as, for example, IoT (Internet of Things). By using IoT, electric refrigerator-freezer 5800 can transmit and receive information such as food ingredients stored in electric refrigerator-freezer 5800 and expiration dates of the food ingredients to the above-mentioned information terminals via the Internet or the like. Furthermore, when transmitting the information, electric refrigerator-freezer 5800 can store the information as a temporary file in the storage device.

[0415] In this example, an electric refrigerator-freezer has been described as an electrical appliance, but other electrical appliances include, for example, vacuum cleaners, microwave ovens, electric ovens, rice cookers, water heaters, induction cookers, water dispensers, heating and cooling appliances including air conditioners, washing machines, dryers, and audio-visual equipment.

[0416] [Game consoles] 14E illustrates a portable game machine 5200, which is an example of a game machine. The portable game machine 5200 includes a housing 5201, a display portion 5202, buttons 5203, and the like.

[0417] FIG. 14F further illustrates a home video game console 7500, an example of a video game console. The home video game console 7500 includes a main unit 7520 and a controller 7522. The controller 7522 can be connected to the main unit 7520 wirelessly or via a cable. Although not shown in FIG. 14F, the controller 7522 can include a display unit for displaying game images, a touch panel serving as an input interface other than buttons, a stick, a rotary knob, a sliding knob, or the like. The shape of the controller 7522 is not limited to that shown in FIG. 14F, and the shape of the controller 7522 may be varied in various ways depending on the genre of the game. For example, in a shooting game such as an FPS (First Person Shooter), a controller shaped like a gun with a trigger as a button can be used. In a music game, for example, a controller shaped like a musical instrument or musical equipment can be used. Furthermore, the stationary game console may not use a controller, but may instead be equipped with a camera, depth sensor, microphone, etc., and be operated by the game player's gestures and / or voice.

[0418] Furthermore, the images of the above-mentioned game machine can be output by a display device such as a television device, a display for a personal computer, a game display, or a head-mounted display.

[0419] A low-power portable game console 5200 can be realized by applying the storage device described in the above embodiment to the portable game console 5200 and the stationary game console 7500. Furthermore, low power consumption can reduce heat generation from a circuit, thereby reducing the influence of heat on the circuit itself, peripheral circuits, and modules.

[0420] Furthermore, by applying the storage device described in the above embodiment to the portable game console 5200 and the stationary game console 7500, temporary files and the like necessary for calculations that occur during game execution can be stored.

[0421] 14E and 14F illustrate a portable game machine and a stationary game machine as examples of game machines, but the electronic device of one embodiment of the present invention is not limited to these. Examples of the electronic device of one embodiment of the present invention include an arcade game machine installed in an entertainment facility (such as a game center or an amusement park) and a pitching machine for batting practice installed in a sports facility.

[0422] [Moving object] The storage device described in the above embodiment can be applied to a vehicle, which is a moving object, and to the vicinity of the driver's seat of the vehicle.

[0423] FIG. 14G illustrates an automobile 5700 as an example of a moving object.

[0424] An instrument panel that provides various information by displaying a speedometer, tachometer, mileage, fuel gauge, gear status, air conditioning settings, etc. may be provided around the driver's seat of the automobile 5700. A display device that shows this information may also be provided around the driver's seat.

[0425] In particular, by displaying images from an imaging device (not shown) installed in the automobile 5700, the display device can compensate for visibility obstructed by pillars, blind spots around the driver's seat, etc., thereby improving safety.

[0426] The storage device described in the above embodiment can temporarily store information, and therefore, for example, the storage device can be used to store necessary temporary information in an automatic driving system of the automobile 5700, a system that provides road guidance, hazard prediction, and the like. The display device may be configured to display temporary information such as road guidance and hazard prediction. The display device may also be configured to store video images from a driving recorder installed in the automobile 5700.

[0427] Although an automobile is described above as an example of a moving body, the moving body is not limited to an automobile. For example, moving bodies can include trains, monorails, ships, and flying bodies (helicopters, unmanned aerial vehicles (drones), airplanes, and rockets).

[0428] [camera] The storage device described in the above embodiment can be applied to a camera.

[0429] 14H shows a digital camera 6240, which is an example of an imaging device. The digital camera 6240 has a housing 6241, a display unit 6242, operation buttons 6243, a shutter button 6244, etc., and is also equipped with a detachable lens 6246. Note that, although the digital camera 6240 is configured such that the lens 6246 can be detached from the housing 6241 and replaced, the lens 6246 and the housing 6241 may be integrated. The digital camera 6240 may also be configured such that a strobe device, a viewfinder, etc. can be separately attached.

[0430] A low-power digital camera 6240 can be realized by applying the storage device described in the above embodiment to the digital camera 6240. Furthermore, low power consumption can reduce heat generation from the circuit, thereby reducing the influence of heat generation on the circuit itself, peripheral circuits, and modules.

[0431] [Video camera] The storage device described in the above embodiment can be applied to a video camera.

[0432] 14I shows a video camera 6300, which is an example of an imaging device. The video camera 6300 has a first housing 6301, a second housing 6302, a display unit 6303, operation keys 6304, a lens 6305, a connection unit 6306, and the like. The operation keys 6304 and the lens 6305 are provided in the first housing 6301, and the display unit 6303 is provided in the second housing 6302. The first housing 6301 and the second housing 6302 are connected by the connection unit 6306, and the angle between the first housing 6301 and the second housing 6302 can be changed by the connection unit 6306. The image on the display unit 6303 may be switched according to the angle between the first housing 6301 and the second housing 6302 at the connection unit 6306.

[0433] When recording video captured by the video camera 6300, it is necessary to encode the video according to the data recording format. By using the storage device described above, the video camera 6300 can store temporary files generated during encoding.

[0434] [ICD] The storage device described in the above embodiment can be applied to an implantable cardioverter defibrillator (ICD).

[0435] 14(J) is a cross-sectional schematic diagram showing an example of an ICD. An ICD main body 5400 has at least a battery 5401, electronic components 4700, a regulator, a control circuit, an antenna 5404, a wire 5402 to the right atrium, and a wire 5403 to the right ventricle.

[0436] The ICD body 5400 is surgically placed in the body, and the two wires are passed through the subclavian vein 5405 and superior vena cava 5406 of the human body so that one wire tip is placed in the right ventricle and the other wire tip is placed in the right atrium.

[0437] The ICD main body 5400 functions as a pacemaker and paces the heart when the heart rate falls outside a specified range. If the heart rate does not improve with pacing (fast ventricular tachycardia, ventricular fibrillation, etc.), treatment with an electric shock is administered.

[0438] The ICD main body 5400 must constantly monitor the heart rate in order to properly perform pacing and administer electric shocks. Therefore, the ICD main body 5400 has a sensor for detecting the heart rate. The ICD main body 5400 can also store in the electronic component 4700 heart rate data acquired by the sensor, the number of pacing treatments performed, the duration, and so on.

[0439] Furthermore, the antenna 5404 can receive power, which is then charged into the battery 5401. Furthermore, the ICD main body 5400 can improve safety by having multiple batteries. Specifically, even if some of the batteries in the ICD main body 5400 become unusable, the remaining batteries can continue to function, so the ICD main body 5400 can also function as an auxiliary power source.

[0440] In addition to the antenna 5404 that can receive power, an antenna that can transmit physiological signals may be provided, and a system for monitoring cardiac activity may be configured in which physiological signals such as pulse rate, respiratory rate, heart rate, and body temperature can be confirmed on an external monitor device.

[0441] [PC expansion device] The storage devices described in the above embodiments can be applied to computers such as PCs (Personal Computers) and expansion devices for information terminals.

[0442] Fig. 15A shows an example of such an expansion device: a portable expansion device 6100 that is external to a PC and equipped with a chip capable of storing information. The expansion device 6100 can store information using the chip by connecting to a PC via, for example, a USB (Universal Serial Bus). Note that while Fig. 15A shows a portable expansion device 6100, the expansion device according to one aspect of the present invention is not limited to this; for example, it may be a relatively large expansion device equipped with a cooling fan or the like.

[0443] The expansion device 6100 has a housing 6101, a cap 6102, a USB connector 6103, and a board 6104. The board 6104 is housed in the housing 6101. The board 6104 is provided with circuits that drive the storage devices and the like described in the above embodiments. For example, the board 6104 is equipped with an electronic component 4700 and a controller chip 6106. The USB connector 6103 functions as an interface for connecting to an external device.

[0444] [SD card] The storage device described in the above embodiment can be applied to an SD card that can be attached to electronic devices such as information terminals and digital cameras.

[0445] FIG. 15B is a schematic diagram of the external appearance of an SD card, and FIG. 15C is a schematic diagram of the internal structure of the SD card. The SD card 5110 has a housing 5111, a connector 5112, and a circuit board 5113. The connector 5112 functions as an interface for connecting to an external device. The circuit board 5113 is housed in the housing 5111. A memory device and a circuit for driving the memory device are provided on the circuit board 5113. For example, an electronic component 4700 and a controller chip 5115 are attached to the circuit board 5113. Note that the circuit configurations of the electronic component 4700 and the controller chip 5115 are not limited to those described above, and the circuit configurations may be changed as appropriate depending on the situation. For example, the write circuit, row driver, read circuit, etc. provided in the electronic component may be incorporated into the controller chip 5115 rather than the electronic component 4700.

[0446] The capacity of the SD card 5110 can be increased by providing the electronic component 4700 also on the back side of the substrate 5113. A wireless chip with a wireless communication function may be provided on the substrate 5113. This allows wireless communication between an external device and the SD card 5110, and enables reading and writing of data from and to the electronic component 4700.

[0447] [SSD] The storage device described in the above embodiment can be applied to an SSD (Solid State Drive) that can be attached to electronic devices such as information terminals.

[0448] FIG. 15D is a schematic diagram of the external appearance of an SSD, and FIG. 15E is a schematic diagram of the internal structure of the SSD. The SSD 5150 has a housing 5151, a connector 5152, and a circuit board 5153. The connector 5152 functions as an interface for connecting to an external device. The circuit board 5153 is housed in the housing 5151. The circuit board 5153 is provided with a storage device and a circuit for driving the storage device. For example, the circuit board 5153 is provided with an electronic component 4700, a memory chip 5155, and a controller chip 5156. The capacity of the SSD 5150 can be increased by providing an electronic component 4700 on the back side of the circuit board 5153 as well. The memory chip 5155 incorporates a work memory. For example, a DRAM chip may be used for the memory chip 5155. The controller chip 5156 incorporates a processor, an ECC circuit, and the like. The circuit configurations of the electronic component 4700, the memory chip 5155, and the controller chip 5156 are not limited to those described above, and may be changed as appropriate depending on the situation. For example, the controller chip 5156 may also be provided with a memory that functions as a work memory.

[0449] By applying the storage device according to the first or second embodiment to a storage device included in the electronic device described above, a novel electronic device can be provided.

[0450] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification. [Explanation of symbols]

[0451] MDV: memory device, MCA: memory cell array, MCA[1]: memory cell array, MCA[p-1]: memory cell array, MCA[p]: memory cell array, PHL: peripheral circuit, MC: memory cell, MC[1,1]: memory cell, MC[m,1]: memory cell, MC[1,n]: memory cell, MC[m,n]: memory cell, BD: circuit, WD: circuit, SD: circuit, RBD: circuit, CLC: circuit, OPC: circuit, M1: transistor, M2: transistor, M3: transistor, M4: transistor, M10: transistor, MD: resistive change device, M E: MTJ element, RM: resistive change element, PCM1: phase change memory, IT1: terminal, IT2: terminal, OT: terminal, BL1: wiring, BL1[1]: wiring, BL1[n]: wiring, BL2: wiring, BL2[1]: wiring, BL2[n]: wiring, WL: wiring, WLa: wiring, WLa[1]: wiring, WLa[m]: wiring, WLb: wiring, WLb[1]: wiring, WLb[m]: wiring, WL[1]: wiring, WL[m]: wiring, RBL: wiring, RBL[1]: wiring, RBL[m]: wiring, SL[1]: wiring, SL[m]: wiring, BGE: wiring, RL: layer, TIS: layer, FL: layer, CA: layer, TE: electrode, CHL: phase change layer, BE: electrode, SIL: layer, OSL[1]: layer, OSL[p]: layer, 300: transistor, 310: substrate, 312: element isolation layer, 313: semiconductor region, 314a: low resistance region, 314b: low resistance region, 315: insulator, 316: conductor, 320: insulator, 322: insulator, 324: insulator, 326: insulator, 328: conductor, 330: conductor, 350: insulator, 352: insulator, 354: insulator, 356: conductor, 360: insulator, 362: insulator, 364: insulator, 366: conductor, 400: memory element, 40 1: conductor, 402: insulator, 403: conductor, 404: conductor, 450: conductor, 452: insulator, 454: insulator, 456: insulator, 457: conductor, 458: conductor, 459: insulator, 460: conductor, 462: insulator, 500A: transistor, 500B: transistor, 503: conductor, 503a: conductor, 503b: conductor, 510: insulator, 512: insulator, 513: insulator, 514: insulator, 516: insulator, 518: conductor, 520: insulator, 522: insulator, 524: insulator, 530: oxide, 530a: oxide, 530b: oxide,530c: oxide, 540a: conductor, 540b: conductor, 542: conductor, 542a: conductor, 542b: conductor, 543a: region, 543b: region, 544: insulator, 546: conductor, 550: insulator, 552: insulator, 560: conductor, 560a: conductor, 560b: conductor, 574: insulator, 576: insulator, 580: insulator, 581: insulator, 582: insulator, 586: insulator, 600: memory cell, 1189: ROM interface, 1190: substrate, 1191: ALU, 1192: ALU controller, 1193: instruction Decoder, 1194: interrupt controller, 1195: timing controller, 1196: register, 1197: register controller, 1198: bus interface, 2621: row decoder, 2622: word line driver circuit, 2630: bit line driver circuit, 2631: column decoder, 2632: precharge circuit, 2633: sense amplifier, 2634: write circuit, 2640: output circuit, 2660: control logic circuit, 4700: electronic component, 4702: printed circuit board, 4704: mounting board, 4710: semiconductor device, 4 714: Wire, 4730: Electronic component, 4731: Interposer, 4732: Package substrate, 4733: Electrode, 4735: Semiconductor device, 4800: Semiconductor wafer, 4800a: Chip, 4801: Wafer, 4801a: Wafer, 4802: Circuit section, 4803: Spacing, 4803a: Spacing, 5110: SD card, 5111: Housing, 5112: Connector, 5113: Substrate, 5115: Controller chip, 5150: SSD, 5151: Housing, 5152: Connector, 5153: Substrate, 5155: Memory chip, 5156: Controller chip 5200: Portable game console, 5201: Housing, 5202: Display unit, 5203: Button, 5300: Desktop information terminal, 5301: Main unit, 5302: Display, 5303: Keyboard, 5400: ICD main unit, 5401: Battery, 5402: Wire, 5403: Wire, 5404: Antenna, 5405: Subclavian vein, 5406: Superior vena cava, 5500: Information terminal, 5510: Housing, 5511: Display unit, 5700: Automobile, 5800: Electric refrigerator-freezer, 5801: Housing, 5802: Refrigerator door, 5803: Freezer door, 5900: Information terminal,5901: Housing, 5902: Display, 5903: Operation buttons, 5904: Operator, 5905: Band, 6100: Expansion device, 6101: Housing, 6102: Cap, 6103: USB connector, 6104: Board, 6106: Controller chip, 6240: Digital camera, 6241: Housing, 6242: Display, 6243: Operation buttons, 6244: Shutter button, 6246: Lens, 6300: Video camera, 6301: First housing, 6302: Second housing, 6303: Display, 6304: Operation keys, 6305: Lens, 6306: Connection part, 7520: Main body, 7522: Controller,

Claims

[Claim 1] a first layer and a second layer overlying the first layer; the first layer having a circuit; the second layer has a first memory cell; the circuitry includes a bit line driver circuit and / or a word line driver circuit that transmits a signal to the first memory cell; the first memory cell includes a first transistor, a second transistor, a conductor, and an MTJ element; The MTJ element has a free layer, the free layer is electrically connected to the conductor; a first terminal of the first transistor electrically connected to a first terminal of the second transistor via the conductor; the circuit has a transistor whose channel forming region contains silicon; each of the first transistor and the second transistor includes a metal oxide in a channel formation region; storage device.

Images