Semiconductor storage device

Abstract

To suppress an increase in circuit area.SOLUTION: A semiconductor storage device (1) includes a memory cell array (3) in which a plurality of memory cells (MC) is connected to a bit line pair (BLT). Upon data reading of the memory cell (MC), a replica bit line signal is outputted to a replica bit line (TRKBL) in response to a replica word line signal, and a sense amplifier signal (SAE) changes in response to the replica bit line signal whereby a sense amplifier circuit (21) is driven. Moreover, upon data writing onto the memory cell (MC), a low potential side of the bit line pair targeted for writing is set at a negative potential by a negative potential boost signal (BOOSTX) outputted from a negative potential generation circuit (25).SELECTED DRAWING: Figure 1B

Description

[Technical Field]

[0001] The present disclosure relates to a semiconductor memory device. [Background technology]

[0002] As the speed of semiconductor memory devices increases, it becomes more difficult to generate various operation signals required for their operation at appropriate timing.

[0003] Patent Document 1 discloses a semiconductor memory device that uses a replica circuit to generate an activation signal for a sense amplifier circuit. The replica circuit includes replica memory cells that have a structure similar to that of memory cells included in a memory array.

[0004] Patent Document 2 discloses the use of a negative bit line technique as a write assist technique in a semiconductor memory device, in which a dummy bit line is connected as a load to a circuit that generates a timing signal that pulls the bit line to a negative potential. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Laid-Open No. 2006-12240 [Patent Document 2] U.S. Patent No. 8,325,512 Summary of the Invention [Problem to be solved by the invention]

[0006] However, conventional circuits that generate activation signals for sense amplifier circuits are used only when reading data from memory cells, and are not used when writing data to memory cells (see, for example, Patent Document 1). Therefore, a separate circuit is required for writing data.

[0007] Furthermore, conventional write assist technology is used only when writing data to memory cells, and is not used when reading data from memory cells (see, for example, Patent Document 2). Therefore, a separate circuit is required for data reading.

[0008] That is, in the prior art, when attempting to support both data read and data write to a memory cell, it is necessary to mount circuits corresponding to each of the two, which poses the problem of an increased circuit area.

[0009] The present disclosure has been made to solve the above-mentioned problems, and aims to eliminate the area overhead caused by providing circuits corresponding to both reading and writing data. [Means for solving the problem]

[0010] In one aspect of the present disclosure, a semiconductor memory device includes a memory cell array including a plurality of memory cells, each of which is connected to a corresponding bit line pair; a replica bit line circuit including a plurality of replica memory cells, each of which outputs a replica bit line signal to a common replica bit line in response to a replica word line signal; a sense amplifier circuit amplifying a signal on the bit line pair in response to a sense amplifier activation signal generated based on the replica bit line signal; and a sense amplifier circuit having a function of setting one bit line of the bit line pair connected to the memory cell to be written to a low potential and setting the low potential side bit line to a negative potential in response to a negative potential boost signal. and a negative potential boost signal generation circuit which generates the negative potential boost signal and includes the replica bit line in a signal generation path of the negative potential boost signal, wherein when data is read from the memory cell, the replica bit line signal is output to the replica bit line in response to the replica word line signal, and the sense amplifier activation signal changes in response to the replica bit line signal to drive the sense amplifier circuit, and when data is written to the memory cell, the negative potential boost signal output from the negative potential boost signal generation circuit sets the low potential side of the bit line pair to a negative potential.

[0011] According to this embodiment, by using a sense amplifier activation signal generated based on the replica bit line signal, optimal activation timing can be supplied to the sense amplifier circuit. Furthermore, since the replica bit lines connected to the replica memory cells are connected to the signal generation path of the negative potential boost signal, the signal can be output from the negative potential boost signal generation circuit at optimal activation timing without providing an additional dummy bit line. In other words, since a single replica circuit is used to generate control signals corresponding to data read and write, it is possible to eliminate the area overhead associated with providing separate circuits for data read and write. [Effects of the Invention]

[0012] According to the present disclosure, in a semiconductor memory device, a single replica circuit is used to generate control signals corresponding to reading and writing data, thereby eliminating the area overhead caused by providing circuits corresponding to both reading and writing data. [Brief explanation of the drawings]

[0013] [Figure 1A] FIG. 1 is a functional block diagram illustrating a portion of the configuration of a semiconductor memory device (first embodiment); [Figure 1B] FIG. 1 is a diagram showing an example of a circuit configuration of an amplifier circuit constituting a semiconductor memory device (first embodiment); [Figure 2] FIG. 1B is a diagram showing an example of a circuit configuration of the memory cell of FIG. 1A; [Figure 3] FIG. 1B is a diagram showing an example of a circuit configuration of the replica cell of FIG. 1A. [Figure 4A] FIG. 1 is a diagram for explaining a generation path of a sense amplifier activation signal; [Figure 4B] FIG. 1 is a diagram for explaining a generation path of a negative potential boost signal; [Figure 5] 1 is a timing chart showing an example of operation of a semiconductor memory device (first embodiment); [Figure 6] 1B for a semiconductor memory device (modification 1 of the first embodiment) [Figure 7] 1A and 1B, which show a semiconductor memory device (modification 2 of the first embodiment) [Figure 8] 1B for a semiconductor memory device (modification 2 of the first embodiment) [Figure 9] FIG. 1B is a diagram illustrating a semiconductor memory device (second embodiment) according to the present invention. [Figure 10] 10 is a timing chart showing an example of operation of the semiconductor memory device (second embodiment); DETAILED DESCRIPTION OF THE INVENTION

[0014] Hereinafter, embodiments will be described with reference to the drawings. In the following description, the same reference numerals may be used to refer to signal lines and signals passing through the signal lines.

[0015] First Embodiment The semiconductor memory device 1 includes a memory cell array 3, a replica bit line circuit 4, and an amplifier circuit 2.

[0016] FIG. 1 (FIGS. 1A and 1B) shows a configuration example of a semiconductor memory device 1 according to the first embodiment. The semiconductor memory device 1 includes a configuration 1a in FIG. 1A and a configuration 1b in FIG. 1B. FIG. 1A shows a configuration example of a memory array 3 and a replica bit line circuit 4 and their peripheral circuits as configuration 1a. FIG. 1B shows a configuration example of an amplifier circuit 2 and its peripheral circuits as configuration 1b.

[0017] -Memory cell array- As shown in FIG. 1A, the memory cell array 3 includes a plurality of memory cells MC arranged in an array of m rows (m is a natural number) by n columns (n ​​is a natural number).

[0018] The memory cell array 3 includes a plurality of word lines WL (m in FIG. 1A) arranged corresponding to the rows of the memory cells MC, and a plurality of bit line pairs BLT (n in FIG. 1A) arranged corresponding to the columns of the memory cells MC. The bit line pair BLT is composed of a pair of bit lines BL and BLX. The word lines WL extend in a first direction (hereinafter referred to as the "row direction"). The bit lines BL and BLX extend in a second direction (hereinafter referred to as the "column direction") intersecting the first direction. Each memory cell MC is connected to the word line WL of the row and the bit line pair BLT (bit lines BL and BLX) of the column corresponding to its arrangement position.

[0019] The word lines WL are connected to a row decoder 8. The row decoder 8 activates the word line WL of the row including the memory cell MC to be operated in accordance with a row address specified by a CPU (not shown).

[0020] The bit line pair BLT is connected to an amplifier circuit 2, which will be described later.

[0021] Fig. 2 is a circuit diagram showing the internal configuration of memory cell MC of Fig. 1A. In Fig. 2, memory cell MC includes N-type transistors NA1 and NA2, P-type transistors PL1 and PL2, and N-type transistors ND1 and ND2.

[0022] The gate of the N-type transistor NA1 is connected to the word line WL and the source is connected to the bit line BL. The gate of the N-type transistor NA2 is connected to the word line WL and the source is connected to the bit line BLX. The source of the P-type transistor PL1 is supplied with a power supply voltage VDD and is connected to the drain of the N-type transistor NA1. The gate of the N-type transistor ND1 is connected to the gate of the P-type transistor PL1, the drain is connected to the drain of the P-type transistor PL1, and the source is connected to the ground potential VSS. The gate of the P-type transistor PL2 is connected to the drain of the N-type transistor NA1, the source is supplied with a power supply voltage VDD, and the drain is connected to the drain of the N-type transistor NA2. The gate of the N-type transistor ND2 is connected to the gate of the P-type transistor PL2, the drain is connected to the drain of the P-type transistor PL2, and the source is connected to the ground potential VSS. The connection node between the gate of the P-type transistor PL1 and the gate of the N-type transistor ND1 is connected to the drain of the N-type transistor NA2.

[0023] Here, the P-type transistor PL1 and the N-type transistor ND1 form a first inverter. The P-type transistor PL2 and the N-type transistor ND2 form a second inverter. The input terminal of the first inverter is connected to the output terminal of the second inverter, and the output terminal of the first inverter is connected to the input terminal of the second inverter, thereby forming a latch circuit.

[0024] -Replica bit line circuit- 1A, the replica bit line circuit 4 includes a plurality of replica memory cells RMC arranged in the column direction. In the example of FIG. 1A, the replica bit line circuit 4 includes m replica memory cells RMC.

[0025] Fig. 3 is a circuit diagram showing the internal configuration of the replica memory cell RMC of Fig. 1A. In Fig. 3, the transistors constituting the replica memory cell RMC have the same size as the transistors constituting the memory cell MC shown in Fig. 2.

[0026] The replica memory cell RMC differs from the memory cell MC in that the power supply voltage VDD is supplied to the gate of the P-type transistor PL1 and the gate of the N-type transistor ND1 in the latch circuit described above.

[0027] The replica memory cells RMC also differ from the memory cells MC in that the gate of the N-type transistor NA1 is connected to a replica word line TRKWL. The replica word lines TRKWL of some replica memory cells RMC are connected to the row decoder 8, while the replica word lines TRKWL of the remaining replica memory cells RMC are connected to the ground potential VSS. The delay amount, which will be described later, can be adjusted by changing the number of replica memory cells RMC connected to the row decoder 8. In the following description, the replica memory cells RMC whose replica word lines TRKWL are connected to the row decoder 8 may be referred to as first replica memory cells RMC, and the replica memory cells RMC whose replica word lines TRKWL are connected to the ground potential VSS may be referred to as second replica memory cells RMC, to distinguish them from each other. The input signal input from the replica word line TRKWL of the first replica memory cell RMC is generated based on a precharge signal PCG and a read enable signal RE.

[0028] When reading data, the replica word line TRKWL of the first replica memory cell RMC goes to "H level" (hereinafter simply referred to as "H"), causing the replica bit line TRKBL to go to "L level" (hereinafter simply referred to as "L"). This causes a replica bit line signal TRKBL to be output from the first replica memory cell RMC. Then, a sense amplifier enable signal SAE, which will be described later, is generated based on the replica bit line signal TRKBL.

[0029] During data write, the replica word line TRKWL goes low, and the first replica memory cell RMC does not operate. This causes the first replica memory cell RMC and the second replica memory cell RMC to function only as load capacitances for the replica bit line TRKBL. Detailed timing will be explained later.

[0030] -Amplifier circuit- 1B, in this example, one amplifier circuit 2 is provided for every two columns. Specifically, the column connected to the bit line pair BLT[0] (hereinafter referred to as the “first column”) and the column connected to the bit line pair BLT[1] (hereinafter referred to as the “second column”) are connected to the amplifier circuit 2.

[0031] The amplifier circuit 2 includes a sense amplifier circuit 21, a write circuit, a negative potential boost signal generating circuit, and a negative potential generating circuit 25.

[0032] (Sense amplifier circuit) The sense amplifier circuit 21 amplifies the signal on the bit line pair BLT in response to a sense amplifier enable signal SAE and outputs the amplified signal to the read data line pair RDT. The read data line pair RDT is made up of a pair of read data lines RD and RDX.

[0033] More specifically, in this example, a column selector 23 is provided between the first and second columns and the sense amplifier circuit 21. The column selector 23 selects one of the first and second columns based on a column selection signal RCA (RCA0X, RCA1X). The column selection signal RCA is generated in the column control circuit 22 based on the column selection signal COLX[1:0].

[0034] The sense amplifier circuit 21 receives the signal of the bit line pair BLT of the selected column, amplifies the signal, and outputs it to the read data line pair RDT.

[0035] 4A, in a circuit configuration common to that of FIG. 1B, a generation path of the sense amplifier enable signal SAE is indicated by a thick solid line. The sense amplifier enable signal SAE is generated based on the replica bit line signal TRKBL output from the first replica memory cell RMC using a predetermined combinational circuit. In other words, the replica bit line signal TRKBL output from the first replica memory cell RMC is provided to the combinational circuit via the replica bit line TRKBL.

[0036] (Write circuit) The write circuit includes a write amplifier that sets one bit line of the bit line pair BLT to a high potential and the other bit line to a low potential. The write amplifier also has a function of pulling down the bit line on the low potential side of the bit line pair BLT (the "other bit line" mentioned above) to a negative potential in response to a negative potential boost signal BOOSTX. The write circuit also includes a write driver 26 driven by a write signal WRITE. The write signal WRITE is generated based on a write enable signal WE and a precharge signal PCG. Each column is also provided with a precharge circuit 24 that operates based on the precharge signal PCG.

[0037] (Negative voltage boost signal generation circuit) The negative potential boost signal generation circuit generates the negative potential boost signal BOOSTX and supplies it to the write amplifier. The signal generation path of the negative potential boost signal BOOSTX includes the replica bit line TRKBL.

[0038] In the negative potential generating circuit 25, the signal generation path of the negative potential boost signal BOOSTX forms a circuit equivalent to the path for writing data. Here, the "equivalent circuit" refers to, for example, a circuit configured so that the delay amount in the signal generation path is as similar as possible.

[0039] After forming an equivalent circuit as described above, a configuration is added to increase the delay amount of some circuits, and various design parameters are changed, etc. This allows the negative potential boost signal BOOSTX to drive the low potential side bit line to a negative potential only after the low potential side bit line BL / BLX has been reliably driven to the ground potential VSS.

[0040] A specific example will be described below. In Fig. 4B, in the circuit configuration common to Fig. 1B, the signal generation path of the negative potential boost signal BOOSTX is indicated by a thick solid line. In other words, in this example, the circuit arranged in the signal generation path of the negative potential boost signal BOOSTX constitutes the negative potential boost signal generation circuit.

[0041] In the example of FIG. 4B, a signal generation path of the negative potential boost signal BOOSTX is provided with a first replica circuit 51, a second replica circuit 52, and a third replica circuit 53 in addition to the replica bit line TRKBL.

[0042] The first replica circuit 51 is a replica circuit of the write driver 26. Specifically, it is a replica circuit that uses transistors of the same size and polarity as the write driver 26, and is configured so that the delay between input and output is as similar as possible to that of the write driver 26.

[0043] The second replica circuit 52 is a replica circuit of the combinational circuit within the frame 28 in Fig. 4B. The second replica circuit 52 is configured so that the delay between input and output is as similar as possible to that of the combinational circuit within the frame 28.

[0044] The third replica circuit 53 is a replica circuit of the combinational circuit within the frame 29 in Fig. 4B. The third replica circuit 53 is configured so that the delay between input and output is as similar as possible to that of the combinational circuit within the frame 29.

[0045] In this way, by providing the first to third replica circuits 51 to 53 in the signal generation path of the negative potential boost signal BOOSTX, it is possible to generate a delay equivalent to the operation of the write amplifier circuit.

[0046] In the signal generation path of the negative potential boost signal BOOSTX configured as described above, for example, the driving power of the transistor TN0 of the third replica circuit 53, which corresponds to the transistor TN2 in the frame 29, is made smaller than that of the transistor TN2. Similarly, the driving power of the transistor TN1 of the third replica circuit 53, which corresponds to the transistor TN3 in the frame 29, is made smaller than that of the transistor TN3. The method for reducing the driving power of the transistors TN0 and TN1 in this case is not particularly limited, but examples include reducing the gate width, increasing the gate length, and / or increasing the threshold voltage.

[0047] -Operation of semiconductor memory device- Next, with reference to FIG. 5, the operation of reading data from and writing data to the memory cells MC in the semiconductor memory device 1 will be described.

[0048] (Data read operation) First, the data read operation of the memory cell MC will be described. In this example, the column selection signal COLX[0] is set to "L", which selects the first column, and the bit line BL[0] is set to "L".

[0049] First, before the precharge signal PCG rises, the write enable signal WE goes low. The write enable signal WE is maintained in the same state during the period when the precharge signal PCG is high.

[0050] After the write enable signal WE is set to the 'L' state, the precharge signal PCG and the signal PCGSA, which is the precharge signal PCG with an expanded pulse width, rise to 'H'. The signal PCGSA is a signal that goes 'H' only during a data read operation.

[0051] When the precharge signal PCG rises, the word line signal WL and replica word line signal TRKWL corresponding to the memory cell MC to be read rise to 'H'. Almost simultaneously with the rise of the precharge signal PCG, the column selection signal COLX[0] and signal READX fall to 'L'. The signal READX changes based on the write enable signal WE and the precharge signal PCG.

[0052] When the word line signal WL and the replica word line signal TRKWL rise to 'H', the bit line signal BL[0] and the replica bit line signal TRKBL accordingly start to fall to 'L'.

[0053] Here, the replica bit line signal TRKBL is adjusted so that it drops to the threshold of the NOR circuit (for example, 1 / 2VDD) when the bit line signal BL[0] drops to a level required for sense amplifier operation. The NOR circuit is a circuit that receives the replica bit line signal TRKBL as an input.

[0054] The sense amplifier enable signal SAE changes based on the output of this NOR circuit. Specifically, when the bit line signal BL[0] drops to the level required for sense amplifier operation, the sense amplifier enable signal SAE rises to 'H'. This activates the sense amplifier, reading 'L' as the read data signal RD[0] and 'H' as the read data signal RDX[0].

[0055] Then, after the sense amplifier enable signal SAE becomes 'H', the precharge signal PCG, word line signal WL, and replica word line signal TRKWL become 'L', and the column selection signal COLX[0] and signal READX become 'H'. After that, the bit line signal BL[0] is precharged to 'H'.

[0056] When the read output is determined, the signal PCGSA goes low, the sense amplifier enable signal SAE also goes low, and the read operation ends.

[0057] As described above, for the read operation, the optimum activation timing can be supplied to the sense amplifier circuit 21 by using the replica memory cells RMC.

[0058] (Data write operation) Next, we will explain the data write operation to the memory cell MC. In this example, we will explain the case where the column selection signal COLX[0] is set to 'L', thereby selecting the first column, and writing the write data signal WDX[0] to 'H' to the bit line BL[0]. In other words, the bit line BL[0] is written to 'L'.

[0059] First, before the precharge signal PCG rises, the write enable signal WE goes to 'H.' As described above, the write enable signal WE is maintained in the same state during the period when the precharge signal PCG is 'H'.

[0060] After the write enable signal WE is set to the 'H' state, the precharge signal PCG rises to 'H'. When writing data, the signal PCGSA remains 'L' and does not change.

[0061] Before the word line signal WL and the write signal WRITE rise, the write data signal WDX[0] becomes 'H'. Since the write data signal WDX[0] is an inverted signal of the write data signal WD[0], the write data signal WD[0] becomes 'L'. Note that this state is maintained while the word line signal WL and the write signal WRITE are in the 'H' state.

[0062] When the precharge signal PCG rises, the word line signal WL and the write signal WRITE rise to 'H'. Almost simultaneously with the rise of the precharge signal PCG, the column selection signal COLX[0] falls to 'L'.

[0063] At this time, the write enable signal WE is 'H', and therefore the signal RE, which is the inverted signal of the write enable signal WE, is 'L'. As a result, the replica word line signal TRKWL remains 'L', and unlike when reading data, the replica memory cell RMC does not operate.

[0064] When the word line signal WL rises to 'H', the bit line signal BL[0] accordingly begins to fall to 'L'. Also, the replica bit line signal TRKBL arranged in the signal generation path of the negative potential boost signal BOOSTX also begins to fall.

[0065] When the replica bit line signal TRKBL falls, the replica bit line TRKBL and the replica memory cell RMC act as a load for the replica bit line signal TRKBL.

[0066] Here, the negative potential boost signal BOOSTX is adjusted to be 'L' when the bit line signal BL[0] drops to the ground potential VSS. As a result, when the signal WGND becomes negative, the bit line signal BL[0] becomes negative, and the desired data is written to the memory cell MC to be written.

[0067] When the write operation is completed, the precharge signal PCG, word line signal WL, and write signal WRITE become 'L', and the column select signal COLX[0] becomes 'H'. Then, when the precharge signal PCG becomes 'L', the bit line signal BL[0] is precharged to 'H'.

[0068] As described above, for the write operation, in generating a timing signal using the negative bit line technique, the replica bit line TRKBL connected to the replica memory cell RMC is connected, so that the optimal start timing can be supplied to the negative potential generation circuit 25 without providing a new dummy bit line.

[0069] As described above, according to this embodiment, a circuit that generates various operation signals for the semiconductor memory device 1 at appropriate timing can be realized without area overhead. More specifically, a single replica circuit is used to generate control signals corresponding to data read and write. This allows control signals to be generated at optimal activation timing, and also eliminates area overhead that would be otherwise required for providing separate circuits for data read and write.

[0070] -Variation 1- Here, a first modification of the semiconductor memory device according to the first embodiment will be described.

[0071] Fig. 6 is a diagram corresponding to Fig. 1B for this modified example 1. The configuration of Fig. 1A can be the same as that of the first embodiment.

[0072] FIG. 6 differs from FIG. 1B in that a delay buffer 56 is provided at a position on the replica bit line TRKBL and on the signal generation path of the negative potential boost signal BOOSTX.

[0073] By providing the delay buffer 56 in this manner, in addition to or instead of adjusting the delay amount in the transistors TN0 and TN1 described above, it is possible to adjust the delay in the signal generation path of the negative potential boost signal BOOSTX, thereby optimizing the timing of the negative potential boost signal BOOSTX.

[0074] -Variation 2- Here, a second modification of the semiconductor memory device 1 according to the first embodiment will be described.

[0075] Fig. 7 is a diagram of Modification 2 corresponding to Fig. 1A, and Fig. 8 is a diagram of Modification 2 corresponding to Fig. 1B.

[0076] 1A in that the replica bit line TRKBL is branched into two. In this modification, as shown in FIG. 7, the replica bit line TRKBL includes a first replica bit line TRKBL1 and a second replica bit line TRKBL2.

[0077] The first replica bit line TRKBL1 corresponds to the replica bit line TRKBL in FIG. 1A, extends parallel to the bit line pair BLT, and is connected to each of the plurality of replica memory cells RMC.

[0078] The second replica bit line TRKBL2 branches at a connection point between the first replica bit line TRKBL1 and the replica memory cell RMC located at the farthest end as seen from the amplifier circuit 2. After branching, the second replica bit line TRKBL2 is folded back at a position farther from the amplifier circuit 2 than the replica memory cell RMC located at the farthest end, and extends in parallel with the first replica bit line TRKBL1.

[0079] The first replica bit line TRKBL1 is used to supply a replica bit line signal TRKBL for generating the sense amplifier enable signal SAE, in other words, the first replica bit line TRKBL1 is connected to a circuit for generating the sense amplifier enable signal SAE.

[0080] The first replica bit line TRKBL1 is also connected to the output node of the transistor TN0 of the third replica circuit 53 that constitutes the negative potential boost signal generation circuit. The circuit downstream of the transistor TN0 (in this example, a "NOR circuit") is then connected via the first replica bit line TRKBL1 and the second replica bit line TRKBL2. This connects a larger resistance and capacitance between the transistor TN0 and the downstream circuit than in FIG. 1A, thereby increasing the delay. As a result, the timing of the negative potential boost signal BOOSTX can be easily optimized.

[0081] The branch position of the replica bit line TRKBL is not limited to the connection position (position in FIG. 7) between the replica memory cell RMC located at the farthest end from the amplifier circuit 2 and the first replica bit line TRKBL1. For example, the second replica bit line TRKBL2 may branch from the first replica bit line TRKBL1 at the middle position in the column direction (vertical direction in the drawing) of the multiple replica memory cells RMC. Then, the second replica bit line TRKBL2 may be extended in parallel to the first replica bit line TRKBL1.

[0082] In this way, by changing the branch position of the second replica bit line TRKBL2, it is possible to change the resistance value of the generation path of the negative potential boost signal BOOSTX, in other words, it is possible to adjust the delay amount of the negative potential boost signal BOOSTX.

[0083] When viewed as a generation path of the sense amplifier enable signal SAE, the resistance remains the same but the capacitance is doubled compared to the first embodiment. In this regard, for example, if it is desired to output the sense amplifier enable signal SAE at the same timing as in the first embodiment, it is advisable to increase (e.g., double) the number of replica memory cells RMC connected in parallel to the first replica bit line TRKBL1.

[0084] Second Embodiment Here, a semiconductor memory device 1 according to the second embodiment will be described.

[0085] 9 is a diagram of the second embodiment, corresponding to FIG. 1B. The configuration of FIG. 1A can be the same as that of the first embodiment. Here, the differences from the first embodiment will be mainly described.

[0086] In this embodiment, the column selection function is omitted from the first embodiment. In the example of Fig. 9, compared to Fig. 1B, the column selection signal COLX[1:0] is not present, and the corresponding circuits (e.g., the column selector 23 and the column control circuit 22) are also omitted. As a result, circuits related to the column selection function (e.g., the second replica circuit 52) ​​are omitted from the generation path of the negative potential boost signal BOOSTX.

[0087] Other configurations and operations are generally the same as those of the first embodiment, and detailed description thereof will be omitted here. Fig. 10 shows a timing chart illustrating an example of operation of the semiconductor memory device 1 according to this embodiment, which corresponds to Fig. 5 of the first embodiment. As shown in Fig. 10, compared to Fig. 5, the column selection signal COLX[0] and the signal READX are absent, but other operations are generally the same as those in Fig. 5.

[0088] As described above, in this embodiment as well, the same effects as in the first embodiment described above can be obtained.

[0089] -Variation 1- In the second embodiment, similarly to the case of FIG. 6, a delay buffer 56 may be provided at a position on the replica bit line TRKBL and on the signal generation path of the negative potential boost signal BOOSTX.

[0090] By providing the delay buffer 56 in this manner, in addition to or instead of adjusting the delay amount in the transistors TN0 and TN1, it is possible to adjust the delay in the signal generation path of the negative potential boost signal BOOSTX, thereby optimizing the timing of the negative potential boost signal BOOSTX.

[0091] -Variation 2- In the second embodiment described above, the replica bit line TRKBL may be branched into a first replica bit line TRKBL1 and a second replica bit line TRKBL2, as in the second modification of the first embodiment.

[0092] By branching the replica bit line TRKBL in this way, a larger resistance and capacitance than those in Figure 9 are connected between the transistor TN0 and the subsequent circuit, which increases the delay amount, making it easier to optimize the timing of the negative potential boost signal BOOSTX.

[0093] In this modification 2, similarly to the modification 2 of the first embodiment, the branching position of the second replica bit line TRKBL2 may be changed, thereby adjusting the delay amount of the negative potential boost signal BOOSTX. [Industrial Applicability]

[0094] According to the present disclosure, a circuit that generates various operation signals for a semiconductor memory device at appropriate timing can be realized without area overhead, which is extremely useful. [Explanation of symbols]

[0095] 1. Semiconductor memory device 3 Memory Cell Array 21 Sense amplifier circuit 25 Negative voltage boost signal generation circuit 51 First replica circuit (replica circuit) 56 Delay Buffer MC memory cell BLT bit line pair TRKBL replica bit lines SAE Sense amplifier enable signal BOOSTX Negative voltage boost signal

Claims

1. A semiconductor memory device, a memory cell array including a plurality of memory cells, each of the plurality of memory cells being connected to a corresponding pair of bit lines; a replica bit line circuit including a plurality of replica memory cells, the plurality of replica memory cells outputting replica bit line signals to a common replica bit line in response to a replica word line signal; a sense amplifier circuit that amplifies the signal of the bit line pair in response to a sense amplifier activation signal generated based on the replica bit line signal; a write circuit that has a function of setting one bit line of a bit line pair connected to the memory cell to be written to a low potential, and sets the bit line on the low potential side to a negative potential in response to a negative potential boost signal; a negative potential boost signal generation circuit that generates the negative potential boost signal, the negative potential boost signal generation circuit including the replica bit lines and a buffer circuit connected to the replica bit lines in a signal generation path of the negative potential boost signal; When reading data from the memory cell, the replica bit line signal is output to the replica bit line in response to the replica word line signal, and the sense amplifier activation signal changes in response to the replica bit line signal, thereby driving a sense amplifier circuit; when writing data to the memory cell, the negative potential boost signal output from the negative potential boost signal generating circuit causes the low potential side of the bit line pair to be written to have a negative potential; A semiconductor memory device characterized by:

2. 2. The semiconductor memory device according to claim 1, the replica bit lines include first replica bit lines that extend parallel to the bit line pairs and are connected to the plurality of replica memory cells, and second replica bit lines that branch off from the first replica bit lines and extend parallel to the first replica bit lines; the replica bit line signal is supplied to the sense amplifier circuit via the first replica bit line; the first replica bit line and the second replica bit line are arranged in a signal generation path of the negative potential boost signal; A semiconductor memory device characterized by:

3. 3. The semiconductor memory device according to claim 2, the second replica bit line is branched at a connection position between the replica memory cell located at the farthest end as viewed from the negative potential boost signal generating circuit and the first replica bit line, and is folded back at a position farther than the replica memory cell located at the farthest end; A semiconductor memory device characterized by:

4. 2. The semiconductor memory device according to claim 1, the memory cell array is configured with a plurality of columns, each of which is a unit of a plurality of the memory cells connected to a common pair of bit lines; a column selector for selecting a column from which data is to be read or written from among the plurality of columns; A semiconductor memory device characterized by:

5. 2. The semiconductor memory device according to claim 1, The buffer circuit a write driver replica circuit connected to the replica bit line and outputting a control signal when data is written to the memory cell; a delay buffer connected to the replica bit line, receiving the control signal and outputting a delayed signal of the control signal; A semiconductor memory device characterized by:

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