Photoelectric conversion device and apparatus

Abstract

To provide a technique advantageous for improving the performance of a photoelectric conversion device.SOLUTION: A photoelectric conversion device comprises a plurality of pixels constituting a plurality of rows and columns, a plurality of output lines, and a row selection part. A signal holding part and a conversion part performing AD conversion are disposed for each column. The signal holding part includes a holding circuit that is supplied with signals from the pixels via two or more output lines assigned to the column in which the signal holding part is disposed, and a selection circuit. The plurality of pixels includes first and second photoelectric conversion parts. The row selection part is connected to the output lines different from each other and causes two or more pixels disposed in the different rows to output first analog signals based on a signal from the first photoelectric conversion part and subsequently output second analog signals based on signals from the first and second photoelectric conversion parts. The selection circuit selects the first and second analog signals held in the holding circuit and outputs the selected analog signals to the conversion part. The selection circuit outputs the smaller number of first analog signals to the conversion part than the number of first analog signals supplied to the holding circuit.SELECTED DRAWING: Figure 8

Description

[Technical Field]

[0001] The present invention relates to a photoelectric conversion device and an apparatus. [Background technology]

[0002] Patent Document 1 describes a need for faster image capture in a photoelectric conversion device that acquires both focus detection signals and image generation signals. Possible ways to achieve this speed include increasing the number of rows that are simultaneously analog-to-digital (AD) converted in one horizontal period, or shortening one horizontal period. Patent Document 1 also describes shortening one horizontal period by not outputting some of the focus detection data that are simultaneously AD converted in one horizontal period. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent Publication No. 2021-153255 Summary of the Invention [Problem to be solved by the invention]

[0004] Photoelectric conversion devices are required to not only increase the image capturing speed but also to achieve high-precision focus detection and reduce power consumption.

[0005] An object of the present invention is to provide a technique that is advantageous for improving the performance of a photoelectric conversion device. [Means for solving the problem]

[0006] In view of the above problems, a photoelectric conversion device according to an embodiment of the present invention is a photoelectric conversion device including a plurality of pixels arranged to form a plurality of rows and a plurality of columns, a plurality of output lines, and a row selection unit that selects a pixel from the plurality of pixels to output a signal, wherein a signal holding unit and a conversion unit that converts an analog signal output from the signal holding unit into a digital signal are arranged for each of the plurality of columns, and the signal holding unit includes a holding circuit to which signals are supplied from pixels connected to the two or more output lines from the plurality of pixels via two or more output lines assigned to the column in which the signal holding unit is arranged, and a selection circuit, and each of the plurality of pixels is the row selection unit outputs a first analog signal based on a signal from the first photoelectric conversion unit to two or more pixels connected to different output lines among the two or more output lines and arranged in different rows among the plurality of rows, and then outputs a second analog signal based on signals from the first photoelectric conversion unit and the second photoelectric conversion unit; the selection circuit selects the first analog signal and the second analog signal held in the holding circuit and outputs them to the conversion unit; and the number of the first analog signals output by the selection circuit to the conversion unit is smaller than the number of first analog signals supplied to the holding circuit. [Effects of the Invention]

[0007] According to the present invention, it is possible to provide a technique that is advantageous for improving the performance of a photoelectric conversion device. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a diagram showing an example of the configuration of a photoelectric conversion device according to an embodiment of the present invention. [Figure 2] FIG. 2 is a diagram showing an example of the configuration of a pixel unit and peripheral circuits of the photoelectric conversion device of FIG. [Figure 3] 2 is a diagram showing an example of the configuration of a signal holding unit of the photoelectric conversion device of FIG. 1; [Figure 4] FIG. 2 is a diagram showing an example of the configuration of a pixel of the photoelectric conversion device of FIG. 1. [Figure 5]FIG. 2 is a diagram showing an example of the configuration of a pixel of the photoelectric conversion device of FIG. 1. [Figure 6] FIG. 2 is a diagram showing an example of the configuration of a control unit of the photoelectric conversion device of FIG. 1. [Figure 7] 2 is a timing chart showing an example of the operation of the photoelectric conversion device of FIG. 1. [Figure 8] 2 is a timing chart showing an example of the operation of the photoelectric conversion device of FIG. 1. [Figure 9] 2 is a timing chart showing an example of the operation of the photoelectric conversion device of FIG. 1. [Figure 10] FIG. 2 is a diagram showing an example of the configuration of a device incorporating the photoelectric conversion device of FIG. 1. DETAILED DESCRIPTION OF THE INVENTION

[0009] Hereinafter, embodiments will be described in detail with reference to the accompanying drawings. Note that the following embodiments do not limit the scope of the invention claimed. Although multiple features are described in the embodiments, not all of these multiple features are necessarily essential to the invention, and multiple features may be combined arbitrarily. Furthermore, in the accompanying drawings, the same reference numerals are used to designate the same or similar components, and redundant explanations will be omitted.

[0010] A photoelectric conversion device according to an embodiment of the present disclosure will be described with reference to FIGS. 1 to 9. FIG. 1 is a block diagram showing an example configuration of a photoelectric conversion device 100 according to the present disclosure. The photoelectric conversion device 100 is controlled, for example, by a CPU 101 arranged externally to the photoelectric conversion device 100. The photoelectric conversion device 100 may include a control unit 102, a row selection unit 103, a pixel unit 104, a column analog-to-digital (AD) conversion unit 105, a data processing unit 106, and a signal output unit 107. The control unit 102 receives synchronization signals and control signals supplied from the CPU 101 and controls each component within the photoelectric conversion device 100. The pixel unit 104 has a plurality of pixels 201 arranged to form a plurality of rows and a plurality of columns. In the configuration shown in FIG. 1, the pixels 201 are arranged in a matrix of n rows and m columns. The row selection unit 103 selects a pixel from among the plurality of pixels 201 to output a signal in accordance with a control signal supplied from the control unit 102. The column AD conversion unit 105 converts analog signals output from the pixel unit 104 into digital signals in accordance with a control signal supplied from the control unit 102. The data processing unit 106 performs signal processing, such as correction processing, on the signals output from the column AD conversion unit 105 in accordance with a control signal supplied from the control unit 102. The signal output unit 107 can be an interface for outputting signals to the outside of the photoelectric conversion device 100.

[0011] 2 is a schematic diagram showing an example of the configuration of the pixel unit 104 and the column AD conversion unit 105 in this embodiment. The pixel unit 104 has a plurality of pixels 201 arranged therein. The pixel unit 104 also has a plurality of output lines 202 arranged such that two or more output lines 202 are assigned to each of a plurality of columns in which the pixels 201 are arranged. In the configuration shown in FIG. 2, four output lines are arranged for each column. The output lines 202 are connected to a constant current source (not shown).

[0012] In the configuration shown in Fig. 2, the pixel 201 in the first column and first row is connected to c1_vl1 of the output lines 202, and the pixel 201 in the first column and second row is connected to c1_vl2 of the output lines 202. Similarly, the pixels 201 are connected to the corresponding output lines 202 every four rows. Also, in Fig. 2, the four output lines 202 connected to the pixel 201 in the first column are represented as c1_vl# (#: 1 to 4), and the four output lines 202 connected to the pixel in the mth column are represented as cm_vl#.

[0013] The output line 202 is connected to the column AD conversion unit 105. The column AD conversion unit 105 includes, for each of a plurality of columns in which the pixels 201 are arranged, a signal holding unit 203 and a conversion unit 204 that converts an analog signal output from the signal holding unit 203 into a digital signal.

[0014] 3, the signal holding unit 203 includes a holding circuit 213 and a selection circuit 223. The holding circuit 213 receives signals from the pixels 201 connected to the corresponding output lines 202, among the plurality of pixels 201, via two or more output lines (four in the configuration shown in FIG. 2) assigned to the column in which the holding circuit 213 is arranged, among the plurality of output lines 202. The selection circuit 223 selects the analog signal held in the holding circuit 213 and outputs the selected signal to the conversion unit 204.

[0015] In this embodiment, one conversion unit 204 is arranged for each column. The conversion unit 204 performs AD conversion on analog signals output from the selection circuit 223 among the analog signals output to the signal holding unit 203 via output lines 202 (c1_vl1, c1_vl2, c1_vl3, and c1_vl4 in the case of the first pixel column). For example, by repeating AD conversion four times, the analog signals output from the pixels 201 arranged in the first column and the first to fourth rows are converted into digital signals. The signals output from the conversion unit 204 are supplied to the data processing unit 106 via a signal line adout_cm. Note that the signals output from the conversion unit 204 are digital data and are multi-bit signals.

[0016] 4 is a circuit diagram showing an example configuration of a pixel 201. Each of the plurality of pixels 201 arranged in the pixel unit 104 includes a photoelectric conversion unit 311 and a photoelectric conversion unit 313. Furthermore, the pixel 201 includes a charge transfer unit 312 that transfers the charge accumulated in the photoelectric conversion unit 311, and a charge transfer unit 314 that transfers the charge accumulated in the photoelectric conversion unit 313. The pixel 201 also includes a floating diffusion unit FD, a reset unit 315, a signal amplification unit 316, and a selection unit 317.

[0017] The photoelectric conversion units 311 and 313 convert incident light into electric charges. For example, the photoelectric conversion units 311 and 313 can be configured using elements such as photodiodes.

[0018] The charge transfer unit 312 is disposed in the electrical path between the photoelectric conversion unit 311 and the floating diffusion unit FD. The charge transfer unit 314 is disposed in the electrical path between the photoelectric conversion unit 313 and the floating diffusion unit FD. The charge transfer unit 312 may be a transfer transistor that reads out the charges accumulated in the photoelectric conversion unit 311, and its conduction / non-conduction (on / off) is controlled by a pixel transfer signal PTXA. Similarly, the charge transfer unit 314 may be a transfer transistor that reads out the charges accumulated in the photoelectric conversion unit 313, and its conduction / non-conduction (on / off) is controlled by a pixel transfer signal PTXB.

[0019] The reset unit 315 is disposed in an electrical path between a wiring pattern to which a power supply voltage VDD is supplied and the floating diffusion unit FD. The reset unit 315 may be a reset transistor that supplies the power supply voltage VDD to the floating diffusion unit FD and resets the potential of the floating diffusion unit FD. The reset unit 315 is controlled to be conductive or non-conductive (on or off) by a pixel unit reset signal PRES.

[0020] The floating diffusion unit FD is connected to the gate of the signal amplifier unit 316. A power supply voltage VDD is connected to one of the drain and source of the signal amplifier unit 316, and the other is connected to the selection unit 317. The signal amplifier unit 316 is a source follower that converts the charge of the floating diffusion unit FD into a voltage and outputs it to the output line 202, and can be configured, for example, by a transistor.

[0021] The selection unit 317 is disposed in the electrical path between the output of the signal amplification unit 316 and the output line 202. The selection unit 317 is a transistor for selecting a pixel row from which a signal is output, and its conduction / non-conduction (on / off) is controlled by a row selection signal PSEL.

[0022] 5 shows a schematic top view of a pixel 201. In each of the pixels 201 arranged in the pixel unit 104, the photoelectric conversion unit 311 and the photoelectric conversion unit 313 share one microlens 318. It can also be said that the photoelectric conversion unit 311 and the photoelectric conversion unit 313 are arranged corresponding to one microlens 318. In other words, the photoelectric conversion unit 311 and the photoelectric conversion unit 313 receive light that has passed through one microlens 318.

[0023] FIG. 6 is a diagram showing an example configuration of the control unit 102 in this embodiment. The control unit 102 may include a register control unit 501, control signal generation units 502, 505, and 507, and timing control counters 503, 504, and 506. The register control unit 501 holds various setting values ​​set by control signals supplied from the CPU 101. The control signal generation unit 502 generates control signals for controlling the timing control counters 503 and 504 based on the horizontal synchronization signal HD supplied from the CPU 101. The timing control counters 503 and 504 operate based on the horizontal synchronization signal HD in accordance with the control signal supplied from the control signal generation unit 502. The timing control counter 503 is used to control a part of the hold circuit 213 in the signal hold unit 203. The timing control counter 504 is used to control another part of the hold circuit 213 in the signal hold unit 203.

[0024] Control signal generation unit 505 generates a control signal for controlling signal holding unit 203 based on the count values ​​of timing control counters 503 and 504 and in accordance with a setting signal supplied from register control unit 501. Control signal generation unit 505 also generates a signal for controlling timing control counter 506. Timing control counter 506 operates based on the count values ​​of timing control counters 503 and 504 and in accordance with a control signal supplied from control signal generation unit 502. Control signal generation unit 507 generates a control signal for controlling conversion unit 204 and data processing unit 106 based on the count value of timing control counter 506 and in accordance with a setting signal supplied from register control unit 501.

[0025] Next, a driving method of the photoelectric conversion device 100 according to this embodiment will be described. FIG. 7 is a timing chart showing an example of the operation of the column AD conversion unit 105. In this embodiment, the photoelectric conversion device 100 simultaneously reads out signals from four rows of pixels 201 in each pixel column. The selection circuit 223 sequentially selects a signal output from one of the four simultaneously read analog signals from the pixels 201 and outputs the selected signal to the conversion unit 204. The conversion unit 204 performs AD conversion on the analog signals output from the selection circuit 223 and sequentially outputs the analog signals one pixel per row. In the following description, the circuit indicated by SH1_# in the holding circuit 213 as shown in FIG. 3 may be referred to as the sample-and-hold circuit SH1, and the circuit indicated by SH2_# may be referred to as the sample-and-hold circuit SH2. As described below, a timing control counter 503 is used to control the sample-and-hold circuit SH1, and a timing control counter 504 is used to control the sample-and-hold circuit SH2.

[0026] At time T1, the CPU 101 supplies a horizontal synchronization signal HD to the control unit 102. The control signal generation unit 502 resets the timing control counter 503 to an initial value (e.g., 0) based on the horizontal synchronization signal HD. At this time, the control signal generation unit 502 does not initialize the timing control counter 504. Next, at time T2, the control signal generation unit 502 does not initialize the timing control counter 503 in response to the horizontal synchronization signal HD output from the CPU 101, but resets the timing control counter 504 to an initial value (e.g., 0). At time T3, the control signal generation unit 502 initializes the timing control counter 503 in response to the horizontal synchronization signal HD output from the CPU 101, but does not initialize the timing control counter 504. At time T4, the control signal generation unit 502 does not initialize the timing control counter 503 in response to the horizontal synchronization signal HD output from the CPU 101, but initializes the timing control counter 504. In this way, the timing control counter 503 and the timing control counter 504 are alternately initialized and operated every time the horizontal synchronization signal HD is input.

[0027] At time T1n, the sample-and-hold circuit SH1 starts sampling the level (N signal) of the output line 202 before reading out signals from the photoelectric conversion units 311 and 313 of the pixel 201, and ends sampling after a sampling time Tsmpl_n has elapsed. Next, the row selection unit 103 causes four pixels 201 connected to different output lines 202 of the four output lines 202 arranged for each pixel column and arranged in different rows of the multiple rows to output analog signals based on the signals from the photoelectric conversion units 311. As a result, at time T1s1, the sample-and-hold circuit SH1 starts sampling the focus detection signal S1 based on the signal from the photoelectric conversion unit 311 read out from the pixel unit 104, and ends sampling after a sampling time Tsmpl_s1 has elapsed. After the sampling of the signal S1 has been completed, the row selection unit 103 causes the four pixels 201 that sampled the signal S1 to output analog signals based on the signals from the photoelectric conversion units 311 and 313. As a result, at time T1s2, the sample and hold circuit SH1 starts sampling the signal S2 for image generation based on the signals of the photoelectric conversion units 311 and 313 read out from the pixel unit 104, and finishes sampling after the elapse of the sampling time Tsmpl_s2. The sample and hold circuit SH1 is in a hold state from time T2 to time T3, and holds the sampled signal.

[0028] At time T3, when the horizontal synchronization signal HD is input and the timing control counter 503 is initialized, the sample-and-hold circuit SH1 enters the sample state again, samples the N signal at time T3n, the S1 signal at time T3s1, and the S2 signal at time T3s2, and transitions to the hold state at time T4.

[0029] At time T2n, the sample-and-hold circuit SH2 starts sampling the level (N) of the output line 202 before reading out signals from the photoelectric conversion units 311 and 313 of the pixels 201, and ends sampling after a sampling time Tsmpl_n has elapsed. Next, the row selection unit 103 outputs analog signals based on signals from the photoelectric conversion units 311 to four pixels 201 that are connected to different output lines 202 out of four output lines 202 arranged for each pixel column and that are arranged in different rows out of multiple rows. For example, if the above-mentioned sample-and-hold circuit SH1 samples signals output from the pixels 201 in the first to fourth rows, the sample-and-hold circuit SH2 can sample signals output from the pixels 201 in the fifth to eighth rows. As a result, at time T2s1, the sample-and-hold circuit SH2 starts sampling the focus detection signal S1 based on signals from the photoelectric conversion units 311 read out from the pixel unit 104, and ends sampling after a sampling time Tsmpl_s1 has elapsed. When the sampling of signal S1 is completed, the row selection unit 103 causes the four pixels 201 that sampled signal S1 (for example, the pixels 201 in the fifth to eighth rows) to output analog signals based on the signals of the photoelectric conversion units 311 and 313. As a result, at time T2s2, the sample and hold circuit SH2 starts sampling the signal S2 for image generation based on the signals of the photoelectric conversion units 311 and 313 read out from the pixel unit 104, and ends sampling after the elapse of sample time Tsmpl_s2. The sample and hold circuit 2 is in a hold state from time T3 to time T4, and holds the sampled signal.

[0030] When the sample-and-hold circuit SH1 is in the hold state, the sample-and-hold circuit SH2 samples the signal, and when the sample-and-hold circuit SH2 is in the hold state, the sample-and-hold circuit SH1 samples the signal. In other words, the sample-and-hold circuits SH1 and SH2 alternately sample and hold the signal each time the horizontal synchronization signal HD is input. Here, one cycle of the repeated input of the horizontal synchronization signal HD is referred to as one horizontal period Thd. In this case, the holding circuit 213 can be said to include a sample-and-hold circuit SH1 to which an analog signal based on the signal from the photoelectric conversion unit 311 and an analog signal based on the signals from the photoelectric conversion units 311 and 313 is supplied during a certain horizontal period, and a sample-and-hold circuit SH2 to which an analog signal based on the signal from the photoelectric conversion unit 311 and an analog signal based on the signals from the photoelectric conversion units 311 and 313 is supplied during a horizontal period following the horizontal period.

[0031] At time T2ad1 when the value of the timing control counter 503 becomes the set value cnt_ad1, the control signal generation unit 505 resets the timing control counter 506 to an initial value (for example, 0). At the same time, the control signal generation unit 507 generates a signal that causes the selection circuit 223 to select one of the eight sample and hold circuits SH1_#. The selection circuit 223 selects the sample and hold circuit in accordance with the control signal generated by the control signal generation unit 507, and outputs the held analog signal to the conversion unit 204. The conversion unit 204 converts the analog signal output from the signal holding unit 203 (selection circuit 223) into a digital signal.

[0032] Similarly, at time T2ad2 when the set value cnt_ad2 is reached, the control signal generating unit 505 resets the timing control counter 506 to an initial value (for example, 0). Furthermore, the control signal generating unit 507 generates a signal that causes the selection circuit 223 to select one of the eight sample and hold circuits SH1_#. This causes the selection circuit 223 to select one of the sample and hold circuits SH1_# and output the held analog signal to the conversion unit 204, which then performs AD conversion. The same is true at times T2ad3 to T2ad8.

[0033] 7, at time T2ad1, the sample and hold circuit SH1_1 (S1) is selected by the selection circuit 223. As a result, the focus detection signal S1 output to cm_vl1 of the output line 202 is output to the conversion unit 204 and AD converted. Similarly, at time T2ad2, the focus detection signal S1 output to cm_vl2 of the output line 202 is selected, at time T2ad3, the focus detection signal S1 output to cm_vl3 of the output line 202 is selected, and at time T2ad4, the focus detection signal S1 output to cm_vl4 of the output line 202 is selected, and each is AD converted.

[0034] Next, at time T2ad5, the sample and hold circuit SH1_1 (S2) is selected by the selection circuit 223. As a result, the image generation signal S2 output to cm_vl1 of the output line 202 is output to the conversion unit 204 and AD converted. Similarly, the image generation signal S2 output to cm_vl2 of the output line 202 is selected at time T2ad6, the image generation signal S2 output to cm_vl3 of the output line 202 is selected at time T2ad7, and the image generation signal S2 output to cm_vl4 of the output line 202 is selected at time T2ad8, and each is AD converted.

[0035] At this time, the sample-and-hold circuit SH2 samples and holds the signal. That is, the conversion unit 204 switches between the signals held by the sample-and-hold circuit SH1 and the sample-and-hold circuit SH2 and performs AD conversion each time the horizontal synchronization signal HD is input. The selection circuit 223 selects the analog signal supplied to the sample-and-hold circuit SH1 in the horizontal period Thd immediately preceding the horizontal period Thd and outputs it to the conversion unit 204. Alternatively, the selection circuit 223 may select the analog signal supplied to the sample-and-hold circuit SH2 in the horizontal period Thd following the horizontal period Thd and output it to the conversion unit 204. In the timing diagram shown in FIG. 7, the conversion unit 204 performs AD conversion four times on the focus detection signal S1 and four times on the image generation signal S2 for each horizontal period Thd, for a total of eight AD conversions in a time-division manner.

[0036] The data processing unit 106 performs black level correction and the like on the AD converted digital signal and outputs it to the signal output unit 107. In this way, the four rows of data simultaneously read out during a certain horizontal period Thd are AD converted row by row and output from the photoelectric conversion device 100 via the signal output unit 107, one pixel per row.

[0037] Next, a further driving method of the photoelectric conversion device 100 in this embodiment will be described with reference to FIG. 8. FIG. 8 is a timing chart showing an example of the operation of the column AD conversion unit 105 when a portion of the focus detection signal S1 is not AD converted. Compared to the operation shown in FIG. 7, the operation of the holding circuit 213 (sample and hold circuits SH1, SH2) in the signal holding unit 203 is unchanged. On the other hand, the operation shown in FIG. 8 differs from the operation shown in FIG. 7 in the operation of the selection circuit 223 in the signal holding unit 203. The following description will focus on the differences, and explanations of points that may be similar will be omitted as appropriate.

[0038] 7, from time T1 to time T2, the sample-and-hold circuit SH1 samples the focus detection signal S1, which is an analog signal based on the signal from the photoelectric conversion unit 311, and the image generation signal S2, which is an analog signal based on the signals from the photoelectric conversion units 311 and 313. Next, the sample-and-hold circuit SH1 enters a hold state at time T2.

[0039] Next, at time T2ad1 when the timing control counter 503 reaches the set value cnt_ad1, the control signal generation unit 507 generates a signal that causes the selection circuit 223 to select the sample and hold circuit SH1_1 (S1). This causes the selection circuit 223 to select the sample and hold circuit SH1_1 (S1) that holds the focus detection signal S1 output to cm_vl1 from the output line 202, and output the signal to the conversion unit 204. The conversion unit 204 performs AD conversion on the signal held in the sample and hold circuit SH1_1 (S1). Similarly, at time T2ad3, the selection circuit 223 selects the sample and hold circuit SH1_3 (S1) that holds the focus detection signal S1 output to cm_vl3 from the output line 202, and output the signal to the conversion unit 204. The conversion unit 204 performs AD conversion on the signal held in the sample and hold circuit SH1_3 (S1).

[0040] 7, at time T2ad5, the sample and hold circuit SH1_1 (S2) is selected by the selection circuit 223. As a result, the image generation signal S2 output to cm_vl1 of the output line 202 is output to the conversion unit 204 and AD converted. Similarly, at time T2ad6, the image generation signal S2 output to cm_vl2 of the output line 202 is selected, at time T2ad7, the image generation signal S2 output to cm_vl3 of the output line 202 is selected, and at time T2ad8, the image generation signal S2 output to cm_vl4 of the output line 202 is selected, and each is AD converted.

[0041] As shown in Fig. 8, the signal sampled by the sample-and-hold circuit SH2 undergoes the same operation as the signal sampled by the sample-and-hold circuit SH1. Thus, in the timing diagram shown in Fig. 8, two AD conversions are performed on the focus detection signal S1 and four AD conversions are performed on the image generation signal S2 during one horizontal period Thd. In other words, a total of six AD conversions are performed during one horizontal period Thd.

[0042] The operation of the holding circuit 213 (sample-and-hold circuits SH1 and SH2) of the signal holding unit 203 and the operation of the conversion unit 204 for each AD conversion remains unchanged. Meanwhile, the number of analog signals for focus detection (signal S1) output by the selection circuit 223 to the conversion unit 204 becomes smaller than the number of analog signals for focus detection (signal S1) supplied to the holding circuit 213. Therefore, the number of analog signals for focus detection (signal S1) converted into digital signals by the conversion unit 204 becomes smaller than the number of analog signals for focus detection (signal S1) supplied to the holding circuit 213. In this case, as shown in FIG. 8 , the number of analog signals for image generation output by the selection circuit 223 to the conversion unit 204 may be the same as the number of analog signals for image generation supplied to the holding circuit 213. As a result, the number of AD conversions performed by the conversion unit 204 is reduced compared to the operation shown in FIG. 7 , and the power consumption of the photoelectric conversion device 100 per horizontal period Thd is reduced.

[0043] In the operation shown in FIG. 8, the conversion unit 204 is on standby for the timing to AD convert the focus detection signal S1 that was thinned out in the operation shown in FIG. 7. However, the selection circuit 223 may select the sample and hold circuit SH1_3 (S1) at time T2ad2. Alternatively, for example, the selection circuit 223 may select the sample and hold circuit SH1_1 (S1) at time T2ad2 and select the sample and hold circuit SH1_3 (S1) at time T2ad3. Alternatively, for example, the selection circuit 223 may select the sample and hold circuit SH1_1 (S1) at time T2ad3 and select the sample and hold circuit SH1_3 (S1) at time T2ad4. Furthermore, for example, the selection circuit 223 may select the sample and hold circuit SH1_1 (S1) at time T2ad1 and select the sample and hold circuit SH1_3 (S1) at time T2ad4.

[0044] The photoelectric conversion device 100 of this embodiment includes the signal holding unit 203 described above. This allows the vertical scanning of the pixel 201 to be the same regardless of whether the operation of reducing AD conversion of the focus detection signal S1 shown in FIG. 8 or the operation of performing AD conversion of all focus detection signals S1 shown in FIG. 7 is performed. That is, the operation of the row selection unit 103 and the holding circuit 213 (sample and hold circuits SH1, SH2) does not change between the operation shown in FIG. 7 and the operation shown in FIG. 8. Therefore, the time for each output line 202 from when the signal is read from the pixel 201 to the holding circuit 213 (sample and hold circuits SH1, SH2) to when the signal is output to the conversion unit 204 does not change depending on whether AD conversion of the focus detection signal S1 is thinned out.

[0045] For example, consider a case where the signal holding unit 203 is not provided and the time from when a signal is read from a pixel 201 to when it is AD converted varies depending on the operation. For example, if the signal S1 output to the second and third output lines 202 is thinned out among the signals output to the four output lines 202, the signal S1 from the fourth output line 202 may be sent to the converter 204 immediately after AD conversion of the signal S1 from the first output line 202. On the other hand, if the signal S1 is not thinned out, the signal S1 from the fourth output line 202 will be sent to the converter 204 after AD conversion of the signals S1 from the first to third output lines 202 is completed, and the time from when the signal S1 is output to the output line 202 to when it is AD converted will change. As a result, if the holding circuit 213 (sample-and-hold circuits SH1 and SH2) is not provided, the accuracy of the AD conversion may be reduced due to changes in the signal level over time caused by leakage from the output line 202. On the other hand, in this embodiment, the signal holding unit 203 can suppress such a reduction in AD conversion accuracy.

[0046] As described above, the operations of the row selection unit 103 and the holding circuit 213 (sample and hold circuits SH1, SH2) do not change between the operation shown in Fig. 7 and the operation shown in Fig. 8. Therefore, when switching between the operation shown in Fig. 7 and the operation shown in Fig. 8 depending on the accuracy of focus detection, etc., the control unit 102 can control the operations of the row selection unit 103 and the holding circuit 213 using the same control signal. In other words, this can facilitate the design of the control signal output by the control unit 102.

[0047] 8, the AD conversion of half of the signals S1 for focus detection is thinned out. However, this is not a limitation, and one signal S1 or three signals S1 may be thinned out. An appropriate number of signals S1 may be thinned out depending on the shooting conditions, the accuracy required for focus detection, etc. Furthermore, the photoelectric conversion device 100 may be configured so that the number (proportion) of signals S1 to be thinned out can be set appropriately depending on the shooting conditions, the accuracy required for focus detection, etc. The number (proportion) of signals S1 to be thinned out may be set appropriately by the user, or may be set automatically depending on the shooting conditions, etc.

[0048] As described above, the photoelectric conversion device 100 of this embodiment can select an appropriate signal from among the signals held in the holding circuit 213 (sample-and-hold circuits SH1, SH2) using the selection circuit 223 and output the selected signal to the conversion unit 204. This not only increases the speed of image capture, but also reduces power consumption by reducing the number of AD conversions. Furthermore, by selecting an appropriate signal, it is possible to suppress a decrease in focus detection accuracy. As a result, the performance of the photoelectric conversion device 100 is improved.

[0049] 8, it has been described that the hold circuit 213 (sample and hold circuits SH1, SH2) holds all of the focus detection signals S1 supplied thereto, and the selection circuit 223 selects a portion of the focus detection signals S1 held in the hold circuit 213, and outputs the selected portion to the conversion unit 204. However, this is not limiting. For example, the hold circuit 213 may hold a portion of the focus detection signals S1 supplied thereto, and the selection circuit 223 may select the held portion of the signals S1, and supply the selected portion to the conversion unit 204. For example, when an analog signal based on a signal from the photoelectric conversion unit 311 of the pixel 201 is output to the output line 202, the hold circuit 213 (sample and hold circuits SH1, SH2) may not hold the signal to be thinned out.

[0050] Next, a modified example of the operation shown in FIG. 8 will be described using FIG. 9. FIG. 9 is a timing chart showing an example of the operation of the column AD conversion unit 105 when a portion of the focus detection signal S1 is not AD converted, similar to the operation shown in FIG. 8. The operation of the holding circuit 213 (sample and hold circuits SH1, SH2) of the signal holding unit 203 is the same as the operation shown in FIGS. 7 and 8. On the other hand, the operation shown in FIG. 9 differs from the operation shown in FIG. 8 in the operation of the selection circuit 223 of the signal holding unit 203. The following description will focus on the differences, and explanations of points that may be similar will be omitted as appropriate.

[0051] 8, the total number of focus detection signals S1 and image generation signals S2 that the selection circuit 223 outputs to the conversion unit 204 during a given horizontal period Thd is the same as the total number of focus detection signals S1 and image generation signals S2 that the selection circuit 223 outputs to the conversion unit 204 during the horizontal period Thd that follows the given horizontal period Thd. In other words, the total number of focus detection signals S1 and image generation signals S2 that the selection circuit 223 selects from the signals held in the sample and hold circuit SH1 and outputs to the conversion unit 204 is the same as the total number of focus detection signals S1 and image generation signals S2 that the selection circuit 223 selects from the signals held in the sample and hold circuit SH2 and outputs to the conversion unit 204. In other words, the same number of focus detection signals S1 and image generation signals S2 are supplied to the conversion unit 204 for each horizontal period Thd.

[0052] 9, the total number of focus detection signals S1 and image generation signals S2 that the selection circuit 223 outputs to the conversion unit 204 in a given horizontal period Thd is different from the total number of focus detection signals S1 and image generation signals S2 that the selection circuit 223 outputs to the conversion unit 204 in a horizontal period Thd following that horizontal period Thd. In other words, a different number of focus detection signals S1 and image generation signals S2 are supplied to the conversion unit 204 for each horizontal period Thd (for example, alternately).

[0053] 9, similarly to the operation shown in Fig. 7, from time T1 to time T2, the sample and hold circuit SH1 samples the focus detection signal S1, which is an analog signal based on the signal of the photoelectric conversion unit 311, and the image generation signal S2, which is an analog signal based on the signals of the photoelectric conversion units 311 and 313. Next, the sample and hold circuit SH1 enters a hold state at time T2.

[0054] Next, at time T2ad5 when the timing control counter 503 reaches the set value cnt_ad5, the control signal generation unit 507 generates a signal that causes the selection circuit 223 to select the sample and hold circuit SH1_1 (S2). This causes the selection circuit 223 to select the sample and hold circuit SH1_1 (S2) that holds the image generation signal S2 output to cm_vl1 of the output line 202, and output the signal to the conversion unit 204. The conversion unit 204 performs AD conversion on the signal held in the sample and hold circuit SH1_1 (S2). Similarly, at time T2ad6, the image generation signal S2 output to cm_vl2 of the output line 202 is selected; at time T2ad7, the image generation signal S2 output to cm_vl3 of the output line 202 is selected; and at time T2ad8, the image generation signal S2 output to cm_vl4 of the output line 202 is selected, and each signal is AD converted.

[0055] In this way, between times T2 and T3, the selection circuit 223 does not output the focus detection signal S1 to the conversion unit 204. Therefore, the focus detection signal SH1 supplied to the sample-and-hold circuit SH1 is not AD converted by the conversion unit 204.

[0056] During the period from time T2 to time T3, the sample and hold circuit SH2 samples the focus detection signal S1, which is an analog signal based on the signal from the photoelectric conversion unit 311, and the image generation signal S2, which is an analog signal based on the signals from the photoelectric conversion units 311 and 313. Next, the sample and hold circuit SH1 enters a hold state at time T2.

[0057] At time T3ad1 when the timing control counter 504 reaches the set value cnt_ad1, the sample and hold circuit SH2_1 (S1) is selected by the selection circuit 223. As a result, the focus detection signal S1 output to cm_vl1 of the output line 202 is output to the conversion unit 204 and AD converted. Similarly, at time T3ad2, the focus detection signal S1 output to cm_vl2 of the output line 202 is selected, at time T3ad3, the focus detection signal S1 output to cm_vl3 of the output line 202 is selected, and at time T3ad4, the focus detection signal S1 output to cm_vl4 of the output line 202 is selected, and each is AD converted.

[0058] Next, at time T3ad5 when the timing control counter 504 reaches the set value cnt_ad5, the sample and hold circuit SH2_1 (S2) is selected by the selection circuit 223. As a result, the image generation signal S2 output to cm_vl1 of the output line 202 is output to the conversion unit 204 and AD converted. Similarly, at time T3ad6, the image generation signal S2 output to cm_vl2 of the output line 202 is selected, at time T3ad7, the image generation signal S2 output to cm_vl3 of the output line 202 is selected, and at time T3ad8, the image generation signal S2 output to cm_vl4 of the output line 202 is selected, and each is AD converted.

[0059] In this way, from time T3 to time T4, the selection circuit 223 outputs all of the focus detection signals S1 and image generation signals S2 held in the sample and hold circuit SH2 to the conversion unit 204. Therefore, all of the focus detection signals SH1 and image generation signals S2 supplied to the sample and hold circuit SH2 are AD converted by the conversion unit 204. The conversion unit 204 performs AD conversion on all of the focus detection signals (S1) and image generation signals (S2) during the hold period from time T3 to time T4.

[0060] In the operation shown in Fig. 9, the focus detection signal S1 supplied to the sample and hold circuit SH1 is not AD converted, and only the image generation signal S2 is AD converted. Furthermore, the focus detection signal S1 and the image generation signal S2 supplied to the sample and hold circuit SH2 are AD converted. In the operation shown in Fig. 8, whether or not to AD convert the focus detection signal S1 is switched between the hold period of the sample and hold circuit SH1 and the hold period of the sample and hold circuit SH2.

[0061] In the operation shown in Fig. 9, four AD conversions are performed on the focus detection signal S1 and eight AD conversions are performed on the image generation signal S2 during a period twice the horizontal period Thd. That is, a total of 12 AD conversions are performed during a period twice the horizontal period Thd. In the operation shown in Fig. 7, 16 AD conversions are performed during a period twice the horizontal period Thd, so the operation shown in Fig. 9 has fewer AD conversions than the operation shown in Fig. 7.

[0062] 9, the operation of the holding circuit 213 (sample-and-hold circuits SH1 and SH2) of the signal holding unit 203 and the operation of the conversion unit 204 for each AD conversion remain unchanged. On the other hand, the number of analog signals for focus detection (signal S1) that the selection circuit 223 outputs to the conversion unit 204 is smaller than the number of analog signals for focus detection (signal S1) that are supplied to the holding circuit 213. Therefore, the number of analog signals for focus detection (signal S1) that the conversion unit 204 converts into digital signals is smaller than the number of analog signals for focus detection (signal S1) that are supplied to the holding circuit 213. As a result, the number of times AD conversion is performed in the conversion unit 204 is reduced compared to the operation shown in FIG. 7, and power consumption of the photoelectric conversion device 100 is reduced.

[0063] 9, the focus detection signal S1 supplied to the sample and hold circuit SH1 is not AD converted. However, this is not limiting, and the focus detection signal S1 supplied to the sample and hold circuit SH1 may be AD converted, while the focus detection signal S1 supplied to the sample and hold circuit SH2 may not be AD converted.

[0064] Furthermore, for example, a portion of the focus detection signals S1 supplied to the sample-and-hold circuit SH1 may be AD converted depending on the shooting conditions, the accuracy required for focus detection, etc. As with the operation shown in Fig. 8, an appropriate number of signals S1 may be thinned out depending on the shooting conditions, the accuracy required for focus detection, etc.

[0065] 9, the photoelectric conversion device 100 of this embodiment can select an appropriate signal from the signals held in the holding circuit 213 (sample-and-hold circuits SH1 and SH2) using the selection circuit 223 and output the selected signal to the conversion unit 204. This not only increases the speed of image capture, but also reduces power consumption by reducing the number of AD conversions. Furthermore, by selecting an appropriate signal, it is possible to prevent a decrease in focus detection accuracy. As a result, the performance of the photoelectric conversion device 100 is improved.

[0066] Furthermore, in the present embodiment, a configuration in which multiple output lines 202 are provided for one column of pixels has been described, but the present invention is not limited to this configuration. For example, only one output line 202 may be provided for one column of pixels. Even in this case, it is sufficient to provide a selection circuit 223 that selects some of the multiple output lines 202, that is, the multiple output lines 202 provided corresponding to the multiple columns of pixels, and outputs a signal to the holding circuit 213. Even in this configuration, the operations shown in each of FIGS. 7 to 9 of this embodiment can be performed.

[0067] An application example of the photoelectric conversion device 100 of this embodiment will now be described with reference to Fig. 10. Fig. 10 is a schematic diagram of an apparatus 9191 including the photoelectric conversion device 100. As shown in Fig. 10, the photoelectric conversion device 100 is housed in a package 920. The package 920 can include a base to which the photoelectric conversion device 100 is fixed, and a lid such as glass that faces the photoelectric conversion device 100. The package 920 can further include bonding members such as bonding wires and bumps that connect terminals provided on the base to pads provided on the photoelectric conversion device 100.

[0068] The device 9191 can include at least one of an optical device 940, a control device 950, a processing device 960, a display device 970, a storage device 980, and a mechanical device 990. The optical device 940 is, for example, a lens, a shutter, or a mirror. The control device 950 controls the photoelectric conversion device 100. The control device 950 is, for example, a semiconductor device such as an ASIC.

[0069] The processing device 960 processes the signal output from the photoelectric conversion device 100. The processing device 960 is a semiconductor device such as a CPU or ASIC for configuring an AFE (analog front end) or a DFE (digital front end). The display device 970 is an EL display device or a liquid crystal display device that displays information (images) obtained by the photoelectric conversion device 100. The storage device 980 is a magnetic device or a semiconductor device that stores information (images) obtained by the photoelectric conversion device 100. The storage device 980 is a volatile memory such as an SRAM or a DRAM, or a non-volatile memory such as a flash memory or a hard disk drive.

[0070] The mechanical device 990 has a moving part or a propulsion part such as a motor or an engine. In the device 9191, the signal output from the photoelectric conversion device 100 is displayed on the display device 970, or transmitted to the outside by a communication device (not shown) provided in the device 9191. For this purpose, the device 9191 may further include a storage device 980 and a processing device 960 in addition to the storage circuit and arithmetic circuit provided in the photoelectric conversion device 100. The mechanical device 990 may be controlled based on the signal output from the photoelectric conversion device 100.

[0071] The device 9191 is also suitable for electronic devices such as information terminals with a photographing function (e.g., smartphones and wearable devices) and cameras (e.g., interchangeable lens cameras, compact cameras, video cameras, and surveillance cameras). The mechanical device 990 in the camera can drive components of the optical device 940 for zooming, focusing, and shutter operation. Alternatively, the mechanical device 990 in the camera can move the photoelectric conversion device 100 for vibration isolation operations.

[0072] The device 9191 can also be applied to an on-board camera mounted on transportation equipment such as a vehicle, a ship, an airplane, or an industrial robot. The mechanical device 990 in transportation equipment can be used as a mobile device. The device 9191 as transportation equipment is suitable for transporting the photoelectric conversion device 100 or for assisting and / or automating driving (piloting) using a photographing function. The processing device 960 for assisting and / or automating driving (piloting) can perform processing for operating the mechanical device 990 as a mobile device based on information obtained by the photoelectric conversion device 100. The device 9191 incorporating the photoelectric conversion device 100 is not limited to transportation equipment, and can be widely applied to equipment that uses object recognition, such as an intelligent transport system (ITS). Alternatively, the device 9191 may be a medical device such as an endoscope, a measuring device such as a distance measuring sensor, an analytical device such as an electron microscope, or an office machine such as a copier.

[0073] The disclosure of this specification includes the following photoelectric conversion devices and instruments.

[0074] (Item 1) A photoelectric conversion device comprising: a plurality of pixels arranged to form a plurality of rows and a plurality of columns; a plurality of output lines; and a row selection unit that selects a pixel from among the plurality of pixels to output a signal, a signal holding unit and a conversion unit that converts an analog signal output from the signal holding unit into a digital signal, for each of the plurality of columns; the signal holding unit includes: a holding circuit to which signals are supplied from pixels among the plurality of pixels connected to the two or more output lines via two or more output lines among the plurality of output lines assigned to a column in which the signal holding unit is arranged; and a selection circuit; each of the plurality of pixels includes a first photoelectric conversion unit and a second photoelectric conversion unit; the row selection unit causes two or more pixels connected to different output lines among the two or more output lines and arranged in different rows among the plurality of rows to output a first analog signal based on a signal from the first photoelectric conversion unit, and then causes two or more pixels to output a second analog signal based on signals from the first photoelectric conversion unit and the second photoelectric conversion unit; the selection circuit selects the first analog signal and the second analog signal held in the holding circuit and outputs them to the conversion unit; a selection circuit for selecting a first analog signal from the first conversion unit and a holding circuit for holding the first analog signal;

[0075] (Item 2) 2. The photoelectric conversion device according to item 1, wherein the plurality of output lines are provided such that two or more output lines are assigned to each of the plurality of columns.

[0076] (Item 3) 3. The photoelectric conversion device according to item 1 or 2, characterized in that the number of the second analog signals output by the selection circuit to the conversion unit is the same as the number of the second analog signals supplied to the holding circuit.

[0077] (Item 4) The photoelectric conversion device described in any one of items 1 to 3, characterized in that the number of the first analog signals converted into digital signals by the conversion unit is smaller than the number of the first analog signals supplied to the holding circuit.

[0078] (Item 5) the holding circuits include a first holding circuit to which the first analog signal and the second analog signal are supplied in a first horizontal period, and a second holding circuit to which the first analog signal and the second analog signal are supplied in a second horizontal period following the first horizontal period; The photoelectric conversion device described in any one of items 1 to 4, characterized in that, during the second horizontal period, the selection circuit selects the first analog signal and the second analog signal supplied to the first holding circuit during the first horizontal period and outputs them to the conversion unit, and during a third horizontal period following the second horizontal period, selects the first analog signal and the second analog signal supplied to the second holding circuit during the second horizontal period and outputs them to the conversion unit.

[0079] (Item 6) 6. The photoelectric conversion device according to item 5, wherein the total number of the first analog signals and the second analog signals that the selection circuit outputs to the conversion unit in the second horizontal period is the same as the total number of the first analog signals and the second analog signals that the selection circuit outputs to the conversion unit in the third horizontal period.

[0080] (Item 7) 6. The photoelectric conversion device according to item 5, wherein the total number of the first analog signals and the second analog signals that the selection circuit outputs to the conversion unit in the second horizontal period is different from the total number of the first analog signals and the second analog signals that the selection circuit outputs to the conversion unit in the third horizontal period.

[0081] (Item 8) 8. The photoelectric conversion device according to item 7, wherein the selection circuit does not output the first analog signal to the conversion unit during the second horizontal period.

[0082] (Item 9) The photoelectric conversion device described in item 8, characterized in that the selection circuit supplies all of the first analog signals supplied to the second holding circuit in the second horizontal period to the conversion unit in the third horizontal period.

[0083] (Item 10) The photoelectric conversion device according to any one of items 1 to 9, wherein the conversion unit converts each of the first analog signal and the second analog signal output from the selection circuit into a digital signal in a time-division manner.

[0084] (Item 11) the first analog signal is a signal for focus detection, 11. The photoelectric conversion device according to any one of items 1 to 10, wherein the second analog signal is a signal for generating an image.

[0085] (Item 12) Each of the plurality of pixels has a microlens; The photoelectric conversion device described in any one of items 1 to 11, characterized in that the first photoelectric conversion unit and the second photoelectric conversion unit of each of the plurality of pixels are arranged corresponding to one of the microlenses.

[0086] (Item 13) the holding circuit holds a portion of the first analog signal that is supplied; 13. The photoelectric conversion device according to any one of items 1 to 12, wherein the selection circuit selects the portion and supplies it to the conversion unit.

[0087] (Item 14) the holding circuit holds all of the first analog signals supplied thereto; 13. The photoelectric conversion device according to any one of items 1 to 12, wherein the selection circuit selects a portion of the first analog signal held in the holding circuit and outputs the selected portion to the conversion unit.

[0088] (Item 15) A photoelectric conversion device according to any one of items 1 to 14, a processing device that processes a signal output from the photoelectric conversion device; An apparatus characterized by comprising:

[0089] The invention is not limited to the above-described embodiments, and various changes and modifications can be made without departing from the spirit and scope of the invention. Accordingly, the following claims are appended to apprise the public of the scope of the invention. [Explanation of symbols]

[0090] 100: Photoelectric conversion device, 103: Row selection unit, 201: Pixel, 202: Output line, 203: Signal holding unit, 204: Conversion unit, 213: Holding circuit, 223: Selection circuit, 311, 313: Photoelectric conversion unit

Claims

1. A photoelectric conversion device comprising: a plurality of pixels arranged to form a plurality of rows and a plurality of columns; a plurality of output lines; and a row selection unit that selects a pixel from among the plurality of pixels to output a signal, a signal holding unit and a conversion unit that converts an analog signal output from the signal holding unit into a digital signal, for each of the plurality of columns; the signal holding unit includes: a holding circuit to which signals are supplied from pixels among the plurality of pixels connected to the two or more output lines via two or more output lines among the plurality of output lines assigned to a column in which the signal holding unit is arranged; and a selection circuit; each of the plurality of pixels includes a first photoelectric conversion unit and a second photoelectric conversion unit; the row selection unit causes two or more pixels connected to different output lines among the two or more output lines and arranged in different rows among the plurality of rows to output a first analog signal based on a signal from the first photoelectric conversion unit, and then causes two or more pixels to output a second analog signal based on signals from the first photoelectric conversion unit and the second photoelectric conversion unit; the selection circuit selects the first analog signal and the second analog signal held in the holding circuit and outputs them to the conversion unit; a selection circuit for selecting a first analog signal from the first conversion unit and a holding circuit for holding the first analog signal;

2. 2. The photoelectric conversion device according to claim 1, wherein the plurality of output lines are provided such that two or more output lines are assigned to each of the plurality of columns.

3. 2. The photoelectric conversion device according to claim 1, wherein the number of the second analog signals output by the selection circuit to the conversion unit is the same as the number of the second analog signals supplied to the holding circuit.

4. 2. The photoelectric conversion device according to claim 1, wherein the number of the first analog signals converted into digital signals by the conversion unit is smaller than the number of the first analog signals supplied to the holding circuit.

5. the holding circuits include a first holding circuit to which the first analog signal and the second analog signal are supplied in a first horizontal period, and a second holding circuit to which the first analog signal and the second analog signal are supplied in a second horizontal period following the first horizontal period; The photoelectric conversion device according to claim 1, characterized in that, during the second horizontal period, the selection circuit selects the first analog signal and the second analog signal supplied to the first holding circuit during the first horizontal period and outputs them to the conversion unit, and during a third horizontal period following the second horizontal period, selects the first analog signal and the second analog signal supplied to the second holding circuit during the second horizontal period and outputs them to the conversion unit.

6. The photoelectric conversion device according to claim 5, characterized in that the total number of the first analog signals and the second analog signals output by the selection circuit to the conversion unit during the second horizontal period is the same as the total number of the first analog signals and the second analog signals output by the selection circuit to the conversion unit during the third horizontal period.

7. The photoelectric conversion device according to claim 5, characterized in that the total number of the first analog signals and the second analog signals that the selection circuit outputs to the conversion unit during the second horizontal period is different from the total number of the first analog signals and the second analog signals that the selection circuit outputs to the conversion unit during the third horizontal period.

8. 8. The photoelectric conversion device according to claim 7, wherein the selection circuit does not output the first analog signal to the conversion unit during the second horizontal period.

9. 9. The photoelectric conversion device according to claim 8, wherein the selection circuit supplies all of the first analog signals supplied to the second holding circuit during the second horizontal period to the conversion unit during the third horizontal period.

10. 2. The photoelectric conversion device according to claim 1, wherein the conversion section converts each of the first analog signal and the second analog signal output from the selection circuit into a digital signal in a time-division manner.

11. the first analog signal is a signal for focus detection, 2. The photoelectric conversion device according to claim 1, wherein the second analog signal is a signal for generating an image.

12. Each of the plurality of pixels has a microlens; The photoelectric conversion device according to claim 1 , wherein the first photoelectric conversion unit and the second photoelectric conversion unit of each of the plurality of pixels are arranged corresponding to one of the microlenses.

13. Each of the plurality of pixels has a microlens; The photoelectric conversion device according to claim 2 , wherein the first photoelectric conversion unit and the second photoelectric conversion unit of each of the plurality of pixels are arranged corresponding to one of the microlenses.

14. the holding circuit holds a portion of the first analog signal that is supplied; 2. The photoelectric conversion device according to claim 1, wherein the selection circuit selects the part and supplies it to the conversion unit.

15. the holding circuit holds all of the first analog signals supplied thereto; 2. The photoelectric conversion device according to claim 1, wherein the selection circuit selects a part of the first analog signal held in the holding circuit and outputs the selected part to the conversion unit.

16. The photoelectric conversion device according to any one of claims 1 to 15, a processing device that processes a signal output from the photoelectric conversion device; An apparatus characterized by comprising:

Images