Selective carbon deposition on top and bottom surfaces of semiconductor substrates

Abstract

To provide a method that can be used to fabricate high quality devices and structures.SOLUTION: A semiconductor processing method comprises a step of supplying a substrate comprising a substrate trench having a top surface and a bottom surface to a reaction chamber. A deposition gas containing a carbon-containing gas and a nitrogen-containing gas is flowed into a plasma excitation region of the reaction chamber to generate a deposition plasma from the deposition gas having an electron temperature of about 4 eV or less to deposit a carbon-containing layer on the top surface and the bottom surface of the substrate trench. The as-deposited carbon-containing layer has a top-to-bottom thickness ratio of about 3:1 or greater. The semiconductor structure also includes a carbon-containing layer as deposited on the top and the bottom surfaces of at least the first trench and the second trench, the carbon-containing layer has the top-to-bottom thickness ratio of about 3:1 or greater.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] cross reference

[0001] This application claims priority to U.S. Application No. 17 / 359,947, filed June 28, 2021, the disclosure of which is incorporated herein by reference in its entirety for all purposes.

[0002]

[0002] The present technology relates to semiconductor systems, processes, and equipment. More particularly, the present technology relates to processes and structures for selectively depositing carbon films. [Background technology]

[0003]

[0003] Integrated circuits are made possible by processes that produce intricately patterned layers of material on substrate surfaces. Creating patterned materials on substrates requires controlled methods for the formation and removal of exposed material. The properties of the materials can affect device operation and can also affect how films are removed relative to each other. Plasma-assisted deposition can produce films with specific properties. Many of the films produced require additional processing to adjust or enhance the material properties of the film to achieve the appropriate properties.

[0004]

[0004] Therefore, there is a need for improved systems and methods that can be used to manufacture high quality devices and structures. These and other needs are addressed by the present technology. Summary of the Invention

[0005]

[0005] An embodiment of the present technology includes a semiconductor processing method including providing a substrate into a reaction chamber, the substrate including a substrate trench having a top surface and a bottom surface. The method also includes flowing a deposition gas into a plasma excitation region of the reaction chamber, the deposition gas including a carbon-containing gas and a nitrogen-containing gas. A deposition plasma having an electron temperature of about 4 eV or less is generated from the deposition gas. The method further includes depositing a carbon-containing layer on the top and bottom surfaces of the substrate trench, the as-deposited carbon-containing layer having a top-to-bottom thickness ratio of about 3:1 or greater.

[0006] In a further embodiment, the deposition gas does not include argon. In a further embodiment, the deposition gas does not include helium. In yet a further embodiment, the method further includes heating the substrate to a temperature of about 100° C. or greater before depositing the carbon-containing layer. In another further embodiment, the method also includes etching through at least a portion of the carbon-containing layer at a bottom surface of the substrate trench, with the carbon-containing layer still covering an upper surface of the substrate trench. In a further embodiment, the method also includes removing the carbon-containing layer from the substrate after etching through at least a portion of the carbon-containing layer at a bottom surface of the substrate trench. In yet a further embodiment, the carbon-containing gas includes methane. In yet a further embodiment, the nitrogen-containing gas includes molecular nitrogen (N). In a further embodiment, the deposition plasma is generated by supplying RF power to the deposition gas, the RF power being characterized by a power of about 300 Watts or less. In a further embodiment, the deposition plasma is characterized by a pressure of about 10 mTorr or less.

[0007]

[0007] Embodiments of the present technology also include a semiconductor processing method including providing a substrate to a reaction chamber, the substrate including a first trench having a first aspect ratio of about 2:1 or greater and a second trench having a second aspect ratio of about 1:2 or less. The first trench and the second trench also each have a top surface and a bottom surface. The method further includes heating the substrate to a temperature of about 100°C or greater. The method also includes flowing a deposition gas into a plasma excitation region of the reaction chamber, the deposition gas including a carbon-containing gas and a nitrogen-containing gas. A deposition plasma is generated from the deposition gas. The method still further includes depositing a carbon-containing layer on the heated substrate, the as-deposited carbon-containing layer having a top-to-bottom thickness ratio of about 3:1 or greater in both the first trench and the second trench.

[0008] In a further embodiment, the method may also include etching through at least a portion of the carbon-containing layer on the bottom surfaces of the first and second substrate trenches, with the carbon-containing layer still covering the top surfaces of the first and second substrate trenches. In a further embodiment, the method may further include removing the carbon-containing layer from the substrate after etching through at least a portion of the carbon-containing layer on the bottom surfaces of the first and second substrate trenches. In yet a further embodiment, the deposition plasma is characterized by an electron temperature of about 4 eV or less. In another further embodiment, the first substrate trench is characterized by a first bottom width of about 50 nm or less, and the second substrate trench is characterized by a second bottom width of about 100 nm or more. In a further embodiment, the carbon-containing layer is characterized by a top thickness of about 5 nm or more and a bottom thickness of about 1.6 nm or less. In yet a further embodiment, the carbon-containing layer comprises solid carbon.

[0009]

[0009] Embodiments of the present technology further include a semiconductor structure including a first trench and a second trench formed in at least one semiconductor material. The first trench and the second trench have a top surface and a bottom surface, the first trench being characterized by a first aspect ratio of about 2:1 or greater, and the second trench being characterized by a second aspect ratio of about 1:2 or less. The semiconductor structure may also include a dielectric layer in contact with the at least one semiconductor material, the dielectric layer forming the top and bottom surfaces of the first trench and the second trench. The semiconductor structure may also include a carbon-containing layer in contact with the dielectric layer at the top and bottom surfaces of the first trench and the second trench. The carbon-containing layer is characterized by a top-to-bottom thickness ratio of about 3:1 or greater in both the first trench and the second trench.

[0010] In a further embodiment, the dielectric layer can include silicon nitride. In a further embodiment, the carbon-containing layer can include solid carbon. In yet a further embodiment, the dielectric layer is characterized by a bottom thickness of about 5 nm or greater. In yet a further embodiment, the carbon-containing layer is characterized by a top thickness of about 5 nm or greater and a bottom thickness of about 1.6 nm or less. In a further embodiment, the semiconductor structure includes a carbon-containing layer at the bottom of the first trench and a contact region positioned below the dielectric layer.

[0011] The above-described technique offers several advantages over conventional methods and structures for providing a thin, easily removable mask layer that protects the top and sidewall surfaces of a semiconductor trench while etching an opening in the bottom surface. Embodiments of the method include using a selective deposition gas that deposits a carbon-containing layer to a greater extent on the top surface of the trench than on the bottom surface of the trench. The thicker carbon-containing layer on the top surface allows for continuous coverage of the top surface layer after an etching process forms holes through the bottom surface layer. This allows openings, such as contact holes and vias, to be formed on the bottom surface without etching the top and side surfaces of the trench. Embodiments of the method also include heating the bottom surface of the substrate trench to a temperature that slows deposition of the carbon-containing layer on the bottom surface relative to the top surface. These embodiments also selectively deposit a greater amount of the carbon-containing layer on the top surface of the trench than on the bottom surface of the trench. These and other embodiments, along with their many advantages and features, are described in more detail below in conjunction with the description and accompanying figures.

[0012] A further understanding of the nature and advantages of the disclosed technology may be realized by reference to the remaining portions of the specification and the drawings. [Brief explanation of the drawings]

[0013] [Figure 1] 1 is a schematic top plan view illustrating an exemplary processing system according to some embodiments of the present technique; [Figure 2] 1 is a schematic cross-sectional view of an exemplary processing system according to some embodiments of the present technique; [Figure 3] 1A-1D illustrate selected steps in a semiconductor processing method according to some embodiments of the present technique. [Figure 4] 1 is a cross-sectional view illustrating a semiconductor structure including a trench structure according to an embodiment of the present technology; [Figure 5] 1 is a cross-sectional view illustrating a semiconductor structure including an additional trench structure according to an embodiment of the present technology. [Figure 6]FIG. 1A is a cross-sectional view showing a semiconductor structure before forming a protective layer according to an embodiment of the present technology; FIG. 1B is a cross-sectional view showing a semiconductor structure after forming a protective layer according to an embodiment of the present technology; and FIG. 1C is a cross-sectional view showing a semiconductor structure after an etching step and removal of the protective layer according to an embodiment of the present technology. DETAILED DESCRIPTION OF THE INVENTION

[0014]

[0021] Some figures are included as schematic diagrams. It should be understood that the figures are for illustrative purposes and should not be considered to scale unless the scale is explicitly stated. Furthermore, as schematic diagrams, the figures are provided to aid in understanding and may not include all aspects or information compared to realistic representations and may include exaggerated material for illustrative purposes.

[0015]

[0022] In the accompanying figures, similar components and / or features may be labeled with the same reference label. Furthermore, various components of the same type may be distinguished by following the reference label with a letter that distinguishes between the similar components. When only a first reference label is used herein, the description is applicable to any one of the similar components having the same first reference label, regardless of the letter.

[0016]

[0023] A feature found in many semiconductor structures is conductive contacts that extend from semiconductor device layers to metallization layers. These contacts are often created by dry etching openings in a dielectric material and filling the openings with a conductive material, such as aluminum, copper, or tungsten. In most of these cases, the manufacturing process also includes depositing a masking layer to protect the unetched portions of the semiconductor device during the etching process. As semiconductor devices continue to shrink in size and the distance between adjacent devices decreases, the etching process to form openings without unintentionally etching portions of the device becomes more challenging.

[0017]

[0024] One approach to protecting semiconductor devices during etching steps to form contacts is to cover the device structure with a layer of protective material, such as carbon. The protective layer prevents the etching process from etching the top and sidewall surfaces of the device structure while etching an opening at the bottom, which is subsequently filled with a conductive material. As semiconductor device structures become smaller, the protective layers become thinner. Unfortunately, protective layers made of easily removable materials, such as carbon, have become so thin (e.g., less than 10 nm) that the etching process often breaks through the layer at both the top and bottom of the trench in the semiconductor device. The etching process does not have the spatial or temporal precision to break through the protective layer deposited on the top surface and etch an opening at the bottom of the trench without damaging the semiconductor device.

[0018]

[0025] Embodiments of the present technology address, among other issues, the destruction of a protective layer on the top surface of a trench in a semiconductor device during etching of the bottom surface of the trench. Embodiments of the present technology include a method for depositing a protective layer made of carbon to a greater extent on the top surface of the trench than on the bottom surface of the trench. The thicker the carbon-containing layer that remains deposited on the top surface of the trench, the less likely the etching process will break through the carbon-containing layer on the top surface. The etching process that forms an opening through the carbon-containing layer at the bottom surface of the trench often etches through one or more additional layers, while leaving the top surface of the device unetched.

[0019]

[0026] Embodiments of the present technology include a plasma deposition gas that increases the selectivity of plasma deposition of a carbon-containing layer on the top surface of a trench relative to its bottom surface. In embodiments, the deposition gas includes a carbon-containing gas, such as methane. In further embodiments, the deposition gas includes a nitrogen-containing gas, such as molecular nitrogen. In still further embodiments, the deposition gas does not include argon or other inert elements and compounds with a molecular weight higher than molecular nitrogen. In still further embodiments, the deposition gas does not include helium or other gases with a relatively low atomic / molecular weight that significantly increase the temperature of the deposition plasma.

[0020]

[0027] A complex relationship has been observed between the temperature of the plasma, the mass of the gas in the plasma, and the difference in carbon deposition rate at the top and bottom of the trench. For plasma gases with higher molecular weights, such as nitrogen and argon, an increase in the molecular weight of the gas correlates with an increase in the deposition rate at the bottom of the trench relative to the top. This is believed to be caused by an increase in the rate at which deposition molecules (e.g., methane) are transported to the bottom of the trench by heavier carrier species. However, with helium, another challenge arises: the deposition rates of the carbon-containing protective layer observed at the top and bottom of the trench are closer together rather than further apart. Despite having a smaller atomic mass than nitrogen and argon, helium-containing plasmas produce higher plasma temperatures than nitrogen- or argon-containing plasmas. Increasing plasma temperature has a greater effect on the deposition rate of the carbon-containing layer at the top of the trench compared to the bottom, thereby reducing the amount of deposition along the top of the trench.

[0021]

[0028] Without wishing to be bound by any particular theory, carbon films deposit preferentially or to a greater extent on cooler surfaces due to a higher sticking coefficient. Helium plasma generates hot electrons, which increase the plasma temperature and the temperature of the top surface of the trench. The increased temperature reduces the deposition rate of the carbon-containing layer at the top surface of the trench relative to the bottom surface. In the case of helium, the reduction in deposition rate at the top surface of the trench is so great that it outweighs the reduction in deposition rate at the bottom surface due to a reduction in the transport rate of carbon-containing deposition molecules. Therefore, deposition plasmas containing helium as the primary carrier species produce carbon-containing layers with thicknesses closer to the top and bottom than nitrogen-containing deposition plasmas, which are characterized by lower plasma temperatures. On the other hand, deposition plasmas containing argon as the primary carrier species produce carbon-containing layers with thicknesses closer to the top and bottom, similar to helium-containing deposition plasmas. In such argon-containing deposition plasmas, the higher bottom deposition rate due to the increased transport rate of the heavy argon species outweighs the favorable top surface deposition conditions due to the lower plasma temperature.

[0022]

[0029] Furthermore, it has been observed that the difference in deposition rate of the carbon-containing layer between the top and bottom surfaces of the trench can occur over a range of substrate temperatures and trench widths. Accordingly, embodiments of the present technique can be used with substrates at temperatures of about 100° C. or higher, as well as with substrates at temperatures of about 100° C. or lower. Additionally, embodiments of the present technique can be used to deposit carbon-containing layers of different thicknesses on the top and bottom surfaces of trenches with widths of about 50 nm or less, as well as trenches with widths of about 100 nm or greater. In further embodiments, an as-deposited carbon-containing layer can be deposited on a substrate having trenches with multiple different widths, where the layer is thicker at the top surface than at the bottom surface of each trench.

[0023]

[0030] While the remainder of the disclosure will always identify specific deposition and etch processes utilizing the present technology, it will be readily understood that the present systems and methods are equally applicable to a variety of other processes and semiconductor structures that may be used with the described chambers. Accordingly, the present technology should not be considered limited to use with only the described systems, methods, and chambers. This disclosure will discuss possible systems and chambers that may be used with the present technology before describing systems and methods or steps of exemplary process sequences according to some embodiments of the present technology. It should be understood that the present technology is not limited to the described equipment, and that the described processes may be performed in any number of processing chambers and systems.

[0024]

[0031] Figure 1 is a top plan view of one embodiment of a deposition, etch, bake, and / or cure chamber processing system 10 according to embodiments. The tool or processing system 10 shown in Figure 1 may include multiple process chambers 24a-d, a transfer chamber 20, a service chamber 26, an integrated metrology chamber 28, and a pair of load lock chambers 16a-b. The process chambers may include any number of structures or components and any number or combination of process chambers.

[0025]

[0032] To transport substrates between chambers, the transfer chamber 20 may include a robotic transport mechanism 22. The transport mechanism 22 may have a pair of substrate transport blades 22a, each attached to the distal end of an extendable arm 22b. The blades 22a may be used to transport individual substrates into and out of the process chambers. In a process, one of the substrate transport blades, such as blade 22a of the transport mechanism 22, may retrieve a substrate W from one of the load lock chambers, such as chambers 16a-b, and transport the substrate W to a first processing stage, e.g., a processing process, as described below, in chambers 24a-d. The chambers may be included to perform individual or combined steps of the described techniques. For example, one or more chambers may be configured to perform a deposition or etching step, while one or more other chambers may be configured to perform a described pre-processing step and / or one or more post-processing steps. Any number of configurations capable of performing any number of additional manufacturing steps typically performed in semiconductor processing are encompassed by the present technology.

[0026]

[0033] If a chamber is occupied, the robot can wait until processing is complete, then remove the processed substrate from the chamber with one blade 22a and insert a new substrate with a second blade. Once the substrate has been processed, it can then be moved to a second processing stage. For each move, the transport mechanism 22 can generally have one blade carrying the substrate and one empty blade to perform the substrate swap. The transport mechanism 22 can wait in each chamber until it can complete the swap.

[0027]

[0034] Once processing is completed in a process chamber, the transport mechanism 22 can remove the substrate W from the last process chamber and transport the substrate W to a cassette in the load lock chambers 16a-b. Substrates can be moved from the load lock chambers 16a-b into the factory interface 12. The factory interface 12 generally operates to transfer substrates between the pod loaders 14a-d and the load lock chambers 16a-b in an atmospheric pressure clean environment. The clean environment of the factory interface 12 generally can be achieved through an air filtration process, such as HEPA filtration. The factory interface 12 can also include a substrate orienter / aligner that can be used to properly align substrates prior to processing. At least one substrate robot, such as robots 18a-b, can be positioned within the factory interface 12 to transport substrates between various locations within the factory interface 12 and to other locations coupled thereto. The robots 18a-b may be configured to move along a track system within the factory interface 12 from a first end to a second end of the factory interface 12.

[0028]

[0035] The processing system 10 may further include an integrated metrology chamber 28 for providing control signals, which may provide adaptive control for any of the processes being performed in the processing chamber. The integrated metrology chamber 28 may include any of a variety of metrology devices for measuring various film properties such as thickness, roughness, composition, etc., and the metrology devices may further be capable of characterizing grating parameters such as critical dimensions, sidewall angles, and feature heights under vacuum in an automated manner.

[0029]

[0036] Each of the processing chambers 24a-d may be configured to perform one or more process steps in the fabrication of semiconductor structures, and any number and combination of processing chambers may be used in the multi-chamber processing system 10. For example, any of the processing chambers may be configured to perform multiple substrate processing steps, including any number of deposition processes, including cyclical layer deposition, atomic layer deposition, chemical vapor deposition, physical vapor deposition, and other steps, including etching, pre-cleaning, pre-treatment, post-treatment, annealing, plasma treatment, degassing, alignment, and other substrate processes. Some specific processes that may be performed in any of the chambers, or combinations of chambers, may include metal deposition, surface cleaning and preparation, thermal annealing such as rapid thermal processing, and plasma treatment. As one skilled in the art would readily appreciate, any other processes, including any of the processes described below, may similarly be performed in a particular chamber incorporated in the multi-chamber processing system 10.

[0030]

[0037] FIG. 2 is a schematic cross-sectional view illustrating an exemplary processing chamber 100 suitable for patterning a layer of material disposed on a substrate 302 in the processing chamber 100. While the exemplary processing chamber 100 is suitable for performing a patterning process, it should be understood that aspects of the present technology can be practiced in any number of chambers, and that the substrate support according to the present technology can be included in an etch chamber, a deposition chamber, a processing chamber, or any other processing chamber. The plasma processing chamber 100 can include a chamber body 105 defining a chamber region 101 in which a substrate can be processed. The chamber body 105 can have sidewalls 112 and a bottom 118 coupled to ground 126. The sidewalls 112 can have a liner 115 to protect the sidewalls 112 and extend the time between maintenance cycles of the plasma processing chamber 100. The dimensions of the chamber body 105 and associated components of the plasma processing chamber 100 are not limited and can generally be proportionally larger than the size of the substrate 302 to be processed therein. Examples of substrate sizes include 200 mm diameter, 250 mm diameter, 300 mm diameter, 450 mm diameter, among others, as well as display substrates, solar cell substrates, and the like.

[0031]

[0038] The chamber body 105 may support the chamber lid assembly 110 and enclose the chamber region 101. The chamber body 105 may be made of aluminum or other suitable materials. A substrate access port 113 may be formed through the sidewall 112 of the chamber body 105 to facilitate transfer of the substrate 302 into and out of the plasma processing chamber 100. As described above, the access port 113 may be coupled to a transfer chamber and / or other chambers of a substrate processing system. A pumping port 145 may be formed through the sidewall 112 of the chamber body 105 and connected to the chamber region 101. A pumping system may be coupled to the chamber region 101 through the pumping port 145 to evacuate and control the pressure within the processing region. The pumping system may include one or more pumps and a throttle valve.

[0032]

[0039] A gas panel 160 may be connected to the chamber body 105 by gas lines 167 to supply process gases into the chamber region 101. The gas panel 160 may include one or more process gas sources 161, 162, 163, 164, and may further include inert, non-reactive, and reactive gases for use in any number of processes. Examples of process gases that may be provided by the gas panel 160 include, but are not limited to, methane, sulfur hexafluoride, silicon chloride, carbon tetrafluoride, hydrogen bromide, hydrocarbon-containing gases, including argon gas, chlorine, nitrogen, helium, or oxygen gas, as well as any number of additional materials. Additionally, the process gas may include nitrogen, chlorine, fluorine, oxygen, and hydrogen-containing gases such as BCl, C, F, C, F, CH, CH, F, CH, NF, NH, CO, SO, CO, N, NO, N, O, and H, among any number of additional precursors.

[0033]

[0040] A valve 166 can control the flow of process gas from the sources 161, 162, 163, and 164 of the gas panel 160 and can be managed by a controller 165. The flow of gas supplied to the chamber body 105 from the gas panel 160 can include a combination of gases from one or more sources. The lid assembly 110 can include a nozzle 114. The nozzle 114 can be one or more ports for introducing process gases from the sources 161, 162, 164, and 163 of the gas panel 160 into the chamber region 101. After the process gases are introduced into the plasma processing chamber 100, a voltage can be applied to the gases to form a plasma. An antenna 148, such as one or more inductor coils, can be provided adjacent to the plasma processing chamber 100. An antenna power supply 142 can supply power to the antenna 148 through a matching circuit 141 to inductively couple energy, such as RF energy, to the process gases to maintain a plasma formed from the process gases in the chamber region 101 of the plasma processing chamber 100. Instead of, or in addition to, the antenna power supply 142, process electrodes below and / or above the substrate 302 can be used to capacitively couple RF power to the process gases to maintain a plasma in the chamber region 101. The operation of the power supply 142 can be controlled by a controller, such as controller 165, which also controls the operation of the other components of the plasma processing chamber 100.

[0034]

[0041] A substrate support pedestal 135 may be disposed in the chamber region 101 to support the substrate 302 during processing. The substrate support pedestal 135 may include an electrostatic chuck 122 for holding the substrate 302 during processing. The electrostatic chuck ("ESC") 122 may hold the substrate 302 to the substrate support pedestal 135 using electrostatic attraction. The ESC 122 may be powered by an RF power supply 125 integrated with a matching network 124. The ESC 122 may include an electrode 121 embedded within a dielectric body. The electrode 121 may be coupled to the RF power supply 125 to provide a bias that attracts plasma ions formed by process gases in the chamber region 101 to the ESC 122 and the substrate 302 seated on the pedestal. The RF power supply 125 may be cycled on and off or pulsed during processing of the substrate 302. The ESC 122 may include an isolator 128 to prevent the plasma from being attracted to the sidewalls of the ESC 122, thereby extending the maintenance cycle life of the ESC 122. Additionally, the substrate support pedestal 135 may include a cathode liner 136 to protect the sidewalls of the substrate support pedestal 135 from the plasma gases, thereby extending the maintenance intervals of the plasma processing chamber 100.

[0035]

[0042] The electrode 121 may be coupled to a power supply 150. The power supply 150 may provide a chucking voltage of approximately 200 volts to approximately 2000 volts to the electrode 121. The power supply 150 may also include a system controller for controlling the operation of the electrode 121 by sending a direct current to the electrode 121 for chucking and dechucking the substrate 302. The ESC 122 may include a heater disposed within the pedestal and connected to a power supply for heating the substrate, and the cooling base 129 supporting the ESC 122 may include conduits for circulating a heat transfer fluid to maintain the temperature of the ESC 122 and the substrate 302 disposed thereon. The ESC 122 may be configured to operate in a temperature range required by the thermal budget of devices fabricated on the substrate 302. For example, the ESC 122 may be configured to maintain the substrate 302 at a temperature of approximately −150° C. or lower to approximately 500° C. or higher, depending on the process being performed.

[0036]

[0043] A cooling base 129 may be provided to assist in temperature control of the substrate 302. To mitigate process drift and time, the temperature of the substrate 302 may be maintained substantially constant by the cooling base 129 throughout the substrate 302's time in the cleaning chamber. In some embodiments, the temperature of the substrate 302 may be maintained at a temperature of about −150° C. to about 500° C. throughout the subsequent cleaning process, although any temperature may be used. A cover ring 130 may be disposed on the ESC 122 and along the periphery of the substrate support pedestal 135. The cover ring 130 may be configured to confine etching gas to a desired portion of the exposed upper surface of the substrate 302 while shielding the upper surface of the substrate support pedestal 135 from the plasma environment inside the plasma processing chamber 100. Lift pins may be selectively translated through the substrate support pedestal 135 to lift the substrate 302 above the substrate support pedestal 135 to facilitate access to the substrate 302 by a transfer robot or other suitable transfer mechanism, as described above.

[0037]

[0044] The controller 165 may be used to control process sequences, regulate gas flow from the gas panel 160 into the plasma processing chamber 100, and control other process parameters. The software routines, when executed by the CPU, transform the CPU into a special-purpose computer, such as a controller, that can control the plasma processing chamber 100 so that processes are performed in accordance with the present disclosure. The software routines may also be stored and / or executed by a second controller that may be associated with the plasma processing chamber 100.

[0038]

[0045] Chamber 100 and other embodiments of processing chambers and systems can be used to fabricate semiconductor structures in accordance with embodiments of the present technology. FIG. 3 illustrates exemplary steps in a method 300 for fabricating a semiconductor structure in accordance with some embodiments of the present technology. Method 300 can be performed in one or more processing chambers, such as chamber 100. Method 300 may or may not include one or more steps prior to the start of the method, including front-end processing, deposition, etching, polishing, cleaning, or any other steps that may be performed before the steps described. For example, steps for forming a semiconductor structure including one or more trenches having top and bottom surfaces and sidewall surfaces can be performed prior to the start of method 300. The method can include numerous optional steps that may or may not be specifically related to some embodiments of methods in accordance with the present technology.

[0039]

[0046] FIG. 3 illustrates exemplary steps in a method 300 for etching openings at the bottom of trenches in a semiconductor structure while protecting the top surfaces of those trenches, in accordance with embodiments of the present technology. Method 300 describes steps for forming embodiments of semiconductor devices 400, 500, and 600, shown in simplified schematic form in FIGS. 4, 5, and 6A-6C, which illustrations will be described in conjunction with the steps of method 300. These semiconductor devices 400, 500, and 600 may include semiconductor logic devices such as CPUs and GPUs, memory devices such as DRAMs, and display devices such as LEDs, among other types of semiconductor devices. It should be understood that FIGS. 4, 5, and 6A-6C illustrate only partial schematic views with limited detail, and that in some embodiments, a substrate may include any number of semiconductor sections having the aspects illustrated in the figures, as well as alternative structural aspects that may still benefit from any aspect of the present technology.

[0040]

[0047] Method 300 includes providing a substrate in step 305. In embodiments, the substrate may include a wafer made of silicon, silicon oxide, germanium, gallium arsenide, or aluminum nitride, among other substrate materials. In further embodiments, the substrate may include semiconductor device structures such as structure 405 formed on substrate 402, structure 505 formed on substrate 502, and structure 605 formed on substrate 602, as shown in FIGS. 4, 5, and 6A-6C, respectively. In the embodiment shown in FIG. 4, each structure 405 may include a base structure 407 and one or more layers 409 positioned on the base structure. In further embodiments, one or more layers 409 may extend to the sidewalls of base structure 407 and across the bottom surfaces of trenches between adjacent base structures. In another further embodiment, each of the one or more layers 409 may include a liner layer or a spacer layer, among other types of layers. In the embodiment shown in FIG. 5 , each structure 505 may include a base structure 507 and one or more layers 509 positioned on the base structure. In further embodiments, the one or more layers 509 may extend to the sidewalls of the base structure 507 and across the entire bottom surface of the trench between adjacent base structures. In other further embodiments, each of the one or more layers 509 may include a liner layer or a spacer layer, among other types of layers. In the embodiment shown in FIGS. 6A-6C , each structure 605 may include a base structure 607 and one or more layers 609 positioned on the base structure. In further embodiments, the one or more layers 609 may extend to the sidewalls of the base structure 607 and across the entire bottom surface of the trench between adjacent base structures. In other further embodiments, each of the one or more layers 609 may include a liner layer or a spacer layer, among other types of layers.

[0041]

[0048] In embodiments, base structures 407, 507, and 607 may include at least one of a semiconductor material or a dielectric material. In embodiments, the semiconductor material may include silicon, silicon carbide, germanium, gallium arsenide, gallium nitride, gallium phosphide, and cadmium sulfide, among other semiconductor materials. In further embodiments, the dielectric material may include silicon oxide, silicon carbonate, silicon nitride, silicon oxynitride, titanium dioxide, aluminum oxide, and zinc oxide, among other dielectric materials. In yet other embodiments, one or more layers 409, 509, and 609 may include one or more semiconductor materials or dielectric materials.

[0042]

[0049] In embodiments, structures 405 and 605 include one or more trenches 410 and 610 that include a top surface 412 and a bottom surface 414. The trenches 410 and 610 may be characterized by an aspect ratio comparing the height of the trench to the width at the bottom of the trench. In further embodiments, the trenches 410 and 610 may have an aspect ratio of about 2:1 or greater, about 2.5:1 or greater, about 3:1 or greater, about 3.5:1 or greater, about 4:1 or greater, about 4.5:1 or greater, about 5:1 or greater, about 5.5:1 or greater, about 6:1 or greater, about 6.5:1 or greater, about 7:1 or greater, about 7.5:1 or greater, about 8:1 or greater, about 8.5:1 or greater, about 9:1 or greater, about 9.5:1 or greater, about 10:1 or greater, or greater. In other further embodiments, the trench bottom width can be about 50 nm or less, about 45 nm or less, about 40 nm or less, about 35 nm or less, about 30 nm or less, about 25 nm or less, about 20 nm or less, about 15 nm or less, about 10 nm or less, or less.

[0043]

[0050] In further embodiments, structure 505 may also include one or more trenches 510 having a top surface 512 and a bottom surface 514. In contrast to trenches 410 and 610 of structures 405 and 605, trenches 510 may be characterized by a lower aspect ratio and a wider trench bottom. In embodiments, trenches 510 may be characterized by an aspect ratio of about 1:1 or less, about 1:2 or less, about 1:5 or less, about 1:10 or less, about 1:20 or less, about 1:50 or less, about 1:80 or less, about 1:100 or less, or less. In further embodiments, trench 510 can have a trench bottom width of about 100 nm or more, about 110 nm or more, about 120 nm or more, about 130 nm or more, about 140 nm or more, about 150 nm or more, about 160 nm or more, about 170 nm or more, about 180 nm or more, about 190 nm or more, about 200 nm or more, or more.

[0044]

[0051] In further embodiments, semiconductor device structures such as structures 405, 505, and 605 may be combined on the same substrate. In these embodiments, a first portion of the semiconductor device structure may have similar spatial characteristics to structures 405 and 605, while a second portion of the device structure may have similar spatial characteristics to structure 505. In further embodiments, the first and second portions of the device structure may be located in separate regions on the substrate, while in further embodiments, the first and second portions of the device structure may be intermixed across a portion or the entire substrate.

[0045]

[0052] Method 300 may also include, in optional step 310, heating the provided substrate, such as substrates 402, 502, and 602, in the reaction chamber. In embodiments in which the substrate is heated, heating may occur from below the substrate. In further embodiments, heating of the substrate may occur by one or more heating elements of an electrostatic chuck (ESC) in contact with the substrate. In yet further embodiments, the substrate may be heated such that the bottom surface of the trench is characterized by a temperature of about 50° C. or higher, about 60° C. or higher, about 70° C. or higher, about 80° C. or higher, about 90° C. or higher, about 100° C. or higher, about 110° C. or higher, about 120° C. or higher, about 130° C. or higher, about 140° C. or higher, about 150° C. or higher, or higher. As discussed above, embodiments of the present technique can produce higher deposition rates on the top surface of the trench than on the bottom surface over a wide range of ESC and substrate temperatures.

[0046]

[0053] Method 300 may further include flowing a deposition gas into the reaction chamber in step 315. In embodiments, the deposition gas may include a carbon-containing gas. In a further embodiment, the carbon-containing gas may include a carbon-hydrogen-containing gas, such as methane. In another further embodiment, the deposition gas may also include one or more additional compounds having a molecular weight that balances mass transport and electron temperature effects to enhance the selectivity of depositing a thicker carbon-containing layer on the top surface of the trench compared to the bottom surface. Embodiments of the deposition gas may include one or more additional gases having an atomic or molecular mass of about 30 g / mol or less. In a further embodiment, the additional gas may have an atomic or molecular mass of about 5 g / mol or greater. In another further embodiment, the additional gas may include a nitrogen-containing gas. In another further embodiment, the nitrogen-containing gas may be molecular nitrogen (N).

[0047]

[0054] In embodiments, the deposition gas may include a carbon-containing gas and an additional gas (e.g., a carrier gas). In further embodiments, the carbon-containing gas may be supplied to a plasma excitation region of a substrate-containing reaction chamber at a flow rate of about 50 standard cubic centimeters per minute (sccm) or less, about 40 sccm or less, about 30 sccm or less, about 20 sccm or less, about 10 sccm or less, or less. In further embodiments, the additional gas may be supplied to a plasma excitation region of a substrate-containing reaction chamber at a flow rate of about 200 sccm or more, about 250 sccm or more, about 300 sccm or more, about 350 sccm or more, about 400 sccm or more, about 450 sccm or more, about 500 sccm or more, or more. In further embodiments, the deposition gas may be characterized by a flow ratio of the carbon-containing gas to one or more additional gases of about 1:5 or less, about 1:10 or less, about 1:15 or less, about 1:20 or less, or less.

[0048]

[0055] In further embodiments, the additional gas has an atomic or molecular mass that is not large enough to increase the transport rate of the carbon-containing gas to the bottom of the trench. It has been found that compounds with a molecular mass equal to or less than approximately diatomic nitrogen (N2) have significantly lower transport rates of carbon-containing compounds in the deposition gas than heavier compounds. In embodiments, the deposition gas may be free of these heavier compounds, such as argon, which are commonly used as carrier gases in the deposition of carbon-containing layers and can increase deposition along the base of the trench by increasing delivery through the trench. It has also been found that compounds significantly lighter than the molecular mass of diatomic nitrogen (N2) can substantially increase the electron temperature of the deposition plasma formed from the deposition gas, thereby increasing the surface temperature of the substrate. In embodiments, the deposition gas may be free of these lighter compounds, such as helium and / or molecular hydrogen (H2), which are commonly used as carrier and reactive gases in the deposition of carbon-containing layers.

[0049]

[0056] The method 300 further includes generating a deposition plasma from the deposition gas in step 320. In embodiments, the deposition plasma may be generated by supplying power to the deposition gas from an RF power source. In further embodiments, the RF power source may be a capacitively coupled plasma power source or an inductively coupled plasma power source. In further embodiments, the RF power source may supply RF power to the deposition gas and deposition plasma characterized by a power of about 500 Watts or less, about 450 Watts or less, about 400 Watts or less, about 350 Watts or less, about 300 Watts or less, about 250 Watts or less, about 200 Watts or less, or less. In yet other embodiments, during generation of the deposition plasma, the reaction chamber may be characterized by a deposition plasma pressure of about 10 mTorr or less, about 9 mTorr or less, about 8 mTorr or less, about 7 mTorr or less, about 6 mTorr or less, about 5 mTorr or less, about 4 mTorr or less, about 3 mTorr or less, about 2 mTorr or less, about 1 mTorr or less, or less.

[0050]

[0057] The power supplied to generate the deposition plasma and the plasma deposition temperature can affect the plasma temperature (i.e., electron temperature). As discussed above, the electron temperature of the deposition plasma has been found to affect the deposition rate selectivity of a carbon-containing layer between the top and bottom surfaces of a trench in a semiconductor device structure. In embodiments, the electron temperature of the deposition plasma can be characterized as about 5 eV or less, about 4.5 eV or less, about 4 eV or less, about 3.5 eV or less, about 3 eV or less, about 2.5 eV or less, about 2 eV or less, about 1.5 eV or less, about 1 eV or less, or less. By generating a low-temperature plasma in conjunction with the increased temperature at the bottom of the trench due to heating from below as described above, the present technique can create a temperature difference between the top and bottom surfaces of the trench due to heat transport effects, as described below. Thus, in some embodiments of the present technology, during deposition, the temperature of the top surface of the trench may be about 1° C. or more cooler than the temperature at the bottom of the trench, about 2° C. or more cooler than the temperature at the bottom of the trench, about 3° C. or more cooler than the temperature at the bottom of the trench, about 4° C. or more cooler than the temperature at the bottom of the trench, about 5° C. or more cooler than the temperature at the bottom of the trench, about 6° C. or more cooler than the temperature at the bottom of the trench, about 7° C. or more cooler than the temperature at the bottom of the trench, or more. This may further increase deposition at the top of the trench due to increased adhesion of carbon material due to the lower temperature.

[0051]

[0058] Method 300 further includes depositing a protective layer from the deposition plasma in step 325. In embodiments of the present technique, the protective layer may be carbon-containing layers 450, 550, and 650 selectively deposited on substrates 402, 502, and 602, respectively. In a further embodiment, the selective deposition deposits a thicker carbon-containing layer on the top surface of the trench than on the bottom surface of the trench in the substrate. In another further embodiment, the as-deposited carbon-containing layer may be characterized by a top thickness to bottom thickness ratio of about 3:1 or greater, about 3.25:1 or greater, about 3.5:1 or greater, about 3.75:1 or greater, about 4:1 or greater, about 4.25:1 or greater, about 4.5:1 or greater, about 4.75:1 or greater, about 5:1 or greater, or greater.

[0052]

[0059] In embodiments, the as-deposited carbon-containing layer may have a top thickness of about 5 nm or more, about 6 nm or more, about 7 nm or more, about 8 nm or more, about 9 nm or more, about 10 nm or more, or more. In other further embodiments, the as-deposited carbon-containing layer may have a bottom thickness of about 2 nm or less, about 1.9 nm or less, about 1.8 nm or less, about 1.7 nm or less, about 1.6 nm or less, about 1.5 nm or less, about 1.4 nm or less, about 1.3 nm or less, about 1.2 nm or less, about 1.1 nm or less, about 1 nm or less, or less. In embodiments, the as-deposited carbon layer may also be formed on the sidewalls of the trench. In further embodiments, the as-deposited carbon layer may have a sidewall thickness that is thinner than the top thickness. In other further embodiments, the as-deposited carbon layer may have a sidewall thickness that is the same as or thicker than the bottom thickness. In further embodiments, the carbon-containing layer can be deposited in about 60 seconds or less, about 50 seconds or less, about 40 seconds or less, about 30 seconds or less, about 20 seconds or less, about 10 seconds or less, about 5 seconds or less, or less.

[0053]

[0060] In further embodiments, the difference in deposition rate of the carbon-containing layer between the top and bottom surfaces of the trenches may vary depending on the aspect ratio of each trench. Trenches with higher aspect ratios may have a larger difference in deposition rate of the carbon-containing layer than trenches with lower aspect ratios under the same deposition conditions. This may be due, at least in part, to the difference in thermal conductivity between trenches with narrow and wide bottom widths. Trenches with narrow bottom widths may have a lower thermal conductivity of the bottom material due to a shorter mean free path of phonon conduction in the material. In contrast, trenches with wide bottom widths may have a higher thermal conductivity of the bottom material due to a longer mean free path of phonon conduction in the material. In embodiments, the wider the trench bottom, the higher the thermal conductivity of the bottom material, which may result in a higher temperature at the bottom and a lower deposition rate of the carbon-containing layer at the bottom of the trench compared to the top surface of the trench. In embodiments, narrower trenches with aspect ratios of about 2:1 or greater may have a higher top-to-bottom thickness ratio than wider trenches with aspect ratios of about 1:1 or less. In further embodiments, the difference in thickness ratio between the narrower and wider trenches can be about 1% or more, about 2.5% or more, about 5% or more, about 7.5% or more, about 10% or more, about 15% or more, about 20% or more, about 25% or more, about 30% or more, about 40% or more, about 50% or more, or more. As discussed above, embodiments of the present technology can produce higher deposition rates on the top surface of a trench than on the bottom surface over a wide range of trench widths.

[0054]

[0061] In further embodiments, the carbon-containing layer can include solid carbon. In another further embodiment, the solid carbon can include a carbon polymer. In another further embodiment, the carbon-containing layer can have silicon, oxygen, and carbon in amounts of about 5% by weight or less, about 4% by weight or less, about 3% by weight or less, about 2% by weight or less, about 1% by weight or less, about 0.5% by weight or less, about 0.1% by weight or less, or less.

[0055]

[0062] In embodiments, a substrate including a carbon-containing layer of the present invention formed with different top and bottom thicknesses over a trench in a substrate can be used in a variety of processes to form openings at the bottom of the trench. In further embodiments, these processes can include high aspect ratio deposition, via formation, and electrical contact formation, among other processes.

[0056]

[0063] In an embodiment described in method 300, the method includes etching an opening in the bottom surface of the trench of the semiconductor device structure in step 330. In an embodiment, the opening can be etched with a dry etching process, such as reactive ion etching (RIE). In a further embodiment, the etching step 330 can be performed in the same reaction chamber without breaking vacuum by evacuating the carbon-containing deposition gas and supplying an etching gas to the chamber. In another further embodiment, an etching plasma can be formed from the etching gas, and ionized etchants can be anisotropically accelerated toward the substrate by applying a bias voltage between the etching plasma and the substrate. In an embodiment, the etching gas can include a fluorine-containing gas, such as CF3H, and a carrier gas, such as nitrogen (N2). In a further embodiment, the reaction chamber can be characterized by a pressure of about 1 mTorr or greater, about 2 mTorr or greater, about 3 mTorr or greater, about 4 mTorr or greater, about 5 mTorr or greater, or greater during the etching step. In a further embodiment, the etching plasma can be formed by supplying power to the etching gas from a plasma power source, such as an RF power source. In embodiments, the power supplied may be characterized as about 300 W or more, about 400 W or more, about 500 W or more, about 600 W or more, about 700 W or more, about 800 W or more, or more. In further embodiments, the bias voltage between the etching plasma and the substrate may be characterized as about 150 VDC or more, about 160 VDC or more, about 170 VDC or more, about 180 VDC or more, about 190 VDC or more, about 200 VDC or more, or more. In yet further embodiments, the bias power may be characterized as about 50 W or more, about 60 W or more, about 70 W or more, about 80 W or more, about 90 W or more, about 100 W or more, or more.

[0057]

[0064] In embodiments, the ionized etchant may impinge on and react with the carbon-containing layer on both the top and bottom surfaces of the trench. In further embodiments, the ionized etchant removes a portion of the carbon-containing layer on the bottom surface of the trench, forming a portion of an opening at the bottom surface. In another further embodiment, the ionized etchant also reduces the thickness of the portion of the carbon-containing layer formed on the top surface of the trench, but does not break through to the top surface layer. In another further embodiment, the ionized etchant also reduces the thickness of the top surface portion of the carbon-containing layer by about 90% or less, about 80% or less, about 70% or less, about 60% or less, about 50% or less, about 40% or less, or less.

[0058]

[0065] Method 300 may include, in optional step 335, forming conductive contacts in the etched openings. In embodiments, conductive contacts, such as low-resistance ohmic contacts, may be formed by depositing a conductive material in the etched openings. In further embodiments, deposition techniques may include sputtering, physical vapor deposition, and chemical vapor deposition, among other deposition techniques. In another further embodiment, the conductive material may be one or more metals, such as aluminum, silicon, tungsten, copper, and titanium, among other metals.

[0059]

[0066] Method 300 may optionally include removing the protective layer in step 340. In an embodiment, this may include removing carbon-containing layer 650 from structure 605, as shown by the absence of carbon-containing layer 650 in FIG. 6C. In a further embodiment, the protective layer is a carbon-containing layer that may be removed by exposing the layer to an oxidizing gas or plasma that reacts with the carbon to form gaseous carbon monoxide and / or carbon dioxide, which are exhausted from the reaction chamber. In a further embodiment, the carbon layer may be removed by oxygen plasma or a plasma formed from nitrogen (N) gas and hydrogen (H) gas. In another further embodiment, the carbon layer may be removed in the same reaction chamber used for the deposition and etching steps, or the carbon layer may be removed in a separate chamber configured to remove the carbon polymer layer.

[0060]

[0067] Embodiments of the present technology, such as method 300, include processes for fabricating semiconductor device structures with reduced damage to upper regions of the device structures caused by etching processes. These processes include selectively depositing a protective layer, such as a carbon-containing layer, on trenches in the device structures. This selective deposition results in a thicker layer of the protective layer on the top surface of the trench compared to the bottom surface where contact openings may be etched. Thus, embodiments of the present technology provide manufacturing methods that reduce damage to semiconductor device structures as device features shrink in size and structures become more densely packed on semiconductor substrates.

[0061]

[0068] In the foregoing specification, for purposes of explanation, numerous details have been set forth in order to provide an understanding of various embodiments of the present technology. However, it will be apparent to one skilled in the art that particular embodiments may be practiced without some of these details or with additional details.

[0062]

[0069] Although several embodiments have been disclosed, those skilled in the art will recognize that various modifications, alternative structures, and equivalents may be used without departing from the spirit of the embodiments. Moreover, in order to avoid unnecessarily obscuring the present technology, some well-known processes and elements have not been described. Therefore, the above specification should not be construed as limiting the scope of the present technology.

[0063]

[0070] Where a range of values ​​is provided, it is understood that each intervening value, to the smallest fraction of the unit of the lower limit, between the upper and lower limit of that range is also specifically disclosed, unless the context clearly dictates otherwise. Any narrower range between any stated value or unstated intervening value in a stated range and any other stated or intervening value in that stated range is also included. The upper and lower limits of these smaller ranges may independently be included or excluded, and each range where either or both limits are included in the smaller ranges is also included within the technology, subject to any specifically excluded limits in the stated range. Where a stated range includes one or both of the limits, ranges excluding either or both of those included limits are also included.

[0064]

[0071] As used in this specification and the appended claims, the singular forms "a," "an," and "the" include plural references unless the context clearly dictates otherwise. Thus, for example, reference to "a layer" includes a plurality of such layers; reference to "the protrusion" includes a reference to one or more protrusions and equivalents thereof known to those skilled in the art, and so forth.

[0065]

[0072] Additionally, as used in this specification and the claims that follow, the terms "comprise," "comprising," "contain," "containing," "include," and "including" specify the presence of stated features, integers, components, or steps, but do not exclude the presence or addition of one or more other features, integers, components, steps, operations, or groups.

Claims

1. 1. A semiconductor processing method comprising: providing a substrate to a reaction chamber, the substrate including a substrate trench having a top surface and a bottom surface; flowing a deposition gas into a plasma excitation region of the reaction chamber, the deposition gas comprising a carbon-containing gas and a nitrogen-containing gas; generating a deposition plasma from the deposition gas, the deposition plasma having an electron temperature of about 4 eV or less; depositing a carbon-containing layer on top and bottom surfaces of the substrate trench, the as-deposited carbon-containing layer having a top-to-bottom thickness ratio of about 3:1 or greater; A method comprising:

2. The semiconductor processing method of claim 1 , wherein the deposition gas is argon and helium-free.

3. 10. The semiconductor processing method of claim 1, further comprising heating the substrate to a temperature of about 100[deg.] C. or greater prior to depositing the carbon-containing layer.

4. 10. The semiconductor processing method of claim 1, further comprising etching through at least a portion of the carbon-containing layer on a bottom surface of the substrate trench, the carbon-containing layer still covering a top surface of the substrate trench.

5. 5. The semiconductor processing method of claim 4, further comprising removing the carbon-containing layer from the substrate after etching at least a portion of the carbon-containing layer on the bottom surface of the substrate trench.

6. 2. The semiconductor processing method of claim 1, wherein said carbon-containing gas comprises methane and said nitrogen-containing gas comprises molecular nitrogen.

7. 10. The semiconductor processing method of claim 1, wherein said deposition plasma is generated by supplying RF power to said deposition gas, said RF power being characterized by a power of about 300 watts or less.

8. 10. The semiconductor processing method of claim 1, wherein the deposition plasma is characterized by a pressure of about 10 mTorr or less.

9. 1. A semiconductor processing method comprising: providing a substrate to a reaction chamber, the substrate including a first trench having a first aspect ratio of about 2:1 or greater and a second trench having a second aspect ratio of about 1:2 or less, the first trench and the second trench each having a top surface and a bottom surface; heating the substrate to a temperature of about 100° C. or greater; flowing a deposition gas into a plasma excitation region of the reaction chamber, the deposition gas comprising a carbon-containing gas and a nitrogen-containing gas; generating a deposition plasma from the deposition gas; depositing a carbon-containing layer on the heated substrate, wherein the as-deposited carbon-containing layer has a top-to-bottom thickness ratio of about 3:1 or greater in both the first trench and the second trench; A method comprising:

10. etching through at least a portion of the carbon-containing layer at a bottom surface of a first substrate trench and a second substrate trench, the carbon-containing layer still covering a top surface of the first substrate trench and the second substrate trench; removing the carbon-containing layer from the substrate after etching at least a portion of the carbon-containing layer on the bottom surfaces of the first substrate trench and the second substrate trench; 10. The semiconductor processing method of claim 9, further comprising:

11. 10. The semiconductor processing method of claim 9, wherein the deposition plasma is characterized by an electron temperature of about 4 eV or less.

12. 10. The semiconductor processing method of claim 9, wherein the first substrate trench is characterized by a first bottom width of about 50 nm or less, and the second substrate trench is characterized by a second bottom width of about 100 nm or more.

13. 10. The semiconductor processing method of claim 9, wherein the carbon-containing layer is characterized by a top thickness of about 5 nm or more and a bottom thickness of about 1.6 nm or less.

14. 10. The semiconductor processing method of claim 9, wherein the carbon-containing layer comprises solid carbon.

15. 1. A semiconductor structure comprising: a first trench and a second trench formed in at least one semiconductor material, the first trench and the second trench having a top surface and a bottom surface, the first trench characterized by a first aspect ratio of about 2:1 or greater and the second trench characterized by a second aspect ratio of about 1:2 or less; a dielectric layer in contact with the at least one semiconductor material, the dielectric layer forming a top surface and a bottom surface of the first trench and the second trench; a carbon-containing layer in contact with the dielectric layer at a top and bottom of the first trench and the second trench, the carbon-containing layer being characterized by a top-to-bottom thickness ratio of about 3:1 or greater in both the first trench and the second trench; A semiconductor structure comprising:

16. 16. The semiconductor structure of claim 15, wherein the dielectric layer comprises silicon nitride.

17. 16. The semiconductor structure of claim 15, wherein the carbon-containing layer comprises solid carbon.

18. 16. The semiconductor structure of claim 15, wherein the dielectric layer is characterized by a bottom thickness of about 5 nm or greater.

19. 16. The semiconductor structure of claim 15, wherein the carbon-containing layer is characterized by a top thickness of about 5 nm or more and a bottom thickness of about 1.6 nm or less.

20. 16. The semiconductor structure of claim 15, further comprising a contact region positioned below the carbon-containing layer and the dielectric layer at a bottom surface of the first trench.

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