Integrated circuit

Abstract

To enable the use of a Delta-Sigma modulation circuit for detecting two kinds of pen signals.SOLUTION: An integrated circuit for detecting pen signals including a first pen signal and a second pen signal includes: a Delta-Sigma modulation unit which includes a subtractor, an integrator, a quantizer, and a DAC; a processing unit for detecting levels of the first and second pen signals based on output values of the Delta-Sigma modulation unit; and a gain control unit which controls levels of feedback signals based on the levels of the first and second pen signals detected by the processing unit. The processing unit includes: a first orthogonal demodulation unit for generating an in-phase component and an orthogonal component of the first pen signal; and a second orthogonal demodulation unit for generating an in-phase component and an orthogonal component of the second pen signal. The processing unit detects the level of the first pen signal based on the components of the first pen signal and detects the level of the second pen signal based on the components of the second pen signal.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The present invention relates to integrated circuits, and more particularly to an integrated circuit for detecting pen signals transmitted by an active pen. [Background technology]

[0002] There is a known electrostatic capacitance detection device that detects passive pointers such as fingers or passive pens. This type of electrostatic capacitance detection device is composed of a sensor having multiple X electrodes and multiple Y electrodes, and an integrated circuit that sends detection signals to the multiple X electrodes and sequentially detects these detection signals at the multiple Y electrodes. The integrated circuit performs processing to derive the position of the passive pointer based on the detected strength of the detection signal at each Y electrode.

[0003] Detection of the detection signal in the integrated circuit is performed using an A / D conversion circuit. Patent Document 1 discloses an example in which a delta-sigma modulation circuit is used as this type of A / D conversion circuit. Use of a delta-sigma modulation circuit can reduce quantization noise generated in the A / D conversion circuit, thereby improving the detection accuracy of the detection signal.

[0004] Active pens are also known that transmit AC signals by applying AC voltage to a pen tip electrode. Patent Document 2 discloses an example of this type of active pen. Hereinafter, the AC signal transmitted by an active pen will be referred to as a "pen signal." [Prior art documents] [Patent documents]

[0005] [Patent Document 1] U.S. Patent Application Publication No. 2007-0046299 [Patent Document 2] International Publication No. 2015 / 111159 Summary of the Invention [Problem to be solved by the invention]

[0006] It is believed that if a delta-sigma modulation circuit could also be used to detect pen signals, the accuracy of pen signal detection could be improved. However, it has not been practical to detect pen signals using a delta-sigma modulation circuit in the past. The reasons for this are explained in detail below.

[0007] First, the delta-sigma modulation circuit includes a subtractor that subtracts a feedback signal from an input signal, an integrator that integrates the output signal of the subtractor, a comparator that quantizes the output signal of the integrator, and an amplifier that generates the feedback signal by amplifying a pulse signal represented by a series of output values ​​("+1" or "-1") from the comparator. The dynamic range of the pen signal input to the A / D conversion circuit is significantly larger than that of the detection signal of a passive pointer. This is because the level (amplitude) of the pen signal arriving at the sensor changes significantly as the distance between the pen tip electrode and the touch surface changes due to user operation.

[0008] With the delta-sigma modulation circuit configured as described above, the level of the feedback signal remains constant regardless of the level of the input pen signal. Therefore, when the pen tip electrode approaches the touch surface and the pen signal level increases beyond a certain level, the output signal of the subtractor stops oscillating. This causes the output value of the comparator to also stop oscillating, making it impossible to detect or demodulate the pen signal using the output value of the delta-sigma modulation circuit. To prevent this, the level of the feedback signal must track the level of the input signal. A previously considered configuration for this purpose was to configure the output-stage quantization circuit with a multi-bit configuration using a large number of comparators (e.g., 129).

[0009] However, a delta-sigma modulation circuit configured to include multiple comparators is large in size and expensive. Furthermore, an integrated circuit for pen signal detection typically requires an A / D conversion circuit for each electrode in the sensor, further increasing the size and cost of the delta-sigma modulation circuit. As a result, it has traditionally been difficult to use a delta-sigma modulation circuit for pen signal detection due to size and cost considerations.

[0010] SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide an integrated circuit that can use delta-sigma modulation circuitry to detect pen signals. [Means for solving the problem]

[0011] The integrated circuit according to the present invention is an integrated circuit that detects a pen signal transmitted from an active pen, and includes a delta-sigma modulation unit including a subtractor that subtracts a feedback signal from the pen signal input from a sensor, an integrator that integrates the output signal of the subtractor, a quantizer that quantizes the output signal of the integrator, and a DAC that generates the feedback signal based on the output value of the quantizer; a processing unit that detects the level of the pen signal based on the output value of the delta-sigma modulation unit; and a gain control unit that controls the level of the feedback signal based on the level of the pen signal detected by the processing unit. [Effects of the Invention]

[0012] According to the present invention, the level of the feedback signal can be made to follow the level of the pen signal without using a multi-bit quantizer, and therefore it becomes possible to use a delta-sigma modulation circuit to detect the pen signal. [Brief explanation of the drawings]

[0013] [Figure 1] 1 is a diagram showing a configuration of a position detection system 1 according to an embodiment of the present invention. [Figure 2]2 is a diagram showing an example of the configuration of a receiving circuit arranged in a receiving unit 41. FIG. [Figure 3] 10 is a diagram showing another example of the configuration of a receiving circuit arranged in the receiving unit 41. FIG. [Figure 4] 4 is a diagram showing in more detail the configuration of the receiving circuit according to the example shown in FIG. 3. FIG. [Figure 5] 10A and 10B are diagrams illustrating simulation results of a received signal Va and an output value Vo. [Figure 6] FIG. 10 is a diagram showing a receiving circuit included in a receiving unit 41 according to a modified example of the embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0014] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0015] Fig. 1 is a diagram showing the configuration of a position detection system 1 according to an embodiment of the present invention. As shown in the figure, the position detection system 1 is configured to include an active pen 2 and an electronic device 3, which is a position detection device that detects the active pen 2. Examples of the electronic device 3 include a tablet computer and a device equipped with a digitizer.

[0016] The electronic device 3 has a touch surface 3a, a sensor 30 arranged directly below the touch surface 3a, a sensor controller 31 connected to the sensor 30, and a host processor 32 that controls each part of the electronic device 3 including these.

[0017] The sensor 30 is a device having a structure in which a plurality of sensor electrodes 30x, 30y are arranged within the touch surface 3a. The plurality of sensor electrodes 30x each extend in the y direction parallel to the touch surface 3a and are arranged at equal intervals within the touch surface 3a in the x direction perpendicular to the y direction. The plurality of sensor electrodes 30y each extend in the x direction and are arranged at equal intervals within the y direction.

[0018] Here, the electronic device 3 may have a display (not shown) arranged overlapping the sensor 30, and in this case, the plurality of sensor electrodes 30x (or the plurality of sensor electrodes 30y) may also serve as a common electrode of the display (an electrode for supplying a ground potential to each pixel in common). When this dual use is performed, the electronic device 3 constitutes a so-called "in-cell type" position detection device. On the other hand, when this dual use is not performed, the electronic device 3 constitutes a so-called "on-cell type" or "out-cell type" position detection device. The present invention can be suitably applied to any of the electronic devices 3.

[0019] The sensor controller 31 is an integrated circuit that has the function of deriving the positions of the active pen 2 and the passive pointer within the touch surface 3a, deriving the tilt of the active pen 2, and receiving data from the active pen 2. The sensor controller 31 is configured to sequentially supply the derived positions and tilt, as well as the received data, to the host processor 32.

[0020] The sensor controller 31 is configured to perform bidirectional communication with the active pen 2 via capacitance CX generated between the active pen 2 and the sensor 30. As will be described in detail later, derivation of the position and tilt of the active pen 2 and reception of data from the active pen 2 are achieved through this bidirectional communication. In the following description, a signal transmitted from the sensor controller 31 to the active pen 2 through the bidirectional communication will be referred to as an uplink signal US, and a signal transmitted from the active pen 2 to the sensor controller 31 will be referred to as a downlink signal DS (pen signal). As will be described in detail later, the active pen 2 has two electrodes for transmitting the downlink signal DS. In the following description, the downlink signal DS transmitted from one of these electrodes, the pen tip electrode 21, will be referred to as a downlink signal DSa, and the downlink signal DS transmitted from the other electrode, the ring electrode 22, will be referred to as a downlink signal DSb, for distinction.

[0021] The sensor controller 31 is also configured to supply (transmit) a passive pointer detection signal to each of the plurality of sensor electrodes 30x and sequentially receive the signal at the plurality of sensor electrodes 30y. As will be described in detail later, the passive pointer position is derived through the passive pointer detection signal thus transmitted and received. The transmission and reception of the passive pointer detection signal and the transmission and reception of the above-mentioned uplink signal US and downlink signal DS are performed in a time-division manner.

[0022] The host processor 32 is a central processing unit of the electronic device 3, and is configured to be able to execute various programs including a drawing application. The drawing application is a program that causes the host processor 32 to execute a process of generating digital ink based on the position, tilt, and data supplied from the sensor controller 31, and a process of storing the generated digital ink in a memory within the electronic device 3 and displaying it on a display.

[0023] 1, the sensor controller 31 includes a switching unit 40, a receiving unit 41, a transmitting unit 42, and a processing unit 43. The switching unit 40 is a functional unit that switches the connection destination of each of the plurality of sensor electrodes 30x, 30y between the transmitting unit 42 and the receiving unit 41 under the control of the processing unit 43.

[0024] The receiver 41 is a functional unit that detects and demodulates the received signal Va supplied from each of the plurality of sensor electrodes 30x, 30y connected via the switching unit 40, and is configured with a receiver circuit for each of the sensor electrodes 30x, 30y. The received signal Va may include one or more of the above-mentioned downlink signal DSa, downlink signal DSb, and passive pointer detection signal. The carrier signals of the downlink signal DSa, downlink signal DSb, and passive pointer detection signal each have different frequencies, and each receiver circuit is configured to separately detect the downlink signal DSa, downlink signal DSb, and passive pointer detection signal by detecting each frequency.

[0025] The transmitter 42 is a functional unit that supplies an uplink signal US or a passive pointer detection signal to the sensor electrode 30x or the sensor electrode 30y connected via the switching unit 40 under the control of the processing unit 43. Normally, when transmitting an uplink signal US, multiple sensor electrodes 30x (or multiple sensor electrodes 30y) are simultaneously connected to the transmitter 42, and as a result, the same uplink signal US is simultaneously transmitted from each sensor electrode 30x (or each sensor electrode 30y). In addition, the passive pointer detection signal is composed of a bit string with different content for each sensor electrode 30x, and is supplied in parallel to each sensor electrode 30x.

[0026] The processing unit 43 is a functional unit that derives the position and tilt of the active pen 2, receives data from the active pen 2, and derives the position of the passive pointer through the control of the switching unit 40, the receiving unit 41, and the transmitting unit 42. The processing performed by the processing unit 43 will be described in detail below.

[0027] First, the processing related to the active pen 2 will be described. First, the processing unit 43 causes the transmitting unit 42 to transmit an uplink signal US at a fixed interval. The uplink signal US is a signal that notifies the active pen 2 of the timing to transmit a downlink signal DS and the timing to receive the next uplink signal US, and also serves to supply commands to the active pen 2. The active pen 2 generates a downlink signal DS in accordance with the command supplied by the uplink signal US, transmits it at the timing notified by the uplink signal US, and receives the next uplink signal US at the timing notified by the uplink signal US.

[0028] The downlink signal DSa is a signal including a first position signal, which is an unmodulated carrier signal, and a data signal, which is a carrier signal modulated with data. The modulation method used to generate the data signal is typically DQPSK (Differential Quadrature Phase-Shift Keying), but other modulation methods such as QAM (Quadrature Amplitude Modulation) may also be used. The downlink signal DSb is a signal including a second position signal, which is an unmodulated carrier signal. The processing unit 43 derives the position of the active pen 2 based on the distribution of the level (reception intensity) of the first position signal at each of the sensor electrodes 30x and 30y. The processing unit 43 also acquires data transmitted by the active pen 2 by controlling the switching unit 40 and the receiving unit 41 to receive the data signal at one or more sensor electrodes 30x and 30y closest to the derived position. The processing unit 43 further derives the position of the ring electrode 22 based on the distribution of the reception strength of the second position signal at each sensor electrode 30x, 30y, and derives the tilt of the active pen 2 based on the difference between the derived position of the ring electrode 22 and the position of the active pen 2 derived based on the first position signal.

[0029] Next, the processing related to the passive pointer will be described. The processing unit 43 is configured to repeat this control for each sensor electrode 30y, selecting one sensor electrode 30y and connecting it to the receiving unit 41, and then controlling the transmitting unit 42 to supply a bit string prepared in advance for each sensor electrode 30x, one bit at a time, in parallel to each sensor electrode 30x. Under the control of the processing unit 43, the transmitting unit 42 generates each bit by phase-modulating a predetermined carrier signal and supplies it to each sensor electrode 30x.

[0030] The receiving unit 41 is configured to acquire the level of the signal supplied from the selected sensor electrode 30y for each bit and supply it to the processing unit 43 each time. The level of the signal supplied to the processing unit 43 in this manner reflects changes in capacitance formed at the intersections between the selected sensor electrode 30y and each sensor electrode 30x. The processing unit 43 then derives the position of the passive pointer based on the level of the signal supplied from the receiving unit 41.

[0031] Next, the active pen 2 is an active electrostatic stylus that communicates bidirectionally with the sensor controller 31, and as shown in Figure 1, is composed of a core body 20, a pen tip electrode 21, a ring electrode 22, a pressure sensor 23, a battery 24, an integrated circuit 25, and a stop filter 26.

[0032] The core body 20 is a member that constitutes the pen shaft of the active pen 2. The tip of the core body 20 constitutes the pen tip of the active pen 2, and the end abuts against the pressure sensor 23. The pen tip electrode 21 and the ring electrode 22 are conductors provided at different positions, with the pen tip electrode 21 being located at the pen tip of the active pen 2 and the ring electrode 22 being located closer to the center of the active pen 2 than the pen tip electrode 21 so as to surround the core body 20.

[0033] The pressure sensor 23 is a sensor that detects the pressure applied to the tip of the core body 20. The pressure detected by the pressure sensor 23 is supplied to the integrated circuit 25 as a writing pressure value, and is placed in the data signal of the downlink signal DSa by the integrated circuit 25. The battery 24 serves to supply the power necessary for the integrated circuit 25 to operate.

[0034] The integrated circuit 25 is an integrated circuit configured by various circuits including a boost circuit, a transmitting circuit, a receiving circuit, and a processing circuit. The transmitting circuit is connected to the pen tip electrode 21 and the ring electrode 22, and plays a role of transmitting the downlink signal DS by applying a change to the pen tip electrode 21 or the ring electrode 22 using the boost circuit.

[0035] The receiving circuit is connected to the ring electrode 22 and serves to receive the uplink signal US by detecting the uplink signal US using the ring electrode 22. The processing circuit generates a downlink signal DS based on the uplink signal US received by the receiving circuit and causes the generated downlink signal DS to be transmitted to the transmitting circuit.

[0036] The stop filter 26 is a filter circuit inserted between the ring electrode 22 and the integrated circuit 25 to enable simultaneous detection of the uplink signal US using the ring electrode 22 and transmission of the downlink signal DSa from the pen tip electrode 21. Specifically, the stop filter 26 may be configured using a band-stop filter (notch filter) that blocks a specific frequency band including the frequency of the downlink signal DSa, or a high-pass filter that passes the pulse waves that make up the uplink signal US while blocking the pulse waves that make up the downlink signal DSa. By using the stop filter 26, even if the active pen 2 fails to receive the uplink signal US and loses the timing to transmit the downlink signal DS, it becomes possible to continue detecting the uplink signal US while also transmitting the downlink signal DSa, thereby enabling input by the active pen 2 to continue.

[0037] 2 is a diagram showing an example of the configuration of a receiving circuit disposed within the receiving unit 41. As shown in the diagram, the receiving circuit within the receiving unit 41 is configured to include a delta-sigma (ΔΣ) modulation unit 50, a processing unit 60, and a gain control unit 70. Of these, the delta-sigma modulation unit 50 is configured to include a subtractor 51, an amplifier 52, an integrator 53, a quantizer 54, and a DAC (Digital-Analog Converter) 55. Note that while FIG. 2 shows an example in which the delta-sigma modulation unit 50 is configured as a single stage having only one integrator 53, the delta-sigma modulation unit 50 may also be configured as a multi-stage configuration having multiple integrators 53, as exemplified in FIG. 4 described later.

[0038] The subtractor 51 is a device that subtracts a feedback signal FB, which is an output signal of the DAC 55, from a reception signal Va input from the corresponding sensor electrode 30x or sensor electrode 30y. The amplifier 52 serves to control the level of the output signal of the subtractor 51. The integrator 53 is a device that integrates the output signal of the subtractor 51 input via the amplifier 52.

[0039] The quantizer 54 is a device that quantizes the output signal of the integrator 53, and is configured with a single comparator that outputs "1" or "-1" based on threshold value judgment of the output signal of the integrator 53. Therefore, the delta-sigma modulation unit 50 is configured to perform 1-bit delta-sigma modulation. The output value of the quantizer 54 is supplied to the processing unit 60 as the output value Vo of the delta-sigma modulation unit 50.

[0040] The DAC 55 is a device that generates a feedback signal FB based on the output value of the quantizer 54. Specifically, the feedback signal FB is generated by amplifying a pulse signal that indicates a series of output values ​​of the quantizer 54 by a given amplification factor (gain). The specific value of the given amplification factor is set in the DAC 55 by the gain control unit 70.

[0041] The processing unit 60 is a functional unit that restores the received signal Va based on the series of output values ​​Vo output from the delta-sigma modulation unit 50 and generates an in-phase component IOUT, a quadrature component QOUT, a level LEVEL (amplitude), and a phase PHASE of the received signal Va by performing quadrature detection. If the received signal Va is a data signal, the processing unit 60 also performs processing to generate a symbol sequence SYMBOL by demodulating the received signal Va based on the generated phase PHASE (and, if necessary, the level LEVEL). The in-phase component IOUT, quadrature component QOUT, level LEVEL, phase PHASE, and symbol sequence SYMBOL generated by the processing unit 60 are supplied to the processing unit 43 shown in FIG. 1. The processing unit 43 derives the position and tilt of the active pen 2 and the position of the passive pointer based on the level LEVEL supplied in this manner, and also acquires data transmitted by the active pen 2 based on the symbol sequence SYMBOL.

[0042] The gain control unit 70 is a functional unit that controls the level of the feedback signal FB based on the level Level of the received signal Va generated by the processing unit 60. This level Level will be described in detail later, but it is generated based on the signal before noise is removed and may differ from the above level LEVEL. The gain control unit 70 in the example of FIG. 2 controls the level of the feedback signal FB by controlling the amplification factor of the pulse signal in the DAC 55 based on the level Level.

[0043] According to the above configuration, the level of the feedback signal FB can be made to follow the level of the received signal Va without using a multi-bit quantizer. Therefore, it becomes possible to use the delta-sigma modulation unit 50 to detect the downlink signal DS (pen signal) which has a wide dynamic range.

[0044] 3 is a diagram showing another example of the configuration of a receiving circuit arranged in the receiving unit 41. This example differs from the example of FIG. 2 in that a gain adjustment unit 56 is provided at the output stage of the quantizer 54, and a gain control unit 70 controls the gain of this gain adjustment unit 56. Even in this case, the level of the feedback signal FB can be made to follow the level of the received signal Va without using a quantizer with a multi-bit configuration, so it is possible to obtain the same effect as the example shown in FIG. 2.

[0045] Fig. 4 is a diagram showing in more detail the configuration of the receiving circuit according to the example shown in Fig. 3. However, Fig. 4 shows an example in which the delta-sigma modulation section 50 has a two-stage configuration. The configuration and operation of the receiving circuit will be described in more detail below with reference to Fig. 4.

[0046] As shown in FIG. 4, the delta-sigma modulation unit 50 is configured to include subtractors 51a and 51b, amplifiers 52a and 52b, integrators 53a and 53b, a quantizer 54, and DACs 55a and 55b, which are configured using analog circuits, and a gain adjustment unit 56, which is configured using a digital circuit.

[0047] The subtractor 51a subtracts a feedback signal FBa, which is the output signal of the DAC 55a, from the received signal Va and supplies the result to an amplifier 52a. The amplifier 52a controls the level of the output signal of the subtractor 51a and supplies it to an integrator 53a. The integrator 53a integrates the output signal of the subtractor 51a input via the amplifier 52a and supplies it to a subtractor 51b. The subtractor 51b subtracts a feedback signal FBb, which is the output signal of the DAC 55b, from the output signal of the integrator 53a and supplies it to an amplifier 52b. The amplifier 52b controls the level of the output signal of the subtractor 51b and supplies it to an integrator 53b. The integrator 53b integrates the output signal of the subtractor 51b input via the amplifier 52b and supplies it to a quantizer 54.

[0048] The quantizer 54 is a comparator having a non-inverting input terminal to which the output signal of the integrator 53b is supplied and an inverting input terminal to which ground potential is supplied, and is configured to output "+1" when the potential of the non-inverting input terminal is greater than the potential of the inverting input terminal, and "-1" otherwise.

[0049] The gain adjustment unit 56 generates an output value Vo by multiplying the output value of the quantizer 54 by a given multiplication value (gain), and supplies the output value Vo to the processing unit 60 and the DACs 55 a and 55 b. The specific value of the given multiplication value is set in the gain adjustment unit 56 by the gain control unit 70.

[0050] The DACs 55a and 55b generate the feedback signals FBa and FBb by amplifying the pulse signal representing the series of output values ​​Vo by a predetermined amplification factor. The specific value of the predetermined amplification factor may be the same for the DACs 55a and 55b or may be different, and is set in advance for each of them.

[0051] The processing unit 60 includes a low-pass filter 61 , quadrature demodulation units 62 a and 62 b , a noise detector 63 , a noise filter 64 , an accumulator 65 , a demodulator 66 , and a computing unit 67 .

[0052] The low-pass filter 61 is a decimation filter that counts (adds) the output value Vo at regular intervals to obtain and output an arithmetic average. The output signal of the low-pass filter 61 is a digital signal that restores the received signal Va.

[0053] The quadrature demodulator 62a is a functional unit that performs quadrature detection of the output signal of the low-pass filter 61 using a predetermined frequency Fa. The quadrature demodulator 62b is a functional unit that performs quadrature detection of the output signal of the low-pass filter 61 using a predetermined frequency Fb, which is different from the frequency Fa. While two quadrature demodulators 62a and 62b are illustrated in FIG. 4, the actual number of quadrature demodulators arranged in the processing unit 60 is determined by the number of frequencies used. In a typical example, three quadrature demodulators are required to perform detection at the respective carrier signal frequencies of the downlink signal DSa, the downlink signal DSb, and the passive pointer detection signal. If tilt detection of the active pen 2 is not required, the downlink signal DSb may not be used. In this case, two quadrature demodulators are required to perform detection of the downlink signal DSa and the passive pointer detection signal. Furthermore, the downlink signal DSa may be transmitted from each of multiple active pens 2 using frequency division multiplexing. In this case, a quadrature demodulator is required for each carrier signal frequency of the downlink signal DSa. In the following, the explanation will be continued on the assumption that two quadrature demodulation units 62a and 62b are used as shown in FIG.

[0054] Specifically, the quadrature detection performed by the quadrature demodulators 62a and 62b is a process of calculating the convolution sum (inner product) of the output signal of the low-pass filter 61 with a sine wave and a cosine wave of a corresponding frequency. The quadrature demodulators 62a and 62b are configured to output to the noise filter 64 an in-phase component IOUT, which is the convolution sum with the cosine wave, and a quadrature component QOUT, which is the convolution sum with the sine wave.

[0055] The noise detector 63 is a functional unit that detects impulse noise (for example, liquid crystal noise generated from a display) included in the output value Vo and supplies the detected impulse noise to the noise filter 64. The noise filter 64 performs processing to remove the impulse noise supplied from the noise detector 63 from the signals (in-phase component IOUT and quadrature component QOUT) supplied from the quadrature demodulation units 62a and 62b.

[0056] The accumulator 65 is a functional unit that calculates a matching degree vector based on the signal (in-phase component IOUT and quadrature component QOUT) after the impulse noise has been removed by the noise filter 64, and further calculates a moving average of the length and slope of the matching degree vector using a window of a predetermined time length, and sequentially outputs the obtained average value of the length as the level (amplitude) and the average value of the slope as the phase PHASE to the processing unit 43 shown in FIG. 1. The accumulator 65 is also configured to output the signal (in-phase component IOUT and quadrature component QOUT) itself supplied from the noise filter 64 to the processing unit 43. Note that in FIG. 4, the in-phase component IOUT, quadrature component QOUT, level LEVEL, and phase PHASE corresponding to the quadrature demodulation unit 62a are each suffixed with "a," and the in-phase component IOUT, quadrature component QOUT, level LEVEL, and phase PHASE corresponding to the quadrature demodulation unit 62b are each suffixed with "b."

[0057] The demodulator 66 is a functional unit that acquires data transmitted by the active pen 2 by demodulating the output value Vo based on the data acquired by the accumulator 65. For example, if the data signal included in the downlink signal DSa is generated by DQPSK modulation, the demodulator 66 is configured to acquire the data transmitted by the active pen 2 based on the phase PHASE acquired by the accumulator 65. Also, for example, if the data signal included in the downlink signal DSa is generated by QAM, the demodulator 66 is configured to acquire the data transmitted by the active pen 2 based on the level LEVEL and phase PHASE acquired by the accumulator 65. The demodulator 66 generates a symbol sequence SYMBOL indicating the acquired data and outputs it to the processing unit 43. In FIG. 4, the symbol sequence SYMBOL corresponding to the quadrature demodulation unit 62a is suffixed with "a," and the symbol sequence SYMBOL corresponding to the quadrature demodulation unit 62b is suffixed with "b."

[0058] The calculator 67 is a functional unit that derives a level (amplitude) for each frequency of the received signal Va using the results of quadrature detection by the quadrature demodulators 62a and 62b, and performs statistical processing on the derived levels. The levels may be derived by performing processing similar to that of the accumulator 65, based on the output signals (in-phase component IOUT and quadrature component QOUT) of the quadrature demodulators 62a and 62b. The statistical processing may be a smoothing process that smoothes the derived levels, or a prediction process that predicts future levels based on levels derived up to that point. The calculator 67 is configured to supply the levels for each frequency obtained by the statistical processing to the gain control unit 70. Note that in FIG. 4, the level corresponding to the quadrature demodulator 62a (frequency Fa) is suffixed with "_a," and the level corresponding to the quadrature demodulator 62b (frequency Fb) is suffixed with "_b."

[0059] The gain control section 70 includes an adder 71, a low-pass filter 72, and a control section 73. The adder 71 is a level determination section that determines the value of the level used to control the levels of the feedback signals FBa and FBb based on a plurality of levels supplied from the calculator 67. Specifically, the value of the level used to control the levels of the feedback signals FBa and FBb may be determined by performing a summation process that adds together a plurality of levels, or a selection process that selects one (for example, the largest one) from the plurality of levels.

[0060] The low-pass filter 72 is a functional unit that generates a control amount LVinfo for the gain adjustment unit 56 based on the level Level determined by the adder 71. As a specific example, the low-pass filter 72 may be configured by a decimation filter that counts (adds) the level Level output from the adder 71 at regular intervals to obtain and output an arithmetic average. The control unit 73 controls the gain (multiplication value) of the gain adjustment unit 56 in accordance with the control amount LVinfo generated by the low-pass filter 72.

[0061] Here, the level LEVEL obtained by the accumulator 65 is not used as the level supplied from the processing unit 60 to the gain control unit 70 because it is preferable to control the gain of the gain adjustment unit 56 based on the level of the signal including noise. As described above, by controlling the gain of the gain adjustment unit 56 using the level Level obtained based on the signal before noise removal, it becomes possible to make the level of the feedback signal follow the level of the received signal Va actually input to the delta-sigma modulation unit 50 (the received signal Va in a state including noise).

[0062] FIG. 5 shows simulation results of the received signal Va and the output value Vo. FIG. 5(a) shows simulation results of a comparative example in which control by the gain control unit 70 is not performed, and FIGS. 5(b) and 5(c) show simulation results of an embodiment in which control by the gain control unit 70 is performed. In this simulation, the delta-sigma modulation unit 50 has a single stage configuration, and the received signal Va is a sine wave with a predetermined period. In addition, in FIGS. 5(a) and 5(b), the level (amplitude) of the received signal Va is increased every two periods, while in FIG. 5(c), the level (amplitude) of the received signal Va is decreased every two periods. Furthermore, each figure plots the received signal Va, the output value Vo, and the output signal ΔV of the subtractor 51.

[0063] 5(a), if control by the gain control unit 70 is not performed, when the level of the received signal Va increases as the active pen 2 approaches the touch surface 3a, the output signal ΔV of the subtractor 51 stops oscillating, and as a result, the output value Vo also stops oscillating. This makes it impossible to restore the received signal Va from the output value Vo, and the quadrature detection by the processing unit 60 stops functioning.

[0064] As shown in FIG. 5(b), if control is performed by the gain control unit 70, even if the level of the received signal Va increases as the active pen 2 approaches the touch surface 3a, the output signal ΔV of the subtractor 51 is maintained in an oscillating state, and as a result, the output value Vo is also maintained in an oscillating state. This allows the quadrature detection by the processing unit 60 to function normally. Note that there is a certain time lag before the level of the received signal Va is detected by the processing unit 60, so as shown in FIG. 5(b), after the level of the received signal Va increases, the output value Vo stops oscillating for a certain period of time. However, this time lag has only a minor effect on the demodulation by the demodulation unit 66 and the detection of position and tilt by the processing unit 43.

[0065] 5(c), when the level of the received signal Va decreases as the active pen 2 moves away from the touch surface 3a, the gain of the gain adjustment unit 56 can be reduced by the control performed by the gain control unit 70. Even in this case, the oscillation state of the output signal ΔV and the output value Vo is maintained. From this result, it can be seen that the control performed by the gain control unit 70 can maintain a state in which the processing unit 60 can perform quadrature detection normally, even if the level of the received signal Va fluctuates in various ways.

[0066] Although the preferred embodiments of the present invention have been described above, the present invention is not limited to these embodiments, and it goes without saying that the present invention can be embodied in various forms without departing from the spirit of the present invention.

[0067] 6 is a diagram showing a receiving circuit included in receiving unit 41 according to a modification of the present embodiment. As can be seen by comparing this figure with FIG. 4, this modification differs from the present embodiment in that delta-sigma modulation unit 50 includes comparators 57a and 57b, gain adjustment units 58a and 58b, and an adder 59.

[0068] The comparators 57a and 57b are not quantizers but are comparators that detect whether the absolute value of the level of the output signal of the integrator 53b exceeds a predetermined value. In one example, the comparator 57a is configured to output "1" when the level of the output signal of the integrator 53b exceeds a predetermined value Vref (Vref>0) and to output "0" otherwise, and the comparator 57b is configured to output "1" when the level of the output signal of the integrator 53b falls below the predetermined value -Vref and to output "0" otherwise.

[0069] The gain adjustment units 58a and 58b are functional units that multiply the output values ​​of the comparators 57a and 57b by a predetermined value, respectively. In one example, the predetermined value that the gain adjustment unit 58a multiplies by is 64, and the predetermined value that the gain adjustment unit 58a multiplies by is −64.

[0070] Adder 59 is a functional unit that controls the levels of feedback signals FBa and FBb by adding the output values ​​of gain adjustment units 58a and 58b to the output value of gain adjustment unit 56. The output values ​​of gain adjustment units 58a and 58b become non-zero only when the absolute value of the level of the output signal of integrator 53b exceeds a predetermined value, and therefore adder 59 controls the levels of feedback signals FBa and FBb when comparators 57a and 57b detect that the absolute value of the level of the output signal of integrator 53b exceeds the predetermined value.

[0071] According to this modification, when the level of the received signal Va increases beyond the adjustment range of the gain control unit 70 and, as a result, the absolute value of the output signal of the integrator 53b becomes too large, the levels of the feedback signals FBa and FBb can be controlled to reduce the absolute value of the output signal of the integrator 53b. Therefore, even if the level of the received signal Va increases beyond the adjustment range of the gain control unit 70, it becomes possible to use the delta-sigma modulation unit 50 to detect the downlink signal DS (pen signal).

[0072] In addition, in the above embodiment, the active pen 2 and the sensor controller 31 communicate bidirectionally, but the present invention can also be suitably applied to a case where the active pen 2 and the sensor controller 31 communicate one-way from the active pen 2 to the sensor controller 31.

[0073] Furthermore, in the above embodiment, an example has been described in which the quantizer 54 is configured with one comparator, but the present invention is also applicable to the case in which a quantizer with a multi-bit configuration including a plurality of comparators is used. [Explanation of symbols]

[0074] 1. Position detection system 2 Active Pen 3 Electronic equipment 3a Touch Surface 20 core body 21 Pen tip electrode 22 Ring electrode 23 Pressure Sensor 24 Battery 25 Integrated Circuits 26 Stop Filter 30 sensors 30x, 30y sensor electrodes 31 Sensor Controller 32 host processor 40 Switching section 41 Receiving unit 42 Transmitter 43 Processing section 50 Delta Sigma Modulation Section 51, 51a, 51b Subtractor 52, 52a, 52b amplifiers 53,53a,53b Integrator 54 Quantizer 55, 55a, 55b DAC 56 Gain adjustment section 57a, 57b Comparator 58a, 58b Gain adjustment section 59 Adder 60 Processing section 61 Low-pass filter 62a, 62b Quadrature demodulation section 63 Noise Detector 64 Noise Filter 65 Accumulator 66 Demodulator 67 Arithmetic unit 70 Gain control section 71 Adder 72 Low-pass filter 73 Control Unit DS, DSa, DSb downlink signals FB, FBa, FBb feedback signals Fa,Fb frequency IOUT,IOUTa,IOUTb Common mode component LEVEL, LEVELLa, LEVELb level Level,Level_a,Level_b Level LVinfo control amount PHASE, PHASEa, PHASEb phase QOUT quadrature component SYMBOL symbol string US uplink signal Va received signal Vo output value

Claims

1. An integrated circuit for detecting pen signals including a first pen signal and a second pen signal transmitted from two electrodes disposed in an active pen, a subtractor for subtracting a feedback signal from the pen signal input from the sensor; an integrator for integrating the output signal of the subtractor; a quantizer for quantizing the output signal of the integrator; and a delta-sigma modulation unit including a DAC that generates the feedback signal based on an output value of the quantizer; a processing unit that detects the levels of the first pen signal and the second pen signal based on the output value of the delta-sigma modulation unit; a gain control unit that controls a level of the feedback signal based on the levels of the first pen signal and the second pen signal detected by the processing unit, The processing unit a low-pass filter that restores the pen signal based on an output value of the delta-sigma modulation unit; and a first quadrature demodulation unit that generates an in-phase component and a quadrature component of the first pen signal by performing quadrature detection on the pen signal restored by the low-pass filter; a low-pass filter that restores the pen signal based on an output value of the delta-sigma modulation unit; and a second quadrature demodulation unit that generates an in-phase component and a quadrature component of the second pen signal by performing quadrature detection on the pen signal restored by the low-pass filter, the processing unit detects a level of the first pen signal based on an in-phase component and a quadrature component of the first pen signal generated by the first quadrature demodulation unit, detects a level of the second pen signal based on an in-phase component and a quadrature component of the second pen signal generated by the second quadrature demodulation unit, and supplies the detected levels of the first pen signal and the second pen signal to the gain control unit. Integrated circuit.

2. An integrated circuit for detecting pen signals including a first pen signal and a second pen signal transmitted from different active pens, a subtractor for subtracting a feedback signal from the pen signal input from the sensor; an integrator for integrating the output signal of the subtractor; a quantizer for quantizing the output signal of the integrator; and a delta-sigma modulation unit including a DAC that generates the feedback signal based on an output value of the quantizer; a processing unit that detects the levels of the first pen signal and the second pen signal based on the output value of the delta-sigma modulation unit; a gain control unit that controls a level of the feedback signal based on the levels of the first pen signal and the second pen signal detected by the processing unit, The processing unit a low-pass filter that restores the pen signal based on an output value of the delta-sigma modulation unit; and a first quadrature demodulation unit that generates an in-phase component and a quadrature component of the first pen signal by performing quadrature detection on the pen signal restored by the low-pass filter; a low-pass filter that restores the pen signal based on an output value of the delta-sigma modulation unit; and a second quadrature demodulation unit that generates an in-phase component and a quadrature component of the second pen signal by performing quadrature detection on the pen signal restored by the low-pass filter, the processing unit detects a level of the first pen signal based on an in-phase component and a quadrature component of the first pen signal generated by the first quadrature demodulation unit, detects a level of the second pen signal based on an in-phase component and a quadrature component of the second pen signal generated by the second quadrature demodulation unit, and supplies the detected levels of the first pen signal and the second pen signal to the gain control unit. Integrated circuit.

3. the gain control unit includes a level determination unit that determines a level of the pen signal used to control a level of the feedback signal based on the levels of the first pen signal and the second pen signal supplied from the processing unit.

3. An integrated circuit according to claim 1 or 2.

4. the level determination unit determines the level of the pen signal used to control the level of the feedback signal by a summation process of summing the levels of the first pen signal and the second pen signal supplied from the processing unit, or a selection process of selecting one of the levels of the first pen signal and the second pen signal supplied from the processing unit.

3. An integrated circuit according to claim 1 or 2.

5. the first quadrature demodulation unit performs quadrature detection at a frequency of a carrier signal of the first pen signal; the second quadrature demodulation unit performs quadrature detection at a frequency of a carrier signal of the second pen signal; 5. An integrated circuit according to any one of claims 1 to 4.

6. the processing unit further includes a noise filter that removes noise from the output signals of the first quadrature demodulation unit and the second quadrature demodulation unit, the processing unit detects the first level based on an in-phase component and a quadrature component of the first pen signal before passing through the noise filter, detects the second level based on an in-phase component and a quadrature component of the second pen signal before passing through the noise filter, and supplies the detected levels of the first pen signal and the second pen signal to the gain control unit.

6. An integrated circuit according to any one of claims 1 to 5.

7. The delta-sigma modulation unit a comparator that detects whether the absolute value of the level of the output signal of the integrator exceeds a predetermined value; an adder that controls the level of the feedback signal when the comparator detects that the absolute value of the level of the output signal of the integrator exceeds a predetermined value.

7. An integrated circuit according to any one of claims 1 to 6.

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