Semiconductor device and method for manufacturing semiconductor device

Abstract

To provide a semiconductor device in which a boundary member is provided between an auxiliary element and a main surface of a semiconductor substrate, thereby reducing the step of a protective film that covers the auxiliary element.SOLUTION: There is provided a semiconductor device that includes a semiconductor substrate having a first main surface with a first region, a second region, and a third region located between the first and second regions in a planar view, a transistor formed in the first region, an auxiliary element formed in the second region, a boundary member formed in the third region, and a protective film covering the auxiliary element and the boundary member. A height from the first main surface to a top surface of the boundary member is lower than a height from the first main surface to a top surface of the auxiliary element.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing the semiconductor device. [Background technology]

[0002] Patent Document 1 discloses an IGBT (Insulated Gate Bipolar Transistor) and a semiconductor device in which a built-in element is formed. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2022-82244 Summary of the Invention [Problem to be solved by the invention]

[0004] In Patent Document 1, forming a protective film made of PSG (Phosphorus Silicate Glass) on the built-in element results in a large step between the auxiliary element and the main surface of the semiconductor substrate. If an electrode is formed there, a metal film remains at the edge of the step, which can cause a short circuit when forming the upper wiring. Therefore, it was necessary to apply SOG (Spin On Glass) to the protective film to smooth the step. Therefore, the objective of this disclosure is to provide a semiconductor device that provides a boundary member between the auxiliary element and the main surface of the semiconductor substrate, thereby reducing the step in the protective film that covers the auxiliary element.

[0005] Other objects and novel features will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]

[0006] According to one embodiment, in the semiconductor device, the step of the protective film of the auxiliary element is reduced. [Effects of the Invention]

[0007] According to the embodiment, it is possible to eliminate residues of the metal film on the protective film without applying SOG to the protective film. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a schematic diagram showing a layout configuration of a semiconductor chip on which a related semiconductor device is mounted. [Figure 2] FIG. 1 is a cross-sectional view of a related semiconductor device. [Figure 3] 1A is a cross-sectional view of a related auxiliary element and a protective film covering it, and FIG. 1B is a cross-sectional view of the auxiliary element and a protective film covering it according to the embodiment. [Figure 4] 10A to 10C are cross-sectional views showing a related method for manufacturing an auxiliary element. [Figure 5] 5A to 5C are cross-sectional views showing a method for manufacturing an auxiliary element according to an embodiment. [Figure 6] (a) is a top view of the auxiliary element and the boundary member, and (b) and (c) are cross-sectional views showing the width limits of the boundary member. DETAILED DESCRIPTION OF THE INVENTION

[0009] Embodiment Hereinafter, embodiments of the present invention will be described with reference to the drawings. However, the invention according to the claims is not limited to the following embodiments. Furthermore, not all of the configurations described in the embodiments are necessarily essential means for solving the problems. For clarity of explanation, the following description and drawings have been omitted and simplified as appropriate. In each drawing, the same elements are given the same reference numerals, and duplicate explanations are omitted as necessary.

[0010] (Example of layout configuration of related semiconductor chips) A related semiconductor device including an IGBT will be described with reference to Figures 1 and 2. Figure 1 is a schematic diagram showing an example of the layout configuration of a semiconductor chip on which the related semiconductor device is mounted. Figure 2 is a cross-sectional view showing the related semiconductor device.

[0011] As shown in FIG. 1, the related semiconductor chip CHP has a rectangular planar shape. In plan view, the semiconductor chip CHP has a gate pad GP, a gate wiring W1, and an emitter pad EP. Furthermore, a collector electrode (not shown in FIGS. 1 and 2) covering the underside of the semiconductor substrate is formed on the lower surface (back surface) opposite to the upper surface of the semiconductor chip CHP. On the upper surface side of the semiconductor chip CHP, there is an annular peripheral region that surrounds the gate pad GP, the gate wiring W1, and the emitter pad EP in plan view and is formed along the outline of the semiconductor chip CHP. On the upper surface of the semiconductor substrate in the peripheral region, for example, a field limiting ring (FLR) that is a termination structure is formed. Furthermore, an annular wiring WR is formed on the semiconductor substrate in the peripheral region.

[0012] FIG. 2 shows, from left to right, regions 1A, 1B, and 1C. The cross section of region 1A shown in FIG. 2 is taken along line AA in FIG. 1, the cross section of region 1B is taken along line BB in FIG. 1, and the cross section of region 1C is taken along line CC in FIG. 1. Region 1A includes peripheral regions surrounding regions 1B and 1C in a plan view. FIG. 2 does not show the element region (cell region) that functions as an IGBT.

[0013] The semiconductor device includes an N-type semiconductor substrate SB and a P-type well PW formed from the upper surface of the semiconductor substrate SB to a predetermined depth in the semiconductor substrate SB. The P-type well PW is a semiconductor region formed across regions 1A, 1B, and 1C. The semiconductor substrate SB also includes an N-type semiconductor layer NL formed near the lower surface of the semiconductor substrate SB, spaced apart from the lower end of the P-type well PW, and having a higher impurity concentration than the semiconductor substrate SB, and a P-type semiconductor layer PL formed from the lower surface of the N-type semiconductor layer NL to the lower surface of the semiconductor substrate SB. That is, the semiconductor substrate SB includes, formed in this order from the lower surface side, a P-type semiconductor layer PL, an N-type semiconductor layer NL, a semiconductor substrate SB, and a P-type well PW. In region 1A, an insulating film IF1, which is a ring-shaped field oxide film, is formed on the semiconductor substrate SB, and the P-type well PW is not formed directly below the insulating film IF1.

[0014] The semiconductor substrate SB is made of single-crystal Si (silicon) doped with N-type impurities such as P (phosphorus). The N-type semiconductor layer NL is a semiconductor region formed by doping N-type impurities (e.g., P (phosphorus)) into the semiconductor substrate SB. The N-type semiconductor layer NL functions as a buffer layer for the IGBT. The P-type semiconductor layer PL and P-type well PW are semiconductor regions formed by doping P-type impurities (e.g., B (boron)) into the semiconductor substrate SB. The P-type semiconductor layer PL is a layer that injects holes into the semiconductor substrate SB.

[0015] In region 1C, a trench (groove) TR is formed in the upper surface of the semiconductor substrate SB, and a trench gate electrode TG is buried in the trench TR via an insulating film IF2. The depth of the trench TR is shallower than the P-type well PW, and the lower end of the trench TR does not reach the lower end of the P-type well PW. The trench gate electrode TG is composed of a polysilicon film buried in the trench TR via the insulating film IF2, which is a trench gate insulating film. P (phosphorus), for example, is doped into the polysilicon film constituting the trench gate electrode TG. Here, the polysilicon film and insulating film IF2 constituting the trench gate electrode TG are not formed on the semiconductor substrate SB in a region outside the trench TR, that is, in a region that does not overlap with the trench TR in a planar view.

[0016] In region 1B, for example, an internal resistor GR is formed on the upper surface of the semiconductor substrate SB via an insulating film IF4. The internal resistor is a gate resistor element. A temperature sensing diode or a gate protection diode may be formed instead of the internal resistor GR. The internal resistor GR is formed directly on the P-type well PW. In other words, the internal resistor GR overlaps the P-type well PW in plan view. The insulating film IF4 is composed of insulating films IF2 and IF3 stacked in this order on the semiconductor substrate SB. The insulating film IF2 is made of a thermal oxide film formed in the same process as the insulating film IF2 formed in the trench TR in region 1C. The insulating film IF3 is, for example, a TEOS film. Therefore, the film thickness of the insulating film IF4 is larger than the film thickness of the insulating film IF2 in the trench TR. In other words, the thickness of the insulating film between the internal resistor GR and the upper surface of the semiconductor substrate SB is larger than the thickness of the insulating film between the surface of the trench TR and the trench gate electrode TG. The film thickness of the insulating film IF4 is approximately 2 to 7 times, specifically, for example, approximately 5 times, the film thickness of the insulating film IF5 of the comparative example.

[0017] Because the trench gate insulating film is formed only from the insulating film IF2, the insulating film IF2 contacts both the surface of the semiconductor substrate SB (surface of the trench TR) and the surface of the trench gate electrode TG. Here, the insulating film IF2, which is the trench gate insulating film, is configured from a single layer of thermal oxide film, which prevents variations in the film thickness of the trench gate insulating film compared to when the trench gate insulating film has a stacked structure of a thermal oxide film and a TEOS film. This reduces variations in the threshold voltage Vth of the IGBT.

[0018] Furthermore, the film thickness of the insulating film IF4 is smaller than the film thickness of the insulating film IF1, which is a field oxide film (field insulating film). This is because if the insulating film IF4 is formed thicker than the field oxide film, its film thickness will be too large to allow accurate exposure in the photolithography process, and there is a risk that patterning will not be performed normally. The insulating film IF2 has a higher relative dielectric constant and a denser structure than the insulating film IF3.

[0019] The film thickness of the insulating film IF3 is larger than that of the insulating film IF4. The film thickness of the insulating film IF4 is, for example, 100 to 700 nm, and more preferably, for example, 200 to 400 nm. The film thickness of the insulating film IF2 is, for example, 70 nm or more, specifically, 100 nm. That is, the shortest distance between the surface of the trench TR and the trench gate electrode TG is 70 nm or more. The film thickness of the insulating film IF3 is, for example, about 450 nm. The film thickness of the insulating film IF1 is, for example, about 700 nm. The insulating film IF3 is not limited to a silicon oxide film, and may be composed of, for example, a silicon nitride film. The insulating film IF1 is, for example, a ring-shaped pattern composed of a silicon oxide film, and surrounds the element region, region 1B, region 1C, an emitter pad EP described later, a gate pad GP, and a gate wiring W1 in a plan view.

[0020] The built-in resistor GR is made of, for example, a polysilicon film and is made conductive by introducing, for example, As (arsenic). Here, the built-in resistor GR and the trench gate electrode TG are spaced apart from each other. The built-in resistor GR is a resistive element made of a resistor connected in series between the gate pad GP and the trench gate electrode TG.

[0021] An interlayer insulating film IL made of, for example, a silicon oxide film is formed on the semiconductor substrate SB so as to cover the trench gate electrodes TG, the insulating films IF1 to IF4, and the built-in resistors GR. The interlayer insulating film IL has connection holes formed at a plurality of locations, penetrating from the upper surface to the lower surface of the interlayer insulating film IL, and plugs PG embedded in the connection holes. The plugs PG are made of, for example, a TiN (titanium nitride) / Ti (titanium) film, which is a barrier metal film continuously covering the bottom and side surfaces of the connection holes, and a W (tungsten) film embedded in the connection holes via the barrier metal film. The plugs PG are connected to the upper surface of the P-type well PW in region 1A, both ends of the upper surface of the built-in resistors GR in region 1B, and the upper surface of the trench gate electrodes TG. Here, the width of the plugs PG in the direction along the upper surface of the semiconductor substrate SB is smaller than the width of the trench gate electrodes TG. Therefore, the bottom surfaces of the plugs PG connected to the trench gate electrodes TG are spaced apart from the upper surface of the semiconductor substrate SB.

[0022] A laminated metal film is formed on the interlayer insulating film IL and the plug PG. The metal film BM is a barrier metal film, and the metal film M1 is a main conductor film. The metal film BM is made of, for example, a TiW (titanium tungsten) film. The metal film M1 is made of, for example, an AlCu (aluminum copper) film. The metal film M1 may also be an AlSi film, which is an Al film with Si added. Among the plurality of laminated metal films, the one electrically connected to the P-type well PW via the plug PG in the region 1A constitutes an emitter pad (emitter electrode) EP. Among the plurality of laminated metal films, the one connected to the upper surface of one end of the internal resistor GR via the plug PG in the region 1B constitutes a gate pad GP. Among the plurality of laminated metal films, the one connected to the upper surface of the other end of the internal resistor GR via the plug PG in the region 1B constitutes a gate wiring W1. The gate wiring W1 is formed from the region 1B to the region 1C. The gate wiring W1 in the region 1C is electrically connected to the trench gate electrode TG via the plug PG. The gate pad GP and the gate wiring W1 are spaced apart from each other.

[0023] In this way, the gate pad GP and the trench gate electrode TG are electrically connected by a plurality of plugs PG connected in series therebetween, the built-in resistor GR, and the gate wiring W1. Specifically, the gate pad GP and the built-in resistor GR are electrically connected via the plugs PG, the built-in resistor GR and the gate wiring W1 are electrically connected via the plugs PG, and the gate wiring W1 and the trench gate electrode TG are electrically connected via the plugs PG.

[0024] The emitter pad EP in region 1A supplies an emitter potential to the emitter region of the IGBT. The gate pad GP in region 1B supplies a gate potential to the trench gate electrode TG via an internal resistor GR. The gate potential supplied to the trench gate electrode TG in region 1C in this manner is supplied to the trench gate electrode of the IGBT formed in the element region (not shown), thereby controlling the operation of the IGBT. The trench gate electrode TG and the P-type semiconductor layer (collector region) PL constitute the IGBT.

[0025] In a peripheral region surrounding the gate pad GP, the gate wiring W1, and the emitter pad EP in plan view, a wiring WR made of the laminated metal film and spaced apart from the emitter pad EP is formed.

[0026] (Explanation of auxiliary element and protective film according to the embodiment) Fig. 3(a) is a cross-sectional view of a related auxiliary element and a protective film covering it, and Fig. 3(b) is a cross-sectional view of the auxiliary element and the protective film covering it according to the embodiment. The auxiliary element and the protective film covering it according to the embodiment will be described with reference to Fig. 3.

[0027] As shown in FIG. 3(a), the related auxiliary element includes a stack of a first insulating film IF4 and a semiconductor layer GR. When a protective film IL is stacked on the related auxiliary element without using SOG (Spin-On-Glass), the thicknesses of the first insulating film IF4 and the semiconductor layer GR are so large that a step occurs between the auxiliary element and the semiconductor substrate SB. This step results in tungsten residue at the edge of the auxiliary element when the tungsten plug PG is formed. This tungsten residue can cause a short circuit when the upper metal film M1 is fabricated.

[0028] Therefore, as shown in FIG. 3(b), the auxiliary element according to the embodiment includes a stack of a first insulating film IF4 and a semiconductor layer GR, similar to the related auxiliary element. However, the auxiliary element according to the embodiment includes a boundary member including a second insulating film IF1 formed around the auxiliary element to reduce the step between the auxiliary element and the semiconductor substrate SB. The boundary member uses the second insulating film IF1 that was used for element isolation. The height from the first main surface of the semiconductor substrate SB to the upper surface of the boundary member is lower than the height from the first main surface to the upper surface of the auxiliary element. In other words, the thickness of the second insulating film IF1 is smaller than the thicknesses of the semiconductor layer GR and the first insulating film IF4. The height of the boundary member is adjusted to the height of the auxiliary element as its upper limit so as to reduce the step between the auxiliary element and the semiconductor substrate SB.

[0029] The protective film IL is made of PSG (Phosphorous Silicate Glass), but not SOG. This configuration provides a semiconductor device in which a boundary member is provided between the auxiliary element and the main surface of the semiconductor substrate, thereby reducing the step of the protective film covering the auxiliary element.

[0030] (Description of a Method for Manufacturing a Semiconductor Device According to an Embodiment) Fig. 4 is a cross-sectional view showing a method for manufacturing a related auxiliary element. Fig. 5 is a cross-sectional view showing a method for manufacturing an auxiliary element according to an embodiment. A method for manufacturing a semiconductor device according to an embodiment will be described with reference to Figs. 4 and 5.

[0031] 4, the related auxiliary element is formed by first forming a second insulating film IF1 for element isolation on a semiconductor substrate SB (a). Next, the second insulating film IF1 is removed (b), and a P-type impurity is introduced to form an impurity region PC (c).

[0032] Next, in the first region where the IGBT is formed, an oxide film TH is formed and a trench is created to embed the gate electrode (d). Next, the formed oxide film is removed, sacrificial oxidation is performed, PC is diffused to form a P-type well PW, and then a gate insulating film IF2 is formed (e). Next, polysilicon TG for the gate electrode is formed and removed (f).

[0033] Next, an insulating film IF3 is formed on the gate insulating film IF2 to reduce the electric field of the auxiliary element, and a semiconductor layer GR is then laminated (g). The gate insulating film IF2 and insulating film IF3 form a first insulating film IF4. The first insulating film IF4 and semiconductor layer GR are then patterned (h). A protective film IL, PSG, is laminated on the semiconductor layer GR (i). Finally, SOG is applied, completing the auxiliary element (j).

[0034] A method for fabricating an auxiliary element according to an embodiment will be described below, with the region where a transistor is formed being the first region, the region where an auxiliary element is formed being the second region, and the region where a boundary member is formed being the third region. As shown in FIG. 5, in the auxiliary element according to the embodiment, first, a second insulating film IF1 for element isolation is formed on a semiconductor substrate SB. Next, the second insulating film IF1 in the second region is removed, leaving the second insulating film IF1 in the third region (b). Next, a P-type impurity is introduced into the second region to form an impurity region PC (c).

[0035] Next, to embed a gate electrode in the first region, an oxide film TH is formed in the first, second, and third regions, and a trench is created in the first region ((d)). Next, the oxide film TH formed in the first, second, and third regions is removed, sacrificial oxidation is performed, PC is diffused, and a P-type well PW is formed. After that, a gate insulating film IF2, which is a third insulating film, is formed on the P-type well PW. Then, the third insulating film IF2 in the third region is removed ((e)).

[0036] Next, gate electrode polysilicon TG is formed in the first region, and the gate electrode polysilicon TG is removed in the second and third regions (f). At this time, in the third region, a semiconductor layer TG, which is a second semiconductor layer, is formed on the sidewall of the second insulating film IF1. Next, a fourth insulating film IF3 for alleviating the electric field of the auxiliary element is formed on the third insulating film in the second region and on the second insulating film in the third region, and a semiconductor layer GR, which is a first semiconductor layer, is stacked on the fourth insulating film IF3 (g). Here, the gate insulating film IF2 and the fourth insulating film IF3 are referred to as the first insulating film IF4.

[0037] Next, the fourth insulating film IF3 and the first semiconductor layer GR in the third region are removed (h). At this time, the fourth insulating film IF3 and the first semiconductor layer GR are formed on the sidewalls of the second insulating film IF1 in the third region. A protective film IL, PSG, is stacked on the semiconductor layer in the second region and the second insulating film in the third region, completing the auxiliary element (i).

[0038] As described above, the method for fabricating the related auxiliary element and the method for fabricating the auxiliary element according to the embodiment are constructed using the same constituent materials. Furthermore, the number of steps is not increased. That is, the auxiliary element according to the embodiment can be fabricated by simply leaving the second insulating film IF1 around the auxiliary element. Furthermore, the step of applying SOG can be eliminated, thereby reducing costs.

[0039] (Planar configuration of boundary member according to embodiment) Fig. 6(a) is a top view of the auxiliary element and the boundary member, and Fig. 6(b) and (c) are cross-sectional views showing the width limit of the boundary member. With reference to Fig. 6, the planar configuration of the boundary member according to the embodiment will be described.

[0040] As shown in Figure 6(a), the boundary member IF1 surrounds the semiconductor layer GR that constitutes the auxiliary element in a planar view. Referring to Figure 1 in conjunction with this, the first main surface of the semiconductor substrate SB that constitutes the semiconductor device includes a first region represented by EP and second and third regions represented by BB. In the semiconductor device, a transistor is formed in the first region, an auxiliary element is formed in the second region, and a boundary member is formed in the third region. The semiconductor device has the third region between the first and second regions, and the third region surrounds the periphery of the second region in a planar view.

[0041] Regarding the width limit of the boundary member, in FIG. 6(b), the P-type well PW is formed entirely below the second insulating film IF1, which is the boundary member. On the other hand, in FIG. 6(c), the P-type well PW is discontinued below the second insulating film IF1, which is the boundary member. The P-type well PW must be formed entirely below the second insulating film IF1, as shown in FIG. 6(b).

[0042] The P-type well PW extends about 5 μm from the implanted location due to diffusion. As shown in FIG. 5(c), the boundary member acts as a mask for the implantation. Therefore, the width of the boundary member is preferably 10 μm or less.

[0043] In Fig. 6(a), the corners of the boundary members are shown as right angles in plan view, but the corners of the boundary members may be rounded in plan view to make the step gentler.

[0044] For example, the semiconductor device according to the above embodiments may be configured such that the conductivity types (p-type or n-type) of the semiconductor substrate, semiconductor layer, diffusion layer (diffusion region), etc. are reversed. Therefore, when one of the n-type and p-type conductivity types is a first conductivity type and the other conductivity type is a second conductivity type, the first conductivity type can be p-type and the second conductivity type can be n-type, or conversely, the first conductivity type can be n-type and the second conductivity type can be p-type.

[0045] The explanation has been given with different names for the reference numerals. This is because the names differ depending on the region. Locations with the same reference numerals are manufactured in the same process.

[0046] The invention made by the inventor has been specifically described above based on the embodiments, but it goes without saying that the present invention is not limited to the embodiments already described, and various modifications are possible within the scope of the gist of the invention. [Explanation of symbols]

[0047] 1A region, 1B region, 1C region, IF1 second insulating film, IF1 boundary member, IF1 insulating film, IF2 gate insulating film, IF2 third insulating film, IF3 insulating film, IF3 fourth insulating film, IF4 first insulating film, IF4 insulating film, GR semiconductor layer, IL protective film, IL interlayer insulating film, PW P-type well, SB semiconductor substrate, TG gate electrode polysilicon, TG semiconductor layer, TG trench gate electrode

Claims

1. a semiconductor substrate having a first main surface having a first region, a second region, and a third region located between the first region and the second region in a plan view; a transistor formed in the first region; an auxiliary element formed in the second region; a boundary member formed in the third region; a protective film covering the auxiliary element and the boundary member; Equipped with A semiconductor device, wherein a height from the first main surface to an upper surface of the boundary member is lower than a height from the first main surface to an upper surface of the auxiliary element.

2. The semiconductor device according to claim 1 , wherein said third region surrounds said second region in a plan view.

3. 2. The semiconductor device according to claim 1, wherein the auxiliary element is a gate resistor element, a temperature sensing diode, or a gate protection diode.

4. 2. The semiconductor device according to claim 1, wherein said protective film is a PSG (Phosphorous Silicate Glass) film.

5. 2. The semiconductor device according to claim 1, wherein the transistor is an IGBT (Insulated Gate Bipolar Transistor).

6. The semiconductor device according to claim 1 , wherein the auxiliary element comprises a stack of a first insulating film and a semiconductor layer.

7. The semiconductor device according to claim 6 , wherein the boundary member comprises a second insulating film different from the first insulating film.

8. forming a second insulating film in a first region, a second region, and a third region located between the first region and the second region in a plan view, on a first main surface of a semiconductor substrate; removing the second insulating film on the second region; forming a third insulating film on the second region and the third region; removing the third insulating film on the third region; forming a fourth insulating film on the second region and the third region, and defining a stack of the third insulating film and the fourth insulating film on the second region as a first insulating film; forming a first semiconductor layer on the second region and the third region; removing the first semiconductor layer and the fourth insulating film on the third region; forming an auxiliary element including the first insulating film and the first semiconductor layer on the second region, and a boundary member including a second insulating film on the third region; The method for manufacturing a semiconductor device further comprises forming a protective film on the auxiliary element and the boundary member.

9. 9. The method for manufacturing a semiconductor device according to claim 8, wherein the fourth insulating film and the semiconductor layer are formed on a side wall of the second insulating film in the third region.

10. The semiconductor device according to claim 8 , wherein said third region surrounds said second region in a plan view.

11. 9. The semiconductor device according to claim 8, wherein the auxiliary element is a gate resistor element, a temperature sensing diode, or a gate protection diode.

12. 9. The semiconductor device according to claim 8, wherein said protective film is a PSG (Phosphorous Silicate Glass) film.

13. 9. The semiconductor device according to claim 8, wherein an IGBT (Insulated Gate Bipolar Transistor) is formed in the first region.

14. forming a second semiconductor layer on the third insulating film in the second region and the third region; removing the second semiconductor layer on the second region and the third region; The semiconductor device according to claim 8 , wherein the second semiconductor layer is formed on a side wall of the second insulating film in the third region.

15. The semiconductor device according to claim 13 , wherein the first semiconductor layer is used in the IGBT.

Images