Constant voltage generating circuit

Abstract

To enable an output voltage to be set to a low value which is close to a lower limit operating voltage of a load circuit.SOLUTION: A reference voltage generating circuit 40 generates and outputs a reference voltage Vref by supplying a constant current from a constant current source to a semiconductor element. An output voltage generating circuit 50 generates and outputs an output voltage Vout based on the generated reference voltage Vref. A malfunction detection circuit 20 generates and outputs an error detection signal 101 for indicating that the output voltage Vout has dropped below a lower limit voltage for operation of a load circuit 60 by employing a semiconductor element that has a similar low-voltage operating characteristic to a semiconductor element used in the load circuit 60. An output voltage correcting circuit 30 comprises a plurality of current adding circuits which, if the error detection signal 101 becomes active, then sequentially increments a current amount of the constant current from the reference voltage generating circuit 40 by adding a current to the same at different timings; and if the error detection signal 101 becomes inactive, then stops adding a voltage to the constant current.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to a constant voltage generating circuit that generates and outputs a constant voltage. [Background technology]

[0002] Electronic circuits such as LSIs use constant voltage generating circuits (regulators) that generate and supply a constant voltage as a power supply for a load circuit (see, for example, Patent Document 1). Such constant voltage generating circuits often use LDO (Low Drop Out) regulators that can operate even when the difference between input and output voltages is small. The use of LDO regulators allows operation when the voltage difference between the input and output voltages is small, thereby suppressing heat generation due to the voltage difference and reducing energy loss. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2005-174351 Summary of the Invention [Problem to be solved by the invention]

[0004] However, the output voltage from such a constant voltage generating circuit fluctuates depending on various environmental conditions such as temperature. If the output voltage falls below the lower limit of the load circuit's operating voltage, the load circuit may malfunction. Therefore, it is necessary to set the output voltage so that it does not fall below the lower limit of the load circuit's operating voltage even if the output voltage fluctuates due to environmental conditions, etc.

[0005] In recent years, demands for lower power consumption in semiconductor devices have been increasing. To achieve this, a sleep mode is often required, in which many circuits are shut down except when necessary, and only the minimum necessary circuits are operating. While the lower the voltage in sleep mode, the lower the current consumption, a problem occurs in that the load circuit becomes unstable and the device cannot return to normal operation mode. Therefore, some devices employ circuit configurations that predetermine a minimum operating voltage and, if the voltage monitoring circuit falls below this limit, reset the load circuit to stop operation. However, even with such a circuit configuration, fluctuations in the output voltage can cause the load circuit to stop operating. Therefore, to minimize load circuit shutdown, the output voltage must be set taking environmental conditions into consideration, and it is difficult to set the output voltage low enough to approach the load circuit's minimum operating voltage.

[0006] SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a constant voltage generating circuit that can set the voltage value of the output voltage low enough to approach the lower limit voltage of the operation of the load circuit. [Means for solving the problem]

[0007] In order to solve the above problems, the constant voltage generating circuit of the present invention includes: a reference voltage generating circuit that generates and outputs a reference voltage by causing a constant current from a constant current source to flow through a semiconductor element; an output voltage generating circuit that generates an output voltage based on the reference voltage generated by the reference voltage generating circuit; a malfunction detection circuit that uses a semiconductor element having low-voltage operating characteristics similar to those of a semiconductor element used in a load circuit that operates using the output voltage from the output voltage generation circuit, and generates and outputs an error detection signal that indicates that the output voltage has become equal to or lower than a lower limit operating voltage of the load circuit; and an output voltage correction circuit having a plurality of current addition circuits that, when an error detection signal from the malfunction detection circuit becomes active, sequentially increase the amount of the constant current at different timings by adding current to the constant current in the reference voltage generation circuit, and, when the error detection signal from the malfunction detection circuit becomes inactive, stop adding voltage to the constant current in the reference voltage generation circuit. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 10 is a diagram illustrating a circuit configuration of a constant voltage generating circuit as a comparative example. [Figure 2] 1 is a diagram showing a circuit configuration of a constant voltage generating circuit according to an embodiment of the present invention; [Figure 3] 3 is a diagram showing a circuit configuration of a malfunction detection circuit 20 shown in FIG. 2. FIG. [Figure 4] 4 is a diagram showing operational waveforms of the malfunction detection circuit 20 shown in FIG. 3. FIG. [Figure 5] 3 is a diagram for explaining detailed circuit configurations of the output voltage correction circuit 30 and the reference voltage generation circuit 40 shown in FIG. 2. FIG. [Figure 6] 6 is a diagram showing operational waveforms of the output voltage correction circuit 30 shown in FIG. 5. DETAILED DESCRIPTION OF THE INVENTION

[0009] Next, an embodiment of the present invention will be described in detail with reference to the drawings.

[0010] Before describing the constant voltage generating circuit of this embodiment, a comparative example will be described in which a constant voltage generating circuit having a circuit configuration that resets a load circuit and puts it into a non-operating state when the output voltage falls below the lower limit voltage for the load circuit.

[0011] FIG. 1 is a diagram showing the circuit configuration of a constant voltage generating circuit as a comparative example.

[0012] 1, the constant voltage generating circuit of this comparative example is configured to include an output voltage generating circuit 110, an output voltage monitoring circuit 120, and a capacitor 131, and supplies the generated output voltage Vout to a load circuit 130. The load circuit 130 is a circuit that operates using the output voltage Vout generated by the output voltage generating circuit 110.

[0013] The output voltage generating circuit 110 is composed of a reference voltage generating circuit 111, an operational amplifier 112, a PMOS transistor 113, and resistor elements R1 and R2.

[0014] The reference voltage generating circuit 111 has a circuit configuration of a general LDO configuration, generates a reference voltage Vref using a BGR (bandgap reference) voltage that is independent of the power supply voltage, temperature, and process, and outputs it to the operational amplifier 112.

[0015] In the operational amplifier 112, the divided voltage value of the resistance elements R1 and R2 is input as a feedback voltage Vfb, and the voltage value obtained by performing differential amplification between the reference voltage Vref and the feedback voltage Vfb is output to the gate of the PMOS transistor 113, thereby generating an output voltage Vout. The output voltage Vout can be adjusted by changing the resistance values ​​of the resistance elements R1 and R2, which are negative feedback resistors.

[0016] The output voltage Vout generated in the output voltage generating circuit 110 is held in a capacitor 131 and then supplied to a load circuit 130 and also input to an output voltage monitoring circuit 120 .

[0017] The output voltage monitoring circuit 120 has a comparator 121, and outputs a reset signal 122 to the load circuit 130 when the output voltage Vout falls below the voltage V1.

[0018] 1, the accuracy of the output voltage Vout is improved by using a reference voltage Vref based on a highly accurate BGR voltage or the like, and the voltage value of the output voltage Vout is set as low as possible, close to the lower limit operating voltage of the load circuit 130. However, in this constant voltage generation circuit, to handle a case where the output voltage Vout drops due to environmental conditions or the like, the output voltage monitor circuit 120 monitors the voltage value of the output voltage Vout, and if the voltage falls below a reference voltage V1, the comparator 121 outputs a reset signal 122 to stop the operation of the load circuit 130.

[0019] Therefore, if the output voltage Vout drops due to environmental conditions or the like, the operation of the load circuit 130 will be stopped, and there was a problem that it was difficult to set the voltage value of the output voltage Vout low enough to approach the lower limit operating voltage of the load circuit 130.

[0020] Next, the circuit configuration of a constant voltage generating circuit according to one embodiment of the present invention is shown in FIG.

[0021] 2, the constant voltage generating circuit of this embodiment is composed of a malfunction detection circuit 20, an output voltage correction circuit 30, a reference voltage generating circuit 40, an output voltage generating circuit 50, and a capacitor 91, and is configured to supply the generated output voltage Vout to a load circuit 60. The load circuit 60 is a circuit that operates using the output voltage Vout generated by the output voltage generating circuit 50.

[0022] The output voltage generation circuit 50 in the constant voltage generation circuit of this embodiment is also a circuit with an LDO configuration similar to the output voltage generation circuit 110 in the comparative example shown in FIG. 1. Specifically, the output voltage generation circuit 50 is composed of an operational amplifier 81, a source-grounded PMOS transistor 82, and resistor elements R1 and R2. The operational amplifier 81 receives the divided voltage value of the resistor elements R1 and R2 as a feedback voltage Vfb, and performs differential amplification between the reference voltage Vref from the reference voltage generation circuit 40 and the feedback voltage Vfb, outputting the resulting voltage value to the gate of the PMOS transistor 82 to generate the output voltage Vout. The output voltage Vout can be adjusted by changing the resistance values ​​of the resistor elements R1 and R2, which serve as negative feedback resistors.

[0023] The voltage value of the output voltage Vout is calculated using the following formula. Vout=Vref×(R1+R2) / R1

[0024] The malfunction detection circuit 20 in this embodiment is a circuit that, when the output voltage Vout drops due to some cause such as environmental conditions and reaches a lower limit voltage at which the load circuit 60 malfunctions, generates and outputs an error detection signal 101 indicating that the output voltage Vout has fallen below the lower limit voltage of the load circuit 60. Specifically, the malfunction detection circuit 20 uses a semiconductor element having low-voltage operating characteristics similar to those of the semiconductor element used in the load circuit 60, which operates using the output voltage Vout from the output voltage generation circuit 50, to generate and output the error detection signal 101 indicating that the output voltage Vout has fallen below the lower limit voltage of the load circuit 60.

[0025] The reference voltage generating circuit 40 generates and outputs a reference voltage Vref by supplying a constant current from a constant current source to a semiconductor element. The output voltage generating circuit 50 generates and outputs a voltage based on the reference voltage Vref generated by the reference voltage generating circuit 40 as an output voltage Vout.

[0026] The output voltage correction circuit 30 has a plurality of current addition circuits that, when the error detection signal 101 from the malfunction detection circuit 20 becomes active, add a current to the constant current in the reference voltage generation circuit 40 to sequentially increase the amount of the constant current at different timings, and, when the error detection signal 101 from the malfunction detection circuit 20 becomes inactive, stop adding a voltage to the constant current in the reference voltage generation circuit 40. The detailed circuit configurations of the output voltage correction circuit 30 and the reference voltage generation circuit 40 will be described later.

[0027] Next, the circuit configuration of the malfunction detection circuit 20 shown in FIG. 2 is shown in FIG.

[0028] As shown in FIG. 3, the malfunction detection circuit 20 is made up of a clock generation circuit 21 and an inverter circuit made up of a PMOS transistor (P-channel MOSFET) 22 and an NMOS transistor (N-channel MOSFET) 23.

[0029] The clock generation circuit 21 generates a clock signal CLK using the output voltage Vout generated in the output voltage generation circuit 50 as a power source. The inverter circuit is composed of a PMOS transistor 22 and an NMOS transistor 23 connected in series between the output voltage Vout and ground, and inverts the logic of the clock signal CLK generated by the clock generation circuit 21 and outputs it as an error detection signal 101.

[0030] Here, the PMOS transistor 22 and the NMOS transistor 23 are semiconductor elements having the same low-voltage operating characteristics as the semiconductor elements used in the load circuit 60, and the inverter circuit also has the same low-voltage operating characteristics as the load circuit 60. In other words, when the output voltage Vout falls below the lower limit operating voltage of the load circuit 60, the inverter circuit formed by the PMOS transistor 22 and the NMOS transistor 23 also becomes inoperable. Therefore, the error detection signal 101 output from the inverter circuit is fixed to a low level (hereinafter abbreviated as L level). Note that when the output voltage Vout is a voltage value greater than the lower limit operating voltage of the load circuit 60, a clock signal obtained by inverting the logic of the clock signal CLK from the clock generation circuit 21 is output to the output voltage correction circuit 30 as the error detection signal 101.

[0031] FIG. 4 shows the operating waveforms of the malfunction detection circuit 20 shown in FIG.

[0032] Referring to Figure 4, it can be seen that when the output voltage Vout gradually decreases and falls below the lower limit voltage level of the load circuit 60 at time T1, the error detection signal 101 is fixed at L level, and when the output voltage Vout gradually increases and exceeds the lower limit voltage level of the load circuit 60 at time T2, the error detection signal 101, which was fixed at L level, becomes a signal that is logically determined to be the clock signal CLK.

[0033] Next, the detailed circuit configurations of the output voltage correction circuit 30 and the reference voltage generation circuit 40 shown in FIG. 2 will be described with reference to FIG.

[0034] The output voltage correction circuit 30, the reference voltage generation circuit 40, and the output voltage generation circuit 50 are configured to be able to operate at a voltage lower than the lower limit operating voltage of the load circuit 60. For example, this can be realized by configuring the output voltage correction circuit 30, the reference voltage generation circuit 40, and the output voltage generation circuit 50 using MOS transistors whose threshold voltage is lower than the threshold voltage of the MOS transistors that make up the load circuit 60.

[0035] The reference voltage generating circuit 40 is configured with a constant current source 71 and two NMOS transistors 72 and 73. The reference voltage generating circuit 40 has a simple circuit configuration in which the reference voltage Vref is generated by flowing the constant current Iref of the constant current source 71 into the two diode-connected NMOS transistors 72 and 73.

[0036] The output voltage correction circuit 30 is composed of NMOS transistors 31, 41, 51, constant current sources 32, 42, 52, capacitors C1 to C3, buffer circuits 33, 43, 53, RS flip-flop circuits (hereinafter abbreviated as RSFF circuits) 34, 44, 54, inverter circuits 35, 45, constant current sources 61 to 63, and switch circuits SW1 to SW3.

[0037] The output voltage correction circuit 30 is configured such that, when the error detection signal 101 from the malfunction detection circuit 20 is fixed at the L level, multiple current addition circuits sequentially add additional currents to the constant current Iref of the constant current source 71 in the reference voltage generation circuit 40 at different timings.

[0038] For example, a constant current source 32, a capacitor C1, an NMOS transistor 31, a buffer circuit 33, an RSFF circuit 34, a constant current source 61, a switch circuit SW1, and an inverter circuit 35 constitute one current adding circuit.

[0039] The capacitor C1 is a capacitor element having one end connected to ground and storing a constant current from the constant current source 32 to increase the voltage it holds.

[0040] In addition, the NMOS transistor 31 has a gate to which the error detection signal 101 from the malfunction detection circuit 20 is input, a source connected to ground, and a drain connected to the other end of the capacitor C1, and when the error detection signal 101 is at a high level (hereinafter abbreviated as H level), it operates to discharge the voltage of the capacitor C1 to ground.

[0041] In addition, the buffer circuit 33, the RSFF circuit 34, and the switch circuit SW1 function as a switching circuit that switches the constant current Iref in the reference voltage generating circuit 40 to add the constant current I1 from the constant current source 61 when the voltage held in the capacitor C1 becomes equal to or higher than a preset threshold.

[0042] Furthermore, one current adder circuit is configured by the constant current source 42, capacitor C2, NMOS transistor 41, buffer circuit 43, RSFF circuit 44, constant current source 62, switch circuit SW2, and inverter circuit 45. Furthermore, one current adder circuit is configured by the constant current source 52, capacitor C3, NMOS transistor 51, buffer circuit 53, RSFF circuit 54, constant current source 63, and switch circuit SW3.

[0043] Next, the operation of the output voltage correction circuit 30 will be described.

[0044] In the output voltage correction circuit 30 , the error detection signal 101 from the malfunction detection circuit 20 is input to the gate of the NMOS transistor 31 .

[0045] During normal operation when the output voltage Vout is equal to or greater than the lower limit operating voltage of the load circuit 60, a periodic clock signal is output from the malfunction detection circuit 20 to the error detection signal 101, so that a signal that periodically alternates between H level and L level is input to the gate of the NMOS transistor 31.

[0046] The circuit is configured so that the charge of capacitor C1, which receives a constant current from constant current source 32, is discharged to ground by NMOS transistor 31. Therefore, while NMOS transistor 31 is periodically turned on, capacitor C1 is repeatedly charged and discharged, thereby suppressing the rise in voltage of capacitor C1.

[0047] Next, when the malfunction detection circuit 20 detects that Vout has fallen below the lower limit operating voltage of the load circuit 60 and the error detection signal 101 is fixed at the L level, the gate of the NMOS transistor 31 is fixed at the L level and is turned off. As a result, the constant current of the constant current source 32 is input to the capacitor C1, and the voltage of the capacitor C1 rises.

[0048] Then, when the voltage of capacitor C1 rises and the potential at the input of buffer circuit 33 exceeds the threshold voltage, the output of buffer circuit 33 changes from L level to H level, RSFF circuit 34 is set, switch circuit SW1 is turned on, and constant current I1 of constant current source 61 is passed as an additional current to NMOS transistors 72 and 73 of reference voltage generation circuit 40.

[0049] Therefore, the constant current I1 of the constant current source 61 flows in addition to the constant current Iref of the constant current source 71 through the NMOS transistors 72 and 73. As a result, the reference voltage Vref increases, and the voltage value of the output voltage Vout output from the output voltage generating circuit 50 also increases.

[0050] Furthermore, as the output of the buffer circuit 33 changes from L level to H level, the output of the inverter circuit 35 changes from H level to L level, and the gate voltage of the NMOS transistor 41 also changes from H level to L level, turning off the NMOS transistor 41. As a result, the voltage of the capacitor C2, which receives the constant current from the constant current source 42, starts to rise.

[0051] If the voltage value of the output voltage Vout increases through the operations up to this point but does not exceed the lower limit voltage for operation of the load circuit 60, the voltage value of the capacitor C2 continues to increase.

[0052] Then, when the voltage of capacitor C2 rises and the potential at the input of buffer circuit 43 exceeds the threshold voltage, the output of buffer circuit 43 changes from L level to H level, RSFF circuit 44 is set, switch circuit SW2 is turned on, and constant current I2 of constant current source 62 is passed as an additional current to NMOS transistors 72 and 73 of reference voltage generation circuit 40.

[0053] Therefore, in addition to the constant current Iref of the constant current source 71, the constant current I1 of the constant current source 61 and the constant current I2 of the constant current source 62 flow through the NMOS transistors 72 and 73. As a result, the reference voltage Vref further increases, and the voltage value of the output voltage Vout output from the output voltage generating circuit 50 also increases.

[0054] Furthermore, as the output of the buffer circuit 43 changes from L level to H level, the output of the inverter circuit 45 changes from H level to L level, and the gate voltage of the NMOS transistor 51 also changes from H level to L level, turning off the NMOS transistor 51. As a result, the voltage of the capacitor C3, which receives the constant current from the constant current source 52, starts to rise.

[0055] If the voltage value of the output voltage Vout increases through the operations up to this point but does not exceed the lower limit voltage for operation of the load circuit 60, the voltage value of the capacitor C3 continues to increase.

[0056] Then, when the voltage of capacitor C3 rises and the potential at the input of buffer circuit 53 exceeds the threshold voltage, the output of buffer circuit 53 changes from L level to H level, RSFF circuit 54 is set, switch circuit SW3 is turned on, and constant current I3 of constant current source 63 is passed as an additional current to NMOS transistors 72 and 73 of reference voltage generation circuit 40.

[0057] Therefore, in addition to the constant current Iref of the constant current source 71, the constant current I1 of the constant current source 61, the constant current I2 of the constant current source 62, and the constant current I3 of the constant current source 63 flow through the NMOS transistors 72 and 73. As a result, the reference voltage Vref further increases, and the voltage value of the output voltage Vout output from the output voltage generating circuit 50 also increases.

[0058] As a result of the above-described operation, the output voltage Vout rises to exceed the lower operating voltage limit of the load circuit 60, allowing the load circuit 60 to operate normally, and the malfunction detection circuit 20 again begins to output a periodic clock signal as the error detection signal 101.

[0059] In this embodiment, the circuit configuration is described as performing current addition in three stages after malfunction detection, but it is necessary to install a number of current addition circuits that will reliably increase the output voltage Vout to a voltage that exceeds the lower operating voltage limit of the load circuit 60.

[0060] The error detection signal 101 is not directly input to the gates of the NMOS transistor 41 in the second-stage current adder circuit and the NMOS transistor 51 in the third-stage current adder circuit, but a signal based on the error detection signal 101, which indicates that the output voltage Vout has fallen below the lower limit operating voltage, is indirectly input to the gates of these transistors.

[0061] FIG. 6 shows the operating waveforms of the output voltage correction circuit 30 shown in FIG.

[0062] Referring to FIG. 6, the reference voltage Vref drops for some reason, causing the output voltage Vout to also drop, and at time T1 it falls below the lower limit operating voltage of the load circuit 60.

[0063] As a result, the error detection signal 101 is fixed at the L level, and the voltage of the capacitor C1 begins to rise. Then, at time T2, when the voltage of the capacitor C1 exceeds the threshold, the output of the RSFF circuit 34 changes from the L level to the H level, and the constant current I1, which is the output of the constant current source 61, is output as the added current.

[0064] Furthermore, at time T2, the output of inverter circuit 35 changes from H level to L level, and the voltage of capacitor C2 starts to rise. Then, at time T3, when the voltage of capacitor C2 exceeds the threshold, the output of RSFF circuit 44 changes from L level to H level, and constant current I2, which is the output of constant current source 62, is further output as an additional current.

[0065] Furthermore, at time T3, the output of inverter circuit 45 changes from H level to L level, and the voltage of capacitor C3 begins to rise. Then, at time T4, when the voltage of capacitor C3 exceeds the threshold, the output of RSFF circuit 54 changes from L level to H level, and constant current I3, which is the output of constant current source 63, is further output as an additional current.

[0066] At time T5, the output voltage Vout exceeds the lower operating voltage limit, causing the error detection signal 101 to become a clock signal that alternates between H level and L level. As a result, the NMOS transistor 31 turns on, the voltage of the capacitor C1 becomes almost zero, the output of the inverter circuit 35 becomes H level, and the NMOS transistor 41 turns on. Therefore, the voltage of the capacitor C2 becomes almost zero, the output of the inverter circuit 45 becomes H level, and the NMOS transistor 51 also turns on. The voltage of the capacitor C3 then becomes almost zero.

[0067] As described above, the constant voltage generating circuit of this embodiment is provided with a malfunction detection circuit 20 for detecting a drop in the output voltage Vout, and the error detection signal 101 output from the malfunction detection circuit 20 is used as a trigger to increase the constant current flowing into the NMOS transistors 72 and 73 in the reference voltage generating circuit 40, thereby raising the reference voltage Vref. As a result, it is possible to raise the output voltage Vout to a voltage level at which the load circuit 60 does not malfunction.

[0068] When the output voltage Vout reaches a voltage level at which the load circuit 60 does not malfunction, the error detection signal 101 output from the malfunction detection circuit 20 becomes a clock signal that periodically switches between L level and H level, and stops the current that is about to be newly added to the diode-connected NMOS transistors 72 and 73. This makes it possible to set the output voltage Vout to a low voltage at which the load circuit 60 does not malfunction, which can greatly contribute to reducing current consumption.

[0069] In this embodiment, the output voltage correction circuit 30 has been described as having three current adder circuits, but it is also possible to increase the adjustment accuracy and set a voltage level that is right at the limit of normal operation by configuring it to have N current adder circuits.

[0070] Furthermore, in the constant voltage generating circuit of this embodiment, the circuit scale can be reduced by using a simplified reference voltage generating circuit 40 that feeds a constant current into diode-connected NMOS transistors 72 and 73 .

[0071] Furthermore, according to the constant voltage generating circuit of this embodiment, the load circuit 60 is operated at the lowest voltage possible without malfunctioning, so absolute precision is not required for the voltage value of the output voltage Vout.

[0072] In this way, according to the constant voltage generating circuit of this embodiment, it is possible to set the voltage value of the output voltage Vout low, close to the lower limit voltage of the operation of the load circuit 60. [Explanation of symbols]

[0073] 20 Malfunction detection circuit 21 Clock generation circuit 22 PMOS transistor (P-channel MOSFET) 23 NMOS transistor (N-channel MOSFET) 30 Output voltage compensation circuit 31, 41, 51 NMOS transistors 32, 42, 52 constant current source 33, 43, 53 Buffer circuits 34, 44, 54 RSFF circuits 35, 45 inverter circuit 40 Reference voltage generation circuit 50 Output voltage generation circuit 60 load circuit 61~63 Constant current source 71 Constant current source 72, 73 NMOS transistors 81 Operational Amplifier 82 PMOS transistors 91 Capacitor 101 Error detection signal 110 Output voltage generation circuit 111 Reference voltage generation circuit 112 operational amplifiers 113 PMOS transistor 120 Output voltage monitor circuit 121 Comparator 122 Reset signal 130 Load circuit 131 Capacitor C1~C3 capacitors CLK Clock signal R1, R2 Resistor elements SW1~SW3 switch circuit Vfb Feedback voltage Vout Output voltage Vref Reference voltage

Claims

1. a reference voltage generating circuit that generates and outputs a reference voltage by causing a constant current from a constant current source to flow through a semiconductor element; an output voltage generating circuit that generates an output voltage based on the reference voltage generated by the reference voltage generating circuit; a malfunction detection circuit that uses a semiconductor element having low-voltage operating characteristics similar to those of a semiconductor element used in a load circuit that operates using the output voltage from the output voltage generation circuit, and generates and outputs an error detection signal that indicates that the output voltage has become equal to or lower than a lower limit operating voltage of the load circuit; an output voltage correction circuit having a plurality of current addition circuits that, when an error detection signal from the malfunction detection circuit becomes active, sequentially increase the amount of the constant current at different timings by adding a current to the constant current in the reference voltage generation circuit, and, when the error detection signal from the malfunction detection circuit becomes inactive, stop adding a current to the constant current in the reference voltage generation circuit; A constant voltage generating circuit comprising:

2. The malfunction detection circuit a clock generation circuit that generates a clock signal using the output voltage generated by the output voltage generation circuit as a power source; an inverter circuit configured by a PMOS transistor and an NMOS transistor connected in series between the output voltage and ground, which inverts the logic of the clock signal generated by the clock generation circuit and outputs the inverted logic as the error detection signal; 2. The constant voltage generating circuit according to claim 1, comprising:

3. Each of the plurality of current adder circuits a first constant current source; a capacitor element having one end connected to ground and configured to increase a voltage to be held by accumulating a constant current from the first constant current source; an NMOS transistor having a gate to which a signal based on the error detection signal from the malfunction detection circuit is input, a source connected to ground, and a drain connected to the other end of the capacitor element, the NMOS transistor operating to discharge the voltage of the capacitor element to ground when the error detection signal is at a high level; a second constant current source; a switching circuit that switches the constant current in the reference voltage generating circuit to add the constant current from the second constant current source when the voltage held in the capacitor element becomes equal to or greater than a preset threshold value; 3. The constant voltage generating circuit according to claim 2, comprising:

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