Method of manufacturing semiconductor device

Abstract

To provide: a semiconductor device having favorable electrical characteristics; a semiconductor device having stable electrical characteristics; and a highly reliable semiconductor device.SOLUTION: A semiconductor device includes: a semiconductor layer; a first insulating layer; a second insulating layer; and an electrically conductive layer. The first insulating layer is in contact with a part of an upper surface of the semiconductor layer, the electrically conductive layer is located on the first insulating layer, and the second insulating layer is located on the semiconductor layer. The semiconductor layer includes a metal oxide and includes a first region overlapping with the electrically conductive layer and a second region not overlapping with the electrically conductive layer. The second region is in contact with the second insulating layer, the second insulating layer includes oxygen and a first element, and the first element is any one or more of phosphorus, boron, magnesium, aluminum, and silicon.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] 1. Field of the Invention One embodiment of the present invention relates to a semiconductor device. One embodiment of the present invention relates to a display device. One embodiment relates to a method for manufacturing a semiconductor device or a display device.

[0002] Note that one embodiment of the present invention is not limited to the above technical fields. The technical field of one embodiment of the present invention is a semiconductor device, a display device, a light-emitting device, a power storage device, a memory device, and the like. , electronic device, lighting device, input device, input / output device, driving method thereof, or manufacturing method thereof Semiconductor devices function by utilizing the semiconductor properties. This refers to all devices that can do this. [Background technology]

[0003] Oxide semiconductors using metal oxides are attracting attention as semiconductor materials that can be used in transistors. For example, in Patent Document 1, a plurality of oxide semiconductor layers are stacked, and the plurality of oxide semiconductor layers are Among the oxide semiconductor layers, an oxide semiconductor layer serving as a channel contains indium and gallium, and By increasing the ratio of indium to that of gallium, the field effect mobility (simply called mobility) can be improved. A semiconductor device with enhanced mobility, or μFE, is disclosed.

[0004] Metal oxides that can be used for the semiconductor layer can be formed using a sputtering method or the like. Therefore, it can be used for the semiconductor layer of a transistor that constitutes a large display device. By improving some of the production facilities for transistors using polycrystalline silicon and amorphous silicon, This allows for the use of metal oxide transistors, which reduces capital investment. The capacitor has a higher field effect mobility than amorphous silicon, so it can be used in the drive circuit. A high-performance display device can be realized.

[0005] Furthermore, Patent Document 2 discloses a method for forming a semiconductor device using aluminum, boron, gallium, etc. in a source region and a drain region. A group consisting of: sodium, indium, titanium, silicon, germanium, tin, and lead An oxide semiconductor film having a low resistance region containing at least one of these as a dopant is used. A thin film transistor is disclosed. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Japanese Patent Application Laid-Open No. 2014-7399 [Patent Document 2] Japanese Patent Application Laid-Open No. 2011-228622 Summary of the Invention [Problem to be solved by the invention]

[0007] An object of one embodiment of the present invention is to provide a semiconductor device with favorable electrical characteristics. Another object is to provide a semiconductor device having stable electrical characteristics. An object of the present invention is to provide a semiconductor device with high performance.

[0008] The description of these problems does not preclude the existence of other problems. It is not necessary for one embodiment to solve all of these problems. The subject matter can be extracted from the description, drawings, claims, etc. [Means for solving the problem]

[0009] One embodiment of the present invention is a semiconductor device including a semiconductor layer, a first insulating layer, a second insulating layer, and a conductive layer. The first insulating layer is in contact with a part of the top surface of the semiconductor layer, and the conductive layer is The insulating layer is located on the semiconductor layer, and the second insulating layer is located on the semiconductor layer. The semiconductor layer is made of a metal oxide. the semiconductor layer has a first region overlapping the conductive layer and a second region not overlapping the conductive layer. The second region is in contact with a second insulating layer. The second insulating layer contains oxygen and a first element. The first element is either phosphorus, boron, magnesium, aluminum, or silicon. In addition, the minimum concentration of the first element in the thickness direction of the second insulating layer is at least one of the above. The ratio of the maximum value to is 1.0 or more and 10.0 or less.

[0010] Another embodiment of the present invention is a semiconductor device including a semiconductor layer, a first insulating layer, a second insulating layer, a conductive layer, and The first insulating layer is in contact with the top and side surfaces of the semiconductor layer, and the conductive layer is The first insulating layer is located on the semiconductor layer, and the second insulating layer is located on the semiconductor layer. The semiconductor layer includes an oxide, and the semiconductor layer has a first region overlapping the conductive layer and a second region not overlapping the conductive layer. The first insulating layer has a third region that overlaps the conductive layer and a second region that does not overlap the conductive layer. and a fourth region, the fourth region being in contact with the second insulating layer. The second insulating layer is made of oxygen and a first element, the first element being phosphorus, boron, magnesium, aluminum, or The second insulating layer is made of at least one of the first element and silicon. The ratio of the maximum value to the minimum value of the density is 1.0 or more and 10.0 or less.

[0011] In the above-described semiconductor device, the fourth region preferably contains the above-described first element.

[0012] In the semiconductor device, the fourth region is preferably thinner than the third region. I wish.

[0013] In the semiconductor device, the second insulating layer has a concentration of the first element of 1×10 2 0 atoms / cm 3 That's it, 1×10 22 atoms / cm 3 Having an area that is: It is preferable that:

[0014] In the semiconductor device, the second insulating layer is characterized by the following properties in X-ray photoelectron spectroscopy analysis: It is preferable that a peak resulting from the bond between the first element and oxygen is observed.

[0015] In the semiconductor device, the second region preferably contains the first element. It's nice.

[0016] In the semiconductor device, the second region has a concentration of the first element of 1×10 20 atoms / cm 3 That's it, 1×10 22 atoms / cm 3 Having a region that is: is preferred.

[0017] In the semiconductor device, the second region is characterized by the following in X-ray photoelectron spectroscopy analysis: It is preferable that a peak resulting from the bond between element 1 and oxygen is observed. [Effects of the Invention]

[0018] According to one embodiment of the present invention, a semiconductor device with favorable electrical characteristics can be provided. Therefore, a semiconductor device with stable properties can be provided, or a display device with high reliability can be provided.

[0019] The description of these effects does not preclude the existence of other effects. An embodiment does not necessarily have to have all of these effects. can be extracted from descriptions in the specification, drawings, claims, etc. [Brief explanation of the drawings]

[0020] [Figure 1] An example of a transistor configuration. [Figure 2] An example of a transistor configuration. [Figure 3] An example of a transistor configuration. [Figure 4] An example of a transistor configuration. [Figure 5] An example of a transistor configuration. [Figure 6] An example of a transistor configuration. [Figure 7] An example of a transistor configuration. [Figure 8] An example of a transistor configuration. [Figure 9] 1A to 1C illustrate a method for manufacturing a transistor. [Figure 10] 1A to 1C illustrate a method for manufacturing a transistor. [Figure 11] 1A to 1C illustrate a method for manufacturing a transistor. [Figure 12] FIG. [Figure 13] FIG. [Figure 14] FIG. [Figure 15] FIG. [Figure 16] 1A and 1B are a block diagram and a circuit diagram of a display device. [Figure 17] FIG. [Figure 18] An example of the display module configuration. [Figure 19] An example of the configuration of electronic devices. [Figure 20] An example of the configuration of electronic devices. [Figure 21] An example of the configuration of electronic devices. [Figure 22] Calculation results of impurity element concentrations. [Figure 23] Cross-sectional STEM image. [Figure 24] Cross-sectional STEM image and EDX spectrum. [Figure 25] Cross-sectional STEM image. [Figure 26] Cross-sectional STEM image and EDX spectrum. DETAILED DESCRIPTION OF THE INVENTION

[0021] Hereinafter, embodiments will be described with reference to the drawings. It is understood that the present invention may be embodied in various different forms without departing from its spirit and scope. It will be readily apparent to those skilled in the art that various modifications may be made to the embodiments and details of the present invention. However, the present invention should not be construed as being limited to the description of the following embodiments.

[0022] In addition, in each figure described in this specification, the size, layer thickness, or area of ​​each component is May be exaggerated for clarity.

[0023] In addition, the ordinal numbers "first," "second," and "third" used in this specification refer to the number of components. This is added to avoid confusion and is not intended to limit the number.

[0024] In addition, in this specification, the terms "above" and "below" that indicate the position of components are used to indicate the position of components. The positional relationship is used for convenience in describing the structure with reference to the drawings. The relationship between the two components changes depending on the direction in which each component is depicted. The terms are not limited to those used above, but can be rephrased appropriately depending on the situation.

[0025] In this specification and the like, the functions of the source and drain of a transistor are The polarity of the resistor or the direction of the current may change during circuit operation. For this reason, the terms source and drain can be used interchangeably. .

[0026] In this specification, the channel length direction of a transistor is the direction in which the source region and the drain region are connected. This refers to one of the directions parallel to the line connecting the gate regions at the shortest distance. The direction corresponds to one of the directions of current flow through the semiconductor layer when the transistor is in the on state. The channel width direction refers to the direction perpendicular to the channel length direction. Depending on the structure and shape of the transistor, the channel length direction and the channel width direction are determined as one. This may not be possible.

[0027] In addition, in this specification, "electrically connected" means "something that has some kind of electrical effect." This includes cases where the device is connected via a "of" is not subject to any particular restrictions as long as it allows the transmission and reception of electrical signals between connected objects. For example, "things that have some kind of electrical action" include electrodes, wiring, and transistors. It has various functions such as switching elements, resistors, inductors, capacitors, etc. This includes elements such as:

[0028] In addition, in this specification and the like, the terms "film" and "layer" are interchangeable. For example, the terms "conductive layer" and "insulating layer" can be interchanged with "conductive film" and "insulating layer." The term "insulating film" may be used interchangeably in some cases.

[0029] Unless otherwise specified, in this specification and the like, the off-state current refers to the current that flows when a transistor is off. This refers to the drain current when the device is in a non-conducting state (also known as a cut-off state). Unless otherwise specified, for an n-channel transistor, the voltage V between the gate and source gs is the threshold voltage V th (For p-channel transistors, V th Higher than (i) This refers to a state.

[0030] In this specification, a display panel, which is one aspect of a display device, displays (outputs) an image or the like on a display surface. Therefore, a display panel is one aspect of an output device.

[0031] In this specification, the substrate of the display panel is provided with, for example, an FPC (Flexible Printed Circuit). Integrated Circuit) or TCP (Tape Carrier Packa ge) or a connector such as COG (Chip On Ground) is attached to the board. The IC mounted on the display panel module is called a display module. It may also be called a display panel or simply a display panel.

[0032] In this specification and the like, a touch panel, which is one aspect of a display device, is a device for displaying images and the like on a display surface. The function of displaying the information and detecting when a detectable object such as a finger or stylus touches, presses, or approaches the display surface. It also functions as a touch sensor to detect when something is touching the screen. A rule is one form of input / output device.

[0033] The touch panel is, for example, a display panel (or display device) with a touch sensor, A touch panel can also be called a display panel (or display device) with a touch function. Alternatively, the display panel may have a touch sensor panel. It may also be configured to have a touch sensor function inside or on the surface.

[0034] In addition, in this specification, a touch panel substrate on which a connector or IC is mounted is referred to as a touch panel. , touch panel module, display module, or simply touch panel. be.

[0035] (Embodiment 1) In this embodiment, a semiconductor device including a transistor 100 according to one embodiment of the present invention and and its manufacturing method will be described.

[0036] One embodiment of the present invention is a method for manufacturing a semiconductor device including: a semiconductor layer in which a channel is formed on a formation surface; A gate insulating layer (also called the first insulating layer) and a conductive layer that functions as a gate electrode are formed on the gate insulating layer. The transistor further comprises a semiconductor layer having a high barrier property against oxygen. It is preferable to have a protective insulating layer (also called a second insulating layer).

[0037] The gate insulating layer is preferably provided in contact with the upper surface of the island-shaped semiconductor layer. In particular, when a metal oxide is used for the semiconductor layer, the gate insulating layer may contain an oxide. preferable.

[0038] The semiconductor layer contains a metal oxide (hereinafter also referred to as an oxide semiconductor) that exhibits semiconductor properties. The semiconductor layer preferably includes a channel forming region where a channel can be formed and a semiconductor layer. The channel forming region has a pair of low resistance regions that function as a source region and a drain region. The pair of low resistance regions are regions that overlap with the gate electrode in the semiconductor layer. The low-resistance region is a region that is provided on either side of the gate-forming region and has a lower resistance than the channel-forming region. Preferably, the low resistance region is in contact with the second insulating layer, and the low resistance region is covered with the second insulating layer.

[0039] The second insulating layer preferably contains an impurity element, such as hydrogen or boron. Carbon, nitrogen, fluorine, phosphorus, sulfur, arsenic, aluminum, magnesium, silicon, Typical examples of rare gases include helium, neon, and argon. In particular, phosphorus, boron, magnesium, aluminum, etc. It is preferable that the material contains one or more selected from aluminum and silicon.

[0040] In this specification, impurity elements refer to elements other than the main components, and are present in an amount of 1 atomic % or more. The contained elements are the main components.

[0041] In particular, the second insulating layer preferably contains an impurity element that easily bonds with oxygen. , boron, phosphorus, aluminum, magnesium, silicon, etc. Second insulating layer By including the above-mentioned impurity element, oxygen contained in the second insulating layer is released from the second insulating layer. The separation is suppressed.

[0042] When oxygen is supplied to the low-resistance region, the carrier density decreases and the electrical resistance increases. However, in one embodiment of the present invention, the second insulating layer is in contact with the low resistance region, and the second As a result, the second insulating layer covers the low resistance region. The supply of oxygen to the low-resistance region is suppressed, and the low-resistance region maintains a low electrical resistance. Furthermore, the supply of oxygen from the second insulating layer to the gate electrode is suppressed, and the gate The electrodes can maintain a low electrical resistance.

[0043] In one embodiment of the present invention, the second insulating layer is in contact with a side surface of the gate insulating layer, and the second insulating layer is in contact with the side surface of the gate insulating layer. As a result, the gate insulating layer covers the low resistance region and the gate electrode. The supply of oxygen to the electrode is suppressed, and the electrical resistance of the low-resistance region and the gate electrode is low. In addition, oxygen contained in the gate insulating layer is released to the second insulating layer side. This suppresses the oxygen released from the gate insulating layer and allows it to efficiently reach the channel formation region of the semiconductor layer. This allows oxygen vacancies in the channel formation region of the semiconductor layer to be compensated for. This allows for filling the gap and realizing a highly reliable transistor.

[0044] By adopting such a structure, oxygen vacancies are sufficiently reduced, and the carrier density is extremely low. It has both a channel forming region and a source region and a drain region with extremely low electrical resistance. As a result, a semiconductor device with excellent electrical characteristics and high reliability can be realized.

[0045] A more specific example will be described below with reference to the drawings.

[0046] <Configuration example 1> 1A is a top view of a transistor 100, and FIG. 1B is a top view of the transistor 100 shown in FIG. FIG. 1(C) corresponds to a cross-sectional view of the cut surface taken along the dashed line A1-A2 shown in FIG. 1(A). It corresponds to a cross-sectional view of the cut surface taken along the dashed line B1-B2. Some of the components of the transistor 100 (such as the gate insulating layer) are omitted in the illustration. The dashed line A1-A2 direction is the channel length direction, and the dashed line B1-B2 direction is the channel width direction. In addition, the top view of the transistor is the same as that of FIG. Similarly, some of the components are omitted in the drawings.

[0047] The transistor 100 is provided on a substrate 102, an insulating layer 103, a semiconductor layer 108, an insulating layer 109, a semiconductor layer 109a, and a semiconductor layer 109b. The semiconductor device includes an edge layer 110, a metal oxide layer 114, a conductive layer 112, an insulating layer 118, etc. The semiconductor layer 108 is provided on the insulating layer 103. The insulating layer 110 is formed on a portion of the semiconductor layer 108. The metal oxide layer 114 and the conductive layer 112 are provided on the insulating layer 110. The insulating layer 118 is stacked in this order and has a portion overlapping with the semiconductor layer 108. A part of the upper surface and the side surface of the conductor layer 108, the side surface of the insulating layer 110, the side surface of the metal oxide layer 114, The insulating layer 118 is provided to cover the upper and side surfaces of the conductive layer 112. It functions as a protective layer to protect the resistor 100.

[0048] A portion of the conductive layer 112 functions as a gate electrode. A portion of the insulating layer 110 functions as a gate insulator. The transistor 100 has a gate electrode provided on the semiconductor layer 108. This is a so-called top-gate transistor.

[0049] The semiconductor layer 108 preferably comprises a metal oxide.

[0050] For example, the semiconductor layer 108 may be made of indium and M (M is gallium, aluminum, silicon, etc.). Ni, boron, yttrium, tin, copper, vanadium, beryllium, titanium, iron, nickel , germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium one or more selected from the group consisting of aluminum, tantalum, tungsten, and magnesium; and zinc. In particular, M is aluminum, gallium, yttrium, or It is preferable to use one or more selected from tin.

[0051] In particular, the semiconductor layer 108 is made of an oxide containing indium, gallium, and zinc. It is preferable.

[0052] The semiconductor layer 108 may be a layer having a different composition, a layer having a different crystallinity, or a layer having a different impurity concentration. Alternatively, a laminated structure may be used in which different layers are laminated.

[0053] The semiconductor layer 108 has a region overlapping with the conductive layer 112 and a pair of low-resistance regions sandwiching the region. The region of the semiconductor layer 108 that overlaps with the conductive layer 112 is a transistor On the other hand, the region 108n functions as a channel forming region of the transistor 100. The source or drain region of the semiconductor substrate is formed by the gate electrode.

[0054] The region 108n is a region having a lower resistance than the channel forming region, a region having a higher carrier density, and an oxide It can also be called a region with a high density of electron vacancies or an n-type region.

[0055] Region 108n can be formed, for example, by exposing a metal oxide to a plasma. When metal oxides are exposed to plasma, defects, typically oxygen vacancies (hereinafter referred to as V O When written as Oxygen vacancies (V) are formed in the metal oxide. O ) and hydrogen, oxygen vacancies The state where hydrogen is added to the O V O H The metal oxide becomes an n-type due to the increase in carrier density. A resistive region 108n is formed.

[0056] For example, the insulating layer 118 may be formed using a plasma enhanced chemical vapor deposition (PECVD) device or a single By using a plasma CVD apparatus, the insulating layer 118 is formed and the region 108 n can be formed in a self-aligning manner.

[0057] As shown in FIGS. 1B and 1C, the region 108n is in contact with the insulating layer 118. Preferably, region 108n is covered with an insulating layer 118.

[0058] The insulating layer 118 includes an oxide. For example, the insulating layer 118 may include silicon oxide, silicon dioxide, or silicon dioxide. Silicon nitride, silicon oxynitride, aluminum oxide, aluminum oxynitride, hafnium oxide Inorganic insulating materials such as tungsten, hafnium aluminate, etc. can be used. The layer 118 preferably further contains an impurity element. The impurity element may be, for example, hydrogen. , boron, carbon, nitrogen, fluorine, phosphorus, sulfur, arsenic, aluminum, magnesium, silicon Typical examples of rare gases include helium, neon, and argon. The insulating layer 118 is easily bonded to oxygen. It is particularly preferable that the alloy contains impurity elements such as phosphorus, boron, magnesium, and aluminum. It is preferable that the impurity element contains one or more selected from the group consisting of tungsten and silicon. It may contain two or more elements.

[0059] In this specification, an oxynitride is a compound having a higher oxygen content than nitrogen. Nitrides refer to substances whose composition contains more nitrogen than oxygen. vinegar.

[0060] The insulating layer 118 contains the above-described impurity element, and oxygen contained in the insulating layer 118 becomes insulating. The insulating layer 118 can prevent impurity elements that easily bond with oxygen from being desorbed from the layer 118. It is particularly preferable that the impurity element contains In this case, oxygen contained in the insulating layer 118 can be efficiently prevented from being released from the insulating layer 118.

[0061] Here, in the insulating layer containing oxygen, oxygen may be released from the insulating layer. When the oxygen reaches the region 108n, the oxygen O Remove hydrogen from H to form water V desorbed as a molecule (H2O) and deprived of hydrogen O H is an oxygen deficiency (V O ) Also, V O Oxygen vacancies (V) formed by the loss of hydrogen from H O ) reaches the area 108n In this way, when oxygen is supplied to the region 108n, the region 10 V that 8n has O H and oxygen vacancies (V O ) decreases, that is, the carrier density in region 108n The resistance of the region 108n may decrease and become higher.

[0062] The transistor 100 according to one embodiment of the present invention includes an insulating layer 118 in contact with the region 108n. With such a structure, oxygen contained in the insulating layer 118 is insulated. This can prevent the desorption from the edge layer 118 and prevent the resistance of the region 108n from increasing. .

[0063] The insulating layer 110 is formed in a region in contact with the channel forming region of the semiconductor layer 108, i.e., the conductive layer 1 12 and has an overlapping area.

[0064] The insulating layer 103 and the insulating layer 110 in contact with the channel forming region of the semiconductor layer 108 are oxidized. It is preferable to use a film made of silicon dioxide, silicon oxynitride, or aluminum oxide. An oxide film such as a aluminum film can be used. During the heat treatment in the manufacturing process, oxygen desorbed from the insulating layer 103 and the insulating layer 110 is transferred to the channel. By supplying the oxygen to the channel formation region, oxygen vacancies in the channel formation region can be reduced.

[0065] As shown in FIGS. 1B and 1C, the side surfaces of the insulating layer 110 are connected to the insulating layer 118. It is preferable to contact

[0066] Here, oxygen contained in the insulating layer 110 is desorbed from the insulating layer 110, and the oxygen is transferred to the region 108n When the V O H and oxygen vacancies (V O ) decreases, and the area 108n In addition, oxygen contained in the insulating layer 110 may be released from the insulating layer 110. However, when the oxygen reaches the conductive layer 112, the conductive layer 112 is oxidized, and the resistance of the conductive layer 112 decreases. It may be higher.

[0067] In the transistor 100 according to one embodiment of the present invention, the side surface of the insulating layer 110 is in contact with the insulating layer 118. The insulating layer 110 is covered with the insulating layer 118. When oxygen contained in 110 diffuses into the insulating layer 118, impurities contained in the insulating layer 118 diffuse into the oxygen. The trapped oxygen is less likely to be released from the insulating layer 118. Oxygen contained in region 108 reaches region 108n and conductive layer 112 through insulating layer 118, and The resistance of the conductive layer 8n and the conductive layer 112 can be prevented from increasing.

[0068] As shown in FIGS. 1A and 1B, the transistor 100 includes an insulating layer 118 The conductive layer 120a and the conductive layer 120b may be disposed on the conductive layer 120a. The conductive layer 120a and the conductive layer 120b function as a source electrode or a drain electrode. 20b are respectively formed through openings 141a and 141b in the insulating layer 118. The semiconductor layer 108 is electrically connected to the region 108n.

[0069] As shown in FIGS. 1B and 1C, a conductive layer 112, a metal oxide layer 114 and an insulating layer 116 are formed. The layers 110 are processed so that their top surface shapes roughly match each other.

[0070] In this specification, the phrase "the upper surface shapes are roughly the same" means that there is at least a small difference between the layers. For example, the upper and lower layers may have the same mask pattern. This includes cases where the entire surface is processed using the same mask pattern, or where part of the surface is processed using the same mask pattern. The shells do not overlap, and the upper layer is sometimes located inside the lower layer, and sometimes the upper layer is sometimes located outside the lower layer. In this case too, it is said that "the top surface shapes roughly match."

[0071] The metal oxide layer 114 located between the insulating layer 110 and the conductive layer 112 is It functions as a barrier film that prevents oxygen contained therein from diffusing toward the conductive layer 112. The metal oxide layer 114 is formed by diffusing hydrogen and water contained in the conductive layer 112 to the insulating layer 110 side. The metal oxide layer 114 also functions as a barrier film to prevent, for example, at least the insulating layer 11 A material that is less permeable to oxygen and hydrogen than 0 can be used.

[0072] The metal oxide layer 114 allows the conductive layer 112 to easily absorb oxygen, such as aluminum or copper. Even if a thin metal material is used, oxygen does not diffuse from the insulating layer 110 to the conductive layer 112. Furthermore, even if the conductive layer 112 contains hydrogen or water, the conductive layer 1 Diffusion of hydrogen and water from the insulating layer 110 to the semiconductor layer 108 can be prevented. As a result, the carrier density in the channel formation region of the semiconductor layer 108 can be made extremely low. It can be said that

[0073] The metal oxide layer 114 can be made of an insulating material or a conductive material. If the metal oxide layer 114 has insulating properties, it functions as a part of the gate insulating layer. If the metal oxide layer 114 is conductive, it functions as a part of the gate electrode.

[0074] The metal oxide layer 114 is made of an insulating material having a higher dielectric constant than silicon oxide. In particular, an aluminum oxide film, a hafnium oxide film, or a hafnium aluminate film is preferable. It is preferable to use a film such as a PET film, since the driving voltage can be reduced.

[0075] The metal oxide layer 114 may be, for example, indium oxide or indium tin oxide (ITO). or silicon-containing indium tin oxide (ITSO), In particular, conductive oxides containing indium are preferred because of their high conductivity. .

[0076] The metal oxide layer 114 may be an oxide material containing one or more of the same elements as the semiconductor layer 108. In particular, it is preferable to use an oxide semiconductor material that can be used for the semiconductor layer 108. In this case, it is preferable to use the same type of metal oxide layer 114 as the semiconductor layer 108. By applying metal oxide films formed using sputtering targets, equipment can be standardized. This is preferable because it can

[0077] Alternatively, both the semiconductor layer 108 and the metal oxide layer 114 may contain indium and gallium. When a metal oxide material containing gallium is used, the metal oxide layer 114 contains more gallium than the semiconductor layer 108. Using a material with a high composition (content ratio) can further improve the barrier properties against oxygen. In this case, the semiconductor layer 108 contains more indium than the metal oxide layer 114. By using a material with a high composition of can.

[0078] The metal oxide layer 114 is preferably formed using a sputtering apparatus. For example, when an oxide film is formed using a sputtering device, it is formed in an atmosphere containing oxygen gas. This allows oxygen to be suitably added to the insulating layer 110 and the semiconductor layer 108.

[0079] FIG. 2(A) shows an enlarged cross-sectional view of the area P surrounded by the dashed line in FIG. 1(B). .

[0080] The semiconductor layer 108 has a region 108n that contacts the insulating layer 118. The region 108n is a conductive region. The insulating layer 110 does not overlap with the insulating layer 112. The side of the insulating layer 110 is in contact with the insulating layer 118.

[0081] The insulating layer 118 has an impurity element concentration of 1×10 19 atoms / cm 3 That's it, 1×1 0 23 atoms / cm 3 Less than or equal to 5 x 10 19 atoms / cm 3 That's it, 5x 10 22atoms / cm 3 Less than or equal to 1×10 20 atoms / cm 3 End , 1×10 22 atoms / cm 3 It is preferred to include a region in which:

[0082] The concentration of impurity elements contained in the insulating layer 118 is measured by, for example, secondary ion mass spectrometry (SIMS) Secondary Ion Mass Spectrometry) and X-ray photoelectron Spectroscopy (XPS: X-ray Photoelectron Spectroscopy) When XPS analysis is used, the surface side or By combining ion sputtering from the backside and XPS analysis, the concentration in the depth direction You can find out the distribution.

[0083] In addition, in the insulating layer 118, the impurity element is preferably present in an oxidized state. For example, impurity elements such as boron, phosphorus, magnesium, aluminum, and silicon are used. It is preferable to use such an element that is easily oxidized. Since it can exist stably in a state of being bonded to oxygen in the edge layer 118, it can be easily heated at a high temperature (for example, Even when subjected to temperatures above 400°C, 600°C, or 800°C, Furthermore, the impurity element is bonded to oxygen in the insulating layer 118, thereby preventing the insulating layer 118 from being broken down. This can prevent oxygen contained in the insulating layer 118 from being desorbed from the insulating layer 118. The insulating layer 118 containing the impurity element in the insulating state is in a state where oxygen is difficult to diffuse. Oxygen is supplied to the region 108n and the conductive layer 112 from outside the layer 118 through the insulating layer 118. Therefore, when performing high-temperature processing, it is important to be careful of the oxygen The process is performed in a state where the region 108n and the conductive layer 112 are covered with an insulating layer 118 having a high barrier property. It is preferable that

[0084] For example, when boron is used as an impurity element, the boron contained in the insulating layer 118 reacts with oxygen. This can be seen in XPS analysis, for example, in the B2O3 bond. This can be confirmed by observing the spectral peaks caused by the SiO2. Spectral peaks due to the existence of elemental boron are not observed or are not measurable. The peak intensity becomes so small that it is buried in the background noise at the lower limit.

[0085] Here, oxygen vacancies that can be formed in the channel formation region of the semiconductor layer 108 will be described. .

[0086] The oxygen vacancies formed in the channel formation region of the semiconductor layer 108 affect the transistor characteristics. For example, if oxygen vacancies are formed in the channel formation region, the oxygen Hydrogen bonds to the electron vacancies and can become a carrier supply source. When a source is generated, the electrical characteristics of the transistor 100 change, typically the threshold voltage. Therefore, it is preferable that there are as few oxygen vacancies as possible in the channel formation region. stomach.

[0087] In one embodiment of the present invention, an insulating film, specifically, a film formed on the insulating film in the vicinity of the channel formation region of the semiconductor layer 108 The insulating layer 110 is located above the channel forming region, and the insulating layer 10 is located below the channel forming region. The insulating layer 103 and the insulating layer 13 are formed by the heat during the manufacturing process. By transferring oxygen from 10 to the channel formation region, oxygen vacancies in the channel formation region are eliminated. It is possible to reduce the

[0088] As shown in Figures 1(B), 1(C) and 2(A), the insulating film has a high barrier property against oxygen. The edge layer 118 contacts the side surface of the insulating layer 110 and covers the insulating layer 110. By this, oxygen that may be released from the insulating layer 110 is prevented from diffusing to the insulating layer 118 side. This can prevent oxygen vacancies in the channel formation region of the semiconductor layer 108 from occurring, and thus oxygen vacancies in the channel formation region of the semiconductor layer 108 can be efficiently reduced. This makes it possible to:

[0089] Furthermore, the semiconductor layer 108 preferably has a region in which the atomic ratio of In is greater than the atomic ratio of M. The higher the atomic ratio of In, the more the field-effect mobility of the transistor can be improved. Cut.

[0090] In the case of metal oxides containing In, Ga, and Zn, the bonding strength between In and oxygen is greater than that between Ga and oxide. Therefore, when the atomic ratio of In is large, oxygen deficiency occurs in the metal oxide film. In addition, even if the metal element shown above as M is used instead of Ga, the same problem occurs. When there are many oxygen vacancies in the metal oxide film, the electrical characteristics of the transistor tend to deteriorate. This can lead to degradation and reduced reliability.

[0091] However, in one embodiment of the present invention, the semiconductor layer 108 containing a metal oxide contains a very large amount of Since oxygen can be supplied, it is possible to use metal oxide materials with a large atomic ratio of In. This allows for extremely high field-effect mobility, stable electrical characteristics, and high reliability. It is possible to realize a transistor having such a structure.

[0092] For example, the atomic ratio of In is 1.5 times or more, or 2 times or more, or Preferably, a metal oxide having a solubility of 3 times or more, 3.5 times or more, or 4 times or more is used. It is possible.

[0093] In particular, the atomic ratio of In, M, and Zn in the semiconductor layer 108 is In:M:Zn=5:1. : 6 or its vicinity (when In is 5, M is 0.5 or more and 1.5 or less, and Zn is 5 It is preferable that the ratio of the number of In, M, and Zn atoms is 7 or more (including 7 or less). It is preferable that the composition of the semiconductor layer 108 is In:M:Zn=4:2:3 or a value close to that. As the composition, the ratio of the number of atoms of In, M, and Zn in the semiconductor layer 108 may be approximately equal. That is, the ratio of the number of In, M, and Zn atoms is In:M:Zn=1:1:1 or It may also include nearby materials.

[0094] For example, the above-mentioned high field effect mobility transistor is used as a gate driver for generating a gate signal. By using this as a driver, it is possible to provide a display device with a narrow frame width (also called a narrow frame). In addition, the above-mentioned transistors with high field effect mobility are used in the source driver (especially the source It can be used for a demultiplexer connected to the output terminal of the shift register of the driver. As a result, it is possible to provide a display device with a small number of wires connected to the display device.

[0095] Even if the semiconductor layer 108 has a region in which the atomic ratio of In is greater than the atomic ratio of M, However, if the crystallinity of the semiconductor layer 108 is high, the field-effect mobility may be reduced. The crystallinity of 108 can be determined by, for example, X-ray diffraction (XRD). or by transmission electron microscopy (TEM). This can be analyzed using a TEM (Electron Microscope).

[0096] Here, impurities such as hydrogen or moisture mixed into the semiconductor layer 108 may cause transistor characteristics Therefore, in the semiconductor layer 108, hydrogen or water The fewer impurities such as fluorine, the better. By using a thin film, a transistor having excellent electrical characteristics can be fabricated. By reducing the impurity concentration and the defect level density (reducing oxygen vacancies), The carrier density of the metal oxide film can be reduced. The transistor has electrical characteristics in which the threshold voltage is negative (also known as normally on). In addition, a transistor using such a metal oxide film has a low off-state current. Significantly smaller characteristics can be obtained.

[0097] When a metal oxide film with high crystallinity is used for the semiconductor layer 108, the semiconductor layer 108 is easily processed. Damage to the insulating layer 110 during film formation can be suppressed, and a highly reliable transistor can be realized. On the other hand, by using a metal oxide film with a relatively low crystallinity for the semiconductor layer 108, This improves the electrical conductivity and allows for the realization of a transistor with high field-effect mobility.

[0098] The semiconductor layer 108 is a c-axis aligned crystal (CAAC) layer, which will be described later. Metal oxide film with stal structure, nc (nano crystal) structure Metal oxide films or metal oxide films with a mixture of CAAC and nc structures can be used. preferable.

[0099] The semiconductor layer 108 may have a stacked structure of two or more layers.

[0100] For example, the semiconductor layer 108 may be formed by stacking two or more metal oxide films having different compositions. For example, when an In-Ga-Zn oxide is used, the number of atoms of In, M, and Zn is The ratio of In:M:Zn=5:1:6, In:M:Zn=4:2:3, In:M:Zn= 1:1:1, In:M:Zn=2:2:1, In:M:Zn=1:3:4, In:M:Z The film formed with a sputtering target having n=1:3:2 or a value close to that range It is preferable to use two or more laminated layers.

[0101] In addition, the semiconductor layer 108 may be formed by stacking two or more metal oxide films having different crystallinity. In this case, by using the same oxide target and changing the film formation conditions, It is preferable that they are formed continuously without touching each other.

[0102] At this time, the semiconductor layer 108 is made of a metal oxide film having an nc structure and a metal oxide film having a CAAC structure. Alternatively, a metal oxide film having an nc structure may be formed. The semiconductor layer 108 may have a stacked structure of a metal oxide film and a metal oxide film having an nc structure. The function or material structure of metal oxides that can be suitably used for the semiconductor layer 108a and the semiconductor layer 108b The composition of the network is based on the Cloud-Aligned Composite (CAC) method described later. It can be used as a reference.

[0103] For example, the oxygen flow rate during the deposition of the first metal oxide film is set to be equal to the oxygen flow rate during the deposition of the second metal oxide film. The oxygen flow rate ratio is set to be smaller than that during the formation of the first metal oxide film. During film formation, oxygen is not allowed to flow. This prevents oxygen from flowing during film formation of the second metal oxide film. In addition, the first metal oxide film is more resistant to the oxidation than the second metal oxide film. On the other hand, the second layer provided on the upper side has a lower crystallinity and a higher electrical conductivity. The second metal oxide film is made to have higher crystallinity than the first metal oxide film, thereby Damage during processing of the insulating layer 08 and during deposition of the insulating layer 110 can be suppressed.

[0104] More specifically, the oxygen flow rate ratio during the formation of the first metal oxide film is set to 0% or more and less than 50%. Preferably, it is 0% or more and 30% or less, more preferably 0% or more and 20% or less, and typically 10%. The oxygen flow rate ratio during the formation of the second metal oxide film is set to 50% or more and 100% or less, preferably Preferably, it is 60% or more and 100% or less, more preferably, 80% or more and 100% or less, and even more preferably The first metal oxide film is preferably 90% or more and 100% or less, and typically 100%. The conditions for forming the first metal oxide film and the second metal oxide film, such as pressure, temperature, and power, may be different. By keeping the conditions other than the oxygen flow rate the same, the time required for the film formation process can be shortened. This is preferable.

[0105] By adopting such a configuration, the transistor 100 has excellent electrical characteristics and high reliability. This can be achieved.

[0106] Next, an example in which the configuration is partially different from that of the above-described transistor 100 will be described.

[0107] 3A is a top view of the transistor 100A, and FIG. 3B is a top view of the transistor 100B. 3(C) is a cross-sectional view of the channel length direction of the transistor 100A, and FIG. 3(D) is a cross-sectional view of the channel width direction of the transistor 100A. 1 is a cross-sectional view in the direction of the arrow.

[0108] The transistor 100A is different from the transistor 100A in that the region 108n contains the impurity element. The main difference is with 100.

[0109] The insulating layer 103 has a region containing the above-described impurity element near the interface where the insulating layer 103 contacts the insulating layer 118. The region 103d may also have a region 103d near the interface where it contacts the region 108n. In this case, the impurity concentration of the portion overlapping with the region 108n is set to the same as that of the insulating layer The concentration may be lower than that of the area in contact with 118.

[0110] In the region 103d, the insulating layer 118 is formed and then subjected to heat treatment, and the insulating layer 118 The impurity element can be diffused into the insulating layer 103. The impurity element contained in the semiconductor layer 118 is diffused into the semiconductor layer 108, and the region 118 containing the impurity element is formed. Thus, the region 108n containing the impurity element can be formed at the same time as the region 108n containing the impurity element is formed. 110d can be formed in a self-aligned manner. The region 108n can also be said to be a region having a higher concentration of impurity elements than the channel formation region. When the insulating layer 118 is formed, the region 108n and the region 108n containing the impurity element can be formed. A region 103d may be formed.

[0111] FIG. 2(B) shows an enlarged cross-sectional view of the area Q surrounded by the dashed line in FIG. 3(B). .

[0112] When the region 108n contains an impurity element, the impurity element in the region 108n is transferred to the insulating layer 118. It is preferable to have a concentration gradient such that the concentration increases as the distance increases. Since the resistance becomes lower toward the upper part of 8n, the contact resistance with the conductive layer 120a (or conductive layer 120b) In addition, the resistance can be reduced more effectively. Since the total amount of impurity elements in the region 108n can be reduced compared to when the region 108n is formed, This allows the amount of impurities that can diffuse into the channel formation region due to the influence of heat, etc., to be kept low. The concentration of the impurity element in the region 108n depends on the conditions for forming the insulating layer 118 and the thickness of the insulating layer 118. The temperature and time of the heat treatment carried out after the formation of the film can be adjusted.

[0113] In FIG. 2B and other figures, the portion of the insulating layer 103 with a high concentration of impurity elements is To exaggerate the position of the region 103d in the insulating layer 103 near the interface with the insulating layer 8, Although the hatched pattern is shown only near the insulating layer 118, in reality, the insulating layer The impurity element may be contained throughout the entire thickness of 103 .

[0114] The region 108n and the region 103d each have an impurity concentration of 1×10 19 atoms / cm 3 That's it, 1×10 23 atoms / cm 3 Less than or equal to 5 x 10 19 atoms / cm 3 That's it, 5 x 10 22 atoms / cm 3 Less than or equal to 1×10 20 at oms / cm 3 That's it, 1×10 22 atoms / cm 3 It is preferred to include areas that are: It's nice.

[0115] The concentration of impurities contained in the region 108n and the region 103d is measured by, for example, secondary ion mass spectrometry. It can be analyzed by analytical methods such as SIMS and X-ray photoelectron spectroscopy (XPS). When using XPS analysis, ion sputtering from the front or back side and XPS By combining this with S analysis, the concentration distribution in the depth direction can be determined.

[0116] In the region 108n, the impurity element is preferably present in an oxidized state. For example, impurity elements such as boron, phosphorus, magnesium, aluminum, and silicon are used. It is preferable to use such an element that is easily oxidized. Since it can exist stably in a state of being bonded to oxygen in the conductor layer 108, it can be easily treated at a high temperature (e.g. Even if exposed to temperatures above 400°C, 600°C, or 800°C, Furthermore, the impurity element removes oxygen from the semiconductor layer 108, thereby preventing the region from being separated. There are many oxygen vacancies (V O ) is generated. This oxygen vacancy (V O ) and in the membrane V bonded to hydrogen O The formation of H increases the carrier density, and the region 108n becomes polar The resistance becomes extremely low.

[0117] When a high-temperature process is performed in a later step, the film may be heated from the outside or the film near the region 108n. If too much oxygen is supplied to the region 108n, the resistance may increase. Therefore, when performing a high-temperature process, the insulating layer 1 having a high barrier property against oxygen is required. It is preferable to treat the material while it is covered with 18.

[0118] Also in the region 103d, the impurity element is preferably present in an oxidized state. Such easily oxidizable elements are stable in a state of being bonded to oxygen in the insulating layer 103. Therefore, even if high temperatures are applied in the subsequent steps, desorption is suppressed. In particular, when the insulating layer 103 contains oxygen (also called excess oxygen) that can be desorbed by heating, In this case, the excess oxygen and the impurity element are bonded and stabilized, so that the region 103d to the region It is possible to suppress the supply of oxygen to 108n. The region 103d containing the element is in a state where oxygen is less likely to diffuse. Furthermore, oxygen is prevented from being supplied to the region 108n from above via the region 103d. can be done.

[0119] For example, when boron is used as an impurity element, the impurity contained in the region 108n and the region 103d is The boron in the sample can exist in a state bonded to oxygen. This is evident from the XPS analysis of B2 This can be confirmed by observing the spectral peaks due to O3 bonds. In this case, no spectral peaks due to the existence of elemental boron are observed. or the peak intensity is so small that it is buried in the background noise at the lower limit of measurement. It gets smaller.

[0120] The region 103d may also be provided near the interface in contact with the region 108n. The impurity concentration of the portion overlapping with the region 108n is lower than that of the portion in contact with the insulating layer 110. It becomes degrees.

[0121] The above is the explanation of the first configuration example.

[0122] <Configuration example 2> An example of a transistor having a configuration that is partially different from that of the above-described Configuration Example 1 will be described below. In the following, explanations of parts that overlap with Configuration Example 1 may be omitted. In the drawings, hatched patterns are used to indicate parts that have the same functions as the above configuration example. Similarly, there are cases where no symbol is attached.

[0123] 4A is a top view of the transistor 100B, and FIG. 4B is a top view of the transistor 100C. 4(C) is a cross-sectional view of the transistor 100B in the channel length direction, and FIG. 4(D) is a cross-sectional view of the transistor 100B in the channel width direction. 1 is a cross-sectional view in the direction of the arrow.

[0124] Transistor 100B has insulating layer 110 extending over region 108n and insulating layer 103. The transistor 100B is mainly different from the first configuration example in that it is formed by insulating The layer 110 is provided in contact with the upper and side surfaces of the semiconductor layer 108 and the upper surface of the insulating layer 103. and has a region that does not overlap with the conductive layer 112.

[0125] FIG. 2(C) shows an enlarged cross-sectional view of the region R surrounded by the dashed line in FIG. 4(B). .

[0126] In the transistor 100B, the region 108n may contain the impurity elements described above. In the region 108n, the impurity element has a concentration gradient such that the concentration increases as it approaches the insulating layer 110. It is preferable that the upper part of the region 108n has a lower resistance. Therefore, the contact resistance with the conductive layer 120a (or the conductive layer 120b) can be more effectively reduced. In addition, compared to when the density is uniform across the entire region 108n, Since the total amount of impurity elements can be reduced, the channel formation region can be prevented from being affected by heat during the manufacturing process. The amount of impurities that can diffuse into the region can be kept small. The degree of the insulating layer 118 depends on the thickness of the insulating layer 110, the conditions for forming the insulating layer 118, and the thickness of the insulating layer 118 after the insulating layer 118 is formed. This can be adjusted by the temperature and time of the heat treatment.

[0127] The insulating layer 110 has a region 108n and a region 110d that contacts the insulating layer 103. 110d contains the above-mentioned impurity element. As shown, the region 110d is not provided in the portion in contact with the channel forming region of the semiconductor layer 108. It is preferable that this is not the case.

[0128] In the insulating layer 110 using an oxide film capable of releasing oxygen by heating, The element-containing region 110d can suppress the release of oxygen compared to other regions. Therefore, the region 110d functions as a barrier layer against oxygen, and the oxygen supplied to the region 108n This can effectively reduce the amount of

[0129] In the region 110d, the insulating layer 118 is formed and then subjected to heat treatment, so that the insulating layer 118 The impurity element can be diffused into the insulating layer 110. The element also diffuses into the semiconductor layer 108, so that the region 108n can contain the impurity element. Cut.

[0130] The region 110d has an impurity concentration of 1×10 19 atoms / cm 3 That's it, 1×10 23 a toms / cm 3 Less than or equal to 5 x 10 19 atoms / cm 3 That's it, 5 x 10 22 atoms / cm 3Less than or equal to 1×10 20 atoms / cm 3 That's it, 1×1 0 22 atoms / cm 3 Preferably, the region 108n includes a region where: , the region 108n has a portion with a higher impurity concentration than the region 110d of the insulating layer 110. This is preferable because it can more effectively reduce the electrical resistance of the

[0131] The concentration of impurities contained in the region 110d can be measured by, for example, secondary ion mass spectrometry (SIMS) or The analysis can be performed using analytical methods such as X-ray photoelectron spectroscopy (XPS). If so, ion sputtering from the front or back side can be combined with XPS analysis. By doing so, the concentration distribution in the depth direction can be determined.

[0132] In the region 110d, the impurity element is preferably present in an oxidized state. For example, impurity elements such as boron, phosphorus, magnesium, aluminum, and silicon are used. It is preferable to use such an element that is easily oxidized. Since it can exist stably in a state of being bonded to oxygen in the insulating layer 110, it can be used at high temperatures in the subsequent process. In particular, even if the insulating layer 110 is heated, the desorption is suppressed. When oxygen (also called excess oxygen) is contained, the excess oxygen and impurity elements are bonded to each other. In order to stabilize the region 108n, oxygen is prevented from being supplied from the region 110d to the region 108n. In addition, the region 110d containing the oxidized impurity element can be formed by diffusing oxygen. Therefore, the area 110d is formed from above the area 110d through the area 110d. It also prevents oxygen from being supplied to 08n.

[0133] For example, when boron is used as the impurity element, the boron contained in the region 110d is mixed with oxygen. This is due to the B2O3 bond in the XPS analysis. In addition, the XPS analysis revealed that the boron Spectral peaks due to the existence of elements in their free state are not observed, or are at the lower limit of measurement. The peak intensity becomes so small that it is buried in the background noise.

[0134] The insulating layer 103 has a region containing the above-mentioned impurity element near the interface where it contacts the insulating layer 110. The region 103d may also have a region 103d near the interface where it contacts the region 108n. In this case, the impurity concentration of the portion overlapping with the region 108n is set to the same as that of the insulating layer The density is lower than that of the area in contact with 110.

[0135] Next, an example in which the configuration is partially different from that of the above-described transistor 100B will be described.

[0136] 5A is a top view of the transistor 100C, and FIG. 5B is a top view of the transistor 100C. 5(C) is a cross-sectional view of the transistor 100C in the channel length direction, and FIG. 5(D) is a cross-sectional view of the transistor 100C in the channel width direction. 1 is a cross-sectional view in the direction of the arrow.

[0137] The transistor 100C has a structure similar to that of the transistor 100A in that the insulating layer 110 has regions of different thicknesses. The main differences are with the TA100B.

[0138] FIG. 2(D) shows an enlarged cross-sectional view of the area S surrounded by the dashed line in FIG. 5(B). .

[0139] In the transistor 100D, the thickness of the insulating layer 110 in the region overlapping with the conductive layer 112 is In comparison, the insulating layer 110 in the region not overlapping the conductive layer 112, i.e., the region 110d, has a thin film thickness. By adopting such a configuration, the distance between the insulating layer 118 and the region 108n is shortened, and the region The impurity concentration in the region 108n can be increased. Also, the thickness of the region 110d can be adjusted. This makes it easy to adjust the concentration of the impurity element in the region 108n. The concentration of the impurity element can be adjusted by the temperature and time of the heat treatment performed after the insulating layer 118 is formed. It is possible.

[0140] This concludes the description of configuration example 2.

[0141] <Configuration example 3> An example of a transistor having a configuration that is partially different from that of the above-described Configuration Example 1 will be described below. In the following, explanations of parts that overlap with Configuration Example 1 may be omitted. In the drawings, hatched patterns are used to indicate parts that have the same functions as the above configuration example. Similarly, there are cases where no symbol is attached.

[0142] FIG. 6A is a top view of transistor 100D, and FIG. 6B is a top view of transistor 100D. 6(C) is a cross-sectional view of the transistor 100D in the channel length direction, and FIG. 6(D) is a cross-sectional view of the transistor 100D in the channel width direction. 1 is a cross-sectional view in the direction of the arrow.

[0143] The transistor 100D has a conductive layer 106 between the substrate 102 and the insulating layer 103. The main difference from the transistor 100 is that the conductive layer 106 is a semiconductor layer 108 and a conductive layer 112.

[0144] FIG. 7A is a top view of a transistor 100E, and FIG. FIG. 7B) is a cross-sectional view of the transistor 100E in the channel length direction, and FIG. 7C) is a cross-sectional view of the transistor 100E in the channel length direction. FIG. 1 is a cross-sectional view of the capacitor 100E in the channel width direction.

[0145] The transistor 100E has a conductive layer 106 between the substrate 102 and the insulating layer 103. The main difference from transistor 100C is that conductive layer 106 is formed between semiconductor layer 108 and conductive layer 109. It has an area that overlaps with layer 112 .

[0146] In the transistor 100D and the transistor 100E, the conductive layer 106 is a first gate electrode. The conductive layer 112 functions as a second gate electrode (also referred to as a bottom gate electrode). The insulating layer 103 also functions as a gate electrode (also referred to as a top gate electrode). A portion of the insulating layer 110 functions as a first gate insulating layer, and a portion of the insulating layer 110 functions as a second gate insulating layer. It works like this.

[0147] The portion of the semiconductor layer 108 that overlaps with at least one of the conductive layer 112 and the conductive layer 106 , which functions as a channel forming region. The portion of the conductive layer 112 of the conductive film 8 is sometimes called a channel forming region. The area (including the area 108n) that does not overlap with the layer 112 but overlaps with the conductive layer 106 is also A channel can be formed.

[0148] As shown in FIG. 6C and FIG. 7C, the conductive layer 106 is formed by the metal oxide layer 114. , the conductive layer 112 and the insulating layer 103 are connected to each other through openings 142 formed in the insulating layer 110 and the insulating layer 103. The conductive layer 106 and the conductive layer 112 may be electrically connected to each other. can be given a rank.

[0149] The conductive layer 106 is made of the same material as the conductive layer 112, the conductive layer 120a, or the conductive layer 120b. In particular, when a material containing copper is used for the conductive layer 106, the wiring resistance can be reduced. This is preferable because it can be done easily.

[0150] As shown in FIGS. 6(A), 6(C), 7(A) and 7(C), the channel width In the direction, the conductive layer 112 and the conductive layer 106 protrude outward beyond the end of the semiconductor layer 108. At this time, as shown in FIG. 6(C) and FIG. 7(C), The entire layer 108 in the channel width direction is connected to the conductive layer 11 via the insulating layer 110 and the insulating layer 103. 2 and the conductive layer 106.

[0151] With this configuration, the semiconductor layer 108 is subjected to an electric field generated by the pair of gate electrodes. In this case, the conductive layer 106 and the conductive layer 112 are electrically surrounded by the same material. It is preferable to apply a potential to the semiconductor layer 108. This induces a channel in the semiconductor layer 108. Since the electric field can be effectively applied, the on-state of the transistor 100D and the transistor 100E Therefore, the transistor 100D and the transistor 100C can increase the on-state current. It will also be possible to miniaturize 00E.

[0152] The conductive layer 112 and the conductive layer 106 may not be connected to each other. A constant potential is applied to one of the gate electrodes of the transistors 100D and 100E. A signal for driving the electrode 0E may be applied. At this time, the potential applied to one of the electrodes is The threshold voltage when the transistor 100D and the transistor 100E are driven by the other electrode is The pressure can also be controlled.

[0153] This concludes the description of configuration example 3.

[0154] <Application example> In the following description, a semiconductor film containing impurities is used as one electrode of a capacitor element, and a transistor is An example in which the capacitor element is formed on the same surface will be described.

[0155] In the cross-sectional view shown in FIG. 8A, a capacitor is arranged next to the transistor 100 illustrated in Configuration Example 1. An element 130A is provided.

[0156] In the cross-sectional view shown in FIG. 8B, the transistor 100D illustrated in Configuration Example 3 is A capacitance element 130A is provided.

[0157] The capacitive element 130A is formed between the semiconductor layer 108c and the conductive layer 120b, and functions as a dielectric. The insulating layer 110 and the insulating layer 118 are provided.

[0158] The semiconductor layer 108c is provided on the same plane as the semiconductor layer 108. For example, the semiconductor layer 1 The region 108c is formed by processing the same metal oxide film as the semiconductor layer 108, and then forming the same impurity layer as the region 108n. It can be formed by adding a pure element.

[0159] By adopting such a configuration, the capacitor element 130A can be manufactured without increasing the number of steps. can be done.

[0160] The capacitor 130B shown in FIG. 8C has a conductive layer 106c and a semiconductor layer 108c. The semiconductor device has a configuration in which an insulating layer 103 is provided, which functions as a dielectric.

[0161] The conductive layer 106c is provided on the same surface as the conductive layer 106. The conductive layer 106 can be formed by processing the same conductive film.

[0162] The capacitance element 130B can have a thinner dielectric than the capacitance element 130A, so A large-capacitance capacitive element can be formed.

[0163] The above is a description of the application example.

[0164] <Components of semiconductor device> Next, the components included in the semiconductor device of this embodiment will be described in detail.

[0165] [substrate] There is no particular restriction on the material of the substrate 102, but it should be strong enough to withstand the subsequent heat treatment. For example, single crystals made of silicon or silicon carbide are Semiconductor substrates, polycrystalline semiconductor substrates, compound semiconductor substrates such as silicon germanium, SOI substrates The substrate 102 may be a plate, a glass substrate, a ceramic substrate, a quartz substrate, a sapphire substrate, or the like. In addition, a substrate having a semiconductor element formed thereon may be referred to as the substrate 102. It may be used.

[0166] In addition, a flexible substrate is used as the substrate 102, and the transistor 10 is directly formed on the flexible substrate. Alternatively, a peeling layer may be provided between the substrate 102 and the transistor 100. The release layer may be removed from the substrate 102 after a semiconductor device is partially or completely completed thereon. The transistor 10 can be separated and transferred to another substrate. 0 etc. can be transferred to substrates with poor heat resistance or flexible substrates.

[0167] [Insulating layer 103] The insulating layer 103 can be formed by sputtering, CVD, evaporation, pulsed laser deposition ( The insulating layer 103 can be formed by using a suitable method such as pulsed laser deposition (PLD). The insulating film can be formed as a single layer or a stack of an oxide insulating film or a nitride insulating film. In order to improve the interface characteristics with the semiconductor layer 108, at least the semiconductor The region in contact with the insulating layer 103 is preferably formed using an oxide insulating film. It is preferable to use a film that releases oxygen when heated.

[0168] The insulating layer 103 may be made of, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, or nitride. silicon oxide, aluminum oxide, hafnium oxide, gallium oxide or Ga-Zn oxide The above may be used, and the layer may be formed as a single layer or a laminate.

[0169] In addition, the insulating layer 103 may have a film other than an oxide film such as a silicon nitride film on the side in contact with the semiconductor layer 108. When the film is used, the surface in contact with the semiconductor layer 108 is pretreated with oxygen plasma or the like. and oxidizing the surface or the vicinity of the surface.

[0170] [Conductive film] The conductive layer 112 and the conductive layer 106 function as a gate electrode and a source electrode, respectively. The conductive layer 120a and the conductive layer 120b functioning as a drain electrode may be made of chromium, copper, or aluminum. Aluminum, gold, silver, zinc, molybdenum, tantalum, titanium, tungsten, manganese, A metal element selected from nickel, iron, and cobalt, or a composite containing the above metal elements. They can be formed using gold or an alloy combining the above-mentioned metal elements.

[0171] In addition, the conductive layer 112, the conductive layer 106, the conductive layer 120a, and the conductive layer 120b contain In. -Sn oxide, In-W oxide, In-W-Zn oxide, In-Ti oxide, In-Ti -Sn oxide, In-Zn oxide, In-Sn-Si oxide, In-Ga-Zn oxide, etc. An oxide conductor or a metal oxide film can also be applied.

[0172] Here, an oxide conductor (OC) will be described. For example, oxygen vacancies are formed in a metal oxide having semiconductor properties, and hydrogen is added to the oxygen vacancies. When the metal oxide is heated, a donor level is formed near the conduction band. As a result, the metal oxide becomes highly conductive. The metal oxide that has been made conductive can be called an oxide conductor.

[0173] In addition, as the conductive layer 112, a conductive film containing the oxide conductor (metal oxide) and a metal Alternatively, a laminated structure of a conductive film containing a metal or an alloy may be used. In this case, the insulating layer that functions as a gate insulating film is It is preferable to apply a conductive film containing an oxide conductor to the side in contact with the edge layer.

[0174] The conductive layers 112, 106, 120a, and 120b are made of the above-mentioned gold. Among the group elements, titanium, tungsten, tantalum, and molybdenum are particularly preferred. It is particularly preferable to use a tantalum nitride film. The tantalum nitride film has electrical conductivity and has the following properties with respect to copper, oxygen, or hydrogen: Since the barrier layer 104 has a high barrier property and releases little hydrogen from itself, it is preferable that the barrier layer 104 is in contact with the semiconductor layer 108. It can be suitably used as a conductive film or a conductive film in the vicinity of the semiconductor layer 108 .

[0175] [Insulating layer 110] The insulating layer 110, which functions as a gate insulating film for the transistor 100, etc., is formed by PECVD. The insulating layer 110 can be formed by a sputtering method or the like. silicon nitride film, silicon oxide nitride film, silicon nitride film, aluminum oxide film, hafnium oxide film um film, yttrium oxide film, zirconium oxide film, gallium oxide film, tantalum oxide film, One or more of magnesium oxide film, lanthanum oxide film, cerium oxide film, and neodymium oxide film The insulating layer 110 may have a two-layer laminate structure or a three-layer or more laminate structure. The above laminated structure may also be used.

[0176] The insulating layer 110 in contact with the semiconductor layer 108 is preferably an oxide insulating film. It is more preferable to have a region containing oxygen in excess of the stoichiometric composition. The insulating layer 110 is an insulating film capable of releasing oxygen. For example, The insulating layer 110 is formed by the above method, and the insulating layer 110 after the film formation is subjected to a heat treatment in an oxygen atmosphere. Alternatively, an oxide film may be formed on the insulating layer 110 in an oxygen atmosphere. Oxygen can also be supplied into the insulating layer 110 by, for example, forming a film.

[0177] In addition, the insulating layer 110 is made of a material having a higher dielectric constant than silicon oxide or silicon oxynitride. Materials such as hafnium oxide can also be used. This allows the thickness of the insulating layer 110 to be increased. The leakage current due to the tunnel current can be suppressed. In particular, hafnium oxide, which has crystallinity, It is preferable because it has a higher relative dielectric constant than crystalline hafnium oxide.

[0178] [Semiconductor layer] When the semiconductor layer 108 is an In-M-Zn oxide, in order to form an In-M-Zn oxide film, The sputtering target used in this method must have an In atomic ratio equal to or greater than the M atomic ratio. The atomic ratio of the metal elements in such a sputtering target is preferably In:M :Zn=1:1:1, In:M:Zn=1:1:1.2, In:M:Zn=2:1:3, In:M:Zn=3:1:2, In:M:Zn=4:2:3, In:M:Zn=4:2: 4.1, In:M:Zn=5:1:6, In:M:Zn=5:1:7, In:M:Zn= 5:1:8, In:M:Zn=6:1:6, In:M:Zn=5:2:5, etc. .

[0179] In addition, a target containing a polycrystalline oxide is used as the sputtering target. This is preferable because the semiconductor layer 108 can be easily formed with crystallinity. The atomic ratio of the semiconductor layer 108 is determined by the atomic ratio of the metal elements contained in the sputtering target. The ratio of the number of atoms may vary by ±40%. When the composition of the ring target is In:Ga:Zn=4:2:4.1 [atomic ratio], film formation The composition of the semiconductor layer 108 is approximately In:Ga:Zn=4:2:3 [atomic ratio]. This may be the case.

[0180] When the atomic ratio is described as In:Ga:Zn=4:2:3 or in the vicinity, it means In When the atomic ratio of Ga is 4, the atomic ratio of Ga is 1 or more and 3 or less, and the atomic ratio of Zn is 2 The atomic ratio of In:Ga:Zn is 5:1:6 or more. When describing it as being in the vicinity of , when the atomic ratio of In is 5, the atomic ratio of Ga is 0. The atomic ratio of Zn is greater than 1 and less than 2, and includes the case where the atomic ratio of Zn is greater than 5 and less than 7. When describing that the atomic ratio is In:Ga:Zn=1:1:1 or close to it, When the atomic ratio of Ga is 1, the atomic ratio of Zn is 0.1 or more and 2 or less. This includes cases where the numerical ratio is greater than 0.1 and less than 2.

[0181] The semiconductor layer 108 has an energy gap of 2 eV or more, preferably 2.5 eV or more. In this way, by using metal oxides with a wider energy gap than silicon, As a result, the off-state current of the transistor can be reduced.

[0182] The semiconductor layer 108 preferably has a non-single-crystal structure. This includes the CAAC structure, polycrystalline structure, microcrystalline structure, and amorphous structure, which will be described later. In the structure, the amorphous structure has the highest defect level density, and the CAAC structure has the lowest defect level density. low.

[0183] Below, we explain about CAAC (c-axis aligned crystal). CAAC represents an example of a crystal structure.

[0184] The CAAC structure has multiple nanocrystals (crystalline regions with a maximum diameter of less than 10 nm). It is one of the crystalline structures of thin films, etc., and each nanocrystal has a c-axis oriented in a specific direction and a-axis and The b-axis and b-axis do not have any orientation, and the nanocrystals are continuously connected without forming grain boundaries. In particular, thin films with a CAAC structure have the following characteristics: The c-axis of the thin film is oriented in the thickness direction, the normal direction to the surface on which it is formed, or the normal direction to the surface of the thin film. It has the characteristic of being easy to use.

[0185] CAAC-OS (Oxide Semiconductor) is a highly crystalline oxide semiconductor. On the other hand, CAAC-OS has no clear grain boundaries, It can be said that the decrease in electron mobility caused by the grain boundaries is unlikely to occur. Crystallinity can be reduced by the inclusion of impurities or the generation of defects. It can be said that CAAC- is an oxide semiconductor with few impurities and defects (such as oxygen vacancies). Oxide semiconductors containing an OS have stable physical properties. Oxide semiconductors are heat resistant and highly reliable.

[0186] In crystallography, the three axes that make up the unit cell, the a-axis, the b-axis, and the c-axis (crystal It is common to take a unit cell with a specific axis as the c-axis for the layer structure. In a crystal with this structure, the two axes parallel to the plane direction of the layers are the a-axis and the b-axis, and the axis intersecting the layers is the The c-axis is generally defined as the plane of the crystal. Graphite is classified as a hexagonal crystal, and the a-axis and b-axis of the unit cell are parallel to the cleavage plane. The c-axis is perpendicular to the cleavage plane. For example, the layered structure of YbFe2O4 type crystal structure The crystal of InGaZnO4 can be classified as a hexagonal system, and the a-axis and The a and b axes are parallel to the plane direction of the layer, and the c axis is perpendicular to the layer (i.e., the a and b axes).

[0187] An oxide semiconductor film with a microcrystalline structure (microcrystalline oxide semiconductor film) is observed by TEM. In some cases, it may not be possible to clearly identify the crystal parts in the microcrystalline oxide semiconductor film. The crystal part to be formed has a size of 1 nm or more and 100 nm or less, or 1 nm or more and 10 nm or less. In particular, microcrystals of 1 nm to 10 nm or 1 nm to 3 nm are often An oxide semiconductor film having nanocrystals (nc) is called nc-OS. (nanocrystalline oxide semiconductor) film In addition, the grain boundaries of the nc-OS film can be clearly seen in the TEM image. It may not be possible.

[0188] The nc-OS film is a microscopic region (e.g., a region of 1 nm to 10 nm, especially a region of 1 nm or less). The nc-OS film has a periodic atomic arrangement in the region of 3 nm or less. There is no regularity in the crystal orientation between the crystal parts, and therefore no orientation is observed throughout the film. Therefore, the nc-OS film cannot be distinguished from an amorphous oxide semiconductor film depending on the analytical method. For example, XRD, which uses X-rays with a diameter larger than that of the crystal part, is used for nc-OS films. When structural analysis is performed using the device, the crystal plane is analyzed using the out-of-plane method. In addition, the peaks shown in the figure are not detected in the nc-OS film because the probe diameter is larger than that of the crystalline part. Electron beam diffraction (also called selected area electron beam diffraction) using an electron beam (for example, 50 nm or larger) When the diffraction pattern is changed to nc-OS film, a halo-like diffraction pattern is observed. The probe diameter is close to or smaller than the size of the crystal part (for example, 1 nm or more and 30 nm or less). When electron beam diffraction (also called nanobeam electron diffraction) is performed using the electron beam (bottom), a circle is drawn. A bright area (ring-shaped) is observed, and multiple spots are observed within the ring-shaped area. Spots may be observed where spots may be observed.

[0189] The nc-OS film has a lower density of defect states than the amorphous oxide semiconductor film. In the S film, there is no regularity in the crystal orientation between different crystal parts. Therefore, the nc-OS film The defect density of the nc-OS film is higher than that of the CAAC-OS film. Compared to the OS film, the carrier density is higher and the electron mobility may be higher. A transistor including an -OS film can exhibit high field-effect mobility.

[0190] The nc-OS film can be formed with a smaller oxygen flow rate than the CAAC-OS film. In addition, the nc-OS film can be formed at a low temperature compared to the CAAC-OS film. For example, the nc-OS film can be formed by lowering the substrate temperature. A state where the temperature is relatively low (for example, below 130°C) or the substrate is not heated. It is suitable for large glass substrates and resin substrates, and can be used for production. It can improve sexuality.

[0191] An example of the crystal structure of a metal oxide will be described below. Sputtering was performed using a Zn oxide target (In:Ga:Zn=4:2:4.1 [atomic ratio]). The following will be explained as an example of a metal oxide film formed by the ring method. Metal oxide formed by sputtering at a plate temperature of 100°C to 130°C is either the nc (nano crystal) structure or the CAAC structure. On the other hand, if the substrate temperature is set to room temperature (RT), Metal oxides formed by sputtering tend to have an nc crystal structure. The term room temperature (RT) as used herein includes the temperature at which the substrate is not heated.

[0192] [Metal oxide composition] Hereinafter, a CAC (C This paper explains the structure of the Cloud-Aligned Composite OS.

[0193] In this specification, CAAC (c-axis aligned crystal) l), and when written as CAC (Cloud-Aligned Composite) CAAC represents an example of a crystal structure, and CAC represents a function or a material configuration. Represents an example.

[0194] CAC-OS or CAC-metal oxide is a material that has a conductive function in some parts. The material has insulating properties in some parts and semiconductor properties in the whole material. Note that CAC-OS or CAC-metal oxide is used as the active material for the transistor. When used in a layer, the conductive function is to allow electrons (or holes) to flow as carriers. The insulating function is to prevent the flow of electrons, which act as carriers. By making the functions of the two complementary to each other, the switching function (On / Off) is realized. The function of activating the CAC-OS or CAC-metal oxide can be added. In CAC-OS or CAC-metal oxide, each function is separated. By combining these, the functions of both can be maximized.

[0195] In addition, CAC-OS or CAC-metal oxide is a conductive region and an insulating region. The conductive region has the above-mentioned conductive function, and the insulating region has the above-mentioned insulating function. In addition, the conductive region and the insulating region in the material are formed by nanoparticle layers. The conductive and insulating regions may be separated by a bell. In addition, the conductive area may be observed as a cloud-like connected area with a blurred periphery. This may be the case.

[0196] In addition, in the CAC-OS or CAC-metal oxide, a conductive region and The insulating regions are each 0.5 nm to 10 nm, preferably 0.5 nm to 3 nm. They may be dispersed in the material at sizes of less than 1 m.

[0197] In addition, CAC-OS or CAC-metal oxide has different band gaps For example, CAC-OS or CAC-metal ox The ide consists of a wide-gap component due to the insulating region and a conductive component due to the conductive region. In this configuration, when carriers flow, In addition, carriers mainly flow in the narrow gap component. The component with a narrow gap acts complementary to the component with a wide gap. Carriers also flow into the wide-gap component in conjunction with the component that has a wide gap. CAC-OS or CAC-metal oxide is used as the channel formation region of the transistor. When used in a transistor, it has a high current driving force in the on-state, i.e., a large on-current. , and high field-effect mobility can be obtained.

[0198] That is, CAC-OS or CAC-metal oxide is a matrix composite. matrix composite, or metal matrix composite It can also be called a matrix composite.

[0199] This concludes the description of the components.

[0200] <Production method example 1> An example of a method for manufacturing a transistor of one embodiment of the present invention will be described below. The transistor 100D illustrated in Configuration Example 3 will be described as an example.

[0201] The thin films (insulating films, semiconductor films, conductive films, etc.) that constitute the semiconductor device are formed by sputtering. method, chemical vapor deposition (CVD) method , vacuum evaporation, pulsed laser deposition (PLD) tion) method, Atomic Layer Deposition (ALD) method The CVD method can be a plasma chemical vapor deposition (PE CVD (Plasma Enhanced CVD) and thermal CVD. One of the thermal CVD methods is metal organic chemical vapor deposition (MOCVD). There is a method called ic CVD.

[0202] In addition, thin films (insulating films, semiconductor films, conductive films, etc.) that constitute semiconductor devices are formed by spin coating, Dip, spray application, inkjet, dispensing, screen printing, offset Printing, doctor knife, slit coating, roll coating, curtain coating, knife coating It can be formed by the following methods.

[0203] Furthermore, when processing the thin films that make up the semiconductor device, photolithography and other methods are used. Other methods include nanoimprinting, sandblasting, and lift-off. The thin film may be processed by a method such as a masking method. The island-shaped thin film may be directly formed by the film method.

[0204] There are two typical photolithography methods: A resist mask is formed on the thin film to be processed by etching or the like. The other method is to remove the photomask after forming a photosensitive thin film. Then, the thin film is processed into a desired shape by performing development.

[0205] In photolithography, the light used for exposure is, for example, i-line (wavelength 365 nm), It uses g-ray (wavelength 436 nm), h-ray (wavelength 405 nm), or a mixture of these. In addition, ultraviolet light, KrF laser light, ArF laser light, etc. can be used. The exposure may also be performed by immersion exposure. Using extreme ultraviolet (EUV) and X-rays, Also, electron beams can be used instead of light for exposure. The use of light, X-rays or electron beams is preferred because it allows for extremely fine processing. When exposure is performed by scanning a beam such as an electron beam, the photomask It is unnecessary.

[0206] There are three methods for etching thin films: dry etching, wet etching, and sandblasting. Methods such as these can be used.

[0207] 9 and 10 show the transistor 100D at each stage of the manufacturing process. The cross sections in the channel length direction and the channel width direction are shown side by side.

[0208] [Formation of Conductive Layer 106] A conductive film is formed on the substrate 102 and processed by etching to form a gate electrode. A functional conductive layer 106 is formed.

[0209] [Formation of insulating layer 103] Subsequently, an insulating layer 103 is formed to cover the substrate 102 and the conductive layer 106 (FIG. 9(A)). The insulating layer 103 can be formed by using a PECVD method, an ALD method, a sputtering method, or the like. can.

[0210] After the insulating layer 103 is formed, a treatment for supplying oxygen to the insulating layer 103 may be performed. For example, plasma treatment or heat treatment can be performed in an oxygen atmosphere. The insulating layer 103 is doped with oxygen by plasma ion doping or ion implantation. Good too.

[0211] [Formation of semiconductor layer 108] Next, a metal oxide film is formed on the insulating layer 103 and processed to form island-shaped semiconductor layers. The conductor layer 108 is formed (FIG. 9(B)).

[0212] The metal oxide film is formed by a sputtering method using a metal oxide target. is preferred.

[0213] In addition, when forming a metal oxide film, in addition to oxygen gas, an inert gas (e.g., helium Gases such as argon gas and xenon gas may be mixed. The higher the ratio of oxygen gas to the total deposition gas when depositing a film (hereinafter referred to as the oxygen flow ratio), This can improve the crystallinity of the metal oxide film, enabling the realization of highly reliable transistors. On the other hand, the lower the oxygen flow rate ratio, the lower the crystallinity of the metal oxide film, and the higher the on-current. The transistor may be a transistor having a gate resistance.

[0214] The metal oxide film is formed under the following conditions: the substrate temperature is preferably from room temperature to 200° C. For example, the film formation temperature may be set to between room temperature and 140°C. If the temperature is less than 1000°C, productivity will be increased, which is preferable. By forming a metal oxide film in the absence of a metal oxide film, the crystallinity can be reduced.

[0215] In addition, before forming the metal oxide film, water, hydrogen, and organic substances adsorbed on the surface of the insulating layer 103 are removed. It is preferable to perform a treatment for removing components or a treatment for supplying oxygen into the insulating layer 103. For example, heat treatment is preferably performed at a temperature of 70°C or higher and 200°C or lower in a reduced pressure atmosphere. Alternatively, plasma treatment may be performed in an atmosphere containing oxygen. When plasma treatment containing nitrogen oxide gas is performed, organic substances on the surface of the insulating layer 103 are suitably removed. After such a treatment, the surface of the insulating layer 103 can be removed without being exposed to the atmosphere. It is preferable to deposit the metal oxide films successively.

[0216] The metal oxide film is processed by either wet etching or dry etching. In this case, the part of the insulating layer 103 that does not overlap with the semiconductor layer 108 may be used. The part may be etched and thinned.

[0217] After the metal oxide film is formed or processed into the semiconductor layer 108, the metal oxide film or Alternatively, heat treatment may be performed to remove hydrogen or water from the semiconductor layer 108. The temperature is typically between 150°C and below the strain point of the substrate, or between 250°C and 450°C. or 300°C or higher and 450°C or lower.

[0218] The heat treatment can be performed in an atmosphere containing a rare gas or nitrogen. After heating in air, the material may be heated in an atmosphere containing oxygen. It is preferable that the mixture does not contain oxygen, water, etc. The heat treatment is carried out using an electric furnace, an RTA device, etc. By using an RTA device, the heat treatment time can be shortened.

[0219] [Formation of insulating film 110f and metal oxide film 114f] Next, an insulating film 110 is formed to cover the insulating layer 103 and the semiconductor layer 108. The metal oxide film 114f that will become the metal oxide layer 114 is then laminated to form a film (FIG. 9(C)). ).

[0220] The insulating film 110f is made of an oxide film such as a silicon oxide film or a silicon oxynitride film. The film is deposited using a plasma enhanced chemical vapor deposition (PECVD) system, or simply called a plasma CVD system. It is preferable to form the film by using a PECVD method using microwaves. It may be formed as follows.

[0221] The metal oxide film 114f is preferably formed in an atmosphere containing oxygen, for example. It is preferable to form the film by sputtering in an atmosphere containing oxygen. Oxygen can be supplied to the insulating film 110f when the metal oxide film 114f is formed.

[0222] The metal oxide film 114f is formed by an oxide film containing the same metal oxide as that of the semiconductor layer 108. When forming the film by a sputtering method using a target, the above method can be used. Cut.

[0223] For example, the metal oxide film 114f is formed under the following conditions: oxygen is used as the film-forming gas; The metal oxide film may be formed by reactive sputtering using a metal target. When aluminum is used as the base, an aluminum oxide film is formed. can be done.

[0224] When forming the metal oxide film 114f, the total flow rate of the film forming gas introduced into the film forming chamber of the film forming apparatus is The higher the oxygen flow rate ratio to the film thickness (oxygen flow rate ratio) or the oxygen partial pressure in the film formation chamber, the greater the insulating film thickness. The oxygen supplied during the 10f can be increased. The oxygen flow ratio or oxygen partial pressure can be increased, for example, 50% or more and 100% or less, preferably 65% ​​or more and 100% or less, more preferably 80% or more The oxygen flow rate ratio is preferably 100% or more, and more preferably 90% or more and 100% or less. It is preferable to set the oxygen partial pressure at 100% and make it as close to 100% as possible.

[0225] In this way, the metal oxide film 114f is formed by sputtering in an atmosphere containing oxygen. By forming the insulating film 110f, oxygen is supplied to the insulating film 110f when the metal oxide film 114f is formed. At the same time, oxygen can be prevented from being released from the insulating film 110f. A large amount of oxygen can be trapped in the film 110f. As a result, a large amount of oxygen can be supplied to the semiconductor layer 108. This reduces oxygen vacancies and enables the realization of highly reliable transistors.

[0226] After the metal oxide film 114f is formed, heat treatment is performed to remove the metal oxide film from the insulating film 110f. Oxygen may be supplied to the semiconductor layer 108. The heat treatment may be performed using one or more of nitrogen, oxygen, and a rare gas. The reaction can be carried out at a temperature of 200°C or higher and 400°C or lower in an atmosphere containing

[0227] Next, after the metal oxide film 114f is formed, the metal oxide film 114f, the insulating film 110f, A part of the insulating layer 103 is etched to form an opening that reaches the conductive layer 106. This allows the conductive layer 112 and the conductive layer 106 to be formed later to be electrically connected through the opening. can be connected to.

[0228] [Formation of insulating layer 110, conductive layer 112, and metal oxide layer 114] Subsequently, a conductive film 112 to be formed on the insulating film 110f and the metal oxide film 114f is deposited. The conductive film 112f is formed by sputtering a metal or alloy. It is preferable to form the film by sputtering using a target.

[0229] Subsequently, the insulating film 110f, the conductive film 112f, and a part of the metal oxide film 114f are etched. This forms an insulating layer 110, a conductive layer 112, and a metal oxide layer 114 (FIG. 9(E)). The insulating film 110f, the conductive film 112f, and the metal oxide film 114f are each formed of the same resist matrix. Alternatively, the conductive layer 112 after etching may be processed using a hard mask. The insulating film 110f and the metal oxide film 114f may be etched using the etching mask.

[0230] As a result, the insulating layer 110, the conductive layer 112, and the metal oxide layer 113 are formed so that their upper surface shapes are roughly the same. 14 can be formed.

[0231] [Formation of insulating layer 118] Next, the insulating layer 118 is formed (FIG. 10(A)). CVD methods such as micro-CVD, low pressure CVD, and ECR CVD can be used. For this purpose, a gas containing an impurity element (impurity element source) can be used.

[0232] For example, when silicon oxide containing an impurity element is formed as the insulating layer 118, the source gas As the source of the impurity element, a silicon source, an oxygen source, and an impurity element source can be used. In the case of silicon oxynitride containing pure elements, the source gases are silicon source, oxygen source, nitrogen source, and impurity element sources can be used. As the silicon source, TEOS (Tetraethyl Ether) organic silanes such as SiH4 (monosilane), Si Inorganic silanes such as 2H6 (disilane) can be used. O2, O3, N2O, etc. can be used as the nitrogen source. NH3, N2O, etc. can be used as the nitrogen source. N2O can be used as an oxygen source and a nitrogen source. In this case, PH3 (phosphine) or the like can be used as the impurity element source. When boron is used, B2H6 (diborane) or the like can be used as the impurity element source. In addition, a plurality of these impurity element sources may be used.

[0233] By forming the insulating layer 118 by adding an impurity element source to the raw material gas, the entire insulating layer 118 By including an impurity element in the entire insulating layer 118, This can efficiently prevent oxygen contained in the insulating layer 118 from being released from the insulating layer 118. In addition, the concentration of the impurity element in the insulating layer 118 can be made uniform in the thickness direction of the insulating layer 118. In the thickness direction of the layer 118, the ratio of the maximum value to the minimum value of the impurity concentration is 1.0 or more and 10 Preferably, the ratio is 1.0 to 7.0, more preferably 1.0 to 5.0. It is preferable that the ratio is 0.0 or less, and more preferably 1.0 or more and 3.0 or less. This reduces the variation in the concentration of impurity elements in the semiconductor device, resulting in a semiconductor device with good electrical characteristics. The device can be manufactured with high productivity.

[0234] In addition, by forming the insulating layer 118 by adding an impurity element source to the raw material gas, the semiconductor layer 1 The insulating layer 118 containing the impurity element source is formed on the semiconductor layer 108 while suppressing damage to the insulating layer 118. Damage to the semiconductor layer 108 during the formation of the insulating layer 118 can be suppressed, and thus the semiconductor This can prevent the crystallinity of the conductive layer 108 from being reduced. Therefore, it is possible to efficiently prevent the crystallinity of the region 108n, which is a region without the crystallinity, from being reduced. The decrease in crystallinity increases the electrical resistance of the region 108n, deteriorating the electrical characteristics of the semiconductor device. In addition, the semiconductor layer 108 in the region overlapping with the conductive layer 112, and The region 108n, which is a region that does not overlap with the conductive layer 112, has both crystallinity. The genders can be equal.

[0235] In addition, by using the plasma CVD method to form the insulating layer 118, the semiconductor layer 108 can be efficiently Oxygen deficiency (V O When the insulating layer 118 is formed by the plasma CVD method, In this case, if the film formation temperature is too high, the impurities contained in the region 108n etc. The diffusion to the peripheral area including the channel forming region and the increase in electrical resistance of the region 108n may occur. The temperature at which the insulating layer 118 is formed is preferably, for example, 150° C. or higher and 400° C. or lower. Preferably, the temperature is 180°C or higher and 360°C or lower, and more preferably, 200°C or higher and 250°C or lower. By forming the insulating layer 118 at a low temperature, a transistor with a short channel length can be formed. Even if the thickness is too small, good electrical properties can be imparted.

[0236] Furthermore, in the step of forming the insulating layer 118, the region of the semiconductor layer 108 that contacts the insulating layer 118 is insufficient. May contain pure elements.

[0237] Next, a method for forming the insulating layer 118 that is different from the above will be described.

[0238] The insulating layer 118 is formed by forming an insulating layer that will become the insulating layer 118 and then adding an impurity element to the insulating layer. The insulating layer 118 can also be formed by performing a supplying (adding or injecting) process. The insulating layer 1 may be made of an oxide that does not contain impurity elements. The insulating layer 18 may be made of an oxide containing an impurity element.

[0239] The insulating layer 118 can be formed by plasma CVD, low pressure CVD, ECRCVD, etc. For example, a silicon oxide film can be used as the insulating layer that will become the insulating layer 118. When forming an insulating film, a silicon source and an oxygen source can be used as source gases. When silicon oxynitride is formed as the insulating layer that becomes the layer 118, silicon is used as the source gas. A nitrogen source, an oxygen source and a nitrogen source can be used.

[0240] The impurity element is supplied to the insulating layer that will become the insulating layer 118 by plasma ion doping or These methods can be used to obtain a concentration profile in the depth direction. The file can be controlled with high precision by adjusting the ion acceleration voltage and dose. By using the plasma ion doping method, productivity can be increased. By using the ion implantation method using the do.

[0241] In the supplying process of the impurity element, the impurity element concentration is the lowest in the insulating layer that will become the insulating layer 118. It is preferable to control the processing conditions so that the ion concentration is high. This allows for more efficient management and increases productivity.

[0242] The impurity element is supplied to the insulating layer 118 as a source gas of the impurity element. When supplying boron, a gas containing B2H6 or B F3 gas can be used. When supplying phosphorus, PH3 gas is typically used. In addition, a mixed gas obtained by diluting these source gases with a rare gas can be used. Good too.

[0243] Other raw material gases include CH4, N2, NH3, AlH3, AlCl3, SiH4, Si2H6, F2, HF, H2, (C5H5)2Mg, and rare gases can be used. In addition, the ion source is not limited to gas, and solids or liquids vaporized by heating can also be used. good.

[0244] The impurity elements are supplied in consideration of the composition, density, thickness, etc. of the insulating layer that will become the insulating layer 118. It can be controlled by setting conditions such as acceleration voltage and dose amount.

[0245] For example, when adding boron by ion implantation or plasma ion doping, The acceleration voltage is, for example, 5 kV or more and 100 kV or less, preferably 7 kV or more and 70 kV or less, more preferably 100 kV or more and 50 kV or less. Preferably, the voltage can be in the range of 10 kV to 50 kV. Ba1×10 13 ions / cm 2 More than 1×10 17 ions / cm 2 Below, preferably 1 x10 14 ions / cm 2 5x10 or more 16 ions / cm 2 Below, more preferably 1 x10 15 ions / cm 2 That's it, 3 x 10 16 ions / cm 2 The following range should be met: can be done.

[0246] In addition, when phosphorus is added by ion implantation or plasma ion doping, The voltage is, for example, 10 kV or more and 100 kV or less, preferably 30 kV or more and 90 kV or less, more preferably More preferably, the voltage can be in the range of 40 kV to 80 kV. For example, 1 x 10 13 ions / cm 2 More than 1×10 17 ions / cm 2 Below, preferably 1×10 14 ions / cm 2 5x10 or more 16 ions / cm 2 Below, more preferably 1×10 15 ions / cm 2 That's it, 3 x 10 16 ions / cm 2 The following ranges This can be done.

[0247] The method of supplying the impurity element is not limited to this, and may be, for example, a plasma treatment or a heating treatment. In the case of the plasma treatment method, the impurity to be added may be By generating plasma in a gas atmosphere containing elements and performing plasma treatment, A pure element can be added. The plasma generating device is a dry etching device. Using a chipping device, ashing device, plasma CVD device, high density plasma CVD device, etc. It is possible.

[0248] The processing conditions are controlled so that the impurity element concentration in the insulating layer that becomes the insulating layer 118 becomes the highest. By this, even if the semiconductor layer 108 has crystallinity, the supply of the impurity element can be prevented. Therefore, the deterioration of the crystallinity can be prevented. This is preferable when the resistance increases.

[0249] [Heat treatment] After the insulating layer 118 is formed, heat treatment is performed. The heat treatment is performed using one or more of nitrogen, oxygen, and a rare gas. In an atmosphere containing the above, the temperature is 150°C or higher and 450°C or lower, preferably 200°C or higher and 400°C or lower. By this heat treatment, V is formed in the semiconductor layer 108. O H is formed As a result, a low-resistance region 108n is formed (FIG. 10(B)). By performing this, the impurity element contained in the insulating layer 118 is diffused, and the region 10 containing the impurity element is formed. 8n and region 103d may be formed. Note that if the temperature of the heat treatment is too high (for example, 500 ℃ or higher), impurity elements diffuse into the channel formation region, causing deterioration in the electrical characteristics and This may result in a deterioration in reliability.

[0250] Furthermore, the heat treatment reduces the thickness of the channel formation region of the semiconductor layer 108 and the thickness of the insulating layer 110. In some cases, the defect can be repaired.

[0251] Furthermore, oxygen is introduced from the insulating layer 110 to the channel formation region of the semiconductor layer 108 by the heat treatment. At this time, since the side surface of the insulating layer 110 is in contact with the insulating layer 118, This suppresses the release of oxygen from the insulating layer 110 to the insulating layer 118. The resistance of the region 108n can be effectively prevented from increasing. Oxygen released from 110 can be selectively supplied to the channel forming region.

[0252] In addition, since the region 108n has more oxygen vacancies than the channel formation region, The heat treatment gets rid of the hydrogen contained in the channel formation region by the oxygen vacancies. This is expected to have the effect of reducing the hydrogen concentration in the channel formation region. This allows for the realization of a more reliable transistor. The hydrogen atoms in the region 108n are bonded to oxygen vacancies in the region 108n to generate carriers. A resistive region 108n can be realized.

[0253] [Formation of Openings 141a and 141b] Next, a mask is formed by lithography at a desired position on the insulating layer 118, and then the insulating layer By etching a part of 118, openings 141a and 141b reaching the region 108n are formed. Form 141b.

[0254] [Formation of Conductive Layer 120a and Conductive Layer 120b] Subsequently, a conductive film is formed on the insulating layer 118 so as to cover the openings 141a and 141b. The conductive film is formed and processed into a desired shape to form the conductive layer 120a and the conductive layer 120b. (Figure 10(C)).

[0255] Through the above steps, the transistor 100D can be manufactured. When the STA 100D is applied to the pixels of a display device, a protective insulating layer, a planarizing layer, A step of forming at least one of the pixel electrodes and the wiring may be added.

[0256] The above is the description of the first example of the manufacturing method.

[0257] <Production method example 2> An example of a method for manufacturing a transistor of one embodiment of the present invention will be described below. The transistor 100E illustrated in the third configuration example will be used as an example for explanation.

[0258] Each diagram in FIG. 11 shows the channel length of the transistor 100E at each stage of the manufacturing process. The cross sections in the direction and the channel width direction are shown side by side.

[0259] The manufacturing method is the same as that shown in <Manufacturing Method Example 1> up to the formation of the conductive film 112f. Therefore, the manufacturing methods of the transistors shown in FIGS. 9A to 9D can be taken into consideration. do.

[0260] [Formation of insulating layer 110, conductive layer 112, and metal oxide layer 114] Next, the insulating film 110f, the conductive film 112f, and the metal oxide film 114f are partially etched. Then, an insulating layer 110, a conductive layer 112, and a metal oxide layer 114 are formed (FIG. 11(A)). During etching, a part of the insulating film 110f in the area that does not overlap with the conductive layer 112 is left. In this way, the insulating layer 110 can be formed to have different thicknesses. The insulating film 110f in the entire region is not etched, and the upper surface, side surface, and By covering the insulating layer 103 with the semiconductor layer, the semiconductor layer can be easily etched when the conductive layer 112 and the like are etched. This can prevent the layer 108 and the insulating layer 103 from being partially etched and becoming thinner. do.

[0261] The insulating film 110f, the conductive film 112f, and the metal oxide film 114f are each formed of the same resist. It is preferable to process the conductive layer 112 using a mask. The insulating film 110f and the metal oxide film 114f may be etched using the mask. .

[0262] This forms the conductive layer 112 and the metal oxide layer 114 whose top surface shapes are roughly the same. It is possible.

[0263] [Formation of insulating layer 118] Next, the insulating layer 118 is formed (FIG. 11(A)). CVD methods such as micro-CVD, low pressure CVD, and ECR CVD can be used. Therefore, a gas containing an impurity element (an impurity element source) can be used. For this, the above description can be referred to, and therefore detailed description will be omitted.

[0264] A method for forming the insulating layer 118 that is different from the above will now be described.

[0265] The insulating layer 118 is formed by forming an insulating layer that will become the insulating layer 118 and then adding an impurity element to the insulating layer. The insulating layer 118 can also be formed by performing a supplying (adding or injecting) process. The insulating layer 1 may be made of an oxide that does not contain impurity elements. An oxide containing an impurity element can be used as the insulating layer 18. The insulating layer 118 may be made of an oxide that does not contain impurity elements.

[0266] For the formation of the insulating layer that becomes the insulating layer 118, the above description can be referred to, and a detailed description thereof will be omitted. The clarification is omitted.

[0267] The impurity element is supplied to the insulating layer that will become the insulating layer 118 by plasma ion doping or The impurity source is introduced into the insulating layer that will become the insulating layer 118. As for the supply of the raw material, the above description can be referred to, and therefore a detailed description thereof will be omitted.

[0268] For example, when adding boron by ion implantation or plasma ion doping, The acceleration voltage is, for example, 5 kV or more and 100 kV or less, preferably 7 kV or more and 80 kV or less, more preferably 100 kV or more and 50 kV or less. Preferably, the voltage can be in the range of 10 kV to 60 kV. Ba1×10 13 ions / cm 2 More than 1×10 17 ions / cm 2 Below, preferably 1 x10 14 ions / cm 2 5x10 or more 16 ions / cm 2 Below, more preferably 1 x10 15 ions / cm 2 That's it, 3 x 10 16 ions / cm 2 The following range should be met: can be done.

[0269] In addition, when phosphorus is added by ion implantation or plasma ion doping, The voltage is, for example, 10 kV or more and 100 kV or less, preferably 30 kV or more and 100 kV or less. More preferably, the voltage can be set in the range of 40 kV to 100 kV. , e.g. 1×10 13 ions / cm 2 More than 1×10 17 ions / cm 2 The following is preferred: 1×10 14 ions / cm 2 5x10 or more 16 ions / cm 2 The following is more preferred: 1×10 15 ions / cm 2 That's it, 3 x 10 16 ions / cm 2 The range is as follows: It is possible.

[0270] [Heat treatment] After the insulating layer 118 is formed, heat treatment is performed. The impurity element diffuses into the semiconductor layer 108 through the insulating layer 110. The impurity element combines with oxygen contained in the semiconductor layer 108, forming oxygen vacancies (V O ) is formed. Furthermore, the oxygen deficiency (V O ) bonds with hydrogen contained in the semiconductor layer 108 to form V O H, A low-resistance region 108n is formed (FIG. 11(B)). The impurity element is also diffused into the layer 103, forming a region 103d. Since the above description can be referred to, detailed description will be omitted.

[0271] [Formation of Openings 141a and 141b] Next, a mask is formed by lithography at a desired position on the insulating layer 118, and then the insulating layer 118 and a portion of the insulating layer 110 are etched to form an opening 118 reaching the region 108n. 41a and an opening 141b are formed.

[0272] [Formation of Conductive Layer 120a and Conductive Layer 120b] Subsequently, a conductive film is formed on the insulating layer 118 so as to cover the openings 141a and 141b. The conductive film is formed and processed into a desired shape to form the conductive layer 120a and the conductive layer 120b. (Figure 11(C)).

[0273] Through the above steps, the transistor 100E can be manufactured. When the STAR 100E is applied to the pixels of a display device, a protective insulating layer, a planarizing layer, A step of forming at least one of the pixel electrodes and the wiring may be added.

[0274] This concludes the description of the second manufacturing method example.

[0275] The configuration examples, manufacturing method examples, and corresponding drawings etc. illustrated in this embodiment mode are merely examples. In addition, a part of it may be implemented by appropriately combining it with other configuration examples, manufacturing method examples, drawings, etc. can be done.

[0276] This embodiment may be combined, at least in part, with other embodiments described in this specification. It can be implemented in combination.

[0277] (Embodiment 2) In this embodiment, an example of a display device including the transistor described in the above embodiment will be described. We will explain the following.

[0278] [Configuration example] 12A shows a top view of a display device 700. The display device 700 is made of a sealing material 712. The first substrate 701 and the second substrate 705 are bonded together. 01, the second substrate 705, and the area sealed by the sealant 712, the first substrate 7 01, a pixel section 702, a source driver circuit section 704, and a gate driver circuit section 706 The pixel portion 702 is provided with a plurality of display elements.

[0279] In addition, an FPC 716 (FP C: Flexible printed circuit) is connected to the FPC terminal 7 The FPC terminal portion 708 and the signal line 710 are connected by the FPC 716. 7, a pixel section 702, a source driver circuit section 704, and a gate driver circuit section 706. Various signals are supplied to each of these.

[0280] A plurality of gate driver circuit sections 706 may be provided. The path section 706 and the source driver circuit section 704 are separately formed on a semiconductor substrate or the like. The IC chip may be in the form of a packaged IC chip. The IC chip is mounted on the first substrate 70. 1 or can be mounted on FPC716.

[0281] The pixel portion 702, the source driver circuit portion 704, and the gate driver circuit portion 706 have The transistor can be a transistor that is a semiconductor device of one embodiment of the present invention. do.

[0282] Examples of display elements provided in the pixel portion 702 include a liquid crystal element and a light-emitting element. The liquid crystal elements used include transmissive liquid crystal elements, reflective liquid crystal elements, and semi-transmissive liquid crystal elements. In addition, LEDs (Light Emitting Diodes) can be used as light emitting elements. Diode), OLED (Organic LED), QLED (Quantum-do Examples of self-luminous light-emitting elements include LEDs, semiconductor lasers, etc. MEMS (Micro Electro Mechanical Systems) using optical interference or optical sensing l Systems) elements, microcapsule type, electrophoresis type, electrowet Display elements that use the LCD technology or the electronic liquid powder technology (registered trademark) can be used. It can also be done as follows.

[0283] The display device 700A shown in FIG. 12(B) is suitable for use in electronic devices having large screens. For example, television equipment, monitor equipment, personal computer Computers (including laptops and desktops), tablets, digital signage It can be suitably used in the following cases:

[0284] The display device 700A includes a plurality of source driver ICs 721 and a pair of gate driver circuits. It has a section 722.

[0285] The plurality of source driver ICs 721 are attached to respective FPCs 723. In addition, the plurality of FPCs 723 are arranged such that one terminal is connected to the substrate 701 and the other terminal is connected to the printed circuit board 72. 4. By bending the FPC 723, the printed circuit board 724 It can be mounted on the back side of the pixel section 702 and installed in an electronic device, thereby saving space in the electronic device. It is possible to achieve this.

[0286] On the other hand, the gate driver circuit section 722 is formed on the substrate 701. It is possible to realize electronic devices with narrow bezels.

[0287] By adopting such a configuration, a large-sized and high-resolution display device can be realized. The surface size is 30 inches or more, 40 inches or more, 50 inches or more, or 60 inches or more diagonally. It can also be applied to the above display devices. Also, the resolution is 4K2K or 8K4K, etc. Such an extremely high-resolution display device can be realized.

[0288] [Cross-section example] Below, we will discuss configurations using liquid crystal elements and EL elements as display elements. 13 to 15. Note that FIGS. 13 to 15 are the same as those in FIG. 12(A) 13 and 14 are cross-sectional views taken along the dashed line QR shown in FIG. FIG. 15 shows a configuration using an EL element.

[0289] [Explanation of common parts of display devices] The display device shown in FIGS. 13 to 15 includes a wiring portion 711, a pixel portion 702, and a The wiring section 711 has a driver circuit section 704 and an FPC terminal section 708. , and a signal line 710. The pixel portion 702 includes a transistor 750 and a capacitor 790. The source driver circuit section 704 includes a transistor 752. In FIG. The case without element 790 is shown.

[0290] The transistor 750 and the transistor 752 are the same as those described in Embodiment 1. can be applied.

[0291] The transistor used in this embodiment is made of a highly purified oxide in which the formation of oxygen vacancies is suppressed. The transistor has a semiconductor film. The off-state current of the transistor can be reduced. The holding time of the electric signal can be extended, and the writing interval can also be set longer when the power is on. This reduces the frequency of refresh operations, thereby reducing power consumption.

[0292] In addition, the transistor used in this embodiment has a relatively high field-effect mobility. For example, a transistor capable of such high speed driving can be used in a display device. By using this in a device, the switching transistor in the pixel section and the driver used in the drive circuit section can be The transistors can be formed on the same substrate, i.e., a silicon wafer. It is also possible to configure the semiconductor device without using a driver circuit formed by the above method, thereby reducing the number of components in the semiconductor device. In addition, by using a transistor that can be driven at high speed in the pixel portion, , high-quality images can be provided.

[0293] The capacitor 790 shown in FIGS. 13 and 15 has the same semiconductor layer as the transistor 750. a lower electrode formed by processing a single film and having a low resistance, and a source electrode or a drain electrode and an upper electrode formed by processing the same conductive film as the lower electrode. A two-layer insulating film covering the transistor 750 is provided between the capacitor element 790 is a laminated structure in which an insulating film that functions as a dielectric film is sandwiched between a pair of electrodes. do.

[0294] In addition, a planarization insulating film is formed on the transistor 750, the transistor 752, and the capacitor 790. A veneer 770 is provided.

[0295] The transistor 750 included in the pixel portion 702 and the transistor 750 included in the source driver circuit portion 704 are A transistor having a different structure from the transistor 752 may be used. A top-gate transistor is applied to one side, and a bottom-gate transistor is applied to the other side. The source driver circuit section 704 may be replaced with a gate driver circuit. It can also be read as road section.

[0296] The signal line 710 is the same as the source and drain electrodes of the transistors 750 and 752. In this case, if a low-resistance material such as a material containing copper is used, the wiring This is preferable because it reduces signal delays caused by line resistance and enables display on a large screen.

[0297] The FPC terminal portion 708 includes a connection electrode 760, an anisotropic conductive film 780, and an FPC 716. The connection electrode 760 is electrically connected to a terminal of the FPC 716 via an anisotropic conductive film 780. Here, the connection electrode 760 is electrically connected to the source electrodes of the transistors 750 and 752. The gate electrode and drain electrode are formed from the same conductive film.

[0298] The first substrate 701 and the second substrate 705 may be, for example, a glass substrate or a plastic substrate. A flexible substrate such as a plastic substrate can be used.

[0299] On the second substrate 705 side, there are a light-shielding film 738, a colored film 736, and an insulating film in contact with these. A velum 734 is provided.

[0300] [Configuration example of a display device using a liquid crystal element] The display device 700 shown in FIG. 13 includes a liquid crystal element 775. The liquid crystal element 775 includes a conductive layer The conductive layer 774 is a second The conductive layer 772 is provided on the substrate 705 side and functions as a common electrode. The conductive layer is electrically connected to a source electrode or a drain electrode of the transistor 750. A film 772 is formed on the planarization insulating film 770 and functions as a pixel electrode.

[0301] The conductive layer 772 can be formed using a material that transmits or reflects visible light. The transparent material may be, for example, an oxide material containing indium, zinc, tin, or the like. As the reflective material, for example, a material containing aluminum, silver, etc. is used. It is good.

[0302] If a reflective material is used for the conductive layer 772, the display device 700 becomes a reflective liquid crystal display device. On the other hand, when a light-transmitting material is used for the conductive layer 772, the liquid crystal display device becomes a transmissive type. In the case of a transmissive liquid crystal display device, a polarizing plate is provided on the viewing side. A pair of polarizing plates is provided to sandwich the liquid crystal element.

[0303] The display device 700 shown in FIG. 14 includes a liquid crystal element 77 of a horizontal electric field type (for example, FFS mode). 5 is used as a common electrode. A conductive layer 774 is provided. An electric field generated between the conductive layer 772 and the conductive layer 774 The alignment state of the liquid crystal layer 776 can be controlled.

[0304] In FIG. 14, a holding container is formed by a laminated structure of a conductive layer 774, an insulating layer 773, and a conductive layer 772. Therefore, there is no need to provide a separate capacitance element, and the aperture ratio can be increased. It is possible.

[0305] Although not shown in FIGS. 13 and 14, an alignment film is provided in contact with the liquid crystal layer 776. In addition, optical members such as polarizing members, phase difference members, and anti-reflection members (optical substrates) may be used. A light source such as a backlight or a sidelight may be provided as appropriate.

[0306] The liquid crystal layer 776 may include a thermotropic liquid crystal, a low molecular weight liquid crystal, a high molecular weight liquid crystal, a polymer dispersion liquid, or the like. Crystal (PDLC: Polymer Dispersed Liquid Crystal) , Polymer Network Liquid Crystal (PNLC) d Crystal), ferroelectric liquid crystal, antiferroelectric liquid crystal, etc. can be used. When the in-plane switching system is adopted, a liquid crystal that exhibits a blue phase without using an alignment film may be used.

[0307] The liquid crystal element mode is TN (Twisted Nematic) mode, VA (Vertical Alignment) mode, IPS (In-Plane-S witching) mode, FFS(Fringe Field Switching) mode, ASM (Axially Symmetric aligned Micro- cell) mode, OCB (Optical Compensated Birefri) ngence) mode, ECB (Electrically Controlled B You can use modes such as reference mode and guest-host mode.

[0308] In addition, the liquid crystal layer 776 uses a polymer dispersed liquid crystal or a polymer network liquid crystal, A scattering type liquid crystal can also be used. In this case, black and white display is performed without providing the colored film 736. Alternatively, a colored film 736 may be used to perform color display.

[0309] In addition, as a driving method of the liquid crystal element, a time-series additive color mixture method is used to display colors. A split display method (also called a field sequential driving method) may be applied. In this case, the colored film 736 may not be provided. For example, it is necessary to provide sub-pixels that exhibit the respective colors R (red), G (green), and B (blue). This has the advantage of improving the pixel aperture ratio and increasing the definition.

[0310] [Display device using light-emitting elements] The display device 700 shown in FIG. 15 includes a light-emitting element 782. The light-emitting element 782 includes a conductive layer The EL layer 786 includes an organic compound. has inorganic compounds such as quantum dots.

[0311] Materials that can be used for the organic compound include fluorescent materials and phosphorescent materials. In addition, materials that can be used for quantum dots include colloidal quantum dots. materials, alloy-type quantum dot materials, core-shell-type quantum dot materials, core-type quantum dot materials, Examples include:

[0312] In the display device 700 shown in FIG. 15, a conductive layer 772 is formed on a planarization insulating film 770. An insulating film 730 is provided. Here, the light-emitting element 782 has a light-transmitting conductive film 788. The light-emitting element 782 is a light-emitting element of a double-emission type. a bottom emission structure in which light is emitted from both the conductive layer 772 and the conductive film 788; A dual emission structure may also be used.

[0313] The colored film 736 is provided at a position overlapping the light emitting element 782, and the light blocking film 738 is an insulating film. 730, the lead wiring portion 711, and the source driver circuit portion 704. The colored film 736 and the light-shielding film 738 are covered with an insulating film 734. The space between the light emitting element 782 and the insulating film 734 is filled with a sealing film 732. 86 is formed in an island shape for each pixel or in a stripe shape for each pixel row, that is, by painting In some cases, the colored film 736 may not be provided.

[0314] [Configuration example of providing an input device to a display device] An input device may be provided in the display device 700 shown in FIGS. An example of the device is a touch sensor.

[0315] For example, the sensor types include capacitance type, resistive film type, surface acoustic wave type, and infrared type. Various methods can be used, such as electrical, optical, and pressure-sensitive methods. Or, two or more of these can be used. may be used in combination.

[0316] The touch panel has a so-called in-cell structure, in which the input device is formed inside a pair of substrates. A touch panel of this type, an input device formed on the display device 700, is a so-called on-cell type touch panel. or a so-called out-cell type touch panel that is attached to the display device 700. There are some.

[0317] The configuration examples exemplified in this embodiment and the corresponding drawings etc. are at least partly The above can be implemented in appropriate combination with other configuration examples or drawings, etc.

[0318] This embodiment may be combined, at least in part, with other embodiments described in this specification. It can be implemented in combination.

[0319] (Embodiment 3) In this embodiment, a display device including a semiconductor device of one embodiment of the present invention will be described with reference to FIG. This will be used to explain.

[0320] The display device shown in FIG. 16A includes a pixel portion 502, a driver circuit portion 504, and a protection circuit 50 6 and a terminal portion 507. Note that the protection circuit 506 may not be provided. .

[0321] The transistors included in the pixel portion 502 and the driver circuit portion 504 are the transistors of one embodiment of the present invention. The protection circuit 506 can also be formed using the transistor of one embodiment of the present invention. may be applied.

[0322] The pixel section 502 is a plurality of pixels arranged in X rows and Y columns (X and Y are each independently a natural number of 2 or more). The display device has a plurality of pixel circuits 501 for driving a number of display elements.

[0323] The driving circuit unit 504 is a gate driver that outputs scanning signals to the gate lines GL_1 to GL_X. a source driver 504a that supplies data signals to the data lines DL_1 to DL_Y; The gate driver 504a includes a driver circuit such as a shift register The source driver 504b may be configured to have, for example, a plurality of analog switches. Also, the source driver 504 is configured using a shift register or the like. b may be configured.

[0324] The terminal unit 507 is used to input power, control signals, image signals, etc. from an external circuit to the display device. This refers to the part where terminals for connecting the power supply to the power source are provided.

[0325] When a potential outside a certain range is applied to the wiring to which the protection circuit 506 is connected, the protection circuit 506 The protection circuit 506 shown in FIG. For example, the scanning line GL, which is the wiring between the gate driver 504a and the pixel circuit 501, Various wirings such as the data line DL which is the wiring between the source driver 504b and the pixel circuit 501 Connected.

[0326] The gate driver 504a and the source driver 504b are connected to the pixel section 502 and The gate driver circuit or the source driver circuit may be provided on the same substrate. A separately formed substrate (for example, a drive circuit substrate formed of a single crystal semiconductor film or a polycrystalline semiconductor film) board) by COG or TAB (Tape Automated Bonding) It may also be configured to be implemented in

[0327] 16(B) and 16(C) are connected to the pixel circuits 501 shown in FIG. 16(A). The configuration shown in (C) can be used.

[0328] The pixel circuit 501 shown in FIG. 16B includes a liquid crystal element 570, a transistor 550, and a capacitor. The pixel circuit 501 also includes a data line DL_n, a scanning line GL_ m, a potential supply line VL, etc. are connected.

[0329] The potential of one of the pair of electrodes of the liquid crystal element 570 is set appropriately according to the specifications of the pixel circuit 501. The orientation state of the liquid crystal element 570 is set by the written data. A common potential is applied to one of a pair of electrodes of the liquid crystal element 570 included in each of the pixel circuits 501. A common potential may be applied to the pair of liquid crystal elements 570 of the pixel circuits 501 in each row. One of the electrodes may be given a different potential.

[0330] The pixel circuit 501 shown in FIG. 16C includes transistors 552 and 554 and a capacitor. The pixel circuit 501 also includes a data line DL_n , scanning lines GL_m, potential supply lines VL_a, power supply lines VL_b, etc. are connected to the pixel electrodes GL_m.

[0331] A high power supply potential VDD is applied to one of the potential supply lines VL_a and VL_b. The other terminal is supplied with a low power supply potential VSS. The current flowing through the light-emitting element 572 is controlled in accordance with the potential applied to the light-emitting element 572. The brightness of the light emitted from 72 is controlled.

[0332] The configuration examples exemplified in this embodiment and the corresponding drawings etc. are at least partly The above can be implemented in appropriate combination with other configuration examples or drawings, etc.

[0333] This embodiment may be combined, at least in part, with other embodiments described in this specification. It can be implemented in combination.

[0334] (Fourth embodiment) In the following, a pixel circuit having a memory for correcting the gradation displayed in the pixel and a The transistors exemplified in Embodiment 1 will be described below. The present invention can be applied to transistors used in pixel circuits.

[0335] [Circuit configuration] 17A shows a circuit diagram of the pixel circuit 400. The pixel circuit 400 includes a transistor M The pixel circuit 400 includes a transistor M2, a capacitor C1, and a circuit 401. The wiring S1, the wiring S2, the wiring G1, and the wiring G2 are connected.

[0336] The transistor M1 has a gate connected to a wiring G1, a source and a drain connected to a wiring S1, and The other terminal is connected to one electrode of the capacitor C1. The gate of the transistor M2 is connected to the wiring. G2, one of the source and drain is connected to the wiring S2, and the other is connected to the other electrode of the capacitor C1, and 401 and 402, respectively.

[0337] The circuit 401 is a circuit including at least one display element. Representative examples include light-emitting elements such as organic EL elements and LED elements, and liquid crystal element, or MEMS (Micro Electro Mechanical Systems) EMS) elements, etc. can be applied.

[0338] The node connecting the transistor M1 and the capacitor C1 is N1, and the node connecting the transistor M2 and the circuit 40 is N2. Let N2 be the node connecting to 1.

[0339] The pixel circuit 400 maintains the potential of the node N1 by turning off the transistor M1. Furthermore, by turning off the transistor M2, the voltage of the node N2 can be maintained. In addition, when the transistor M2 is in the off state, the transistor By writing a predetermined potential to node N1 via capacitor M1, capacitive coupling via capacitor C1 This allows the potential of the node N2 to be changed in accordance with the change in the potential of the node N1.

[0340] Here, one or both of the transistors M1 and M2 may be The transistor using an oxide semiconductor, as exemplified in 1, can be used. Therefore, the potentials of the nodes N1 and N2 can be maintained for a long period of time due to the extremely low off-state current. In addition, when the period for which the potential of each node is held is short (specifically, when the frame In cases where the system frequency is 30 Hz or more, a transistor using a semiconductor such as silicon is used. A printer may also be used.

[0341] [Drive method example] Next, an example of a method of operating the pixel circuit 400 will be described with reference to FIG. (B) is a timing chart relating to the operation of the pixel circuit 400. For ease of understanding, various resistances such as wiring resistance, parasitic capacitances of transistors and wiring, The influence of the threshold voltage of the transistor and the like is not taken into consideration.

[0342] In the operation shown in FIG. 17B, one frame period is divided into a period T1 and a period T2. T1 is a period during which a potential is written to node N2, and T2 is a period during which a potential is written to node N1. It is a period.

[0343] [Period T1] In the period T1, a potential that turns on the transistor is applied to both the wiring G1 and the wiring G2. In addition, the wiring S1 is connected to a fixed potential V ref The first data is supplied to the wiring S2. Voltage V w supply.

[0344] The node N1 is connected to the line S1 via the transistor M1. ref is given. The node N2 is supplied with a first data potential V w is given. Therefore, the potential difference V across the capacitance C1 w -V ref is maintained.

[0345] [Period T2] Subsequently, in a period T2, a potential that turns on the transistor M1 is applied to the wiring G1. A potential that turns off the transistor M2 is applied to the line G2. Data potential V data A predetermined constant potential is applied to the wiring S2, or a floating potential is applied to the wiring S3. It may also be used as a

[0346] The node N1 is supplied with a second data potential V data is given. At this time, due to the capacitive coupling of the capacitor C1, the second data potential V data Depending on node N That is, the first data potential Vw and the potential In FIG. 17(B), dV is a positive value. Although the potential V data is the potential V re f It may be lower.

[0347] Here, the potential dV is roughly determined by the capacitance value of the capacitor C1 and the capacitance value of the circuit 401. When the capacitance value of the capacitor C1 is sufficiently larger than the capacitance value of the circuit 401, the potential dV is Data potential V data The potential is close to

[0348] In this way, the pixel circuit 400 is a circuit including a display element that combines two types of data signals. Since the potential supplied to the line 401 can be generated, the gradation can be corrected in the pixel circuit 400. It will be possible to do this.

[0349] Furthermore, the pixel circuit 400 generates a potential that exceeds the maximum potential that can be supplied to the wirings S1 and S2. For example, when a light-emitting element is used, a high dynamic range ( In addition, when using liquid crystal elements, overdriving is possible. It is possible to realize drive, etc.

[0350] [Application example] [Example using liquid crystal element] The pixel circuit 400LC shown in FIG. 17C includes a circuit 401LC. has a liquid crystal element LC and a capacitor C2.

[0351] The liquid crystal element LC has one electrode connected to the node N2 and one electrode connected to the capacitor C2, and the other electrode connected to the Potential V com2 The capacitor C2 is connected to the wiring where the other electrode is at potential V com1 Connect with the wiring given.

[0352] The capacitor C2 functions as a storage capacitor. If the capacitor C2 is not required, it can be omitted. Cut.

[0353] The pixel circuit 400LC can supply a high voltage to the liquid crystal element LC, so that, for example, Overdrive operation allows for high-speed display, and liquid crystal materials with high drive voltage are used. In addition, by supplying a correction signal to the wiring S1 or wiring S2, The gradation can also be corrected according to the operating temperature and the deterioration state of the liquid crystal element LC.

[0354] [Example using a light-emitting element] The pixel circuit 400EL shown in FIG. 17D includes a circuit 401EL. includes a light-emitting element EL, a transistor M3, and a capacitor C2.

[0355] The transistor M3 has a gate connected to the node N2 and one electrode of the capacitor C2, and a source and drain connected to the node N2 and one electrode of the capacitor C2. One of the drains is a wiring to which a potential VH is applied, and the other is one electrode of the light-emitting element EL. The capacitor C2 is connected to the other electrode at a potential V com Connect with the wiring given. The other electrode of the light-emitting element EL is at a potential V L Connect with the wiring given.

[0356] The transistor M3 has a function of controlling the current supplied to the light-emitting element EL. functions as a storage capacitor. Capacitor C2 can be omitted if not required.

[0357] In this example, the anode side of the light-emitting element EL is connected to the transistor M3. However, a transistor M3 may be connected to the cathode side. H and potential V L The value of can be changed as appropriate.

[0358] The pixel circuit 400EL generates a light-emitting element by applying a high potential to the gate of the transistor M3. Since a large current can be passed through the child EL, it is possible to realize, for example, HDR display. Furthermore, by supplying a correction signal to the wiring S1 or the wiring S2, the transistor It is also possible to correct variations in the electrical characteristics of M3 and the light-emitting element EL.

[0359] The circuit is not limited to the circuits illustrated in FIGS. 17(C) and 17(D), and may include other transistors or A configuration in which capacitance or the like is added may also be adopted.

[0360] This embodiment may be combined, at least in part, with other embodiments described in this specification. It can be implemented in combination.

[0361] (Embodiment 5) In this embodiment, a display module that can be manufactured using one embodiment of the present invention will be described. and explain.

[0362] The display module 6000 shown in FIG. 18(A) includes an upper cover 6001 and a lower cover 6002. Between the display device 6006 and the frame 6009, the FPC 6005 is connected. The device has a main board 6010 and a battery 6011.

[0363] For example, a display device manufactured according to one embodiment of the present invention can be used as the display device 6006. The display device 6006 realizes a display module with extremely low power consumption. It is possible.

[0364] The upper cover 6001 and the lower cover 6002 are designed to fit the size of the display device 6006. The shape and dimensions can be changed as appropriate.

[0365] The display device 6006 may have a function as a touch panel.

[0366] The frame 6009 has a function of protecting the display device 6006 and a function of preventing the display device 6006 from being damaged by the operation of the printed circuit board 6010. The insulating film may have a function of blocking electromagnetic waves generated by the insulating film, a function as a heat sink, etc.

[0367] The printed circuit board 6010 includes a power supply circuit, a signal circuit for outputting a video signal and a clock signal. It has a signal processing circuit, a battery control circuit, etc. Even if it is powered by a battery 6011 good.

[0368] FIG. 18B is a schematic cross-sectional view of a display module 6000 equipped with an optical touch sensor. is.

[0369] The display module 6000 includes a light emitting section 6015 and a receiving section 6016 provided on a printed circuit board 6010. The optical unit 6016 is enclosed by an upper cover 6001 and a lower cover 6002. The region has a pair of light guide portions (light guide portion 6017a, light guide portion 6017b).

[0370] The display device 6006 is connected to a printed circuit board 6010 and a battery via a frame 6009. The display device 6006 and the frame 6009 are provided so as to overlap with the light guide unit 6011. 017a and fixed to the light guiding portion 6017b.

[0371] Light 6018 emitted from the light emitting unit 6015 is guided to the display device 600 by the light guiding unit 6017a. 6, and reaches the light receiving part 6016 through the light guiding part 6017b. A touch operation is detected when the light 6018 is blocked by a detection object such as an illustration. It is possible.

[0372] A plurality of light emitting sections 6015 are provided along two adjacent sides of the display device 6006, for example. A plurality of light receiving sections 6016 are provided at positions facing the light emitting sections 6015. It is possible to obtain information about the position where the touch operation was performed.

[0373] The light emitting unit 6015 can use a light source such as an LED element, and in particular, can emit infrared light. It is preferable to use a light source that emits light. A photoelectric element that receives light and converts it into an electrical signal can be used. A photodiode such as a photodiode can be used.

[0374] The light emitting section 6015 and the light guiding section 6017a and the light guiding section 6017b transmit light 6018. The light receiving unit 6016 can be disposed below the display device 6006, and external light is received by the light receiving unit 601. 6 and prevent the touch sensor from malfunctioning. By using a resin that allows wires to pass through, malfunction of the touch sensor can be more effectively suppressed.

[0375] This embodiment may be combined, at least in part, with other embodiments described in this specification. It can be implemented in combination.

[0376] (Embodiment 6) In this embodiment, electronic devices including a display device manufactured using one embodiment of the present invention will be described. and explain.

[0377] The electronic devices exemplified below include a display device according to one embodiment of the present invention in a display portion. Therefore, it is an electronic device that has achieved high resolution. Also, high resolution and a large screen It is possible to make an electronic device that is compatible with both.

[0378] The display unit of the electronic device according to one embodiment of the present invention may be configured to display, for example, full high-definition, 4K2K, 8K4 It can display images with resolutions of 16K, 16K, 8K, or higher.

[0379] Examples of electronic devices include television sets, notebook personal computers, Equipped with relatively large screens such as monitor devices, digital signage, pachinko machines, and game machines In addition to electronic devices, digital cameras, digital video cameras, digital photo frames, mobile phones, Examples of such devices include mobile phones, portable game machines, personal digital assistants, and audio playback devices.

[0380] An electronic device to which one aspect of the present invention is applied may be installed on the interior or exterior walls of a house or building, or the interior of a car or the like. It can be incorporated along a flat or curved surface of the packaging or exterior.

[0381] FIG. 19(A) shows the appearance of the camera 8000 with the viewfinder 8100 attached. This is a diagram.

[0382] The camera 8000 includes a housing 8001, a display unit 8002, operation buttons 8003, and a shutter. The camera 8000 has a button 8004 and the like. The camera 8000 also has a detachable lens 8006. It is attached.

[0383] The camera 8000 may have the lens 8006 and the housing integrated together.

[0384] The camera 8000 can be operated by pressing the shutter button 8004 or by using the touch panel. An image can be captured by touching the display portion 8002.

[0385] The housing 8001 has a mount with electrodes, and is equipped with a finder 8100 and a strobe. It is possible to connect devices such as

[0386] The finder 8100 includes a housing 8101, a display unit 8102, buttons 8103, etc. .

[0387] The housing 8101 is configured to mount the camera 8000 by a mount that engages with the mount of the camera 8000. The finder 8100 is attached to the camera 8000. It can be displayed on the display unit 8102.

[0388] The button 8103 has a function such as a power button.

[0389] The display unit 8002 of the camera 8000 and the display unit 8102 of the viewfinder 8100 are The display device of one embodiment of the present invention can be applied. It may also be La 8000.

[0390] FIG. 19B is a diagram showing the appearance of the head mounted display 8200.

[0391] The head-mounted display 8200 includes a mounting part 8201, a lens 8202, and a main body 82 8203, a display unit 8204, a cable 8205, etc. It has a built-in 8206 battery.

[0392] A cable 8205 supplies power from a battery 8206 to the main body 8203. 203 is equipped with a wireless receiver and the like, and can display received video information on a display unit 8204. The main body 8203 is also equipped with a camera, and can input information on the movements of the user's eyes and eyelids. It can be used as a step.

[0393] In addition, the attachment part 8201 has a flow sensor that moves in accordance with the movement of the user's eyeball at a position where it comes into contact with the user. A plurality of electrodes capable of detecting the electric current passing through the sensor may be provided, and the sensor may have a function of recognizing the viewpoint. In addition, the device may have a function of monitoring the pulse of the user by measuring the current flowing through the electrodes. The mounting part 8201 is equipped with various sensors such as a temperature sensor, a pressure sensor, and an acceleration sensor. The display unit 8204 may have a function to display the user's biological information, and the head of the user may have a function to display the user's biological information. The display unit 8204 may have a function of changing the image displayed on the display unit 8204 in accordance with the user's movements.

[0394] The display device of one embodiment of the present invention can be applied to the display portion 8204.

[0395] 19(C), 19(D), and 19(E) show the head mounted display 830. 83. The head-mounted display 8300 includes a housing 8301 and a display It has a display part 8302, a band-shaped fixture 8304, and a pair of lenses 8305.

[0396] A user can view the display on the display unit 8302 through the lens 8305 . If the display unit 8302 is curved, the user can feel a high sense of presence. In addition, it is preferable to display different images in different areas of the display unit 8302 through the lens 8304. By viewing through 305, it is possible to perform a three-dimensional display using parallax. The configuration is not limited to one display unit 8302, but two display units 8302 may be provided, and one of the display units may be One display unit may be arranged for each eye.

[0397] Note that the display device of one embodiment of the present invention can be applied to the display portion 8302. A display device including the semiconductor device of one embodiment of this invention has extremely high definition. Even if the image is enlarged using the lens 8305, the pixels are not visible to the user, and the image is displayed more clearly. This makes it possible to display images with a higher sense of reality.

[0398] The electronic devices shown in FIGS. 20A to 20G include a housing 9000, a display portion 9001, a screen Speaker 9003, operation keys 9005 (including a power switch or an operation switch), connection terminal Child 9006, sensor 9007 (force, displacement, position, velocity, acceleration, angular velocity, number of rotations, distance, Light, liquid, magnetism, temperature, chemical substances, sound, time, hardness, electric field, current, voltage, power, radiation, (including functions to measure flow rate, humidity, gradient, vibration, odor or infrared rays), It has 9008, etc.

[0399] The electronic devices shown in FIGS. 20A to 20G have various functions. Function to display various information (still images, videos, text images, etc.) on the display, touch panel function , calendar, date or time display functions, various software (programs) a function to control processing by wireless communication, a program recorded on a recording medium, or The electronic device can have the function of reading and processing data. The electronic device may have a variety of functions, including but not limited to the above. In addition, a camera or the like may be provided in the electronic device to take still images or videos and store them on a recording medium (external). It has functions such as saving the captured image to a memory card (built-in to the camera or the internal memory) and displaying the captured image on the display. It may be possible.

[0400] The electronic devices shown in FIGS. 20A to 20G will be described in detail below.

[0401] FIG. 20A is a perspective view showing a television device 9100. 100 is a display unit 9001 with a large screen, for example, 50 inches or more, or 100 inches or more It is possible to incorporate.

[0402] 20(B) is a perspective view showing a portable information terminal 9101. For example, the mobile information terminal 9101 can be used as a smartphone. A speaker 9003, a connection terminal 9006, a sensor 9007, etc. may be provided. The terminal 9101 can display text and image information on multiple surfaces. (See FIG. 20B.) An example of displaying three icons 9050 is shown in the figure. 051 can also be displayed on another surface of the display unit 9001. An example of the information 9051 is , notifications of incoming emails, SNS, phone calls, etc., subject of emails and SNS, sender Name, date and time, battery level, antenna reception strength, etc. An icon 9050 or the like may be displayed in the position where 51 is displayed.

[0403] 20C is a perspective view showing a portable information terminal 9102. , and has the function of displaying information on three or more surfaces of the display unit 9001. An example is shown in which information 9053 and information 9054 are displayed on different surfaces. The person holds the mobile information terminal 9102 in the breast pocket of his / her clothes. The user can also check the information 9053 displayed in a position that can be observed from above. The display can be checked without taking the mobile information terminal 9102 out of a pocket, and for example, a telephone call can be made. You can decide whether to accept it or not.

[0404] 20(D) is a perspective view showing a wristwatch-type portable information terminal 9200. The display unit 9001 can be used as a smart watch, for example. The display surface is curved, and the display can be performed along the curved display surface. In addition, the mobile information terminal 9200 can communicate with, for example, a wireless headset. Therefore, hands-free calling is also possible. The terminal 9006 can transmit data to and from other information terminals and can also charge the device. Charging can also be performed by wireless power supply.

[0405] 20(E), 20(F), and 20(G) show a foldable mobile information terminal 920. 20(E) is a perspective view showing the mobile information terminal 9201 in an unfolded state, and FIG. 20(G) is the folded state, and Fig. 20(F) is the state of Fig. 20(E) and Fig. 20(G) from one side to the other. 9 is a perspective view of the mobile information terminal 9201 in the folded state. It is highly portable and has a seamless, large display area when unfolded, making it easy to see the display. The display unit 9001 of the portable information terminal 9201 is connected by a hinge 9055. It is supported by three housings 9000. For example, the display unit 9001 has a curvature radius of 1 mm or more. It can be bent to less than 150mm.

[0406] FIG. 21A shows an example of a television device. The television device 7100 includes a housing 7 The display unit 7500 is built into the housing 7101. 101 is shown as a supported configuration.

[0407] The television device 7100 shown in FIG. 21A is operated by an operation switch provided in the housing 7101. This can be done by a separate remote control 7111 or a display unit 75. A touch panel may be applied to the remote control 71, and the remote control 71 may be operated by touching the panel. The device 11 may have a display unit in addition to the operation buttons.

[0408] The television device 7100 may be a television broadcast receiver or a network connection device. The communication device may include:

[0409] FIG. 21B shows a notebook personal computer 7200. The mobile computer 7200 includes a housing 7211, a keyboard 7212, a pointing device, and a The housing 7211 includes a display unit 7500 and an external connection port 7214. It is embedded.

[0410] 21(C) and 21(D) show the digital signage. An example of a digital signage (ge: electronic sign) is shown below.

[0411] The digital signage 7300 shown in FIG. 21C includes a housing 7301, a display unit 7500, and a speaker 7303. In addition, LED lamps, operation keys (power switch, It may have a variety of functions, including a control switch, connection terminals, various sensors, a microphone, etc. Cut.

[0412] FIG. 21(D) shows a digital signage 740 attached to a cylindrical pillar 7401. The digital signage 7400 is a display unit provided along the curved surface of a pillar 7401. It has 7500.

[0413] The larger the display 7500, the more information can be displayed at once, and the closer it is to the human eye. It is easy to attach to the surface, which has the effect of increasing the advertising effectiveness of advertisements, for example.

[0414] It is preferable that the display unit 7500 be configured as a touch panel so that a user can operate it. This will enable the information to be used not only for advertising purposes but also for route information, traffic information, and commercial facility guidance information. It can also be used to provide information that users are looking for.

[0415] Also, as shown in FIG. 21(C) and FIG. 21(D), a digital signage 7300 or The digital signage 7400 is an information terminal device 73 such as a smartphone owned by a user. 11 via wireless communication. The information of the advertisement to be displayed on the screen of the information terminal 7311, By operating it, the display on the display unit 7500 can be switched.

[0416] In addition, the Digital Signage 7300 or Digital Signage 7400 can be used with an information terminal. It is also possible to run games using the 7311 as an operating means (controller). This allows an unspecified number of users to participate in and enjoy the game at the same time.

[0417] The display device of one embodiment of the present invention is applied to the display portion 7500 in FIGS. It is possible.

[0418] Although the electronic device of this embodiment has a display unit, the present invention can also be applied to electronic devices that do not have a display unit. One embodiment of the present invention can also be applied to the above.

[0419] This embodiment may be combined, at least in part, with other embodiments described in this specification. It can be implemented in combination. [Example]

[0420] In this example, an insulating film was formed on a conductive film, and the conductive film after heat treatment was evaluated.

[0421] The samples consisted of two samples: Sample A, which is one embodiment of the present invention, and a comparative sample. The insulating film used was a boron-containing insulating film. The comparative sample was a boron-free insulating film. An insulating film was used.

[0422] <Sample preparation> First, for sample A and the comparative sample, a tungsten film with a thickness of approximately 150 nm was deposited on a quartz substrate. The tungsten film was formed by sputtering a tungsten target. The film was formed.

[0423] Next, for each of Sample A and the comparative sample, an acid film with a thickness of about 150 nm was formed on the tungsten film. The silicon oxynitride film was formed by using silane gas and dinitrogen monoxide gas. The film was formed by plasma CVD using a deposition gas. The substrate temperature during film formation was 20 The temperature was set to 0°C.

[0424] Next, an impurity element was added to Sample A. Boron ( 11 B) The impurity element was added using an ion implantation device without a mass separation mechanism. No impurity element was implanted.

[0425] The boron implantation was optimized to maximize the boron concentration in the silicon oxynitride film. The boron implantation conditions were a beam energy of 20 keV and a dose of 5 x10 15 cm -2 It was decided.

[0426] Next, the sample A and the comparative sample were each subjected to a heat treatment. The heating was carried out under atmospheric conditions at 600°C for 1 hour.

[0427] <Injection volume simulation> The boron implantation amount in the depth direction of the sample was calculated using the Monte Carlo method. TRIM (Transport ion implantation model) is a software for calculating the ion implantation process. f Ion in Matter) was used.

[0428] The implanted film used in the calculation is an insulating film with a thickness of 300 nm and a density of 2.2 g / cm3 Oxidation of The silicon film was formed using boron as an impurity element, with a dose of 5 × 10 15 cm -2 and The beam energy was set to 20 keV.

[0429] The calculation results are shown in Figure 22. In Figure 22, the vertical axis represents the volume concentration of boron ( 11 B con The horizontal axis indicates the depth. It was confirmed that the boron concentration was highest at a depth of approximately 100 nm from the surface.

[0430] <Cross-section observation and EDX analysis> Next, sample A and the comparative sample were irradiated with a focused ion beam (FIB). The thin section was made by ion beam and the cross section was observed under a scanning transmission electron microscope (STEM). Observation by Transmission Electron Microscopy For STEM observation, a scanning transmission electron microscope (HD-230, Hitachi High-Technologies Corporation) was used. 0 was used, and the acceleration voltage was 200 kV.

[0431] STEM images of the cross section of sample A are shown in Figures 23(A) and 23(B). Transmission electron image (TE image) at 100,000 times magnification Figure 23(B) shows the same area as Figure 23(A) at 100,000 times magnification. The ZC image is a Z Contrast Image. As shown in Figures 23(A) and 23(B), the material with the larger number appears brighter. No hetero-layer was observed between the tungsten film and the silicon oxynitride film.

[0432] Using the cross-sectional STEM image shown in FIG. 23(B), EDX analysis of the tungsten film was carried out. The EDX analysis was performed at point A shown in Figure 24(A). The EDX spectrum at nt A is shown in Figure 24(B). In Figure 24(B), the vertical axis indicates the The horizontal axis indicates the energy of the X-rays, and the horizontal axis indicates the intensity. As shown in FIG. 24(B), tungsten was detected in sample A, and oxygen was undetectable. It was below the limit.

[0433] The titanium and copper detected by EDX analysis were determined by the samples used for STEM observation and EDX analysis. The nickel in the sample holder is due to the mesh used to fix the sample. The detection limit is approximately 0.5 atomic %.

[0434] STEM images of the cross section of the comparative sample are shown in Figures 25(A) and 25(B). Figure 25(B) is a TE image at a magnification of 100,000 times of the same location as Figure 25(A). As shown in FIG. 25(B), the tungsten film and the silicon oxynitride film are separated by a ZC image. In the ZC image, the heterogeneous layer was observed to be darker than the tungsten.

[0435] Using the cross-sectional STEM image shown in Figure 25(B), EDX analysis of the tungsten film and the heterolayer was performed. The EDX analysis was performed at point B1 and point B2 shown in FIG. Point B1 is a tungsten film. Point B2 is The EDX spectrum at point B1 is shown in Figure 26(B), and the EDX spectrum at point B 2 is shown in Figure 26(C). In Figures 26(B) and 26(C), the vertical axis represents the energy of characteristic X-rays. The horizontal axis shows the energy, and the horizontal axis shows the intensity. As shown in B), tungsten was detected in the tungsten film, and oxygen was below the detection limit. As shown in FIG. 26(C), tungsten and oxygen were detected in the heterogeneous layer. It turned out to be tungsten oxide.

[0436] Cross-sectional observation and EDX analysis showed that the comparison sample was a tungsten film and a silicon oxynitride film. In contrast, sample A had a tungsten film and a silicon oxynitride film. No heterogeneous layer was observed between the silicon oxide nitride film and the silicon nitride film. It is thought that the tungsten film was oxidized by the oxygen in the solution, forming a tungsten oxide film. On the other hand, in Sample A which is one embodiment of the present invention, the silicon oxynitride film contains boron. As a result, oxygen contained in the silicon oxynitride film is less likely to be released, and the tungsten film is less likely to be oxidized. In other words, the oxide insulating film containing boron is less likely to be broken down into oxide insulating films. It was confirmed that the film has the function of making it difficult for oxygen to be released. [Explanation of symbols]

[0437] 100, 100A, 100B, 100C, 100D, 100E: Transistor, 102: Substrate, 103, 110, 118: insulating layer, 103d, 108n, 110d: region, 106 , 106c, 112, 120a, 120b: conductive layers, 108, 108c: semiconductor layers, 11 2f: Conductive film, 114: Metal oxide layer, 114f: Metal oxide film, 130A, 130B: Capacitor elements 141a, 141b, 142: openings

Claims

[Claim 1] forming a first conductive layer on a substrate; forming a first insulating layer covering the substrate and the first conductive layer; forming a semiconductor layer on the first insulating layer; forming a second insulating film on the semiconductor layer; forming a metal oxide film on the second insulating film; forming a second conductive film on the metal oxide film; etching a portion of the second insulating film, a portion of the metal oxide film, and a portion of the second conductive film to form a second insulating layer, a metal oxide layer, and a second conductive layer; forming a third insulating layer that covers the top surface of the first insulating layer, the top surface and side surfaces of the semiconductor layer, the side surfaces of the second insulating layer, the side surfaces of the metal oxide layer, and the top surface and side surfaces of the second conductive layer; etching a portion of the third insulating layer to form a first opening and a second opening that reach the semiconductor layer; forming a third conductive layer in contact with the semiconductor layer in the first opening and a fourth conductive layer in contact with the semiconductor layer in the second opening; the metal oxide layer comprises aluminum or hafnium; the semiconductor layer includes a metal oxide; the third insulating layer is formed by a CVD method using at least a silicon source, an oxygen source, and an impurity element source as raw material gases; The impurity element source is PH ３ and B ２ H ６ At least one of the third insulating layer has a ratio of a maximum value to a minimum value of impurity concentration in a thickness direction of the third insulating layer during formation of the third insulating layer, the ratio being 1.0 or more and 10.0 or less.

Images