Electronic equipment

Abstract

To provide electronic equipment capable of reducing damage due to high temperature and high pressure.SOLUTION: Electronic equipment has a semiconductor substrate, a chip, a connection part, and an insulation film. A chip differs in thermal coefficient of expansion from the semiconductor substrate. The connection part includes a porous metal layer connecting connection pads provided on opposed principal surfaces of the semiconductor substrate and chip. The insulation film covers peripheral edge parts of the connection pads. With respect to the insulation film, recess opening parts of the connection pads which are not covered with the insulation film has a larger diameter than the connection parts.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to electronic devices. [Background technology]

[0002] One technique for mounting electronic component chips on a semiconductor substrate is flip-chip mounting, in which metal bumps provided on the upper surface of the semiconductor substrate are heated and pressed against connection pads on the underside of the chip (see, for example, JP 2011-077308 A). Bump materials typically used are bulk gold, copper, solder, and the like. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2011-077308 Summary of the Invention [Problem to be solved by the invention]

[0004] However, when using bulk gold or copper as the bump material to flip-chip mount a chip with a different thermal expansion coefficient than the semiconductor substrate to a semiconductor substrate, the bump connection must be made at high temperature and pressure, which can damage the chip and reduce the reliability of the electronic device.

[0005] Furthermore, when solder is used as the bump material, the semiconductor substrate and chip can be connected at relatively low temperatures and pressures, but the connection strength is lower than that of gold or copper bumps, so if the thermal expansion coefficients of the semiconductor substrate and chip are different, the reliability in terms of connection strength decreases. [Means for solving the problem]

[0006] According to the present disclosure, an electronic device is provided. The electronic device has a semiconductor substrate, a chip, a connection portion, and an insulating film. The chip has a thermal expansion coefficient different from that of the semiconductor substrate. The connection portion includes a porous metal layer that connects connection pads provided on opposing main surfaces of the semiconductor substrate and the chip. The insulating film covers the periphery of the connection pad. The diameter of the opening of a recess in the connection pad that is not covered by the insulating film is larger than the diameter of the connection portion. [Brief explanation of the drawings]

[0007] A more complete appreciation of the present invention and its attendant advantages will be readily obtained from the following detailed description of the invention when considered in conjunction with the accompanying drawings.

[0008] [Figure 1] FIG. 1 is an explanatory diagram showing a cross section of an electronic device according to the present disclosure. [Figure 2A] 1A to 1C are explanatory views showing a process of forming bumps on a semiconductor substrate according to the present disclosure. [Figure 2B] 1A to 1C are explanatory views showing a process of forming bumps on a semiconductor substrate according to the present disclosure. [Figure 2C] 1A to 1C are explanatory views showing a process of forming bumps on a semiconductor substrate according to the present disclosure. [Figure 2D] 1A to 1C are explanatory views showing a process of forming bumps on a semiconductor substrate according to the present disclosure. [Figure 3A] 1A to 1C are explanatory views showing a process of forming bumps on a chip according to the present disclosure. [Figure 3B] 1A to 1C are explanatory views showing a process of forming bumps on a chip according to the present disclosure. [Figure 3C] 1A to 1C are explanatory views showing a process of forming bumps on a chip according to the present disclosure. [Figure 3D] 1A to 1C are explanatory views showing a process of forming bumps on a chip according to the present disclosure. [Figure 4] 1 is a block diagram showing an example of the configuration of a distance measuring device according to an embodiment. [Figure 5] FIG. 2 is an explanatory diagram showing an example of the arrangement of components in the distance measuring device according to the embodiment. [Figure 6] FIG. 2 is a circuit diagram showing an equivalent model of a drive circuit according to an embodiment. [Figure 7] 5A and 5B are diagrams illustrating the rise time and fall time of a current flowing in a light-emitting element according to the embodiment. [Figure 8] 1 is an explanatory diagram of a cross-sectional structure of a light source device according to an embodiment. [Figure 9A] 5A to 5C are explanatory diagrams illustrating an assembly process of the light source device according to the embodiment. [Figure 9B] 5A to 5C are explanatory diagrams illustrating an assembly process of the light source device according to the embodiment. [Figure 9C] 5A to 5C are explanatory diagrams illustrating an assembly process of the light source device according to the embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0009] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. In the following embodiments, the same components are designated by the same reference numerals and hatched, and redundant description will be omitted.

[0010] [1. Cross-sectional structure of electronic device] 1, electronic device 1 according to the present disclosure includes semiconductor substrate 2, chip 3, and connection portions (hereinafter referred to as bumps 4) that connect connection pads 21, 31 provided on opposing main surfaces of semiconductor substrate 2 and chip 3. The semiconductor substrate 2, chip 3, and connection pads 21, 31 are described in detail below. Other embodiments may include other exemplary details.

[0011] The chip 3 is, for example, a semiconductor laser, and has connection pads 31, a semiconductor laser light emitting section 32, and the like formed inside a GaAs (gallium arsenide) base material. The light emitting section 32 has a plurality of light emitting elements 321 arranged two-dimensionally and emitting laser light. Note that the electronic components formed on the substrate of the chip 3 may be any electronic components other than the semiconductor laser light emitting section 32. The base material of the chip 3 may also be, for example, a semi-insulating base material such as InP (indium phosphide).

[0012] The semiconductor substrate 2 is, for example, a Si (silicon) substrate, and has a drive circuit 22 formed therein for driving the semiconductor laser. Note that the electronic circuit formed inside the semiconductor substrate 2 may be any electronic circuit other than the drive circuit 22 for the semiconductor laser.

[0013] In the electronic device 1, a chip 3 is flip-chip mounted on a semiconductor substrate 2, and a drive circuit 22 in the semiconductor substrate 2 and the chip 3, which is a semiconductor laser, are electrically connected by bumps 4.

[0014] In a typical flip-chip mounting process, a chip is mounted on a semiconductor substrate by heating bulk metal bumps such as gold (Au), copper (Cu), and solder that are provided on the opposing main surfaces of the semiconductor substrate or chip while pressing them together.

[0015] However, when the thermal expansion coefficients of the semiconductor substrate and the chip differ by, for example, 0.1 ppm / ° C. or more, the following problems arise when bulk Au, Cu, solder, or the like is used as the bump material.

[0016] For example, when bulk gold is used as the bump material, in order to stably connect a semiconductor substrate and a chip, which have different thermal expansion coefficients, using the bumps, it is necessary to heat them to a high temperature of 300°C or higher and apply a high pressure of 100 MPa or higher between the semiconductor substrate and the chip.

[0017] Furthermore, when bulk Cu is used as the bump material, heating to 380°C or higher is required. Thus, when bulk Au or Cu is used as the bump material, the bump connection must be performed at high temperature and pressure, and such high temperature and pressure can damage the chip and reduce the reliability of the electronic device.

[0018] On the other hand, when solder is used as the bump material, bump connections can be made at lower temperatures and pressures than with Au or Cu, but solder is inferior to Au or Cu in heat resistance and connection strength. For this reason, when a chip expands due to heat generated by an electronic component such as a semiconductor laser mounted on the chip, solder bumps can cause open circuit failures due to the difference in thermal expansion coefficients between the semiconductor substrate and the chip, which can reduce the reliability of the electronic device.

[0019] As described above, the semiconductor substrate 2 according to the present disclosure is a Si substrate with a thermal expansion coefficient of 5.7 ppm / °C. On the other hand, the base material of the chip 3 according to the present disclosure is GaAs with a thermal expansion coefficient of 2.6 ppm / °C.

[0020] As described above, the difference in thermal expansion coefficient between the semiconductor substrate 2 and the chip 3 of the electronic device 1 is much greater than 0.1 ppm / °C. Therefore, if the bump material of the electronic device 1 is bulk Au, Cu, or solder, the above-mentioned problems may occur, resulting in a decrease in reliability.

[0021] Therefore, the bump 4 of the electronic device 1 includes, for example, an Au porous metal layer 41. The porous metal layer 41 includes Au particles with a particle diameter of 0.005 μm to 1.003 μm. The component of the porous metal layer 41 may be, for example, Cu, Ag (silver), or Pt (platinum).

[0022] Porous metal layer 41, which contains metal particles with a particle size of 0.005 μm to 1.0 μm, can achieve metal bonding at temperatures lower than the melting point of the bulk metal due to the size effect of the particle size. For example, porous metal layer 41 can connect semiconductor substrate 2 and chip 3 at temperatures of about 100°C when the component is Au, about 250°C when the component is Ag, and about 150°C when the component is Cu. This reduces damage to chip 3 due to heat in electronic device 1, thereby improving reliability.

[0023] For example, the ratio of the height of the porous metal layer 41 to the height of the bump 4, e.g., the ratio of the thickness or longitudinal elongation of the porous metal layer 41 to the thickness or longitudinal elongation of the bump 4, may be 90% or more, or may be 95% or more. Here, the longitudinal elongation refers to elongation along the vertical direction, which may be the stacking direction of the semiconductor substrate 2 and the chip 3, e.g., the direction perpendicular to the main surface of the semiconductor substrate 2 or the chip 3. In addition to the porous metal layer 41, the bump 4 may include one or more layers that are non-porous or have a porosity smaller than that of the porous metal layer 41, e.g., the porosity is the volume fraction of voids. Examples of metal layers are described below with reference to metal films 42 and 43. Furthermore, since the porous metal layer 41 is elastic, it undergoes elastic deformation even if the chip 3 expands at a different thermal expansion coefficient from that of the semiconductor substrate 2 due to heat generated by a semiconductor laser, thereby suppressing open circuit failures. As a result, the electronic device 1 having the above-described ratio of the height of the porous metal layer 41 to the height of the bumps 4 can have improved reliability compared to, for example, a case in which solder bumps are used.

[0024] Such an electronic device 1 is manufactured by stacking a chip 3 on a semiconductor substrate 2 having bumps 4 on its upper surface, and flip-chip mounting the chip 3 on the semiconductor substrate 2 by connecting the porous metal layer 41 of the bumps 4 to the connection pads 31 without melting them.

[0025] Alternatively, the electronic device 1 may be manufactured by stacking a chip 3 having bumps including a porous metal layer 41 on the underside thereof on the semiconductor substrate 2, and connecting the porous metal layer 41 of the bumps to the connection pads 21 without melting them, thereby flip-chip mounting the chip 3 on the semiconductor substrate 2. Note that the bumps may be provided on both the semiconductor substrate 2 and the chip 3 before stacking.

[0026] When the bump 4 is provided on the semiconductor substrate 2 side, it has a metal film 42 between the porous metal layer 41 and the connection pad 21 on the semiconductor substrate 2 side. When the bump is provided on the chip 3 side, it has a metal film between the porous metal layer 41 and the connection pad 31 on the chip 3 side.

[0027] In the present disclosure, the ratio of the film thickness of the metal film 42 to the thickness of the bumps 4 in the direction perpendicular to the main surface of the semiconductor substrate 2 is set to 2% to 10% or less, thereby enabling a fine pitch of 20 μm or less for the bumps 4. Such a fine pitch will be described later together with the process of forming the bumps 4.

[0028] [2. Bump formation process] Next, the bump forming process according to the present disclosure will be described with reference to Figures 2A to 3D. Figures 2A to 2D are explanatory views showing the process of forming bumps 4 on a semiconductor substrate 2 according to the present disclosure. Figures 3A to 3D are explanatory views showing the process of forming bumps 4a (see Figure 3D) on a chip 3 according to the present disclosure.

[0029] 2A, when forming bumps 4 on the semiconductor substrate 2, first, a photoresist layer 51 is formed on the surface of the semiconductor substrate 2 on the side where the connection pads 21 are provided. Then, by photolithography, through holes are formed in the photoresist layer 51 at positions where the bumps 4 will be formed later, thereby exposing the surfaces of the connection pads 21.

[0030] At this time, the through holes are formed so that the distance between the centers of adjacent through holes is 20 μm (20 μm pitch). These through holes are filled with paste 40 containing metal particles that will become the material of porous metal layer 41 in a later process, but because the through holes have a fine structure with a 20 μm pitch, if paste 40 is filled in this state, there is a risk that the fine structure will be damaged and collapse.

[0031] 2B, a metal film 42 is formed on the upper surfaces of the photoresist layer 51 and the connection pads 21 by, for example, sputtering. A metal having the same composition as the metal particles contained in the paste 40 that will be later filled into the through holes is selected as the material for the metal film 42. In this example, the metal film 42 is made of Au.

[0032] As a result, the photoresist layer 51 hardens as its surface is coated with the metal film 42, which prevents the fine structure from collapsing when the through-holes are filled with the paste 40 containing metal particles.

[0033] Furthermore, if the metal film 42 formed here is too thick, the opening of the through-hole will be narrow, making it difficult to fill the through-hole with the paste 40 containing metal particles. Therefore, here, a thin metal film 42 is formed so that the ratio of the thickness of the metal film 42 to the depth D of the through-hole, in other words, the thickness of the bump 4 formed later in the direction perpendicular to the main surface of the semiconductor substrate 2 (height D of the bump 4) is 10% or less.

[0034] For example, when forming bumps 4 with a height of 10 μm arranged at a pitch of 20 μm, the thickness of the metal film 42 is set to 0.2 μm. This prevents the opening of the through-hole from narrowing even when the metal film 42 is formed, and therefore allows the through-hole to be sufficiently filled with the paste 40 containing metal particles in a later process.

[0035] 2C, paste 40 containing Au particles with a purity of 99.9% by weight or more and a particle diameter of 0.005 μm to 1.0 μm is filled into the through-holes formed in photoresist layer 51. Any method can be used to fill the through-holes with paste 40, such as screen printing or spreading dropped paste 40 with a spatula.

[0036] Thereafter, the paste 40 is dried and sintered, and then the photoresist layer 51 is removed using a remover or the like. As a result, as shown in FIG. 2D, a two-layer bump 4 is completed in which an Au metal film 42 and a porous metal layer 41 containing Au particles with a particle diameter of 0.005 μm to 1.0 μm are sequentially laminated on the surface of the connection pad 21.

[0037] In this way, the bump 4 includes the metal film 42 whose film thickness is 10% or less relative to the height of the bump 4. The metal film 42 is formed on the surface of the photoresist layer 51 and the connection pad 21 to prevent the fine structure of the bump 4 patterned on the photoresist layer 51 from collapsing. This allows the bumps 4 to be formed at a fine pitch of 20 μm or less.

[0038] Furthermore, since the metal film 42 is formed on the surface of the connection pad 21 by sputtering, it is firmly bonded to the connection pad 21 even if the connection pad 21 is made of a metal with a different composition from that of the metal film 42.

[0039] Furthermore, the metal film 42 may be formed of a metal of a different composition from that of the porous metal layer 41 laminated on the surface, but if it is formed of the same composition, Au, the porous metal layer 41 will be bonded to the metal film 42 with stronger bonding strength than if it were provided on another metal film of a different composition. Note that if the bump 4 is made of a composition other than Au (for example, Cu, Ag (silver) or Pt (platinum)), the metal film 42 may also be made of a composition other than Au (for example, Cu, Ag (silver) or Pt (platinum)).

[0040] Next, a description will be given of the process of forming bumps 4a shown in Fig. 3D on chip 3. As shown in Fig. 3A, when forming bumps 4a on chip 3, first, a photoresist layer 52 is formed on the surface of chip 3 on the side where connection pads 31 are provided. Then, by photolithography, through holes are formed in photoresist layer 52 at positions where bumps 4a will be formed later, exposing the surfaces of connection pads 31.

[0041] 3B, a metal film 43 is formed by, for example, sputtering on the upper surfaces of the photoresist layer 52 and the connection pads 31. The material of the metal film 43 is selected to be the same as the material of the particles contained in the paste 40 that will be later filled into the through holes, and is, for example, Au.

[0042] As a result, the photoresist layer 52 hardens as its surface is coated with the metal film 43, which prevents the fine structure from collapsing when the through-holes are filled with a paste 40 containing particles, such as Au particles.

[0043] Also, here, a thin metal film 43 is formed such that the ratio of the thickness of the metal film 43 to the depth D of the through hole, in other words, the thickness of the bump 4a to be formed later in a direction perpendicular to the main surface of the chip 3 (height D of the bump 4a) is 10% or less.

[0044] For example, when forming 10 μm high bumps arranged at a 20 μm pitch, like the bumps 4 on the semiconductor substrate 2, the thickness of the metal film 43 is set to 0.2 μm. This prevents the opening of the through-hole from narrowing even when the metal film 43 is formed, and therefore allows the through-hole to be sufficiently filled with the paste 40 containing Au particles in a later process.

[0045] Subsequently, as shown in FIG. 3C, the through holes formed in the photoresist layer 52 are filled with a paste 40 containing particles, for example, Au particles with a particle diameter of 0.005 μm to 1.0 μm, with a purity of 99.9% by weight or more.

[0046] Thereafter, the paste 40 is dried and sintered, and then the photoresist layer 52 is removed using a remover or the like. As a result, as shown in Fig. 3D, a two-layer bump 4a is completed on the surface of the connection pad 31, in which, for example, a metal film 43 made of Au and a porous metal layer 41 containing Au particles with a particle diameter of 0.005 µm to 1.0 µm are sequentially laminated.

[0047] In this way, the bumps 4a are provided with the metal film 43 whose thickness is 10% or less relative to the height of the bumps 4a, which allows the bumps 4a to be fine-pitched to a pitch of 20 μm or less, similar to the bumps 4 on the semiconductor substrate 2 side.

[0048] Furthermore, the bump 4a, like the bump 4 on the semiconductor substrate 2 side, can firmly bond the metal film 43 to the connection pad 31, and can firmly bond the metal film 43 to the porous metal layer 41.

[0049] In the above-described embodiment, a case where a chip 3 without bumps 4a is mounted on a semiconductor substrate 2 with bumps 4, and a case where a chip 3 with bumps 4a is mounted on a semiconductor substrate 2 without bumps 4 are described, but this is merely an example.

[0050] The electronic device according to the present disclosure may have a configuration in which a chip 3 provided with bumps 4a is mounted on a semiconductor substrate 2 provided with bumps 4. In such a configuration, the ratio of the film thickness of the metal films 42, 43 to half the thickness in a direction perpendicular to the main surfaces of the semiconductor substrate 2 and the chip 3 in the stack of the bumps 4 and 4a that serve as the connecting portions connecting the semiconductor substrate 2 and the chip 3 is 10% or less, preferably 5% or less.

[0051] In addition, in the above-described embodiment, the base material of the chip 3 is described as a base material other than Si, but the base material of the chip 3 may also be Si doped with impurities as long as it has a thermal expansion coefficient different from that of the semiconductor substrate 2.

[0052] The chip 3 including the semiconductor laser light emitting unit 32 and the semiconductor substrate 2 including the semiconductor laser drive circuit 22 are mounted on a distance measuring device such as a ToF sensor or structured light. When mounted on a distance measuring device, the semiconductor laser light emitting unit 32 functions as a light source for the ToF sensor or structured light, for example.

[0053] Next, a distance measuring device in which the electronic device 1 according to the embodiment is installed will be described with reference to Fig. 4. Fig. 4 is a block diagram showing an example of the configuration of the distance measuring device 100 according to the embodiment. As shown in Fig. 4, the distance measuring device 100 includes a light source device 110, an imaging device 120, and a control unit 130.

[0054] The light source device 110 includes a chip 3 having a light emitting unit 32, a semiconductor substrate 2 having a drive circuit 22, a power supply circuit 111, and an emission-side optical system 112. The imaging device 120 includes an imaging-side optical system 121, an image sensor 122, and an image processing unit 123.

[0055] The control unit 130 includes a distance measurement unit 131. The control unit 130 may be included in the light source device 110, the imaging device 120, or may be configured separately from the light source device 110 and the imaging device 120.

[0056] The light emitting unit 32 includes a plurality of light emitting elements 321 (see FIG. 1) that are arranged two-dimensionally and emit laser light. Each light emitting element 321 has, for example, a VCSEL (Vertical Cavity Surface Emitting Laser) structure.

[0057] The drive circuit 22 has an electric circuit for driving the light emitting unit 32. The power supply circuit 111 generates a power supply voltage for the drive circuit 22 from an input voltage supplied from, for example, a battery (not shown) or the like provided in the distance measuring device 100. The drive circuit 22 drives the light emitting unit 32 using the power supply voltage.

[0058] Light emitted from the light-emitting unit 32 is irradiated onto the subject S to be measured via the light-emitting side optical system 112. Then, the light thus irradiated is reflected from the subject S and enters the imaging surface of the image sensor 122 via the imaging side optical system 121.

[0059] The image sensor 7 has an imaging element such as a CCD (Charge Coupled Device) sensor or a CMOS (Complementary Metal Oxide Semiconductor) sensor, and receives reflected light from the subject S that enters via the imaging side optical system 121 as described above, converts it into an electrical signal, and outputs it.

[0060] The image sensor 122 performs, for example, CDS (Correlated Double Sampling) processing, AGC (Automatic Gain Control) processing, etc. on the electrical signal obtained by photoelectrically converting the received light, and further performs A / D (Analog / Digital) conversion processing.

[0061] The image sensor 122 then outputs the image signal as digital data to the image processing unit 123, which will be described later. The image sensor 122 also outputs a frame synchronization signal to the drive circuit 22. This enables the drive circuit 22 to cause the light emitting element 321 in the light emitting unit 32 to emit light at a timing according to the frame cycle of the image sensor 122.

[0062] The image processing unit 123 is configured by an image processor such as a DSP (Digital Signal Processor), etc. The image processing unit 123 performs various types of image signal processing on the digital signal (image signal) input from the image sensor 122.

[0063] The control unit 130 is configured by, for example, a microcomputer having a CPU (Central Processing Unit), ROM (Read Only Memory), RAM (Random Access Memory), etc., or an information processing device such as a DSP. The control unit 130 controls the drive circuit 22 for controlling the light emitting operation by the light emitting unit 32, and controls the image capturing operation by the image sensor 122.

[0064] The control unit 130 also functions as a distance measuring unit 131. The distance measuring unit 131 measures the distance to the subject S based on an image signal input via the image processing unit 123 (i.e., an image signal obtained by receiving reflected light from the subject S).

[0065] Furthermore, the distance measuring unit 131 measures the distance to each part of the subject S in order to enable identification of the three-dimensional shape of the subject S. Furthermore, the control unit 130 may be configured to control the power supply circuit 111.

[0066] Here, we will explain a specific distance measurement method used in the distance measuring device 100. As a distance measurement method used in the distance measuring device 100, for example, a distance measurement method using an STL (Structured Light) method or a ToF (Time of Flight) method can be adopted.

[0067] The STL method is a method for measuring distance based on an image obtained by capturing an image of a subject S illuminated with light having a predetermined light / dark pattern, such as a dot pattern or a grid pattern.

[0068] In the STL method, pattern light with a dot pattern is irradiated onto the subject S. The pattern light is divided into multiple blocks, and a different dot pattern is assigned to each block so that the dot patterns do not overlap between blocks. When the STL method is employed, the light emitting unit 32 functions as a light source for the STL.

[0069] The ToF method is a method for measuring the distance to an object by detecting the time of flight (time difference) of light emitted from the light-emitting unit 32, reflected by the object, and reaching the image sensor 122.

[0070] When a so-called direct ToF method is adopted as the ToF method, a SPAD (Single Photon Avalanche Diode) is used as the image sensor 122, and the light emitting unit 32 is pulse-driven.

[0071] In this case, the distance measurement unit 131 calculates the time difference between the light emitted from the light emitting unit 32 and the light received by the image sensor 122 based on the image signal input via the image processing unit 123, and calculates the distance to each part of the subject S based on the time difference and the speed of light.

[0072] When a so-called indirect ToF method (phase difference method) is adopted as the ToF method, for example, an IR (infrared) image sensor is used as the image sensor 7. When the ToF method is adopted, the light emitting unit 32 functions as a light source for the ToF sensor.

[0073] Next, an example of the arrangement of components in the distance measuring device 100 according to the embodiment will be described with reference to Fig. 5. Fig. 5 is an explanatory diagram showing an example of the arrangement of components in the distance measuring device 100 according to the embodiment.

[0074] As shown in Fig. 5, the distance measuring device 100 has a light source device 110 and an imaging device 120 mounted on the same plane of a mounting substrate 101. Note that the control unit 130 is not shown in Fig. 5. The imaging device 120 has an image sensor 122 in which a plurality of imaging elements 124 are arranged, and an image processing unit 123, and the image sensor 122 is stacked on the image processing unit 123.

[0075] Furthermore, the light source device 110 has a chip 3 including a light emitting unit 32 and a semiconductor substrate 2 including a drive circuit 22, and the chip 3 is flip-chip mounted on the semiconductor substrate 2. In this way, the semiconductor substrate 2 and the chip 3 have a layered structure.

[0076] Therefore, the light source device 110 can be made smaller by reducing the area occupied by the mounting substrate 101 compared to when the semiconductor substrate 2 and the chip 3 are mounted side by side on the same plane, for example.

[0077] The light source device 110 may be configured such that a chip 3 having a light emitting unit 32 is stacked on a semiconductor substrate having a temperature sensor and flip-chip mounted, and a semiconductor substrate 2 having a drive circuit 22 is mounted on the same plane as the semiconductor substrate 2 on the mounting substrate 101.

[0078] In such a configuration, the temperature sensor detects the temperature near the light-emitting unit 32. The drive circuit 22 controls the drive of the light-emitting unit 32 in accordance with the temperature near the light-emitting unit 32 detected by the temperature sensor. This allows the drive circuit 22 to suppress fluctuations in the light-emitting characteristics of the light-emitting unit 32 caused by changes in temperature.

[0079] The semiconductor substrate 2 and the chip 3 are connected by the bumps 4 including the aforementioned Au porous metal layer 41. This allows the semiconductor substrate 2 and the chip 3 to be connected under relatively low temperature and pressure conditions, thereby reducing damage caused by heat.

[0080] Furthermore, when the semiconductor substrate 2 is made of silicon and the chip 3 is made of GaAs material, even if the chip 3 generates heat and expands at a thermal expansion coefficient different from that of the semiconductor substrate 2, the porous metal layer 41 will elastically deform, thereby preventing open failures in the bumps 4.

[0081] Furthermore, the light source device 110 has the chip 3 stacked on the semiconductor substrate 2 and flip-chip mounted by bumps 4 including a porous metal layer 41 of Au. With this configuration, light emission can be accelerated compared to when the semiconductor substrate 2 and the chip 3 are mounted side by side on the same plane. This enables the distance measurement unit 131 to improve distance measurement accuracy. Next, such accelerated light emission and improved distance measurement accuracy will be described with reference to FIGS. 6 and 7.

[0082] Fig. 6 is a circuit diagram showing an equivalent model of the drive circuit 22 according to the embodiment. Fig. 7 is a diagram illustrating the rise time and fall time of a current flowing through a light-emitting element 321 according to the embodiment. As shown in Fig. 6, when a current is passed through the light-emitting element 321 to cause it to emit light, the drive circuit 22 passes a large light-emitting current I1 through the light-emitting element 321, which serves as an active resistor R.

[0083] At this time, a shunt current I2 also flows through the parasitic capacitance C of the bump 4 connecting the drive circuit 22 and the light emitting section 32, and a drive current I3 also flows through the parasitic inductance L, but a counter electromotive current I4 flows through the parasitic inductance L.

[0084] For this reason, as shown by the dashed line in Figure 7, it is ideal for the current flowing through the light-emitting element 321 to rise and fall instantaneously, but in reality, as shown by the thick solid line, the light-emitting current I1 becomes sluggish when driven with a large current due to the influence of the back electromotive current I4.

[0085] This increases the rise time (Tr) and fall time (Tf) of the light-emitting current I1 flowing through the light-emitting element 321. The rise time Tr and fall time Tf increase as the connection line connecting the drive circuit 22 and the light-emitting unit 32 increases.

[0086] Therefore, in the case of a light source device in which the semiconductor substrate 2 and the chip 3 are mounted side by side on the same plane, the drive circuit 22 in the semiconductor substrate 2 and the light emitting section 32 in the chip 3 are connected by a long bonding wire, which results in a long rise time Tr and fall time Tf.

[0087] In contrast, in the light source device 110 according to the embodiment, the drive circuit 22 and the light emitting unit 32 are connected by bumps 4 that are shorter than bonding wires, and therefore it is possible to prevent the rise time Tr and fall time Tf from becoming longer. Therefore, the light source device 110 can emit light faster than a light source device in which the semiconductor substrate 2 and the chip 3 are mounted side by side on the same plane.

[0088] Furthermore, in the case of a light source device in which the semiconductor substrate 2 and the chip 3 are mounted side by side on the same plane, the rise time Tr becomes long, which may result in a decrease in distance measurement accuracy. For example, in the case where the distance measuring device 100 is a ToF sensor, the distance measuring unit 131 measures the distance to the subject S based on the time from when the light emission luminance of the light emitting element 321 reaches its peak to when the light reception luminance of the image sensor 122 reaches its peak.

[0089] At this time, as described above, the light source device in which the semiconductor substrate 2 and the chip 3 are mounted side by side on the same plane has a longer rise time Tr. Accordingly, the light emission luminance of the light emitting element 321 increases gradually, and the light reception luminance of the image sensor 122 also increases gradually.

[0090] As a result, the distance measurement unit 131 erroneously determines that the received light luminance by the image sensor 122 has reached its peak before it actually does, and measures the distance to the subject S as shorter than the actual distance, resulting in reduced distance measurement accuracy.

[0091] In contrast to this, the light source device 110 according to the embodiment is capable of emitting light at high speed, and therefore can quickly increase the light emission luminance of the light emitting element 321. As a result, the light reception luminance of the image sensor 122 also quickly increases.

[0092] Therefore, the distance measurement unit 131 can accurately measure the distance to the subject S by more accurately determining the timing at which the luminance of light received by the image sensor 122 reaches its original peak, thereby improving the accuracy of distance measurement.

[0093] Next, an example of the cross-sectional structure of the light source device 110 will be described with reference to Fig. 8. Fig. 8 is an explanatory diagram of the cross-sectional structure of the light source device 110 according to the embodiment. As shown in Fig. 8, the light source device 110 has a structure in which a chip 3 is stacked and flip-chip mounted on a Si semiconductor substrate 2 on which a drive circuit 22 (see Fig. 1) is formed.

[0094] The chip 3 has, for example, a plurality of light-emitting elements 321 formed on the surface (the lower surface in FIG. 8) of a GaAs substrate 141. Each of the plurality of light-emitting elements 321 has a cathode on the GaAs substrate 141 side and an anode on the semiconductor substrate 2 side, with the cathodes connected to each other. Note that each of the light-emitting elements 321 may have an anode on the GaAs substrate 141 side and a cathode on the semiconductor substrate 2 side. In this case, the anodes are connected to each other.

[0095] Each of the plurality of light-emitting elements 321 has an anode electrode 142 and a cathode electrode 143 arranged side by side on the same plane. The plurality of light-emitting elements 321 emits light when a current flows from the anode electrode 142 to the cathode electrode 143, and emits laser light in a direction from the front surface (lower surface) to the back surface (upper surface) of the GaAs substrate 141, as shown by the white arrow in FIG.

[0096] The semiconductor substrate 2 has a plurality of connection pads 150 provided on the surface facing the chip 3. The plurality of connection pads 150 are provided at positions facing the anode electrodes 142 and cathode electrodes 143 of the stacked chips, respectively.

[0097] The connection pad 150 is connected to the anode electrode 142 and the cathode electrode 143 by a bump 4 including an Au porous metal layer 41. The connection pad 150 connected to the cathode electrode 143 is connected to ground (not shown) via a wiring 151.

[0098] Furthermore, one end of a switch 154 is connected to the connection pad 150 connected to each anode electrode 142 via a wire 152 and a pad 153 provided between one end of the switch 154 and the connection pad 150. The other end of the switch 154 is connected to a current source that supplies a light-emitting current I1. When the electrode 142 serves as a cathode electrode and the electrode 143 serves as an anode electrode, the switch 154 is connected to each electrode that serves as a cathode.

[0099] Each switch 154 is individually controlled by the drive circuit 22. This allows the drive circuit 22 to individually and independently control each light-emitting element 321. As a result, when the distance measuring device 100 measures distance using the STL method, the light source device 110 can irradiate the subject S with pattern light of various types of dot patterns. Note that each switch 154 may be shared by multiple light-emitting elements 321 and controlled for each group of several light-emitting elements 321.

[0100] Next, the assembly process of the light source device 110 will be described with reference to Figures 9A to 9C. Figures 9A to 9C are explanatory views of the assembly process of the light source device 110 according to the embodiment. Here, the process of connecting the chip 3 and the semiconductor substrate 2 will be described.

[0101] 9A to 9C, the same components as those shown in Fig. 8 are denoted by the same reference numerals as those shown in Fig. 8, and redundant description will be omitted. Note that, although a case where a bump 4a (see Fig. 3D) is provided on the anode electrode 142 side of the light emitting element 321 will be described here, a bump 4 (see Fig. 2D) may also be provided on the connection pad 150 side of the semiconductor substrate 2.

[0102] As shown in FIG. 9A, when the bump 4a is provided on the anode electrode 142 side of the light emitting element 321, that is, on the chip 3 side, it includes, for example, an Au metal film 43 between the Au-containing porous metal layer 41 and the anode electrode 142.

[0103] The ratio of the thickness of the metal film 43 to the height of the bumps 4a is less than 10%, more preferably less than 5%. For example, when a porous metal layer 41 with a height (thickness) of 10 μm is formed, the metal film 43 is formed to have a thickness of 0.2 μm.

[0104] Similarly, when bumps 4 (see FIG. 2D) are provided on the connection pads 150 of the semiconductor substrate 2, the metal film 42 is formed so that the ratio of the film thickness to the height of the bumps 4 is less than 10%, more preferably less than 5%. For example, when a porous metal layer 41 with a height (thickness) of 10 μm is formed, the metal film 42 is formed so that the film thickness is 0.2 μm.

[0105] The metal film 43 is formed to strengthen the fine structure of the photoresist layer 52 (see FIG. 3B) that has been patterned to form the bumps 4a on the chip 3. This allows the bumps 4a to be fine-pitched, with a pitch of 20 μm or less, when the height is set to about 10 μm.

[0106] In addition, the following description is given assuming that the component of the connection pad 150 on the semiconductor substrate 2 side is Au, the same as that of the porous metal layer 41. However, if the component of the connection pad 150 is other than Au, a film of Au, the same as that of the porous metal layer 41, is formed on the surface of the connection pad 150. This can increase the connection strength between the connection pad 150 and the porous metal layer 41.

[0107] When connecting such a chip 3 to a semiconductor substrate 2, as shown in FIG. 9A, first, the chip 3 is placed on the semiconductor substrate 2, and the connection pad 150 provided on the upper surface of the semiconductor substrate 2 is aligned with the bump 4a provided on the anode electrode 142 on the chip 3 side.

[0108] 9B, the chip 3 is lowered to bring the lower surfaces of the bumps 4a into contact with the upper surfaces of the connection pads 150, and a predetermined pressure is applied. After that, the bumps 4a are heated to a relatively low temperature of about 100°C, and the connection pads 150 and the anode electrodes 142 are connected by the bumps 4a without melting the Au porous metal layers 41.

[0109] At this time, the porous metal layer 41 is slightly crushed in the thickness direction by the overheating temperature and the applied pressure, reducing its height (thickness). As a result, after the chip 3 and the semiconductor substrate 2 are connected by the bumps 4a, the ratio of the film thickness of the metal film 43 to the height of the bumps 4a becomes less than 20%.

[0110] Similarly, when a bump 4 (see FIG. 2D) is provided on the connection pad 150 side of the semiconductor substrate 2, after the chip 3 and the semiconductor substrate 2 are connected by the bump 4, the ratio of the film thickness of the metal film 42 to the height of the bump 4 will be less than 20%.

[0111] Here, the side surfaces of the light emitting element 321 provided on the chip 3 and the side surfaces and bottom peripheral portions of the anode electrode 142 provided on the anode of the light emitting element 321 are covered with an insulating film 144. Such insulating film 144 may contain at least one of SiO2 (silicon oxide) and SiN (silicon nitride), for example.

[0112] The side surfaces and the periphery of the upper surface of the connection pad 150 provided on the upper surface of the semiconductor substrate 2 are covered with an insulating film 155. The insulating film 155 may contain, for example, at least one of SiO2 and SiN. The portion of the upper surface of the connection pad 150 that is not covered with the insulating film 155, in other words, the diameter of the upper opening of the insulating film 155, is formed to be larger than the diameter of the bump 4a.

[0113] As a result, even if there is a slight misalignment between the position of the connection pad 150 and the position of the bump 4a, the connection pad 150 and the anode electrode 142 of the light emitting element 321 can be reliably connected by the bump 4a.

[0114] Thereafter, as shown in FIG. 9C, insulating resin 102 is filled between the semiconductor substrate 2 and the chip 3 and between the connection portions between the semiconductor substrate 2 and the chip 3, thereby insulating adjacent bumps 4a and completing the assembly of the light source device 110.

[0115] As a result, in the light source device 110, adjacent bumps 4a are insulated from each other by the insulating resin 102, so that short circuit failures between the bumps 4a can be prevented, and open circuit failures of the bumps 4a due to impact can also be prevented.

[0116] [3.Effects] The electronic device 1 has a semiconductor substrate 2, a chip 3, and connection portions (bumps 4). The chip 3 has a thermal expansion coefficient different from that of the semiconductor substrate 2. The bumps 4 include a porous metal layer 41 that connects connection pads 21, 31 provided on the opposing main surfaces of the semiconductor substrate 2 and the chip 3.

[0117] This allows the electronic device 1 to connect the connection pads 21, 31 of the semiconductor substrate 2 and the chip 3 together using a low-temperature, low-pressure process, compared to when connecting the connection pads 21, 31 of the semiconductor substrate 2 and the chip 3 together using bulk metal bumps. Therefore, the electronic device 1 can reduce damage caused by high temperatures and high pressures, thereby improving reliability.

[0118] Furthermore, the chip 3 has a thermal expansion coefficient that differs by 0.1 ppm / °C or more from that of the semiconductor substrate 2. As a result, even if the chip 3 generates heat and expands at a thermal expansion coefficient different from that of the semiconductor substrate 2, the porous metal layer 41 elastically deforms in the electronic device 1, and therefore, open circuit failures in the bumps 4 can be suppressed.

[0119] Furthermore, the chip 3 is a semiconductor laser, and the semiconductor substrate 2 has a drive circuit 22 that drives the semiconductor laser. As a result, even if the chip 3 expands at a different thermal expansion rate from the semiconductor substrate 2 due to heat generated by the light emission of the semiconductor laser, the porous metal layer 41 elastically deforms, so that the occurrence of open circuit failures in the bumps 4 can be suppressed.

[0120] The chip 3 is a semiconductor laser. The semiconductor substrate has a temperature sensor. This allows the drive circuit 22 that drives the semiconductor laser to control the drive of the light emitting unit 32 in accordance with the temperature near the light emitting unit 32 detected by the temperature sensor, thereby suppressing fluctuations in the light emission characteristics of the light emitting unit 32 caused by changes in temperature.

[0121] The semiconductor laser also has a plurality of light-emitting elements 321 that are two-dimensionally arranged and emit laser light. The plurality of light-emitting elements 321 have anode electrodes 142 and cathode electrodes 143 that are provided on the same plane. This allows the semiconductor laser to be easily connected to the drive circuit 22.

[0122] The semiconductor substrate 2 also has switches 154. The switches 154 are connected to the anode electrode 142 or the cathode electrode 143. As a result, when the distance measuring device 100 measures distance using the STL method, the drive circuit 22 can individually control each switch 154 to irradiate the subject S with pattern light having various types of dot patterns.

[0123] Furthermore, the switch 154 is connected to each of the plurality of light-emitting elements 321. The light emission of the light-emitting elements 321 is controlled for each group. This allows the distance measuring device 100 to change the light emission pattern for each group of the light-emitting elements 321, thereby enabling various types of patterned light to be irradiated onto the subject S.

[0124] Furthermore, the switch 154 is connected to each light-emitting element 321. The light-emitting elements 321 are individually controlled to emit light, so that the distance measuring device 100 can irradiate the subject S with pattern light of any desired light-emitting pattern.

[0125] Furthermore, the light emitting elements 321 are formed on a common substrate, which allows the semiconductor laser to share one anode electrode 142 or one cathode electrode 143 with a plurality of light emitting elements 321.

[0126] Furthermore, each anode electrode 142 or each cathode electrode 143 and each switch 154 are connected by a connection portion (bump 4). This allows light source device 110 to connect semiconductor substrate 2 and chip 3 using a low-temperature, low-pressure process, compared to when semiconductor substrate 2 and chip 3 are connected by bulk metal bumps. Therefore, light source device 110 can reduce damage caused by high temperature and high pressure, thereby improving reliability.

[0127] The light emitting element 321 has a VCSEL structure, which allows the light source device 110 to reduce power consumption and be mass-produced.

[0128] Furthermore, insulating resin 102 is filled between semiconductor substrate 2 and chip 3 and between connecting portions (bumps 4). As a result, adjacent bumps 4 in light source device 110 are insulated from each other by insulating resin 102, so short circuit failures between bumps 4 can be prevented, and open failures of bumps 4 due to impact can also be prevented.

[0129] The porous metal layer 41 contains metal particles with a particle diameter of 0.005 μm to 1.0 μm. Due to the size effect of the metal particles, the porous metal layer 41 can form a metal bond at a temperature lower than the melting point of the bulk metal. As a result, in the electronic device 1, the connection pads 21, 31 of the semiconductor substrate 2 and the chip 3 are connected to each other by the porous metal layer 41, which can form a metal bond at a relatively low temperature, thereby reducing damage caused by heat and improving reliability.

[0130] In addition, the bump 4 has metal films 42, 43 of the same composition as the porous metal layer 41 at least either between the porous metal layer 41 and the connection pad 21 on the semiconductor substrate 2 side, or between the porous metal layer 41 and the connection pad 31 on the chip 3 side.

[0131] As a result, even if the connection pads 21, 31 and the porous metal layer 41 have different components, the connection pads 21, 31 can be firmly connected by the metal films 42, 43 and the porous metal layer 41.

[0132] The metal films 42 and 43 are thin films formed to harden the surfaces of the patterned photoresist layers 51 and 52 used in the process of forming the bumps 4 and 4 a. This allows the bumps 4 and 4 a to be formed with a fine structure, thereby enabling the bumps 4 and 4 a to be arranged at a fine pitch.

[0133] The ratio of the thickness of the metal film 42 to the thickness of the bump 4 in a direction perpendicular to the main surface of the semiconductor substrate 2 is less than 10%, preferably less than 5%. The ratio of the thickness of the metal film 43 to the thickness of the bump 4a in a direction perpendicular to the main surface of the chip 3 is less than 10%, preferably less than 5%.

[0134] This makes it possible to prevent the through holes patterned in the photoresist layers 51 and 52 for forming the bumps 4 and 4 a from being narrowed by the formation of the metal films 42 and 43. As a result, the through holes patterned in the photoresist layers 51 and 52 can be appropriately filled with the paste 40 containing metal particles that will be the material for the bumps 4 and 4 a.

[0135] In addition, in the case of an electronic device in which a semiconductor substrate 2 and a chip 3 are connected by bumps 4 and bumps 4a, the ratio of the film thickness of the metal films 42, 43 to half the thickness of the stack of bumps 4, 4a in a direction perpendicular to the main surfaces of the semiconductor substrate 2 and chip 3 is less than 10%, preferably less than 5%.

[0136] This makes it possible to prevent the through holes patterned in the photoresist layers 51 and 52 for forming the bumps 4 and 4 a from being narrowed by the formation of the metal films 42 and 43. As a result, the through holes patterned in the photoresist layers 51 and 52 can be appropriately filled with the paste 40 containing metal particles that will be the material for the bumps 4 and 4 a.

[0137] The electronic device 1 also has a semiconductor substrate 2 and a bump 4. The bump 4 includes a metal film 42 and a porous metal layer 41 that are sequentially laminated on the surface of a connection pad 21 provided on the main surface of the semiconductor substrate 2. The ratio of the film thickness of the metal film 42 to the thickness of the bump 4 in a direction perpendicular to the main surface of the semiconductor substrate 2 is less than 10%.

[0138] This allows the bumps 4 on the semiconductor substrate 2 to be fine-pitched, and also enables flip-chip mounting of chips 3 with a thermal expansion coefficient different from that of the semiconductor substrate 2 through low-temperature, low-pressure processing compared to when bulk metal bumps are used.

[0139] The semiconductor substrate 2 also has a drive circuit 22 that drives the semiconductor laser, which is flip-chip mounted, for example. The drive circuit 22 controls each switch 154 that connects the anode electrode 142 of each of the plurality of light-emitting elements 321 included in the semiconductor laser to a current source, thereby independently controlling each light-emitting element. This allows the drive circuit 22 to cause the light source device 110 to irradiate the subject S with pattern light of various types of dot patterns when the distance measuring device 100 measures distance using the STL method.

[0140] The electronic device 1 also has a chip 3 and bumps 4a. The bumps 4a include a metal film 43 and a porous metal layer 41 that are sequentially laminated on the surfaces of connection pads 31 provided on the main surface of the chip 3. The ratio of the thickness of the metal film 43 to the thickness of the bumps 4a in a direction perpendicular to the main surface of the chip 3 is 10% or less.

[0141] This allows the chip 3 to have finer pitched bumps 4a, and also allows flip-chip mounting to a semiconductor substrate 2 with a different thermal expansion coefficient than the chip 3 through low-temperature, low-pressure processing compared to when bulk metal bumps are used.

[0142] The chip 3 is a semiconductor laser. The semiconductor laser has a plurality of light-emitting elements 321 that are arranged two-dimensionally and emit laser light. The plurality of light-emitting elements 321 have an anode electrode 142 and a cathode electrode 143 that are provided on the same plane. This allows the semiconductor laser to be easily connected to the drive circuit 22.

[0143] Furthermore, since the chip 3 can be bonded onto the drive circuit 22 via the bumps 4, the area of ​​the mounting substrate 101 can be reduced.

[0144] The effects described in this specification are merely examples and are not limiting, and other effects may also be present.

[0145] The present technology can also be configured as follows. (1) a semiconductor substrate; a chip having a coefficient of thermal expansion different from that of the semiconductor substrate; a connection portion including a porous metal layer connecting connection pads provided on the opposing main surfaces of the semiconductor substrate and the chip; An electronic device having: (2) The chip is The coefficient of thermal expansion differs from that of the semiconductor substrate by 0.1 ppm / °C or more The electronic device described in (1) above. (3) The chip is a semiconductor laser, The semiconductor substrate is A drive circuit for driving the semiconductor laser is provided. The electronic device according to (1) or (2). (4) The chip is a semiconductor laser, The semiconductor substrate is Has a temperature sensor The electronic device according to any one of (1) to (3). (5) The semiconductor laser is a plurality of light-emitting elements that are two-dimensionally arranged and that emit laser light; Each of the plurality of light-emitting elements The anode and cathode electrodes are provided on the same plane. The electronic device according to (3) or (4). (6) The semiconductor substrate is A switch is provided. The switch is connected to the anode electrode or the cathode electrode The electronic device according to (5) above. (7) The switch is A plurality of the light emitting elements are connected to each group, The light-emitting element is Light emission is controlled for each group. The electronic device according to (6) above. (8) The switch is Each of the light-emitting elements is connected to The light-emitting element is Individual lighting control The electronic device according to (6) above. (9) Each of the anode electrodes or each of the cathode electrodes and each of the switches are connected by the connection portion. The electronic device according to any one of (6) to (8). (10) The light-emitting element is formed on a common substrate The electronic device according to any one of (5) to (9). (11) The light-emitting element is Has a VCSEL (Vertical Cavity Surface Emitting Laser) structure The electronic device according to any one of (5) to (10) above. (12) An insulating resin is filled between the semiconductor substrate and the chip and between the connecting portions. The electronic device according to any one of (1) to (11) above. (13) The porous metal layer is The electronic device according to any one of (1) to (12) above, which contains metal particles having a particle diameter of 0.005 μm to 1.0 μm. (14) The connection portion is The electronic device described in any one of (1) to (13), wherein at least one of the following is provided: between the porous metal layer and the connection pad on the semiconductor substrate side; and between the porous metal layer and the connection pad on the chip side; and a metal film of the same composition as the porous metal layer is provided. (15) The metal film is The electronic device according to (14), wherein the ratio of the film thickness to the thickness in the direction perpendicular to the main surface in the connection portion is 10% or less. (16) The metal film is The electronic device according to (15), wherein the ratio of the film thickness to the thickness in the direction perpendicular to the main surface in the connection portion is less than 5%. (17) The metal film is The electronic device according to (14), wherein the ratio of the film thickness to half the thickness in the direction perpendicular to the main surface in the connection portion is 10% or less. (18) The metal film is The electronic device according to (17), wherein the ratio of the film thickness to half the thickness in the direction perpendicular to the main surface in the connection portion is less than 5%. (19) The electronic device according to any one of (1) to (18), wherein the ratio of the height of the porous metal layer and the height of the connection portion in a direction perpendicular to the main surface is greater than 90%. (20) a semiconductor substrate; a bump including a metal film and a porous metal layer sequentially laminated on the surface of a connection pad provided on the main surface of the semiconductor substrate; and The metal film is The ratio of the film thickness to the thickness of the bump in a direction perpendicular to the main surface is 10% or less. electronic equipment. (twenty one) The semiconductor substrate is a drive circuit for driving a flip-chip mounted semiconductor laser; The drive circuit Each of the plurality of light emitting elements provided in the semiconductor laser is controlled by controlling each switch connecting the light emitting element to a current source, thereby independently controlling each of the light emitting elements. The electronic device according to (20) above. (twenty two) Chips and bumps including a metal film and a porous metal layer sequentially laminated on the surfaces of connection pads provided on the main surface of the chip; and The metal film is The electronic device, wherein the ratio of the film thickness of the bump to the thickness in a direction perpendicular to the main surface is 10% or less. (twenty three) The chip is a semiconductor laser, The semiconductor laser is a plurality of light-emitting elements that are two-dimensionally arranged and that emit laser light; Each of the plurality of light-emitting elements The anode and cathode electrodes are provided on the same plane. The electronic device according to (22) above.

[0146] Although preferred embodiments of the present disclosure have been described in detail above with reference to the accompanying drawings, the technical scope of the present disclosure is not limited to such examples. It is clear that a person skilled in the art of the present disclosure can conceive of various modifications or alterations within the scope of the technical ideas described in the claims, and these modifications are naturally understood to fall within the technical scope of the present disclosure. The aspects and features described above with at least one previously described example or figure may be combined with other examples, and preferred features of such other examples may be substituted for or additionally introduced. For example, the structural and / or functional details described above may be similarly applied to electronic devices configured as described in (19) to (23).

Claims

1. a semiconductor substrate; a chip having a coefficient of thermal expansion different from that of the semiconductor substrate; a connection portion including a porous metal layer connecting connection pads provided on the opposing main surfaces of the semiconductor substrate and the chip; an insulating film covering the peripheral edge of the connection pad; and the insulating film has a recess opening in the connection pad that is not covered with the insulating film, the recess opening having a diameter larger than a diameter of the connection portion; electronic equipment.

2. The chip is The coefficient of thermal expansion differs from that of the semiconductor substrate by 0.1 ppm / °C or more. The electronic device according to claim 1 .

3. The porous metal layer is Contains metal particles with a particle size of 0.005 μm to 1.0 μm The electronic device according to claim 1 .

4. The connection portion is A metal film made of the same material as the porous metal layer is provided between the porous metal layer and the connection pad on the semiconductor substrate side, or between the porous metal layer and the connection pad on the chip side. The electronic device according to claim 1 .

5. The metal film is The ratio of the film thickness to the thickness in the direction perpendicular to the main surface at the connection portion is 10% or less.

5. The electronic device according to claim 4.

6. The metal film is The ratio of the film thickness to the thickness in the direction perpendicular to the main surface at the connection portion is less than 5%. The electronic device according to claim 5 .

7. The metal film is The ratio of the film thickness to half the thickness in the direction perpendicular to the main surface at the connection portion is 10% or less.

5. The electronic device according to claim 4.

8. The metal film is The ratio of the film thickness to half the thickness in the direction perpendicular to the main surface at the connection portion is less than 5%.

8. The electronic device according to claim 7.

9. The ratio of the thickness or longitudinal elongation of the porous metal layer to the thickness or longitudinal elongation of the connection portion is 90% or more. The electronic device according to claim 1 .

10. The semiconductor substrate is Has a temperature sensor The electronic device according to claim 1 .

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