Semiconductor device

Abstract

To provide a semiconductor device capable of improving the degree of freedom of an assembly of the semiconductor device by increasing the bondable area with respect to the entire periphery of the semiconductor device.SOLUTION: A semiconductor device includes a semiconductor substrate having an active region with a tetragonal shape in a top view, and a terminal region provided around the active region. The active region includes a gate electrode formed on an upper surface of the semiconductor substrate, and the terminal region includes a gate wire formed on an upper surface side of the semiconductor substrate and electrically connected to the gate electrode. The gate wire has a tetragonal shape in a top view and is provided surrounding the active region. The gate wire has a gate pad part of externally connecting the gate electrode by bonding. The gate pad part is provided entirely in at least one side on the gate wire.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to semiconductor devices. [Background technology]

[0002] Patent Document 1 discloses a semiconductor device having gate electrode wiring electrically connected to gate electrodes, and gate electrode pads which are electrically connected to the gate electrode wiring and are regions for connecting each gate electrode to an external device by bonding. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2022-178755 Summary of the Invention [Problem to be solved by the invention]

[0004] In the semiconductor device described in Patent Document 1, the area where the gate electrode pad is provided is limited to one location on the entire periphery of the semiconductor device. In other words, the area available for bonding on the entire periphery of the semiconductor device is limited, which imposes restrictions on the assembly of the semiconductor device.

[0005] The present disclosure has been made to solve the above-mentioned problems, and aims to provide a semiconductor device that can improve the freedom of assembly of the semiconductor device by increasing the area that can be bonded around the entire periphery of the semiconductor device. [Means for solving the problem]

[0006] The semiconductor device according to the present disclosure is a semiconductor device including a semiconductor substrate having an active region that is rectangular in top view and a termination region provided around the active region, and further including: a gate electrode formed on the top surface of the semiconductor substrate in the active region; and a gate wiring formed on the top surface of the semiconductor substrate in the termination region and electrically connected to the gate electrode, the gate wiring having a rectangular shape in top view and provided so as to surround the active region, the gate wiring having a gate pad portion that connects the gate electrode to an external device by bonding, and the gate pad portion being provided on at least one entire side of the gate wiring. [Effects of the Invention]

[0007] According to the semiconductor device according to the present disclosure, the area where bonding is possible is increased, and therefore the degree of freedom in assembling the semiconductor device can be improved. [Brief explanation of the drawings]

[0008] [Figure 1] 1 is a schematic top view of a semiconductor device according to a first embodiment. [Figure 2] 1 is a schematic top view of a semiconductor device according to a first embodiment. [Figure 3] 2 is a schematic cross-sectional view of the semiconductor device according to the first embodiment taken along line AA in FIG. 1. [Figure 4] 1 is a schematic top view of a semiconductor device according to a first embodiment. [Figure 5] FIG. 1 is a schematic top view of a semiconductor device according to a conventional technique. [Figure 6] FIG. 10 is a schematic top view of a semiconductor device according to a second embodiment. [Figure 7] FIG. 7 is a schematic cross-sectional view of the semiconductor device according to the second embodiment taken along line AA in FIG. 6. [Figure 8] FIG. 10 is a schematic top view of a semiconductor device according to a modification of the second embodiment. [Figure 9] 9 is a schematic cross-sectional view of the semiconductor device according to a modified example of the second embodiment, taken along line AA in FIG. 8. FIG. DETAILED DESCRIPTION OF THE INVENTION

[0009] <Introduction> In the following description, n-type and p-type indicate the conductivity types of semiconductors, and in this disclosure, the first conductivity type will be described as n-type and the second conductivity type as p-type, but the first conductivity type may be p-type and the second conductivity type may be n-type. - The n type indicates that the impurity concentration is lower than that of the n type. + The p type indicates that the impurity concentration is higher than that of the n type. - The impurity concentration is lower than that of p-type, and p + The type indicates that the impurity concentration is higher than that of the p-type.

[0010] Furthermore, one side in a direction parallel to the depth direction of the semiconductor device is referred to as "top" and the other side as "bottom." Of the two main surfaces of a substrate, layer, or other member, one surface is referred to as the top surface and the other surface is referred to as the bottom surface. The directions of "top" and "bottom" are not limited to the direction of gravity or the directions when the semiconductor device is mounted.

[0011] For ease of explanation, the width direction of the semiconductor device will be referred to as the x direction, the depth direction of the semiconductor device that intersects with the x direction as the y direction, and the thickness direction or depth direction of the semiconductor device, i.e., the normal direction to the xy plane, as the z direction.

[0012] Furthermore, the drawings are schematic, and the relative sizes and positions of images shown in different drawings are not necessarily accurately depicted and may be changed as appropriate. In the following description, similar components are denoted by the same reference numerals, and their names and functions are also the same. Therefore, detailed descriptions thereof may be omitted.

[0013] Embodiment 1 The first embodiment will be described below with reference to the drawings. FIG. 1 is a schematic top view showing the overall top surface configuration of a semiconductor device 100 according to the first embodiment. The dotted lines in FIG. 1 indicate gate wiring 3 covered with a protective film 5. FIG. 2 is a diagram showing the schematic top view of the first embodiment with the protective film 5 on an active region 20 omitted. As shown in FIG. 1, the semiconductor device 100 includes an active region 20 that is rectangular in top view and a termination region 30 provided around the active region 20. Note that the rectangular shape is not limited to a strict rectangular shape as long as the overall shape is approximately rectangular, and includes, for example, an approximately rectangular shape with rounded corners. A semiconductor switching element is configured in the active region 20. The semiconductor switching element may be an insulated gate bipolar transistor (hereinafter abbreviated as IGBT), or may be an RC-IGBT (Reverse Conducting Insulated Gate Bipolar Transistor) in which an IGBT region and a diode region are provided within a single semiconductor switching element. Termination region 30 is provided to maintain the breakdown voltage of semiconductor device 100.

[0014] As shown in FIG. 1 , gate wiring 3 is provided in the termination region 30 so as to surround the active region 20. In this embodiment, since the active region 20 has a rectangular shape in top view, the gate wiring 3 also has a rectangular shape in top view. Also, as shown in FIG. 2 , a gate electrode 8 is provided in the active region 20. The gate electrode 8 is formed on the upper surface of a semiconductor substrate 1 (described later) and is electrically connected to the gate wiring 3. Also, as shown in FIG. 2 , the gate electrode 8 may be a trench-type gate electrode 8 provided in a striped pattern. Note that the method of connecting the gate wiring 3 and the gate electrode 8 is similar to a conventional method, and detailed description thereof will be omitted. For example, as shown in FIG. 2 , when the gate electrodes 8 are provided in a striped pattern, both ends of each gate electrode 8 may be physically connected to the gate wiring 3. Alternatively, the gate wiring 3 may be used as a main gate wiring, and secondary gate wirings may be led from the main gate wiring 3 toward the active region 20, and the secondary gate wirings may be physically connected to the respective gate electrodes 8. This allows electrical connection between the gate wiring 3 and each gate electrode 8. 1, 3, and 4, the detailed structure of the semiconductor device 100 of this embodiment will be described below. Note that the detailed structure of the active region 20 of the semiconductor device 100 is a conventional structure, and therefore its description will be omitted. Also, the detailed structure of the lower surface side of the semiconductor substrate 1 in the termination region 30 of the semiconductor device 100 is a conventional structure, and therefore its description will be omitted.

[0015] 3 is a cross-sectional view of the semiconductor device 100 according to the first embodiment in a direction perpendicular to the extension direction of the gate wiring 3 in the termination region 30. FIG. 3 shows a cross section taken along the dashed dotted line A-A in FIG. 1. The cross-sectional configuration of the semiconductor device 100 will be described with reference to FIG. 3. As shown in FIG. 3, the semiconductor device 100 includes a semiconductor substrate 1, and in the termination region 30, a gate wiring 3 and a gate pad portion 4.

[0016] The semiconductor substrate 1 has the above-described active region 20 and termination region 30. The semiconductor substrate 1 also has an n-type drift layer. The semiconductor substrate 1 is made of various semiconductor materials such as silicon (Si), silicon carbide (SiC), or gallium nitride (GaN).

[0017] The gate wiring 3 is provided on the upper surface side of the semiconductor substrate 1 in the termination region 30. An insulating film 2 may be provided between the semiconductor substrate 1 and the gate wiring 3.

[0018] As shown in FIG. 3, a field plate 6 may be provided on the upper surface of the semiconductor substrate 1. The field plate 6 is provided at a distance so as not to interfere with the gate wiring 3. Alternatively, a VLD 7 may be provided on the upper surface of the semiconductor substrate 1 as shown in FIG. 2. The VLD 7 is a so-called VLD (Variation of Lateral Doping) in which the active region 20 is surrounded by a P-type well layer with a concentration gradient. Instead of the field plate 6 or VLD 7, any known breakdown voltage support structure may be appropriately selected and provided in the termination region 30.

[0019] 1, a protective film 5 is preferably provided on the surfaces of the active region 20 and the termination region 30. This makes it possible to protect the surfaces of the active region 20 and the termination region 30. In this embodiment, as shown in FIGS. 1 and 3, a portion of the protective film 5 on the gate line 3 in the termination region 30 is opened. Note that, as shown in FIGS. 1 and 3, the protective film 5 may be opened so that the protective film 5b remains in the region on the gate line 3 on the active region 20 side; in the following description, the protective film 5b will be referred to as the first protective film 5b.

[0020] The gate pad 4 is provided on the gate wiring 3. The gate pad 4 is provided to connect the gate electrode to an external device, and bonding is performed at the gate pad 4. In this embodiment, the gate pad 4 is the gate wiring 3 itself. As shown in FIGS. 1 and 2, it is preferable to open a portion of the protective film 5 provided on the surface of the termination region 30 to form an opening 5a, and to allow the gate wiring 3 exposed by the opening 5a to function as the gate pad 4. As shown in FIG. 1, the gate pad 4 is provided on all four sides of the gate wiring 3. By providing the gate pad 4 on all four sides of the gate wiring 3, wire bonding can be performed from anywhere in the 360-degree circumference of the semiconductor device 100, thereby improving the flexibility of assembly of the semiconductor device.

[0021] It is preferable that the gate wiring 3 exposed by the opening 5a is sealed with a sealing resin after bonding, so that the exposed gate wiring 3 can be protected.

[0022] While FIG. 1 shows an example in which the gate pad portion 4 is provided on all four sides of the gate wiring 3, it does not necessarily have to be on all four sides; it may be provided on at least one side. FIG. 4 shows an example in which the gate pad portion 4 is provided on one side of the gate wiring 3. The dotted line in FIG. 4 indicates the gate wiring 3 covered with the protective film 5. In the example of FIG. 4, the protective film 5 provided on the surface of the termination region 30 is opened on only one side of the gate wiring 3 to form an opening 5a, and only the side of the gate wiring 3 exposed by the opening 5a functions as the gate pad portion 4. In the example of FIG. 4, wire bonding can be performed anywhere on the gate pad portion 4 provided on one side of the gate wiring 3, thereby improving the flexibility of assembly of the semiconductor device.

[0023] Furthermore, when the gate pad portion 4 is provided only on some sides of the gate wiring 3, the gate wiring 3 on the side where the gate pad portion 4 is not provided does not function as a gate pad, so the width of the gate wiring 3 on the side where the gate pad portion 4 is not provided may be made smaller than the width of the gate wiring 3 on the side where the gate pad portion 4 is provided. This allows the semiconductor device 100 to be made smaller than when all the gate wirings 3 are formed with the same width.

[0024] Although it has been described above that the gate pad portion 4 is provided over the "entire" of at least one side of the gate wiring 3, this does not necessarily mean "entire" in the strict sense. It is sufficient that the gate pad portion 4 is formed over substantially the entire one side of the gate wiring 3 to the extent that bonding positions can be freely selected from the formed gate pad portion 4, and there may be some portions where the gate pad portion 4 is not formed.

[0025] For comparison with the semiconductor device 100 of this embodiment, a semiconductor device of the prior art is shown in FIG. 5 as a comparative example. Note that the dotted line in FIG. 5 indicates the gate wiring 3 covered with the protective film 5. As shown in FIG. 5, in the conventional semiconductor device, a wide portion of the gate wiring 3 extending toward the center of the active region 20 is the gate pad portion 4, which functions as a gate pad. This portion is an ineffective region directly below which no semiconductor switching element is present. As shown in FIG. 5, a recess exists in the active region 20 due to the ineffective region. Therefore, in order to ensure the operational performance of the semiconductor device, it is necessary to enlarge the active region 20 relative to the size of the semiconductor device by the size of the recess.

[0026] In contrast, in the semiconductor device 100 of this embodiment, the active region 20 is rectangular in top view, and the gate wiring 3 is formed so as to surround the rectangular active region 20, so there is no recess in the active region 20. Therefore, there is no need to make the active region 20 large relative to the size of the semiconductor device. In other words, the active region 20 can be made smaller relative to the size of the semiconductor device than in the past, while still maintaining the same operating performance as in the past semiconductor device.

[0027] Furthermore, because termination region 30 is provided with a breakdown voltage structure and the like for protecting active region 20, termination region 30 is generally formed to be relatively large relative to active region 20. Therefore, even in a configuration in which active region 20 is rectangular and gate wiring 3 is formed to surround rectangular active region 20, there is no need to secure a separate area for forming a gate pad. Therefore, the above-described configuration allows active region 20 to be small relative to the size of the semiconductor device, making it possible to miniaturize the semiconductor device.

[0028] Next, a method for manufacturing the semiconductor device 100 of this embodiment will be described. The method for manufacturing the semiconductor device 100 of this embodiment is basically the same as the method for manufacturing a conventional semiconductor device. Note that the gate wiring formation process and the gate pad portion formation process are also basically the same as the conventional manufacturing methods, so some of them will not be described.

[0029] The method for manufacturing the semiconductor device 100 of this embodiment includes a gate wiring forming step and a gate pad portion forming step.

[0030] First, the gate wiring formation process will be described. In this embodiment, the gate wiring 3 is formed on the upper surface of the semiconductor substrate 1. By forming the gate wiring 3 wider than conventionally, the gate wiring 3 can function as a gate pad. The width of the gate wiring 3 only needs to be large enough to allow bonding, and may be set appropriately depending on the thickness of the bonding wire, etc.

[0031] Next, the gate pad formation process will be described. As an example of the gate pad formation process, a method of forming an opening 5a in a protective film 5 provided on the surface of the termination region 30 and forming the gate pad 4 will be described. First, the protective film 5 is formed on the surface of the termination region 30. The protective film 5 is formed by, for example, a CVD method. Next, an opening 5a is formed in the protective film 5 that is formed on the gate wiring 3 by etching or the like. By forming the opening 5a so that it reaches the top surface of the gate wiring 3, the gate wiring 3 is exposed, and the exposed gate wiring 3 can function as the gate pad 4.

[0032] Note that the protective film 5 is opened over one entire side of the gate line 3, allowing at least one entire side of the gate line 3 to function as the gate pad section 4. It is also preferable to open the protective film 5 over all four sides of the gate line 3, allowing all four sides of the gate line 3 to function as the gate pad section 4.

[0033] As described above, according to the semiconductor device 100 of this embodiment, the gate pad portion 4 is provided on at least one entire side of the gate wiring 3, thereby increasing the area available for bonding around the entire periphery of the semiconductor device 100 and improving the degree of freedom in assembling the semiconductor device.

[0034] Embodiment 2 A semiconductor device 200 according to the second embodiment will be described with reference to FIGS. 6 and 7. FIG. 6 is a schematic top view of the semiconductor device 200 according to the second embodiment. FIG. 7 is a schematic cross-sectional view of the semiconductor device 200 according to the second embodiment. Note that FIG. 7 shows a cross section taken along the dashed dotted line A-A shown in FIG. 6. Note that the dotted line in FIG. 6 indicates the gate wiring 3 covered with the protective film 5 and the conductor.

[0035] In the semiconductor device 200 of the second embodiment, the gate pad portion 4 is a conductor electrically connected to the gate wiring 3. As shown in Figures 6 and 7, the conductor is provided on the gate wiring 3. This differs from the first embodiment in that a conductor separately provided on the gate wiring 3 functions as the gate pad portion 4, rather than the gate wiring 3 itself.

[0036] 6, the conductor is preferably provided on all four sides of the gate line 3, but it is sufficient that the conductor is provided on at least one entire side of the gate line 3. The conductor may be made of solder, for example.

[0037] 6 and 7, it is preferable to form an opening 5a by opening a portion of the protective film 5 provided on the surface of the termination region 30, and to provide a conductor on the gate wiring 3 exposed by the opening 5a, allowing the conductor to function as the gate pad portion 4. Also, as shown in FIG. 7, it is preferable to form the conductor thicker than the surface of the protective film 5. This makes it possible to perform bonding on the conductor without using the opening 5a. Therefore, the width of the opening 5a only needs to be wide enough to connect the gate wiring 3 and the conductor, so the width of the opening 5a can be made smaller than in the first embodiment.

[0038] The semiconductor device 200 of the second embodiment is configured in this manner. The conductor separately provided on the gate wiring 3 is made to function as the gate pad portion 4, and the conductor is provided over at least one entire side of the gate wiring 3, thereby increasing the area available for bonding over the entire periphery of the semiconductor device 200, thereby improving the degree of freedom in assembling the semiconductor device, as in the first embodiment.

[0039] Furthermore, by making the gate pad portion 4 a conductor, the size of the termination region 30 can be reduced compared to the first embodiment in which the gate pad portion 4 is the gate wiring 3 itself. When the gate wiring 3 itself is used as the gate pad portion 4, the gate pad region depends on the size of the gate wiring 3. In contrast, in the configuration in which the gate pad portion 4 is a conductor, the conductor can be formed by utilizing the surface of the termination region 30 on which a breakdown voltage retention structure such as a field plate 6 is provided. Therefore, since the gate pad region does not depend on the size of the gate wiring 3, the gate wiring 3 can be formed with a conventional width, and the size of the termination region 30 can be reduced compared to the first embodiment. In other words, the semiconductor device 200 of the second embodiment allows for further miniaturization of the semiconductor device compared to the first embodiment.

[0040] Next, a method for manufacturing the semiconductor device 200 of the second embodiment will be described. The method for manufacturing the semiconductor device 200 of the second embodiment differs from the method of the first embodiment in a part of the gate wiring formation process and a part of the gate pad portion formation process. The following describes in detail the differences from the first embodiment in the gate wiring formation process and the gate pad portion formation process.

[0041] In the second embodiment, the gate pad portion 4 is a conductor. An example of a method for forming a conductor on the gate line 3 will be described below.

[0042] First, the gate wiring formation process will be described. As in the first embodiment, the gate wiring 3 is formed on the upper surface of the semiconductor substrate 1. In the first embodiment, the gate wiring 3 is formed wider than conventionally so that it functions as a gate pad, but in this embodiment, the gate wiring 3 itself does not function as a gate pad, so the width of the gate wiring 3 may be formed to be the conventional width.

[0043] Next, the gate pad formation process will be described. As an example of the gate pad formation process, a method of forming an opening 5a in a protective film 5 provided on the surface of the termination region 30 and forming a gate pad 4 will be described. First, a protective film 5 is formed on the surface of the termination region 30. The protective film 5 is formed, for example, by a CVD method. Next, an opening 5a is formed in the protective film 5 formed on the gate wiring 3 using etching or the like. By forming the opening 5a so that it reaches the top surface of the gate wiring 3, the gate wiring 3 is exposed, and a conductor is formed on the exposed gate wiring 3. The conductor is electrically connected to the gate wiring 3, so that it can function as the gate pad 4. The width of the conductor may be large enough to allow bonding, and may be set appropriately depending on the thickness of the bonding wire, etc.

[0044] An opening is made in the protective film 5 over one entire side of the gate line 3, and a conductor is formed over at least one entire side of the gate line 3. It is also preferable to make an opening in the protective film 5 over all four sides of the gate line 3, and to form a conductor over all four sides of the gate line 3.

[0045] Next, a modification of the second embodiment will be described with reference to FIGS. 8 and 9. FIG. 8 is a schematic top view of a semiconductor device according to the modification. FIG. 9 is a schematic cross-sectional view of the semiconductor device according to the modification. FIG. 9 is a cross-sectional view showing the cross section indicated by the dashed dotted line AA in FIG. 8. The dotted line in FIG. 8 indicates the gate wiring 3 covered with the protective film 5 and the conductor.

[0046] As shown in FIGS. 8 and 9, in a modification of the second embodiment, a protective film 5 is provided on the surface of the termination region 30. Utilizing the surface area of ​​the termination region 30, a conductor may be formed on the protective film 5 so as to extend in a direction away from the active region 20, as shown in FIG. 8. This increases the area available for bonding in the width direction of the gate wiring 3, further improving the degree of freedom in assembly. Furthermore, because bonding can be performed at a position away from the active region 20, it is less likely to interfere with the active region 20 when mounting the semiconductor device, thereby improving safety.

[0047] 9 , of the protective films 5 provided on the gate line 3, the first protective film 5b provided on the active region 20 side may be formed to be thicker than the other protective films 5, and the conductor may be formed extending outward from the first protective film 5b on the protective film 5 in a direction away from the active region 20. By forming the first protective film 5b to be thicker than the other protective films 5, it is possible to prevent the conductor from flowing into the active region 20 when the conductor is formed on the protective film 5 extending in a direction away from the active region 20. Therefore, the conductor can be easily formed only in the termination region 30.

[0048] The configurations shown in the above embodiments are merely examples of the contents of the present disclosure and may be combined with other known technologies. Furthermore, it is also possible to combine the embodiments with each other and the modified examples with each other. Furthermore, it is also possible to omit or modify part of the configurations without departing from the scope of the present disclosure. [Explanation of symbols]

[0049] 1 semiconductor substrate, 3 gate wiring, 4 gate pad portion, 5 protective film, 5a opening, 5b first protective film, 8 gate electrode, 20 active region, 30 termination region, 100 200 semiconductor device

Claims

1. A semiconductor device including a semiconductor substrate having an active area that is rectangular in top view and a termination area provided around the active area, a gate electrode formed on an upper surface of the semiconductor substrate in the active region; a gate wiring formed on the upper surface side of the semiconductor substrate in the termination region and electrically connected to the gate electrode; the gate wiring has a rectangular shape in a top view and is provided so as to surround the active region; the gate wiring has a gate pad portion for connecting the gate electrode to an external device by bonding; The gate pad portion is provided on at least one entire side of the gate wiring.

2. 2. The semiconductor device according to claim 1, wherein the gate pad portion is the gate wiring itself.

3. a protective film is further provided on the surface of the termination region; the protective film has an opening formed by opening a part of the protective film, 3. The semiconductor device according to claim 2, wherein the gate wiring exposed by the opening is the gate pad portion.

4. 2. The semiconductor device according to claim 1, wherein the gate pad portion is a conductor provided on the gate wiring and electrically connected to the gate wiring.

5. a protective film is further provided on the surface of the termination region; the protective film has an opening formed by opening a part of the protective film, The semiconductor device according to claim 4 , wherein the conductor is provided on the gate wiring exposed by the opening.

6. The semiconductor device according to claim 5 , wherein the conductor is formed so as to extend on the protective film in a direction away from the active region.

7. the protective film includes a first protective film formed on a region on the gate wiring that is on the active region side; the first protective film is formed to be thicker than the other protective films, The semiconductor device according to claim 6 , wherein the conductor is formed outside the first protective film and extends on the protective film in a direction away from the active region.

8. 5. The semiconductor device according to claim 1, wherein the gate pad portion is provided on all four sides of the gate wiring.

9. 5. The semiconductor device according to claim 1, wherein a breakdown voltage holding structure is provided in the termination region.

10. 5. The semiconductor device according to claim 1, wherein the semiconductor substrate is made of SiC.

11. A semiconductor switching element is formed in the active region, 5. The semiconductor device according to claim 1, wherein the semiconductor switching element is an RC-IGBT.

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