Logic semiconductor device

Abstract

To provide a semiconductor device capable of shortening the distance between a semiconductor chip and a trench capacitor.SOLUTION: In a logic semiconductor device 1, a silicon substrate portion 12, a transistor layer 14, a wiring layer 16, and a capacitor portion 50 in which a through via 53 and a capacitor 60 are formed are formed in this order.SELECTED DRAWING: Figure 5

Description

[Technical Field]

[0001] The present invention relates to a logic semiconductor device. [Background technology]

[0002] Deep trench capacitors are known as capacitors that achieve high capacitance while minimizing the area they occupy on a substrate surface. Patent Document 1 discloses a method for fabricating deep trench capacitors used in DRAM (Dynamic Random Access Memory) cells. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2004-103777 Summary of the Invention [Problem to be solved by the invention]

[0004] Conventionally, when a deep trench capacitor is fabricated in a semiconductor device, the deep trench capacitor is fabricated on a silicon interposer. The semiconductor chip and the silicon interposer are bonded via bumps. Therefore, conventional semiconductor packages have a problem in that the distance between the transistor formed on the semiconductor chip and the deep trench capacitor is long.

[0005] SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a semiconductor device that can shorten the distance between a semiconductor chip and a trench capacitor. [Means for solving the problem]

[0006] The logic semiconductor device of the present invention includes a silicon substrate portion, a transistor layer, a wiring layer, and a capacitor portion in which a through via and a capacitor are formed, formed in this order. [Effects of the Invention]

[0007] According to the present invention, it is possible to provide a semiconductor device that can shorten the distance between the semiconductor chip and the trench capacitor. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a cross-sectional view of the logic semiconductor device of this embodiment. [Figure 2] FIG. 2 is a diagram showing an outline of a semiconductor package in which the logic semiconductor device of this embodiment is used. [Figure 3] FIG. 3 is a diagram showing how the chip wafer and the capacitor wafer are bonded together. [Figure 4A] FIG. 4A is a diagram showing a capacitor wafer bonding surface of a capacitor wafer. [Figure 4B] FIG. 4B is a diagram showing the chip wafer bonding surface of the chip wafer. [Figure 5] FIG. 5 is a diagram showing the state before the silicon chip portion and the capacitor portion are bonded together. [Figure 6] FIG. 6 is a diagram showing the bonding surface of the capacitor part. [Figure 7] FIG. 7 is a diagram showing the bonding surface of the tip portion. [Figure 8] FIG. 8 is a cross-sectional view of a trench capacitor. [Figure 9] FIG. 9 is a diagram showing an outline of a conventional semiconductor package. DETAILED DESCRIPTION OF THE INVENTION

[0009] (Logic Semiconductor Devices) An embodiment of the invention will be described with reference to the drawings. First, a logic semiconductor device 1 according to an embodiment of the present invention will be described with reference to FIG. 1. FIG. 1 is a diagram showing a cross section of the logic semiconductor device 1. Hereinafter, the X direction, Y direction, and Z direction may be indicated in the drawings. The X direction, Y direction, and Z direction are directions that are perpendicular to one another. The Z direction is the direction in which a silicon chip section 10 and a capacitor section 50, which will be described later, are stacked. FIG. 1 shows a cross section of the logic semiconductor device 1 taken along a plane parallel to the X direction and the Z direction.

[0010] In the logic semiconductor device 1 of this embodiment, a silicon substrate section 12, a transistor layer 14, a wiring layer 16, and a capacitor section 50 are formed in this order. Each will be described below in order.

[0011] (silicon chip and capacitor) The logic semiconductor device 1 includes a silicon chip section 10 and a capacitor section 50. The silicon chip section 10 and the capacitor section 50 are integrated by being directly bonded together. Direct bonding means bonding without using any material other than the silicon chip section 10 and the capacitor section 50, such as an adhesive, a solder bump, or a liquid curable resin such as underfill. An example of direct bonding is hybrid bonding.

[0012] (Chip bonding surface and capacitor bonding surface) The surface of the silicon chip portion 10 that is bonded to the capacitor portion 50 is called the chip portion bonding surface 11. The surface of the capacitor portion 50 that is bonded to the silicon chip portion 10 is called the capacitor portion bonding surface 51. In the logic semiconductor device 1 of this embodiment, the chip portion bonding surface 11 and the capacitor portion bonding surface 51 are directly bonded by hybrid bonding to form the logic semiconductor device 1. Note that the direct bonding between the chip portion bonding surface 11 and the capacitor portion bonding surface 51 is not limited to hybrid bonding.

[0013] (Silicon chip part) The silicon chip portion 10 includes a silicon substrate portion 12, a transistor layer 14, and a wiring layer 16. The silicon substrate portion 12, the transistor layer 14, and the wiring layer 16 are stacked in this order in the Z direction. The silicon chip portion 10 can function as a logic semiconductor.

[0014] (silicon substrate and transistor layer) The silicon substrate portion 12 is a substrate for forming transistors on at least one surface thereof. The transistor layer 14 is a layer including transistors formed on the surface of the silicon substrate portion 12. The number of transistors included in the transistor layer 14 is not limited.

[0015] (wiring layer) The wiring layer 16 is a layer for connecting transistors and the like included in the transistor layer 14 to electrodes and the like formed in the capacitor section 50. The wiring layer 16 includes a chip section insulating section 18 and a wiring section. The wiring section is not shown. The wiring section includes wiring for electrically connecting transistors and the like included in the transistor layer 14 to electrodes and the like formed in the capacitor section 50. The chip section insulating section 18 is an insulating portion formed between wires in the wiring section. Furthermore, if the surface of the wiring layer 16 that contacts the capacitor section 50 is defined as the wiring layer bonding surface, the wiring layer bonding surface is the same as the chip section bonding surface 11.

[0016] (Capacitor section) Next, a description will be given of the capacitor section 50. The capacitor section 50 includes a through via 53, a trench capacitor 60, and a capacitor section insulating section 52. In the capacitor section 50, the surface opposite to the capacitor section bonding surface 51 is called a capacitor section back surface 58.

[0017] (Through Via) The through via 53 is a conductive through hole that penetrates from the capacitor unit bonding surface 51 to the capacitor unit rear surface 58. The through via 53 is also called a TSV (Through Silicon Via).

[0018] (trench capacitor) The trench capacitor 60 may be a so-called deep trench capacitor. In FIG. 1, the length of the capacitor section 50 in the Z direction is shown as length 160. Length 160 indicates the thickness of the capacitor section 50 in the Z direction. The length of the trench capacitor 60 in the Z direction is shown as length 162. Length 162 indicates the depth of the trench capacitor 60. Length 160 is, for example, 100 μm. Meanwhile, length 162 is, for example, 20 μm or more and 40 μm or less. Note that the above-mentioned lengths 160 and 162 are examples. The lengths of length 160 and length 162 are not particularly limited.

[0019] The capacitor portion insulating portion 52 is an insulating portion that fills the gaps between the through vias 53 and between the through vias 53 and the trench capacitor 60. The material of the capacitor portion insulating portion 52 can be silicon.

[0020] (Semiconductor package) Before describing the logic semiconductor device 1 in detail, an example of how the logic semiconductor device 1 is used will be described. Figure 2 is a diagram showing an overview of a semiconductor package 100. The logic semiconductor device 1 can constitute a part of the semiconductor package 100.

[0021] 2, the semiconductor package 100 includes a logic semiconductor device 1 and a package substrate 110. Package wiring 112 is formed on the package substrate 110. Package insulating portions 114 are formed between the package wiring 112, etc. Furthermore, ball-shaped package solder portions 116 (solder bumps) are formed on the surface of the semiconductor package 100 opposite the surface on which the logic semiconductor device 1 is disposed.

[0022] The logic semiconductor device 1 is connected to one surface of the package substrate 110 via device solder parts 59 (solder bumps).

[0023] (Semiconductor package) A conventional semiconductor package 200 will now be described with reference to FIG. 9. FIG. 9 is a diagram showing an outline of the conventional semiconductor package 200. Note that in the following description, the matters described with reference to FIG. 2 will not be described again. In the conventional semiconductor package 200, a portion having the same function as the logic semiconductor device 1 shown in FIG. 2 is composed of two components: a silicon chip 210 and an interposer 220. A through via 222 and a trench capacitor 224 are formed in the interposer 220. The silicon chip 210 and the interposer 220 are connected via ball-shaped silicon chip solder portions 212 (solder bumps). The interposer 220 is also connected to the package substrate 110 via ball-shaped interposer solder portions 226 (solder bumps).

[0024] 2 and 9, the logic semiconductor device 1 of this embodiment makes it possible to combine the conventional silicon chip 210 and interposer 220 into a single component. This allows the logic semiconductor device 1 of this embodiment to shorten the distance between the semiconductor chip and the trench capacitor. Furthermore, the logic semiconductor device 1 of this embodiment allows the thickness of the semiconductor package 100 to be reduced and the configuration of the semiconductor package 100 to be simplified.

[0025] The logic semiconductor device 1 will be described in detail. FIG. 3 is a diagram showing how a chip wafer 310 and a capacitor wafer 350 are bonded together. The diagram indicated by arrow 301 in FIG. 3 shows an overview of a chip wafer bonding surface 311 of the chip wafer 310. The chip wafer 310 is a silicon wafer on which a plurality of silicon chip portions 10 are formed. The chip wafer 310 is bonded to a capacitor wafer 350, which will be described later. The surface of the chip wafer 310 that is bonded to the capacitor wafer 350 is called the chip wafer bonding surface 311. The surface of the chip wafer 310 opposite to the chip wafer bonding surface 311 is called the chip wafer back surface 312.

[0026] The diagram indicated by arrow 302 in Fig. 3 shows the state before chip wafer 310 and capacitor wafer 350 are bonded. Capacitor wafer 350 is a silicon wafer on which a plurality of capacitor sections 50 are formed. The surface of capacitor wafer 350 that is bonded to chip wafer 310 is called capacitor wafer bonding surface 351.

[0027] When bonding the chip wafer 310 and the capacitor wafer 350, the chip wafer bonding surface 311 of the chip wafer 310 is opposed to the capacitor wafer bonding surface 351 of the capacitor wafer 350. In the example shown in Fig. 3 , the chip wafer 310 is turned over as shown by arrow 361, so that the chip wafer bonding surface 311 of the chip wafer 310 is opposed to the capacitor wafer bonding surface 351 of the capacitor wafer 350.

[0028] The silicon chip units 10 and the capacitor units 50 are formed at corresponding positions on each wafer so that the individual silicon chip units 10 and capacitor units 50 are bonded without misalignment when the chip wafer 310 and the capacitor wafer 350 are superimposed. This will be described with reference to FIGS. 4A and 4B. FIG. 4A is a diagram showing a capacitor wafer bonding surface 351 of the capacitor wafer 350. FIG. 4B is a diagram showing the chip wafer bonding surface 311 of the chip wafer 310 as seen through in the direction of arrow 363 in FIG. 3. As shown in FIGS. 4A and 4B, the capacitor units 50 and the silicon chip units 10 are arranged on each wafer so that they contact each other without misalignment when the capacitor wafer 350 and the chip wafer 310 are superimposed. Note that the symbols shown in FIGS. 4A and 4B but not explained will be explained later with reference to FIGS. 6 and 7.

[0029] Returning to Figure 3, after the chip wafer 310 is inverted as shown by arrow 361, at least one of the chip wafer 310 and the capacitor wafer 350 is moved relative to one another as shown by arrow 363, so that the chip wafer bonding surface 311 and the capacitor wafer bonding surface 351 come into contact with each other.

[0030] In this manner, the silicon chip portion 10 formed on the chip wafer 310 and the capacitor portion 50 formed on the capacitor wafer 350 are brought into contact with each other and bonded together.

[0031] The bonding between the silicon chip unit 10 and the capacitor unit 50 will be specifically described below. In the following explanation, the bonding between the silicon chip unit 10 and the capacitor unit 50 will be described by focusing on one of the plurality of silicon chip units 10 formed on the chip wafer 310 and one of the plurality of capacitor units 50 formed on the capacitor wafer 350.

[0032] (Before joining) Fig. 5 is a diagram showing the state before the silicon chip unit 10 and the capacitor unit 50 are bonded. The directions indicated by arrows 151 and 152 in Fig. 5 are both along the Z direction. The directions indicated by arrows 151 and 152 are opposite to each other.

[0033] The silicon chip portion 10 and the capacitor portion 50 are bonded by moving the silicon chip portion 10 relative to the capacitor portion 50 in the direction of arrow 151, and moving the capacitor portion 50 relative to the silicon chip portion 10 in the direction of arrow 151. In this way, the logic semiconductor device 1 is formed.

[0034] The capacitor unit 50 and the silicon chip unit 10 are bonded by bonding the capacitor unit bonding surface 51 and the chip unit bonding surface 11. The capacitor unit bonding surface 51 and the chip unit bonding surface 11 will be described with reference to FIGS. 6 and 7. FIG. 6 illustrates the capacitor unit bonding surface 51. FIG. 7 illustrates the chip unit bonding surface 11. Both FIGS. 6 and 7 show the object viewed in the direction of arrow 153 shown in FIG. 5. The direction of arrow 153 is the direction viewed from the (+) side to the (-) side in the Z direction. Note that the chip unit bonding surface 11 shown in FIG. 7 shows the chip unit bonding surface 11 viewed in the direction of arrow 153 beyond the silicon substrate unit 12, transistor layer 14, and wiring layer 16. That is, as shown by arrow 154 in FIG. 5, the chip unit bonding surface 11 appears as viewed from inside the wiring layer 16, in other words, from the back surface 11R of the chip unit bonding surface 11.

[0035] (Capacitor joint surface) First, the capacitor portion bonding surface 51 will be described with reference to Fig. 6. The capacitor portion insulating portion 52 is exposed on the capacitor portion bonding surface 51. Furthermore, the through electrode 54, the capacitor electrode 62, and the connection wiring 77 are arranged on the capacitor portion bonding surface 51. In other words, on the capacitor portion bonding surface 51, the through electrode 54, the capacitor electrode 62, and the connection wiring 77 are arranged within the capacitor portion insulating portion 52. The capacitor portion bonding surface 51 is covered with the capacitor portion insulating portion 52, the through electrode 54, the capacitor electrode 62, and the connection wiring 77.

[0036] (Through electrode) The through electrode 54 is an electrode electrically connected to the through via 53 formed in the capacitor section 50. The through electrode 54 is a portion where the end of the through via 53 is exposed on the bonding surface 51 of the capacitor section.

[0037] A plurality of through electrodes 54 are arranged on the capacitor portion bonding surface 51. The number of through electrodes 54 corresponds to the number of through vias 53 formed in the capacitor portion 50. Usually, one through electrode 54 is formed for each through via 53.

[0038] The arrangement of the through electrodes 54 corresponds to the arrangement of the through vias 53 formed in the capacitor section 50. In the example shown in Fig. 6, the through electrodes 54 are arranged in a matrix, but there are no particular limitations on the arrangement of the through electrodes.

[0039] The planar shape of the through electrode 54 is circular. This is because the through via 53 has a cylindrical shape. The cross-sectional shape of the through via is not limited to a circle, and may be a donut shape, a square shape, or the like.

[0040] The material of the through electrode 54 can be the same as the material forming the through via 53. An example of the material of the through electrode 54 is copper. However, the material of the through electrode 54 is not limited to copper. Furthermore, the material of the through electrode 54 may be different from the material forming the through via 53.

[0041] (capacitor electrode) The capacitor electrode 62 is the electrode portion of the trench capacitor 60 formed in the capacitor section 50 .

[0042] (trench capacitor) Here, an outline of the configuration of trench capacitor 60 will be described. FIG. 8 is a diagram showing a cross section of trench capacitor 60. The position of line segment 155-156 in FIG. 8 corresponds to the position of line segment 155-156 in FIG. 6. Trench capacitor 60 includes a capacitor electrode 62, a dielectric layer 66, a first electrode layer 68, and a second electrode layer 69. Capacitor electrode 62 includes a first capacitor electrode 64 and a second capacitor electrode 65.

[0043] The dielectric layer 66 is sandwiched between a first electrode layer 68 and a second electrode layer 69. The material of the dielectric layer 66 is not particularly limited. Capacitance can be increased by using a material with a high dielectric constant, and silicon oxide, silicon nitride, tantalum oxide, titanium oxide, hafnium oxide, hafnium silicate, HfSiON, HfAlON, etc. can be used. A capacitance is formed in the dielectric layer 66. The first capacitor electrode 64 is the capacitor electrode 62 connected to the first electrode layer 68. The second capacitor electrode 65 is the capacitor electrode 62 connected to the second electrode layer 69.

[0044] The first electrode layer 68, the dielectric layer 66, and the second electrode layer 69 extend in the Z direction to form a trench capacitor.

[0045] The first capacitor electrode 64 and the second capacitor electrode 65 are exposed at the capacitor portion bonding surface 51. A capacitor portion insulating portion 52 is disposed between the first capacitor electrode 64 and the second capacitor electrode 65 at the capacitor portion bonding surface 51. For example, by using the first capacitor electrode 64 as a (+) electrode and the second capacitor electrode 65 as a (-) electrode, a capacitance can be formed in the dielectric layer 66.

[0046] 8 is an example, and the configuration of the trench capacitor 60 can be changed as appropriate.

[0047] (capacitor electrode) Returning to Figure 6, the capacitor electrode 62 will be described below. The first capacitor electrode 64 and the second capacitor electrode 65 shown in Figure 6 are the first capacitor electrode 64 and the second capacitor electrode 65 of the trench capacitor 60 described with reference to Figure 8 that are exposed at the capacitor portion bonding surface 51. The first capacitor electrode 64 and the second capacitor electrode 65 are separated from each other at the capacitor portion bonding surface 51 by the capacitor portion insulating portion 52.

[0048] 6, the first capacitor electrode 64 and the second capacitor electrode 65 have a rectangular shape. However, the shapes of the first capacitor electrode 64 and the second capacitor electrode 65 are not limited to a rectangular shape. Furthermore, in the example shown in FIG. 6, the size of the first capacitor electrode 64 is smaller than the size of the second capacitor electrode 65. However, the sizes of the first capacitor electrode 64 and the second capacitor electrode 65 are not limited to the example shown in FIG. 6.

[0049] The material of the capacitor electrodes 62 is, for example, copper, but the material of the capacitor electrodes 62 is not limited to copper.

[0050] (Connection wiring) The connection wiring 77 is a wiring that electrically connects the through electrode 54 and the capacitor electrode 62. The connection wiring 77 includes a first connection wiring 78 and a second connection wiring 79.

[0051] The through electrode 54 adjacent to the first capacitor electrode 64 is called a first through electrode 55. The first connection wiring 78 is a connection wiring 77 that connects the first through electrode 55 and the first capacitor electrode 64 together.

[0052] The through electrode 54 adjacent to the second capacitor electrode 65 is called the second through electrode 56. The second connection wiring 79 is the connection wiring 77 that connects the second through electrode 56 and the second capacitor electrode 65 together.

[0053] (power and ground wires) 6, for example, the first through electrode 55 can correspond to a power line, and the second through electrode 56 can correspond to a ground line, thereby connecting the trench capacitor 60 between the power line and the ground line.

[0054] Here, transistor operation involves the supply and release of charge to the transistor. This generates switching noise on the power line. Reducing switching noise is important for achieving stable, high-speed transistor operation. To achieve this, it is effective to install a large-capacity capacitor capable of retaining charge as close to the transistor as possible. In the logic semiconductor device 1 of this embodiment, power lines from the transistor layer 14 can be connected to the trench capacitor 60 without using bumps or other devices. This eliminates the connection distance of several hundred micrometers to several millimeters that would have been required with conventional bumps.

[0055] The above-described method of connecting the trench capacitor 60 to the line is an example, and the method of connecting the trench capacitor 60 to the line is not limited to this.

[0056] The material of the connection wiring 77 is, for example, copper, but the material of the connection wiring 77 is not limited to copper.

[0057] (Tip joint surface) Next, the chip part bonding surface 11 will be described with reference to Figure 7. The chip part insulating part 18 is exposed on the chip part bonding surface 11. Furthermore, wiring electrodes 26 and pads are arranged on the chip part bonding surface 11. In this embodiment, the pads are dummy pads 20. In other words, on the chip part bonding surface 11, the wiring electrodes 26 and dummy pads 20 are arranged within the chip part insulating part 18. The chip part bonding surface 11 is covered with the chip part insulating part 18, the wiring electrodes 26, and the dummy pads 20.

[0058] (wiring electrode) The wiring electrode 26 is an electrode electrically connected to the wiring portion formed in the wiring layer 16. The wiring electrode 26 is the end portion of the wiring portion exposed on the chip portion bonding surface 11.

[0059] The wiring electrode 26 is bonded to the through electrode 54 of the capacitor portion bonding surface 51. That is, the wiring electrode 26 is electrically connected to the through electrode 54 of the capacitor portion bonding surface 51.

[0060] 6 and 7, the planar shapes of the wiring electrode 26 and the through electrode 54 are both circular. The position of the wiring electrode 26 on the chip portion bonding surface 11 is the same as the position of the through electrode 54 on the capacitor portion bonding surface 51.

[0061] By configuring the wiring electrodes 26 in the planar shape and arrangement as described above, the wiring electrodes 26 and the through electrodes 54 can be bonded to each other without leaving any residue.

[0062] The material of the wiring electrodes 26 can be the same as the material forming the wiring portion. An example of the material of the wiring electrodes 26 is copper. However, the material of the wiring electrodes 26 is not limited to copper. Furthermore, the material of the wiring electrodes 26 may be different from the material forming the wiring portion.

[0063] (dummy pad) The dummy pad 20 is a pad formed of a conductor on the chip portion bonding surface 11. The dummy pad 20 may be a floating pad (floating island pad) that is not connected to any other conductor. The dummy pad 20 is bonded to the capacitor electrode 62. The planar shape of the dummy pad 20 is the same as the planar shape of the capacitor electrode 62. The position of the dummy pad 20 on the chip portion bonding surface 11 is the same as the position of the capacitor electrode 62 on the capacitor portion bonding surface 51.

[0064] The dummy pads 20 include a first dummy pad 21 and a second dummy pad 22. The first dummy pad 21 is a dummy pad 20 that is bonded to the first capacitor electrode 64. The second dummy pad 22 is a dummy pad 20 that is bonded to the second capacitor electrode 65.

[0065] The material of the dummy pad 20 can be the same as the material of the capacitor electrode 62. For example, if the material of the capacitor electrode 62 is copper, it is preferable that the material of the dummy pad 20 is also copper. Note that the pad formed on the chip portion bonding surface 11 and bonded to the capacitor electrode 62 is not limited to a floating pad, but may also be a pad connected to a wiring. For example, this pad may be connected to the wiring electrode 26 on the chip portion bonding surface 11 by a connecting wiring (not shown). In this case, the connecting wiring 77 may not be formed on the capacitor portion bonding surface 51.

[0066] (Bonding of the capacitor bonding surface and the chip bonding surface) Here, we will explain the bonding between the capacitor portion bonding surface 51 and the chip portion bonding surface 11. The capacitor portion bonding surface 51 and the chip portion bonding surface 11 are directly bonded. As mentioned above, being directly bonded means that they are bonded in contact with each other without any other material between them, such as an adhesive, a solder bump, or a liquid hardening resin such as underfill.

[0067] (hybrid bonding) An example of direct bonding is hybrid bonding. A case where the capacitor portion bonding surface 51 and the chip portion bonding surface 11 are hybrid bonded will be described. In order to perform hybrid bonding, it is preferable that the two surfaces to be bonded are made of the same material.

[0068] (Capacitor insulation and chip insulation) The capacitor portion insulating portion 52 on the capacitor portion bonding surface 51 is an insulating portion made of silicon. Therefore, the material of the chip portion insulating portion 18 on the chip portion bonding surface 11 is made of silicon, the same as that of the capacitor portion insulating portion 52. This results in a hybrid bond between the capacitor portion insulating portion 52 and the chip portion insulating portion 18.

[0069] Hybrid bonding between capacitor portions is formed, for example, as follows. First, the hydroxyl groups at the ends of the silicon that make up capacitor portion insulating portion 52 and tip portion insulating portion 18 bond together through hydrogen bonding. Then, the interface between capacitor portion bonding surface 51 and tip portion bonding surface 11 is heated. This heating causes dehydration from the hydrogen bonds, and capacitor portion insulating portion 52 and tip portion insulating portion 18 are bonded together through siloxane bonding.

[0070] The materials for the capacitor portion insulating portion 52 and the tip portion insulating portion 18 are not limited to the above-mentioned materials. The materials for the capacitor portion insulating portion 52 and the tip portion insulating portion 18 can also be, for example, silicon oxide or silicon carbonitride. These materials can also be used as insulating materials for hybrid bonding.

[0071] (Through electrodes and wiring electrodes) Next, the bonding between the through electrode 54 and the wiring electrode 26 will be described. For example, assume that the material of the through electrode 54 and the material of the wiring electrode 26 are both copper. In this case, by bringing the through electrode 54 and the wiring electrode 26 into contact with each other, the copper diffuses into each other, creating a diffusion bond. The through electrode 54 and the wiring electrode 26 can be bonded by this diffusion bond.

[0072] In this way, when bonding the capacitor portion bonding surface 51 and the chip portion bonding surface 11, hybrid bonding can be achieved by using the same material for the contacting parts of the capacitor portion bonding surface 51 and the chip portion bonding surface 11.

[0073] The above description of the bonding is merely an example. The materials of each part can be changed as appropriate. For example, the materials of the through electrodes 54 and the wiring electrodes 26 are not limited to copper.

[0074] (dummy pad) The role of the dummy pad 20 in hybrid bonding will be described below. The dummy pad 20 can increase the bonding strength between the capacitor portion bonding surface 51 and the chip portion bonding surface 11.

[0075] As described above, in hybrid bonding between the capacitor portion bonding surface 51 and the chip portion bonding surface 11, it is preferable that the materials of the contacting portions of the capacitor portion bonding surface 51 and the chip portion bonding surface 11 are the same. As shown in FIG. 6 , a capacitor electrode 62 is formed on the capacitor portion bonding surface 51. The capacitor electrode 62 is typically made of a metal such as copper. If no dummy pad 20 is formed on the chip portion bonding surface 11, the chip portion bonding surface 11 that is in contact with the capacitor electrode 62 becomes the chip portion insulating portion 18. The chip portion insulating portion 18 is made of an insulating material. Therefore, no hybrid bonding is formed between the capacitor electrode 62 and the chip portion insulating portion 18. This is because one is made of a metal material and the other is made of an insulating material.

[0076] If there is a portion where bonding is not performed between the capacitor portion bonding surface 51 and the chip portion bonding surface 11, the bonding strength between the silicon chip portion 10 and the capacitor portion 50 may be weakened.

[0077] In the silicon chip unit 10 of this embodiment, a dummy pad 20 is formed on the chip unit bonding surface 11. The dummy pad 20 is disposed in a position that overlaps with the capacitor electrode 62 when the capacitor unit bonding surface 51 and the chip unit bonding surface 11 are bonded. The dummy pad 20 is also formed from the same material as the capacitor electrode 62. Therefore, when the capacitor unit bonding surface 51 and the chip unit bonding surface 11 are bonded, a bond can be formed between the dummy pad 20 and the capacitor electrode 62. This can increase the bonding strength between the capacitor unit bonding surface 51 and the chip unit bonding surface 11.

[0078] (Manufacturing method) A method for manufacturing the logic semiconductor device 1 of this embodiment will be described. The logic semiconductor device 1 is manufactured by bonding a silicon chip portion 10 and a capacitor portion 50. Specifically, as shown in FIG. 3, by bringing a chip wafer 310 and a capacitor wafer 350 into contact with each other, the individual silicon chip portions 10 formed on the chip wafer 310 are bonded to the individual capacitor portions 50 formed on the capacitor wafer 350. The silicon chip portions 10 and the capacitor portions 50 can also be manufactured using conventional techniques. Here, the bonding of the silicon chip portions 10 and the capacitor portions 50 will be described.

[0079] The silicon chip unit 10 and the capacitor unit 50 can be bonded by hybrid bonding. First, a chip wafer 310 on which the silicon chip unit 10 is formed and a capacitor wafer 350 on which the capacitor unit 50 is formed are prepared. Next, the chip wafer bonding surface 311 of the chip wafer 310 and the capacitor wafer bonding surface 351 of the capacitor wafer 350 are planarized by CMP (chemical mechanical planarization) or the like. Thereafter, the silicon chip unit 10 of the chip wafer 310 and the capacitor unit 50 of the capacitor wafer 350 are aligned. Then, the chip wafer bonding surface 311 and the capacitor wafer bonding surface 351 are brought close to each other, more specifically, the chip unit bonding surface 11 and the capacitor unit bonding surface 51 are brought close to each other, thereby bonding the chip unit bonding surface 11 and the capacitor unit bonding surface 51. At this time, heat or pressure may be applied to the interface between the chip unit bonding surface 11 and the capacitor unit bonding surface 51. Alternatively, an annealing treatment may be performed after bonding. After bonding, the semiconductor device is diced or the like to obtain individual logic semiconductor devices 1.

[0080] The method for manufacturing the logic semiconductor device 1 is not limited to the above-described method. In the above description, the silicon chip portion 10 and the capacitor portion 50 are bonded together while being formed on the chip wafer 310 or the capacitor wafer 350, respectively, and then singulated to obtain individual logic semiconductor devices 1. Alternatively, the silicon chip portion 10 and the capacitor portion 50 may be cut out from the chip wafer 310 or the capacitor wafer 350, respectively, and the singulated silicon chip portion 10 and the capacitor portion 50 may be bonded together to obtain the logic semiconductor device 1. Alternatively, one may be in a wafer state and the other in a chip state, and these may be bonded together by hybrid bonding or the like. For example, the silicon chip portion 10 singulated by dicing may be bonded to the capacitor wafer 350 by hybrid bonding or the like.

[0081] Although the present invention has been described above as an embodiment, it is not limited to the above-described embodiment, and various changes, modifications, and combinations are possible.

[0082] (1) A logic semiconductor device has a silicon substrate section, a transistor layer, a wiring layer, and a capacitor section in which a through via and a capacitor are formed, formed in this order. (2) The logic semiconductor device, wherein the wiring layer and the capacitor section are in direct contact with each other. (3) The logic semiconductor device as described above, wherein the capacitor is a trench capacitor. (4) When the surface of the capacitor portion that contacts the wiring layer is a capacitor portion bonding surface, A capacitor electrode, which is an electrode of the capacitor, is exposed on the joint surface of the capacitor portion, When a surface of the wiring layer that contacts the capacitor portion is defined as a wiring layer bonding surface, In the logic semiconductor device, a pad made of metal is formed on the wiring layer junction surface at a portion in contact with the capacitor electrode. (5) A method for manufacturing a logic semiconductor device includes the steps of: preparing a chip wafer on which a plurality of silicon chip portions each having a silicon substrate portion, a transistor layer, and a wiring layer in that order are formed; A step of producing a capacitor wafer having a plurality of capacitor portions each having a through via and a capacitor formed therein; bringing the chip wafer and the capacitor wafer into contact with each other and bonding the wiring layer and the capacitor portion; The method includes cutting out logic semiconductor devices each having a silicon chip portion and a capacitor portion bonded together from the chip wafer and the capacitor wafer. [Explanation of symbols]

[0083] 1. Logic semiconductor device 10 Silicon chip part 11 Tip joint surface 11R Back side of the tip joint surface 12 Silicon substrate part 14 Transistor Layer 16 wiring layer 18 Tip insulation 20 dummy pad 21 First dummy pad 22 Second dummy pad 26 Wiring electrode 50 Capacitor section 51 Capacitor joint surface (wiring layer joint surface) 52 Capacitor insulation part 53 Through Via 54 Through electrode 55 First through electrode 56 Second through electrode 58 Back side of capacitor 59 Device soldering section 60 Trench Capacitor (Capacitor) 62 Capacitor electrode 64 first capacitor electrode 65 Second capacitor electrode 66 Dielectric Layer 68 First electrode layer 69 Second electrode layer 77 Connection wiring 78 First connecting wire 79 Second connecting wire 100 Semiconductor Packages 110 Package substrate 112 Package Wiring 114 Package insulation 116 Package solder area 200 Semiconductor Packages 210 Silicon Chip 212 Silicon chip soldering part 220 Interposer 222 Through Via 224 Trench Capacitor 226 Interposer soldering part 310 chip wafer 311 Chip wafer bonding surface 312 Chip wafer backside 350 Capacitor Wafer 351 Capacitor wafer bonding surface

Claims

1. A logic semiconductor device, comprising: a silicon substrate portion; a transistor layer; a wiring layer; and a capacitor portion in which a through via and a capacitor are formed, formed in this order.

2. 2. The logic semiconductor device according to claim 1, wherein said wiring layer and said capacitor section are in direct contact with each other.

3. 3. The logic semiconductor device according to claim 1, wherein said capacitor is a trench type capacitor.

4. When a surface of the capacitor portion that is in contact with the wiring layer is defined as a capacitor portion bonding surface, A capacitor electrode, which is an electrode of the capacitor, is exposed on the joint surface of the capacitor portion, When a surface of the wiring layer that contacts the capacitor portion is defined as a wiring layer bonding surface, 3. The logic semiconductor device according to claim 1, wherein a pad made of metal is formed on a portion of said wiring layer junction surface in contact with said capacitor electrode.

5. a step of producing a chip wafer on which a plurality of silicon chip portions each having a silicon substrate portion, a transistor layer, and a wiring layer in that order are formed; A step of producing a capacitor wafer having a plurality of capacitor portions each having a through via and a capacitor formed therein; bringing the chip wafer and the capacitor wafer into contact with each other to bond the wiring layer and the capacitor portion; A method for manufacturing a logic semiconductor device, comprising the step of cutting out logic semiconductor devices each having a silicon chip portion and a capacitor portion bonded together from the chip wafer and the capacitor wafer.

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