Compensation for power semiconductor variations

Abstract

To provide a method for correcting variations in power semiconductors driven by an active gate driver (AGD).SOLUTION: A method includes generating a plurality of drive patterns for an AGD 404 and controlling a power semiconductor 406 under a plurality of operating conditions using the AGD, and a computer (PC) 402 acquires, for each operating condition, one or more electrical signals of the power semiconductor, detects variations in one or more key parameters of the power semiconductor from the one or more electrical signals, generates a drive pattern corresponding to the variations in the one or more key parameters on the basis of a predetermined relationship between the variations in the one or more key parameters and the one or more drive parameters of the drive pattern, and stores the generated drive pattern for each operating condition and the corresponding variations in the one or more key parameters in a memory.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The present invention relates to the field of active gate drives (AGDs) and power semiconductors. In particular, the present invention relates to a method and system for generating a drive pattern from an active gate drive that can compensate for variations in the power semiconductors driven by the active gate driver. [Background technology]

[0002] Power semiconductors are electronic devices that are widely used in many industrial applications, such as renewable energy systems and electric vehicles. To put power semiconductors into practical use, gate drivers are used to provide the voltage and current levels required to switch the power semiconductors on and off quickly, efficiently, and safely.

[0003] However, power semiconductors are susceptible to variations in key parameters that affect their switching performance, resulting in reliability issues in application systems. These power semiconductor variations include, but are not limited to, threshold voltage, transconductance, parasitic capacitance, gate resistance, etc.

[0004] The causes of these variations include changes in physical properties due to manufacturing and processing, as well as changes in operating voltage and temperature. Correcting such variations and ensuring the reliability of power semiconductors is important for the commercialization and industrial application of power semiconductor systems.

[0005] Therefore, there is a need to improve the switching performance of power semiconductors when such variations occur.

[0006] By way of example only, please refer to the accompanying drawings in which: [Brief explanation of the drawings]

[0007] [Figure 1] Figure 1 shows the basic structure of an open-loop active gate driver. [Figure 2] Figure 2 shows a closed-loop active gate driver using high-speed sensing. [Figure 3] Figure 3 shows a closed-loop active gate driver using an oscilloscope. [Figure 4] FIG. 4 shows a proposed method for developing drive patterns for power semiconductors using active gate drivers. [Figure 5] FIG. 5 shows a proposed method for selecting a drive pattern for a power semiconductor using an active gate driver. [Figure 6] FIG. 6 illustrates a closed-loop active gate driver according to one embodiment. [Figure 7] FIG. 7 shows an example of a driving pattern. [Figure 8] FIG. 8 shows an example of a driving pattern. [Figure 9] FIG. 9 shows an example of a driving pattern. [Figure 10] FIG. 10 shows a circuit diagram of a MOSFET in series with a diode. [Figure 11] Figure 11 shows the main switching waveforms of the MOSFET. DETAILED DESCRIPTION OF THE INVENTION

[0008] According to one embodiment, a method for generating multiple drive patterns for an active gate driver (AGD) is provided, the method comprising controlling a power semiconductor under multiple operating conditions using the AGD. For each operating condition, one or more electrical signals of the power semiconductor are obtained, variations in one or more key parameters of the power semiconductor are detected from the one or more electrical signals, and a drive pattern corresponding to the variations in the one or more key parameters is generated based on a predetermined relationship between the variations in the one or more key parameters and the one or more drive parameters of the drive pattern. The generated drive pattern for each operating condition and the corresponding variations in the one or more key parameters are stored in a memory.

[0009] The carrier mobility of a power semiconductor can change under different operating conditions. This changes the way the power semiconductor behaves. However, measuring the changes in a power semiconductor due to differences in operating conditions is often not feasible during use. These changes often result in variations in the key parameters (e.g., electrical characteristics) of the power semiconductor. However, directly measuring the key parameters of a power semiconductor during use is often difficult to achieve. Instead, electrical signals (e.g., voltage, current, etc.) from the power semiconductor can be used to detect variations in the key parameters of the power semiconductor. Thus, the electrical signals serve as a variation indicator for the variations in the key parameters.

[0010] By storing drive patterns for variations in key parameters, those drive patterns can later be used by a device equipped with an AGD to select the most appropriate drive pattern when a variation in the key parameter is detected, or to fine-tune the selected drive pattern as needed. This results in a significant reduction in computational resources compared to having to derive a new drive pattern from scratch. In this way, storing drive patterns allows a device to improve its operation by generating the most appropriate drive pattern without requiring the use of a complex controller / computer. This allows drive patterns to be generated for different key parameters of a power semiconductor that may result from variations in the power semiconductor due to different operating conditions. Thus, an appropriate drive pattern can be used for the corresponding variation in the key parameter.

[0011] The drive pattern comprises a plurality of steps, which may be defined by drive parameters including, for example, gate voltage, gate current, and timing (i.e., time duration) of each step in the drive pattern.

[0012] The different operating conditions may comprise, for example, a change in operating voltage and / or a change in operating temperature.

[0013] The predetermined relationship may be derived, for example, from data contained in the data sheet of the power semiconductor.

[0014] The one or more key parameters of the power semiconductor may be one or more electrical characteristics of the power semiconductor.

[0015] The AGD may be driven with a reference drive pattern.

[0016] The method may be computer-implemented.

[0017] The method may further comprise determining, for each operating condition, a number of drive parameters of the generated drive pattern that differ from a corresponding plurality of drive parameters of a reference drive pattern, and determining whether the number of drive parameters that differ from the corresponding plurality of drive parameters of the reference drive pattern is greater than a threshold number, wherein a drive pattern of the generated plurality of drive patterns is stored if the number of drive parameters of the drive pattern that differ from the corresponding plurality of drive parameters of the reference drive pattern is greater than a threshold number.

[0018] The threshold number may be, for example, 1, 2, 3, or 4.

[0019] One of the one or more key parameters may include a turn-on delay time, and wherein generating the drive pattern may comprise adapting one or more step timings of a reference drive pattern to generate the drive pattern.

[0020] The one or more electrical signals may comprise a gate voltage waveform and a drain current waveform, where the turn-on delay time is the time between when the AGD starts to output voltage and when the drain current starts to flow.

[0021] A predetermined relationship between variations in one or more turn-on delays and one or more drive parameters of the drive pattern may indicate that the timing of a step of the drive pattern increases as the turn-on delay increases and decreases as the first turn-on delay decreases. The amount by which the timing increases / decreases may be derived, for example, from a theoretical analysis of the particular model of the power semiconductor used. Data sheets for the power semiconductors often contain information that can be used to derive such increases / decreases. The timing of a step may be the first timing of a first step.

[0022] The threshold voltage variation may also be derived from the turn-on delay time (eg, using theoretical analysis, datasheet relationships, and / or machine learning).

[0023] The plurality of operating conditions may comprise at least one of a plurality of operating voltages and a plurality of operating temperatures.

[0024] Also provided herein is a method for generating a plurality of drive patterns for an active gate driver (AGD), the method comprising: controlling a plurality of power semiconductors of the same model using the AGD; obtaining, for each power semiconductor, one or more electrical signals of the power semiconductor; detecting variations in one or more key parameters of the power semiconductor from the one or more electrical signals; and generating a drive pattern corresponding to the variations in the one or more key parameters based on a predetermined relationship between the variations in the one or more key parameters and the one or more drive parameters of the drive pattern. The method further comprises storing the generated plurality of drive patterns for each power semiconductor and the corresponding variations in the one or more key parameters in a memory.

[0025] Different power semiconductors of the same model often have somewhat different physical properties due to, for example, manufacturing tolerances. These differences can result in variations in key parameters of power semiconductors of the same model.

[0026] The method may be computer-implemented.

[0027] The method may further comprise determining, for each power semiconductor, a number of drive parameters of the generated drive pattern that differ from a corresponding plurality of drive parameters of a reference drive pattern, and determining whether the number of drive parameters that differ from the corresponding plurality of drive parameters of the reference drive pattern is greater than a threshold number, wherein a drive pattern of the generated plurality of drive patterns is stored if the number of drive parameters of the drive pattern that differ from the corresponding plurality of drive parameters of the reference drive pattern is greater than a threshold number.

[0028] One of the one or more key parameters may include a turn-on delay time, and wherein generating the drive pattern may comprise adapting one or more step timings of a reference drive pattern to generate the drive pattern.

[0029] The one or more electrical signals may comprise a gate voltage waveform and a drain current waveform, where the turn-on delay time is the time between when the AGD starts to output voltage and when the drain current starts to flow.

[0030] Also provided herein is a method for controlling an active gate driver (AGD), the method comprising: controlling a power semiconductor with the AGD using a first drive pattern from a plurality of predetermined drive patterns, wherein each predetermined drive pattern corresponds to a variation in one or more key parameters of the power semiconductor; obtaining one or more electrical signals of the power semiconductor; detecting the variation in the one or more key parameters of the power semiconductor based on the one or more electrical signals; selecting a second drive pattern from the plurality of predetermined drive patterns that corresponds to the variation in the one or more key parameters; and controlling the power semiconductor with the AGD using the second drive pattern.

[0031] This allows a corresponding drive pattern to be selected based on detected variations in key parameters (e.g., turn-on delay time), thus reducing the sensing requirements during use and the required computational resources, thereby reducing the amount and complexity of components needed to obtain a suitable drive pattern.

[0032] The method may be computer-implemented.

[0033] The method may further comprise determining a number of drive parameters of the first drive pattern to be adapted based on variations in one or more key parameters, wherein selecting the second drive pattern from the plurality of predetermined drive patterns is based on the number of drive parameters being greater than a threshold number, and wherein the method further comprises adapting the first drive pattern based on variations in one or more key parameters to generate the second drive pattern based on the number of drive parameters being less than or equal to the threshold number.

[0034] Adapting the first drive pattern may be based on a known, predetermined relationship between the variation in one or more key parameters and one or more drive parameters of the drive pattern.

[0035] One of the one or more key parameters may include a turn-on delay time.

[0036] The one or more electrical signals may comprise a gate voltage waveform and a drain current waveform, where the turn-on delay time is the time between when the AGD starts to output voltage and when the drain current starts to flow.

[0037] The method may further comprise obtaining a plurality of drive patterns according to any of the above methods used to generate the drive patterns.

[0038] Also provided herein is a computer program comprising computer program code which, when executed on a processing device, causes the processing device to perform all the steps of any of the above methods.

[0039] Also provided herein is a system for generating a plurality of drive patterns for an active gate driver (AGD), comprising: an AGD, a power semiconductor, a memory, and a controller, wherein the controller is configured to: control the power semiconductor under a plurality of operating conditions using the AGD; obtain, for each operating condition, one or more electrical signals of the power semiconductor; detect variations in one or more key parameters of the power semiconductor from the one or more electrical signals; generate a drive pattern corresponding to the variations in the one or more key parameters based on a predetermined relationship between the variations in the one or more key parameters and the one or more drive parameters of the drive pattern; and store the generated plurality of drive patterns for each operating condition and the corresponding variations in the one or more key parameters in the memory.

[0040] Also provided herein is a system for generating a plurality of drive patterns for an active gate driver (AGD), comprising: an AGD; a plurality of power semiconductors; a memory; and a controller, wherein the controller is configured to: control a plurality of power semiconductors of the same model using the AGD; for each power semiconductor, obtain one or more electrical signals of the power semiconductor; detect variations in one or more key parameters of the power semiconductor from the one or more electrical signals; and generate a drive pattern corresponding to the variations in the one or more key parameters based on a predetermined relationship between the variations in the one or more key parameters and the one or more drive parameters of the drive pattern; and store the generated plurality of drive patterns for each operating condition and the corresponding variations in the one or more key parameters in the memory.

[0041] Also provided herein is a system for controlling an active gate driver (AGD), comprising: an AGD; a power semiconductor; a memory storing a plurality of predetermined drive patterns, wherein each predetermined drive pattern corresponds to a variation in one or more key parameters of the power semiconductor; and a controller, wherein the controller is configured to: control the power semiconductor with the AGD using a first drive pattern from the plurality of predetermined drive patterns; acquire a plurality of electrical signals of the power semiconductor; detect a variation in the one or more key parameters of the power semiconductor based on the plurality of electrical signals; select a second drive pattern from the plurality of predetermined drive patterns that corresponds to the variation in the one or more key parameters; and control the power semiconductor with the AGD using the second drive pattern.

[0042] Provided herein is an active gate driver (AGD) for compensating for variations in a power semiconductor (e.g., a MOSFET, an IGBT, etc.), the power semiconductor being driven by the AGD via its gate terminal. The power semiconductor may be a transistor.

[0043] Also provided herein is an algorithm for generating drive patterns for multiple power semiconductors. A set of predetermined correction rules is developed and used to generate the drive patterns.

[0044] The algorithm may further comprise generating a drive pattern that improves switching performance and provides a trade-off between overshoot voltage / current and switching losses in the power semiconductors.

[0045] The configuration of the AGD and the generation of the drive pattern can be performed during factory testing before shipping to the customer.

[0046] The predetermined correction rules in the algorithm can be extracted manually or using machine learning methods.

[0047] A look-up table (LUT) of the active gate driver can store the driving patterns, and the LUT may remain the same for the same model of power semiconductor from development to in-service operation.

[0048] Also provided herein is a computer-implemented method for configuring an AGD with a drive pattern capable of correcting variations in any model of power semiconductor, the computer-implemented method comprising: receiving input data by the AGD from the power semiconductor during its switching transient; transferring the input data from the AGD to a computer; applying a set of predetermined correction rules to the input data to generate a drive pattern for the power semiconductor; storing the drive pattern in the AGD; and optionally driving the power semiconductor using the AGD with the drive pattern.

[0049] Also provided herein is a controller-implemented system for compensating for any model variations of power semiconductors in real operation, the method comprising receiving input data from the power semiconductors during a switching transient to an AGD, transferring the data from the AGD to a controller, selecting a drive pattern previously stored in the AGD, and adjusting the selected drive pattern as needed. The selected or further adjusted drive pattern drives the power semiconductors.

[0050] The selection from the LUT may further depend on the operating conditions of the power semiconductor, including the current passing through it and the voltage across it.

[0051] The AGD may include an analog-to-digital converter, a look-up table, and / or isolation between the input and output.

[0052] The AGD may be an integrated IC or may be a dedicated circuit using discrete components.

[0053] The AGD may further be capable of outputting multi-stage gate drive patterns with variable magnitudes.

[0054] The variations in power semiconductors may comprise variations in key parameters that affect the switching performance of the power semiconductors, such as threshold voltage, transconductance, parasitic capacitance between the gate and source, parasitic capacitance between the gate and drain, parasitic capacitance between the drain and source, and / or gate resistance.

[0055] Input data from power semiconductors can be used as an indicator for detecting variations other than the entire switching waveform during switching transients.

[0056] The controller may be a microcontroller, a digital signal processing (DSP) controller, a field programmable gate array (FPGA), or any other type.

[0057] Provided herein is an AGD with an algorithm that compensates for variations while ensuring proper switching performance of power semiconductors. By compensating for variations, the AGD can be applied to a wider range of devices in a wider range of operating scenarios while still ensuring proper switching performance.

[0058] Compared to conventional gate drivers, AGDs use shaped waveforms to drive power semiconductors. AGDs are used for various types of power semiconductors because they improve the trade-off between voltage / current overshoot and switching losses compared to other techniques such as gate resistor tuning or snubber insertion. Thus, AGDs provide improved system efficiency and electromagnetic compatibility performance.

[0059] 1 shows the basic structure of an open-loop AGD, where an AGD 104 sits between a controller 102 and a driven power semiconductor, in this case a metal-oxide-semiconductor field-effect transistor (MOSFET) 106. There is no feedback from the driven MOSFET 106.

[0060] In open-loop AGD, the drive pattern is fixed and determined a priori; therefore, the AGD 104 cannot account for variations in the MOSFET 106. For example, the threshold voltage depends on the epitaxial layer thickness, channel length, and concentration of interface traps in the MOSFET 106. For a particular MOSFET type, the above physical variations between different MOSFETs of the same type can result in a variation of 0.7 V in the threshold voltage. There are also variations in the internal gate resistance and parasitic capacitance for different MOSFETs of the same type. In this case, open-loop AGD may be appropriate in one scenario but may not be appropriate in another scenario when such variations occur.

[0061] Furthermore, key parameters of the MOSFET 106 are temperature dependent and therefore susceptible to changes in operating temperature. Thus, if the operating conditions (e.g., temperature) differ from those assumed during the generation of the drive pattern being used, the switching performance of the MOSFET 106 may change. Thus, a drive pattern developed for a particular set of operating conditions may no longer be appropriate when used to switch a power semiconductor (e.g., the MOSFET 106) operating under different operating conditions.

[0062] Moving on from open-loop AGD, closed-loop AGD can be used to account for variations in the power semiconductors being driven and different operating conditions. There are various ways to provide a closed-loop feedback signal.

[0063] Figure 2 shows a closed-loop AGD using high-speed sensing 202 for the MOSFET 106. This is based on the time-dependent change in drain current (di / dt) and the time-dependent change in drain-source voltage (dv / dt). However, as the transients become faster, the requirements for implementing such sensing (i.e., sensing circuitry, analog-to-digital converter (ADC), etc.) in the AGD also need to become faster. Since the switching frequency of power semiconductors is typically kHz or higher, such high sensing requirements are difficult to achieve in practical operation.

[0064] Alternatively, an oscilloscope can be used to measure the variations in the electrical signals from within the MOSFET 106 .

[0065] 3 shows a closed-loop AGD using an oscilloscope 302 to measure the electrical signal from the MOSFET 106. A computer (PC) can then perform power analysis of the electrical signal and adapt the driving pattern of the AGD 104 in real time. However, oscilloscopes and PCs are generally large instruments and therefore impractical to use.

[0066] The methods for dealing with variations in power semiconductors described above with reference to Figures 2 and 3 are not feasible or applicable in actual operation because they require the use of additional equipment or highly demanding sensing circuits. Furthermore, these methods require a lot of hardware modification when adapting from one model of power semiconductor to another.

[0067] 4 and 5 show an embodiment method for switching power semiconductors with AGD using a closed loop and pre-developed correction rules.

[0068] 4 shows a method for generating a driving pattern 408 for a power semiconductor 406. Based on theoretical modeling or machine learning-based methods, a variation compensation rule is developed in a PC. According to this rule, a driving signal is generated under the variation of the power semiconductor.

[0069] If theoretical analysis is selected, a mathematical model is constructed for the power semiconductor 406, and the relationship between the variability index and the variability is derived.

[0070] If the machine learning method is selected, the computer (PC) 402 controls the AGD 404 to switch the power semiconductor 406 using reference drive patterns for multiple operating conditions. For each operating condition, a drive pattern with improved switching performance can be generated.

[0071] This results in multiple drive patterns, each with a corresponding variation, which can be stored for later use, or the correction rules adjust the drive patterns with the corresponding variations.

[0072] The drive patterns may be stored in a memory (e.g., a look-up table). The method may be performed during computer-implemented development. Algorithms may also be developed that include correction rules that specify which drive pattern should be used depending on power semiconductor variations, or how to further adjust the selected drive pattern if necessary.

[0073] 5 illustrates a method for using the generated drive patterns 408. The microcontroller 502 controls the AGD 504 to switch the power semiconductor 506 based on one of the drive patterns 408. One or more electrical characteristics of the power semiconductor 506 are then obtained during use. The microcontroller 502 can then select a different drive pattern from the set of predetermined drive patterns 408 based on detected variations in key parameters of the power semiconductor. Alternatively, the selected drive pattern can be further adjusted, if necessary.

[0074] Both the proposed AGD and the method described above are suitable for multiple power semiconductors. Figure 4 shows the developed method as implemented on a computer. Figure 5 shows the controller-implemented system in real operation (i.e., in use). Both the developed method and the in-use operation show steps in how to adapt the AGD and algorithms from one model of power semiconductor to another.

[0075] During the development stage, a computer is used to develop the drive patterns and provide flexibility, so that operation during use does not require the use of a computer or any manual intervention, which can be beneficial in commercialized user end cases, as for example a microcontroller can be used to select the drive patterns.

[0076] The approach shown in Figures 4 and 5 requires minimal on-chip and off-chip hardware, making it easy to adapt to conventional designs. Complex switching details of power semiconductors are not required, providing flexibility in the design of the ADC.

[0077] When developing driving patterns for different models of power semiconductors, no hardware changes are required because the LUT can be updated with the generated driving patterns. Therefore, the above method can be adapted to different models / types of power semiconductors by redeveloping the algorithms and driving patterns. This means that the practical design can remain the same for different models / types of power semiconductors.

[0078] The communication between the active gate driver and the computer or controller can be a serial peripheral interface (SPI) or an inter-integrated circuit (I2C), etc., as long as it meets the data transfer requirements.

[0079] 6 shows a closed-loop AGD according to one embodiment. The controller 102 controls the AGD 104 to switch the MOSFET 106. The variation indicators (i.e., electrical signals) of the MOSFET 106 are then measured via line 602 and fed back to the controller 102. The variation of the MOSFET 106 can then be detected from the measured variation indicators, and the controller can then select a new drive pattern for the MOSFET 106.

[0080] Compared to the open-loop AGD of FIG. 1, this closed-loop circuit can compensate for variations in the MOSFET 106 while ensuring good switching performance, something that is not possible with conventional open-loop AGDs. Similarly, compared to other feedback / closed-loop AGDs such as those shown in FIGS. 2 and 3, this closed-loop AGD is more easily adaptable from one model of power semiconductor to another with minimal effort. Furthermore, in actual operation, this closed-loop AGD does not require additional equipment or high-speed sensing circuitry, nor does it require continuous feedback, manual intervention, or complex switching details to compensate for variations.

[0081] Furthermore, minimal on-chip and off-chip hardware is required, allowing easy adaptation of existing designs. The proposed algorithm can be applied to different power semiconductors, where the AGD only needs to be configured to fit one model of the power semiconductor. Once the AGD is configured during development, the LUT can be stored in the active gate driver and remain constant in real-world operation.

[0082] In this case, only the variation metrics need to be measured in service, rather than the entire switching transient. This provides the advantage of the relative speed of the ADC, while also giving the algorithm enough information to populate the lookup table during development and select the LUT during operation.

[0083] The proposed development method allows power semiconductors to be switched based on one of several drive patterns. By adapting the drive pattern based on the current electrical characteristics of the power semiconductors, the controller can compensate for variations in the power semiconductors while ensuring good performance. This is also advantageous for industrial implementation and application.

[0084] Another advantage is that drive pattern development can be done during the development of the AGD, while variation detection and correction can be done during use.

[0085] The development stage is for configuring the AGD by generating drive patterns for specific electrical characteristics of a specific model of power semiconductor, which occurs before the AGD is used (e.g., before shipping the AGD to a customer).

[0086] An in-use operation is to select an appropriate drive pattern based on the detected variations, which may be done during pre-testing of the system or while the system is in use.

[0087] Figures 7, 8, and 9 show three drive patterns. Figure 7 shows a drive pattern 700 with two steps. Figure 8 shows a drive pattern 800 with three steps. Figure 9 shows a drive pattern 900 with n steps. Each drive pattern is shown with gate voltage divided by gate current on the Y-axis and time on the X-axis.

[0088] As shown in Figures 7, 8, and 9, the drive patterns can be two-step, three-step, or n-step drive patterns to suit various system requirements and complexities. A two-step drive pattern has a parameter vector of [N1, T1, N2, T2], where N1 and N2 are the values ​​of gate voltage relative to gate current, and T1 and T2 are the timing for each step. A three-step drive pattern has a parameter vector of [N1, T1, N2, T2, N3, T3]. An n-step drive pattern has a parameter vector of [N1, T1, ..., Nn, Tn].

[0089] All drive patterns may be stored in the LUT for selection. However, depending on the memory type of the LUT, i.e., volatile or non-volatile, the controller may function as an exchange storage for these drive patterns. Furthermore, the controller may support the LUT when changes in the parameter vector are minimal (e.g., only one drive parameter is changed). For example, if only one parameter (e.g., T1) of a three-step drive pattern [N1, T1, N2, T2, N3, T3] needs to be changed to correct for variations, the new drive pattern should be [N1, T1new, N2, T2, N3, T3]. In this case, it may not be necessary to store this drive pattern in a lookup table because changing only a single drive parameter does not require relatively large computational resources. During use, the controller may identify variations, modify the original drive pattern, and generate a new drive pattern [N1, T1new, N2, T2, N3, T3] in real time to drive the power semiconductor. Thus, the amount of available memory can be used more efficiently than, for example, if all possible drive patterns were stored.

[0090] Figure 10 shows a circuit diagram 1000 of a MOSFET in series with a diode. Figure 11 shows the main switching waveforms of the MOSFET. In particular, graph 1102 shows the drain current over time, graph 1104 shows the drain and diode voltages over time, graph 1106 shows the gate voltage over time, and graph 1108 shows the gate current over time.

[0091] Here, as an example, the threshold voltage V of the MOSFET TK31V60X using the AGD drive pattern th The compensation for variations is shown in Figure 10. Circuit diagram 1000 in Figure 10 is an equivalent switching circuit of the above MOSFET in series with a diode. V DC is the DC voltage, and L P is the parasitic inductance in the circuit, and I L is the load current, and i g represents the output of AGD, and C gd , C gs , and C ds is the parasitic capacitance of the MOSFET.

[0092] As shown in Figure 11, t0-t1 is the turn-on delay time. It is the time from when the AGD starts to output current to when the gate voltage V g V th and hence the drain current I d This is defined as the time between when the MOSFET starts to flow and when V g <V th Therefore:

[0093]

number

[0094] Gate current i g is the time between t0 and t1 g0 is fixed as:

[0095]

number

[0096] According to the TK31V60X datasheet, V th =3V, C gs +C gd =3000pF, I g0 = 3A, t1 = 3ns is obtained. th Considering V th =4.5V (50% shift to the right), C gs +C gd =3000pF, I g0 = 3A, we get a new t1 = 4.5ns.

[0097] In this case, a three-step driving pattern [N1, T1, N2, T2, N3, T3] can be applied to the TK31V60X. th After detecting the change in turn-on delay time due to the induced noise, a new driving pattern can be generated as [N1, T1new, N2, T2, N3, T3], where T1new=T1+(4.5ns-3ns)=T1+1.5ns to T1+2ns.

[0098] In this way, after detecting the variation in turn-on delay time, a new driving pattern is generated by adjusting T1 to T1new, thus correcting the variation in Vth.

[0099] In this way, the newly generated drive pattern corresponds to the measured turn-on delay. Thus, in use, the turn-on delay can be measured as the time between t0 when the gate voltage is output by the AGD and t1 when the drain current starts to flow, as shown in Figure 11.

[0100] Of course, it will be appreciated that any drive parameters of the drive pattern may be adapted / modified depending on the particular use case and the variations detected.

[0101] In the above examples, MOSFETs have been used as power semiconductors, however, it will be appreciated that other types of power semiconductors may also be used in the above examples.

[0102] The methods described herein may be used in power electronic converters (i.e., power factor correction (PFC), DC-DC converters, etc.), motor drives used in electric vehicles, renewable energy systems, power grids, industrial applications, etc.

[0103] It will be understood that any of the methods described herein may be computer-implemented. A computer-implemented method may be implemented through the use of a processor and / or a controller. Furthermore, the steps of any of the methods described herein may be performed by one or more processors and / or one or more controllers.

[0104] All of the methods described herein may use an AGD to control a power semiconductor to drive a load.

[0105] Implementations of the subject matter and operations described herein may be realized in digital electronic circuitry, or in computer software, firmware, or hardware, including the structures disclosed herein and their structural equivalents, or in one or more combinations thereof. Implementations of the subject matter described herein may be realized using one or more computer programs, i.e., one or more modules of computer program instructions, encoded on a computer storage medium for execution by or to control the operation of a data processing device. Alternatively or additionally, the program instructions may be encoded in an artificially generated propagated signal, e.g., a machine-generated electrical, optical, or electromagnetic signal generated to encode information for transmission to a suitable receiver for execution by a data processing device. A computer storage medium may be, or may be included in, a computer-readable storage device, a computer-readable storage substrate, a random-access or serial-access memory array or device, or one or more combinations thereof. Furthermore, while a computer storage medium is not a propagated signal, a computer storage medium may be a source or destination of computer program instructions encoded in an artificially generated propagated signal. A computer storage medium may also be, or may be contained in, one or more separate physical components or media (e.g., multiple CDs, disks, or other storage devices).

[0106] While specific embodiments have been described, these embodiments are presented by way of example only and are not intended to limit the scope of the invention. Indeed, the novel methods, devices, and systems described herein may be embodied in a variety of forms, and various omissions, substitutions, and changes in the form of the methods and systems described herein may be made without departing from the spirit of the invention. The appended claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the invention.

Claims

1. 1. A method for generating multiple drive patterns for an active gate driver (AGD), comprising: using the AGD to control power semiconductors under a plurality of operating conditions; For each operating condition, acquiring one or more electrical signals of the power semiconductor; detecting variations in one or more key parameters of the power semiconductor from the one or more electrical signals; and generating a drive pattern corresponding to the variation in the one or more key parameters based on a predetermined relationship between the variation in the one or more key parameters and one or more drive parameters of the drive pattern; storing in a memory the generated plurality of drive patterns for each operating condition and the corresponding variations in the one or more key parameters; A method comprising:

2. For each operating condition, determining a number of drive parameters of the generated drive pattern that differ from a corresponding plurality of drive parameters of a reference drive pattern; determining whether the number of drive parameters that differ from the corresponding plurality of drive parameters of the reference drive pattern is greater than a threshold number; Furthermore, 2. The method of claim 1 , wherein a drive pattern of the generated plurality of drive patterns is stored if the number of drive parameters of the drive pattern that differ from the corresponding plurality of drive parameters of the reference drive pattern is greater than the threshold number.

3. 2. The method of claim 1 , wherein one of the one or more key parameters includes a turn-on delay time, and wherein generating the drive pattern comprises adapting one or more step timings of a reference drive pattern to generate the drive pattern.

4. 4. The method of claim 3, wherein the one or more electrical signals comprise a gate voltage waveform and a drain current waveform, and wherein the turn-on delay time is the time between when the AGD begins to output a voltage and when a drain current begins to flow.

5. The method of claim 1 , wherein the plurality of operating conditions comprises at least one of a plurality of operating voltages or a plurality of operating temperatures.

6. 1. A method for generating multiple drive patterns for an active gate driver (AGD), comprising: using the AGD to control multiple power semiconductors of the same model; For each power semiconductor, acquiring one or more electrical signals of the power semiconductor; detecting variations in one or more key parameters of the power semiconductor from the one or more electrical signals; and generating a drive pattern corresponding to the variation in the one or more key parameters based on a predetermined relationship between the variation in the one or more key parameters and one or more drive parameters of the drive pattern; storing the generated plurality of drive patterns for each power semiconductor and the corresponding variations in the one or more key parameters in a memory; A method comprising:

7. For each power semiconductor, determining a number of drive parameters of the generated drive pattern that differ from a corresponding plurality of drive parameters of a reference drive pattern; determining whether the number of drive parameters that differ from the corresponding plurality of drive parameters of the reference drive pattern is greater than a threshold number; Furthermore, 7. The method of claim 6, wherein a drive pattern of the generated plurality of drive patterns is stored if the number of drive parameters of the drive pattern that differ from the corresponding plurality of drive parameters of the reference drive pattern is greater than the threshold number.

8. 7. The method of claim 6, wherein one of the one or more key parameters includes a turn-on delay time, and wherein generating the drive pattern comprises adapting one or more step timings of a reference drive pattern to generate the drive pattern.

9. 9. The method of claim 8, wherein the one or more electrical signals comprise a gate voltage waveform and a drain current waveform, and wherein the turn-on delay time is the time between when the AGD begins to output a voltage and when a drain current begins to flow.

10. 1. A method for controlling an active gate driver (AGD), comprising: controlling a power semiconductor using the AGD using a first drive pattern from a plurality of predetermined drive patterns, wherein each predetermined drive pattern corresponds to a variation in one or more key parameters of the power semiconductor; acquiring one or more electrical signals of the power semiconductor; detecting variations in one or more key parameters of the power semiconductor based on the one or more electrical signals; selecting a second drive pattern from the plurality of predetermined drive patterns that corresponds to the variation in the one or more key parameters; controlling the power semiconductor with the AGD using the second drive pattern; A method comprising:

11. determining a number of drive parameters of the first drive pattern to be adapted based on the variation in the one or more key parameters; wherein selecting the second drive pattern from the plurality of predetermined drive patterns is based on the number of drive parameters being greater than a threshold number; 11. The method of claim 10, wherein the method further comprises adapting the first drive pattern based on the variation in the one or more key parameters to generate the second drive pattern based on the number of drive parameters being less than or equal to the threshold number.

12. The method of claim 10 , wherein one of the one or more key parameters includes a turn-on delay time.

13. 13. The method of claim 12, wherein the one or more electrical signals comprise a gate voltage waveform and a drain current waveform, and wherein the turn-on delay time is the time between when the AGD begins to output a voltage and when a drain current begins to flow.

14. 11. The method of claim 10, further comprising obtaining the plurality of predetermined drive patterns by generating, for each operating condition, a drive pattern corresponding to the variation in the one or more key parameters based on a predetermined relationship between the variation in the one or more key parameters and one or more drive parameters of the drive pattern.

15. 10. A non-transitory computer medium comprising a computer program comprising computer program code that, when executed on a processing device, causes the processing device to perform the method of claim 1.

16. 1. A system for generating multiple drive patterns for an active gate driver (AGD), comprising: AGD and Power semiconductors and Memory and Controller and Equipped with The controller using the AGD to control the power semiconductors under a plurality of operating conditions; For each operating condition, acquiring one or more electrical signals of the power semiconductor; detecting variations in one or more key parameters of the power semiconductor from the one or more electrical signals; and generating a drive pattern corresponding to the variation in the one or more key parameters based on a predetermined relationship between the variation in the one or more key parameters and one or more drive parameters of the drive pattern; storing the generated drive patterns for each operating condition and the corresponding variations in the one or more key parameters in the memory; A system configured to:

17. 1. A system for generating multiple drive patterns for an active gate driver (AGD), comprising: AGD and Multiple power semiconductors, Memory and Controller and Equipped with The controller using the AGD to control the plurality of power semiconductors of the same model; For each power semiconductor, acquiring one or more electrical signals of the power semiconductor; detecting variations in one or more key parameters of the power semiconductor from the one or more electrical signals; and generating a drive pattern corresponding to the variation in the one or more key parameters based on a predetermined relationship between the variation in the one or more key parameters and one or more drive parameters of the drive pattern; storing the generated plurality of drive patterns for each power semiconductor and the corresponding variations in the one or more key parameters in the memory; A system configured to:

18. 1. A system for controlling an active gate driver (AGD), comprising: AGD and Power semiconductors and a memory that stores a plurality of predetermined drive patterns, wherein each predetermined drive pattern corresponds to a variation in one or more key parameters of the power semiconductor; Controller and Equipped with The controller controlling the power semiconductor using the AGD using a first drive pattern from the plurality of predetermined drive patterns; acquiring a plurality of electrical signals of the power semiconductor; Detecting variations in one or more key parameters of the power semiconductor based on the plurality of electrical signals; selecting a second drive pattern from the plurality of predetermined drive patterns that corresponds to the variation in the one or more key parameters; controlling the power semiconductor with the AGD using the second drive pattern; A system configured to:

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