Semiconductor package device and manufacturing method for the same

Abstract

To provide a semiconductor package device with improved bonding quality, and a manufacturing method for the same.SOLUTION: A semiconductor package device 200 includes a support substrate 10 having a first surface 12 and a second surface 14 facing each other and having a cavity 16 extending from the first surface to the second surface, a first semiconductor chip 20 disposed in the cavity, a first die structure CD1 including a first gap filling film 30 that fills a gap between an inner wall of the cavity and the first semiconductor chip, and a second die structure CD2 stacked on the first die structure and including a second semiconductor chip 40 electrically connected to the first semiconductor chip. An outer surface of the support substrate and an outer side surface of the second semiconductor chip exist on the same plane.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a semiconductor package device and a manufacturing method thereof, and more particularly to a semiconductor package device including stacked semiconductor chips and a method for manufacturing the semiconductor package device. [Background technology]

[0002] To manufacture a semiconductor package including stacked semiconductor chips, a plurality of first semiconductor chips are arranged on a carrier substrate, and a gap fill film is filled between the plurality of dies to form a reconstituted wafer. The reconstituted wafer is then attached to a target wafer having a second semiconductor chip by wafer-to-wafer bonding. However, a step may occur between the top surface of the first semiconductor chip and the top surface of the gap fill film in the reconstituted wafer, which may result in voids during the wafer-to-wafer bonding process. Furthermore, a bevel step may occur in the edge region of the reconstituted wafer, which may result in voids in the bevel region during the wafer-to-wafer bonding process. Summary of the Invention [Problem to be solved by the invention]

[0003] SUMMARY OF THE INVENTION It is an object of the present invention to provide a semiconductor package device with improved bonding quality.

[0004] Another object of the present invention is to provide a method for manufacturing the semiconductor package device. [Means for solving the problem]

[0005] According to one aspect of the present invention, there is provided a semiconductor package device including a first die structure and a second die structure stacked on the first die structure. The first die structure includes a support substrate having a cavity, a first semiconductor chip disposed in the cavity, and a first gap fill film filling a gap between the inner wall of the cavity and the first semiconductor chip. The second die structure is stacked on the first die structure and includes a second semiconductor chip electrically connected to the first semiconductor chip. The first semiconductor chip includes a first substrate, a first front insulating film formed on a first surface of the first substrate and having a first bonding pad thereon, and a first rear insulating film formed on a second surface of the first substrate opposite the first surface and having a second bonding pad thereon. The second semiconductor chip includes a second substrate and a second front insulating film formed on a first surface of the second substrate and having a third bonding pad, the second bonding pad and the third bonding pad being directly bonded to each other.

[0006] According to one aspect of the present invention, there is provided a semiconductor package device including: a support substrate having a first surface and a second surface opposite to the first surface and having a cavity extending from the first surface to the second surface; a first die structure including a first semiconductor chip disposed in the cavity; and a first gap fill film that fills a gap between an inner wall of the cavity and the first semiconductor chip; and a second die structure including a second semiconductor chip stacked on the first die structure and electrically connected to the first semiconductor chip, wherein an outer surface of the support substrate and an outer surface of the second semiconductor chip are located on the same plane.

[0007] According to one aspect of the present invention, a semiconductor package device includes a buffer die, a plurality of die structures sequentially stacked on the buffer die, and a top core die stacked on a top die structure among the plurality of die structures. Each of the plurality of die structures includes a support substrate having a cavity, a core die disposed in the cavity, and a first gap fill film that fills a gap between an inner wall of the cavity and the core die. An outer surface of the support substrate of the top die structure and an outer surface of the top core die are located on the same plane.

[0008] In order to achieve another object of the present invention, a method for manufacturing a semiconductor package device according to one aspect of the present invention includes providing a support substrate having a first surface and a second surface opposite to the first surface, forming a cavity in the support substrate having a predetermined depth from the first surface, placing a first semiconductor chip in the cavity, forming a first gap fill film to fill a gap between an outer surface of the first semiconductor chip and an inner surface of the recess, partially removing the second surface of the support substrate to expose the first semiconductor chip, and bonding a second semiconductor chip to the support substrate so as to be electrically connected to the first semiconductor chip. [Effects of the Invention]

[0009] According to the present invention, a semiconductor package device includes a first die structure and a second die structure stacked on the first die structure. The first die structure includes a support substrate having a cavity, a first semiconductor chip disposed in the cavity, and a first gap fill film filling a gap between the inner wall of the cavity and the first semiconductor chip. The second die structure includes a second semiconductor chip electrically connected to the first semiconductor chip. The first semiconductor chip includes a first substrate, a first front insulating film formed on a first surface of the first substrate and having a first bonding pad thereon, and a first rear insulating film formed on a second surface of the first substrate opposite the first surface and having a second bonding pad thereon.

[0010] An outer surface of the second semiconductor chip is coplanar with an outer surface of the support substrate. A first rear insulating film of the first semiconductor chip extends laterally from the second surface of the first substrate to cover the first gap-fill layer and the top surface of the support substrate. The first rear insulating film of the first semiconductor chip and the second front insulating film of the second semiconductor chip are directly bonded to each other.

[0011] The second surface of the first substrate of the first semiconductor chip is coplanar with a top surface of the support substrate including silicon, and the second surface of the first substrate of the first semiconductor chip is coplanar with a top surface of the first gap-fill film.

[0012] Therefore, since no step occurs between the rear surface of the first substrate of the first semiconductor chip and the upper surface of the first gap fill filling film, it is possible to prevent voids from occurring during the wafer-to-wafer bonding process of the support substrate on which the first semiconductor chip is provided and the second semiconductor chip.

[0013] However, the effects of the present invention are not limited to the effects mentioned above, and can be variously expanded within the scope of the concept and scope of the present invention. [Brief explanation of the drawings]

[0014] [Figure 1] FIG. 1 is a cross-sectional view showing a semiconductor package device according to one embodiment of the present invention. [Figure 2] FIG. 2 is an enlarged cross-sectional view of part A in FIG. [Figure 3] FIG. 3 is a plan view showing the lower die structure in FIG. [Figure 4] FIG. 4 is a diagram for explaining a method for manufacturing a semiconductor package device according to one embodiment of the present invention. [Figure 5] FIG. 5 is a diagram for explaining a method for manufacturing a semiconductor package device according to one embodiment of the present invention. [Figure 6] FIG. 6 is a diagram for explaining a method for manufacturing a semiconductor package device according to one embodiment of the present invention. [Figure 7] FIG. 7 is a diagram for explaining a method for manufacturing a semiconductor package device according to one embodiment of the present invention. [Figure 8] FIG. 8 is a diagram for explaining a method for manufacturing a semiconductor package device according to one embodiment of the present invention. [Figure 9] FIG. 9 is a diagram for explaining a method for manufacturing a semiconductor package device according to one embodiment of the present invention. [Figure 10] FIG. 10 is a diagram for explaining a method for manufacturing a semiconductor package device according to an embodiment of the present invention. [Figure 11] FIG. 11 is a diagram for explaining a method for manufacturing a semiconductor package device according to an embodiment of the present invention. [Figure 12] FIG. 12 is a diagram for explaining a method for manufacturing a semiconductor package device according to an embodiment of the present invention. [Figure 13] FIG. 13 is a diagram for explaining a method for manufacturing a semiconductor package device according to an embodiment of the present invention. [Figure 14] FIG. 14 is a diagram for explaining a method for manufacturing a semiconductor package device according to an embodiment of the present invention. [Figure 15] FIG. 15 is a diagram for explaining a method for manufacturing a semiconductor package device according to an embodiment of the present invention. [Figure 16] FIG. 16 is a diagram for explaining a method for manufacturing a semiconductor package device according to an embodiment of the present invention. [Figure 17] FIG. 17 is a diagram for explaining a method for manufacturing a semiconductor package device according to an embodiment of the present invention. [Figure 18] FIG. 18 is a diagram for explaining a method for manufacturing a semiconductor package device according to an embodiment of the present invention. [Figure 19] FIG. 19 is a diagram for explaining a method for manufacturing a semiconductor package device according to an embodiment of the present invention. [Figure 20] FIG. 20 is a cross-sectional view showing a semiconductor package device according to one embodiment of the present invention. [Figure 21] 21 is a cross-sectional view of the intermediate core die stack of the semiconductor package device of FIG. [Figure 22] FIG. 22 is a cross-sectional view illustrating a method for manufacturing a semiconductor package device according to an embodiment of the present invention. [Figure 23] FIG. 23 is a cross-sectional view illustrating a method for manufacturing a semiconductor package device according to an embodiment of the present invention. [Figure 24] FIG. 24 is a cross-sectional view illustrating a method for manufacturing a semiconductor package device according to an embodiment of the present invention. [Figure 25] FIG. 25 is a cross-sectional view illustrating a method for manufacturing a semiconductor package device according to an embodiment of the present invention. [Figure 26] FIG. 26 is a cross-sectional view illustrating a method for manufacturing a semiconductor package device according to an embodiment of the present invention. [Figure 27] FIG. 27 is a cross-sectional view illustrating a method for manufacturing a semiconductor package device according to an embodiment of the present invention. [Figure 28] FIG. 28 is a cross-sectional view illustrating a method for manufacturing a semiconductor package device according to an embodiment of the present invention. [Figure 29]FIG. 29 is a cross-sectional view showing a semiconductor package according to one embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0015] Hereinafter, preferred embodiments of the present invention will be described in more detail with reference to the accompanying drawings.

[0016] Fig. 1 is a cross-sectional view showing a semiconductor package device according to an embodiment of the present invention. Fig. 2 is an enlarged cross-sectional view of part A in Fig. 1. Fig. 3 is a plan view showing a lower die structure in Fig. 1. Fig. 1 includes a cross section taken along line B-B' in Fig. 3.

[0017] 1 to 3, the semiconductor package device 200 includes a first die structure (CD1) having a first semiconductor chip 20, and a second die structure (CD2) having a second semiconductor chip 40 stacked on the first die structure (CD1) and bonded to the first semiconductor chip 20. The semiconductor package device 200 also includes conductive bumps 50 provided on the outer surface of the first semiconductor chip 20.

[0018] In one embodiment of the present invention, the semiconductor package device 200 is a multi-chip package (MCP) including semiconductor chips of different types. The semiconductor package device 200 is a stacked semiconductor chip as a chiplet package including multiple chiplet dies. The stacked semiconductor chip includes a first semiconductor chip 20 as a first chiplet die and a second semiconductor chip 40 as a second chiplet die. Each of the first semiconductor chip 20 and the second semiconductor chip 40 is a small building block or IP block that constitutes a processor chip. The first semiconductor chip 20 and the second semiconductor chip 40 are stacked together to provide a semiconductor chip with a single independent function.

[0019] The semiconductor package device 200 is provided as a logic chip including a logic circuit. The logic chip is a controller that controls memory elements of a memory chip. For example, the semiconductor chip is an ASIC serving as a host such as a CPU, NPU, GPU, or SOC, or a processor chip such as an AP (Application Processor). The memory chip includes DRAM, SRAM, etc.

[0020] In this embodiment, the semiconductor package device as a multi-chip package includes two stacked first chiplet dies 20 and a second chiplet die 40. However, this is not limited thereto, and the semiconductor package device may include, for example, 4, 8, 12, or 16 stacked semiconductor chips.

[0021] In one embodiment of the present invention, a first die structure (CD1) as a lower die structure includes a support substrate 10 having a cavity 16, a first semiconductor chip 20 disposed in the cavity 16, and a first gap fill film 30 that fills a gap between the inner wall of the cavity 16 and the first semiconductor chip 20. A second die structure (CD2) as an upper die structure is stacked on the first die structure (CD1). The second die structure (CD2) includes a second semiconductor chip 40 electrically connected to the first semiconductor chip 20.

[0022] As shown in FIG. 1, the support substrate 10 has a first surface (lower surface) 12 and a second surface (upper surface) 14 that face each other. The support substrate 10 has a cavity 16 in the center. The cavity 16 extends from the first surface 12 to the second surface 14 of the support substrate 10. The support substrate 10 includes, for example, a silicon substrate, a glass substrate, a non-metallic or metallic plate, etc. The thickness of the support substrate 10 is in the range of 10 μm to 50 μm.

[0023] The first semiconductor chip 20 is provided in the cavity 16 of the support substrate 10. The first semiconductor chip 20 includes a first substrate 21, a first front insulating film 22, a plurality of first bonding pads 23, a plurality of through electrodes 24, and a plurality of second bonding pads 27.

[0024] The first substrate 21 has a first surface 212 and a second surface 214 opposite to each other. The first surface 212 is an active surface, and the second surface 214 is a non-active surface. A circuit pattern is provided on the first surface 212 of the first substrate 21. The first surface 212 is a front side surface on which the circuit pattern is formed, and the second surface 214 is a back side surface. For example, the first substrate 21 is a single crystal silicon substrate. The circuit pattern includes transistors, capacitors, diodes, etc. The circuit pattern can form circuit elements. Therefore, the first semiconductor chip 20 is a semiconductor device in which many circuit elements are formed.

[0025] 2, the first front insulating film 22 is provided on the first surface 212, i.e., the active surface, of the first substrate 21. The first front insulating film 22 includes a plurality of insulating layers 222, 224 and wiring 223 within the insulating layers. In addition, a first bonding pad 23 is provided on the outermost insulating layer of the first front insulating film 22.

[0026] For example, the first front insulating film 22 includes a metal wiring layer 222 and a first passivation film 224. The metal wiring layer 222 includes a plurality of wirings 223 therein. For example, the metal wiring layer 222 includes a metal wiring structure including a plurality of wirings 223 vertically stacked on a buffer film and an insulating film. The first bonding pad 23 is formed on the uppermost wiring of the plurality of wirings 223. For example, the wiring includes aluminum (Al), copper (Cu), tin (Sn), nickel (Ni), gold (Au), platinum (Pt), or an alloy thereof.

[0027] The first passivation film 224 is formed on the metal wiring layer 222 and exposes at least a portion of the first bonding pad 23. The first passivation film 224 includes a plurality of stacked insulating films. For example, the first passivation film 224 includes silicon oxide, silicon nitride, or silicon carbonitride. The first passivation film 224 has a single film or a multi-layer film structure.

[0028] A first bonding pad 23 is provided on the first passivation film 224. The first bonding pad 23 is exposed through the outer surface of the first passivation film 224. Although not shown in the drawings, an interlayer insulating film is provided on the first surface 212 of the first substrate 21 and covers the circuit pattern.

[0029] A through silicon via (TSV) 24 vertically penetrates the interlayer insulating film and extends from the first surface 212 to the second surface 214 of the first substrate 21. The through electrode 24 contacts the lowest wiring of the metal wiring structure. Thus, the through electrode 24 is electrically connected to the first bonding pad 23 by a wiring 223.

[0030] A first rear insulating film 26 is formed on the second surface 214, i.e., the rear surface, of the first substrate 21. A second bonding pad 27 is provided on the first rear insulating film 26. For example, the second bonding pad 27 is disposed on the exposed surface of the through electrode 24. The first rear insulating film 26 includes silicon oxide, carbon-doped silicon oxide, silicon carbonitride (SiCN), etc. Thus, the first and second bonding pads 23, 27 are electrically connected to each other by the through electrode 24.

[0031] As shown in FIG. 3, the first gap-fill filling film 30 fills the gap (G) between the outer surface of the first semiconductor chip 20 and the inner surface of the cavity 16 of the support substrate 10. For example, the first gap-fill filling film 30 includes a silicon oxide such as TEOS. The first gap-fill filling film includes an inorganic dielectric film or an organic dielectric film. The inorganic dielectric film includes silicon oxide, silicon oxynitride, PSG (Phosphosilicate Glass), BPSG (Boro-Phosphosilicate Glass), and the like. The first gap fill filling layer includes an insulating material having a thermal expansion coefficient smaller than that of the support substrate 10. The first gap fill filling layer has a hardness smaller than that of the support substrate 10.

[0032] The first front insulating film 22 of the first semiconductor chip 20 is exposed by the first gap-fill filling film 30. The outer surface, i.e., the lower surface, of the first front insulating film 22 is located on the same plane as the lower surface of the first gap-fill filling film 30. The lower surface of the first gap-fill filling film 30 and the first surface 12 of the support substrate 10 are located on the same plane.

[0033] The second surface 214 of the first substrate 21 of the first semiconductor chip 20 is coplanar with the second surface 14 of the support substrate 10. The second surface 214 of the first substrate 21 is coplanar with the top surface of the first gap fill filling film 30. The top surface of the first gap fill filling film 30 and the second surface 14 of the support substrate 10 are coplanar.

[0034] The first backside insulating film 26 of the first semiconductor chip 20 extends laterally from the second surface 214 of the first substrate 21 to cover the first gap-fill filling film 30 and the second surface 14 of the support substrate 10.

[0035] In one embodiment of the present invention, the second semiconductor chip 40 is stacked on the first semiconductor chip 20 and the support substrate 10. The second semiconductor chip 40 includes a second substrate 41, a second front insulating film 42, and a plurality of third bonding pads 43.

[0036] A circuit pattern is provided on the first surface 412, i.e., the active surface, of the second substrate 41. For example, the second substrate 41 is a single-crystal silicon substrate. The circuit pattern includes transistors, capacitors, diodes, etc. The circuit pattern can form circuit elements. Therefore, the second semiconductor chip 40 is a semiconductor device with many circuit elements formed therein.

[0037] The second front insulating film 42 is provided on the first surface 412, i.e., the active surface, of the second substrate 41. The second front insulating film 42 includes a plurality of insulating layers 422, 424 and wiring 423 within the insulating layers. In addition, a third bonding pad 43 is provided on the outermost insulating layer of the second front insulating film 42.

[0038] For example, the second front insulating film 42 includes a metal wiring layer 422 and a third passivation film 424. The metal wiring layer 422 includes a plurality of wirings 423 therein. For example, the metal wiring layer 422 includes a metal wiring structure including a plurality of wirings 423 vertically stacked on the buffer film and the insulating film. The third bonding pad 43 is formed on the uppermost wiring of the plurality of wirings 423. For example, the wiring includes aluminum (Al), copper (Cu), tin (Sn), nickel (Ni), gold (Au), platinum (Pt), or an alloy thereof.

[0039] The third passivation film 424 is formed on the metal wiring layer 422 and exposes at least a portion of the third bonding pad 43. The third passivation film 424 includes a plurality of stacked insulating films. For example, the third passivation film 424 includes silicon oxide, silicon nitride, or silicon carbonitride. The third passivation film 424 can have a single film structure or a multi-layer film structure.

[0040] The third passivation film 424 is provided with a third bonding pad 43. The third bonding pad 43 can be exposed through the outer surface of the third passivation film 424b.

[0041] 2, the second semiconductor chip 40 and the first semiconductor chip 20 are bonded to each other by hybrid bonding. The front surface 412 of the second substrate 41 of the second semiconductor chip 40 is disposed facing the rear surface 214 of the first substrate 21 of the first semiconductor chip 20. The second front insulating film 42 of the second semiconductor chip 40 and the first rear insulating film 26 of the first semiconductor chip 20 can be directly bonded to each other. Then, the second bonding pad 27 of the first semiconductor chip 20 and the third bonding pad 43 of the second semiconductor chip 40 are bonded to each other by copper-copper hybrid bonding (pad to pad direct bonding).

[0042] The first back insulating film 26 of the first semiconductor chip 20 and the second front insulating film 42 of the second semiconductor chip 40 are directly bonded to each other. The first back insulating film 26 and the second front insulating film 42 are in contact with each other, providing a bonding structure including an insulating material that provides excellent bonding strength. The first back insulating film 26 and the second front insulating film 42 are bonded to each other while in contact with each other through a high-temperature annealing process. Here, the bonding structure can have even stronger bonding strength due to the covalent bond.

[0043] In one embodiment of the present invention, the outer surface of the second semiconductor chip 40 is located on the same plane as the outer surface of the support substrate 10. The first semiconductor chip 20 has a first size, and the second semiconductor chip 40 has a second size larger than the first size. The first semiconductor chip 20 has a first width (L1), and the second semiconductor chip 40 has a second width larger than the first width. The first semiconductor chip 20 is disposed on a central region of the second semiconductor chip 40.

[0044] In one embodiment of the present invention, the support substrate 10 has a first coefficient of thermal expansion, and the first gap-fill filling film 30 has a second coefficient of thermal expansion greater than the first coefficient of thermal expansion. Because the support substrate 10, which includes silicon, has a denser composition than the first gap-fill filling film 30, the support substrate 10 can have superior mechanical strength and thermal properties with temperature changes compared to the first gap-fill filling film 30. The percentage of the total area of ​​the first die structure (CD1) occupied by the support substrate 10 is in the range of 5% to 30%.

[0045] In one embodiment of the present invention, the conductive bumps 50 are disposed on the first bonding pads 23 on the first front insulating film 22 of the first semiconductor chip 20. For example, each of the conductive bumps 50 includes a pillar bump 52 on the first bonding pad 23 and a solder bump 54 on the pillar bump 52. For example, the pillar bump includes copper (Cu), aluminum (Al), tin (Sn), nickel (Ni), gold (Au), platinum (Pt), or an alloy thereof. The solder bump includes solder. The semiconductor package device 200 can be mounted on a substrate such as a package substrate, an interposer, or a redistribution layer via the conductive bumps 50 to form a semiconductor package.

[0046] As described above, the semiconductor package device 200 includes a first die structure (CD1) and a second die structure (CD2) stacked on the first die structure (CD1). The first die structure (CD1) includes a support substrate 10 having a cavity 16, a first semiconductor chip 20 disposed in the cavity 16, and a first gap fill filling film 30 that fills a gap between the inner wall of the cavity 16 and the first semiconductor chip 20. The second die structure (CD2) includes a second semiconductor chip 40 electrically connected to the first semiconductor chip 20.

[0047] The outer surface of the second semiconductor chip 40 is flush with the outer surface of the support substrate 10. The first rear insulating film 26 of the first semiconductor chip 20 extends laterally from the second surface 214 of the first substrate 21 to cover the first gap-fill filling film 30 and the second surface 14 of the support substrate 10. The first rear insulating film 26 of the first semiconductor chip 20 and the second front insulating film 42 of the second semiconductor chip 40 are directly bonded to each other.

[0048] The second surface 214 of the first substrate 21 of the first semiconductor chip 20 is located on the same plane as the second surface 14 of the support substrate 10, which includes silicon. The second surface 214 of the first substrate 21 of the first semiconductor chip 20 is located on the same plane as the top surface of the first gap fill filling film 30. The top surface of the first gap fill filling film 30 is located on the same plane as the second surface 14 of the support substrate 10. Therefore, no step is formed between the rear surface of the first substrate 21 of the first semiconductor chip 20 and the top surface of the first gap fill filling film 30, which prevents voids from occurring during the wafer-to-wafer bonding process of the support substrate 10 on which the first semiconductor chip 20 is formed and the second semiconductor chip 40.

[0049] A method for manufacturing the semiconductor package of FIG. 1 will now be described.

[0050] 4 to 19 are views for explaining a method for manufacturing a semiconductor package device according to an embodiment of the present invention. FIGS. 4, 6, 9 to 12, 14, and 16 to 19 are cross-sectional views for explaining a method for manufacturing a semiconductor package device according to an embodiment of the present invention. FIG. 7 is an enlarged cross-sectional view of portion D in FIG. 6. FIG. 13 is an enlarged cross-sectional view of portion F in FIG. 12. FIG. 15 is an enlarged cross-sectional view of portion G in FIG. 14. FIG. 5 is a plan view of FIG. 4. FIG. 4 is a cross-sectional view taken along line CC' in FIG. 5. FIG. 8 is a plan view of FIG. 6. FIG. 6 is a cross-sectional view taken along line EE' in FIG. 8.

[0051] As shown in Figures 4 and 5, a carrier substrate (C1) is provided with a recess (RC) formed therein.

[0052] In one embodiment of the present invention, the carrier substrate (C1) serves as a support frame for placing a first semiconductor chip (lower die) in the recess (RC), forming a gap fill layer to fill the recess, and bonding the first semiconductor chip to a second semiconductor chip of a target wafer at the wafer level. The carrier substrate (C1) may have a shape corresponding to a wafer or panel on which a semiconductor process is performed. For example, the carrier substrate (C1) may include a silicon substrate, a glass substrate, a non-metallic or metallic plate, etc.

[0053] The carrier substrate (C1) includes a silicon substrate 10 having a first surface 12 and a second surface 14 opposite to each other. The carrier substrate (C1) includes a package region (PR) in which the first semiconductor chip is mounted, and a cutting region (CR) surrounding the package region (PR). As will be described later, the carrier substrate (C1) can be cut along the cutting region (CR) to be separated into individual support substrates surrounding the first semiconductor chips.

[0054] As shown in FIGS. 4 and 5, an align key pattern (AL) is first formed on the second surface 14 of the carrier substrate (C1). For example, an oxide film serving as a passivation film may be formed on the second surface 14 of the silicon substrate 10, and the align key pattern (AL) may be formed on the oxide film through a patterning process and a plating process. The align key pattern (AL) may include a metal material such as aluminum or copper. The align key pattern (AL) may be formed in the peripheral region or cutting region (CR) of the package region (PR). The process of attaching the first semiconductor chip is performed using the align key pattern (AL).

[0055] Next, recesses (RC) for accommodating the first semiconductor chips are formed on the second surface 14 of the carrier substrate (C1). The recesses (RC) are formed in the package regions (PR) of the carrier substrate (C1). The recesses (RC) are formed by a plasma etching process. Alternatively, the recesses (RC) can be formed by a laser drilling process, a wet etching process, etc.

[0056] The recess (RC) is formed in correspondence with the region where the first semiconductor chip is to be disposed. The recess (RC) may have an area larger than the area of ​​the first semiconductor chip. The recess (RC) has a predetermined depth from the second surface 14 of the silicon substrate 10. For example, the area of ​​the recess (RC) is in the range of 105% to 115% of the area of ​​the first semiconductor chip. The predetermined depth (D) of the recess (RC) is in the range of 15 μm to 50 μm. The area and depth of the recess (RC) are determined taking into consideration the area, thickness, etc. of the first semiconductor chip.

[0057] In another embodiment, the alignment key pattern (AL) is formed in the recess (RC). In this case, an oxide film serving as a passivation film is formed on the bottom surface of the recess (RC) of the silicon substrate 10, and the alignment key pattern (AL) can be formed on the oxide film by patterning and plating processes.

[0058] As shown in FIGS. 6 to 8, a first semiconductor chip 20 is disposed in the recess (RC) of the silicon substrate 10. As shown in FIG.

[0059] In one embodiment of the present invention, a first semiconductor chip 20, which has been cut from a wafer by a cutting process, is placed in a recess (RC) of a silicon substrate 10. The first semiconductor chip 20 is stacked so that its front surface faces the silicon substrate 10. The top of the first semiconductor chip 20 is exposed from the recess (RC). In another embodiment, the first semiconductor chip 20 is a first chiplet die (lower chiplet die). The first semiconductor chip 20 is a small building block or IP block that constitutes a processor chip. As will be described later, the first chiplet die can constitute one chip together with a second semiconductor chip as a second chiplet die.

[0060] 7, the first semiconductor chip 20 includes a first substrate 21 and a first front insulating film 22 having first bonding pads 23 provided on its outer surface. The first semiconductor chip 20 also includes a plurality of through electrodes 24 provided in the first substrate 21 and electrically connected to the first bonding pads 23.

[0061] The first substrate 21 has a first surface 212 and a second surface 214 opposite to the first surface 212. A circuit pattern is formed on the first surface 212 of the first substrate 21. For example, the first substrate 21 includes a semiconductor material such as silicon, germanium, silicon-germanium, etc., or a III-V compound semiconductor such as gallium phosphide (GaP), gallium arsenide (GaAs), gallium antimonide (GaSb), etc. According to another embodiment, the first substrate 21 is a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate.

[0062] The circuit pattern includes transistors, capacitors, diodes, etc. The circuit pattern can constitute a circuit element. Therefore, the semiconductor chip is a semiconductor package device in which a number of circuit elements are formed. The circuit pattern is formed on the first surface 212 of the first substrate 21 by a Front End of Line (FEOL) process for manufacturing semiconductor elements. The surface of the substrate formed by the FEOL process is called the front side surface of the substrate, and the surface opposite to the front side is called the backside. surface).

[0063] The first front insulating film 22 is an interlayer insulating film and is formed on the first surface 212, i.e., the front surface, of the first substrate 21. The first front insulating film 22 includes a plurality of insulating layers 222, 224 and wiring 223 within the insulating layers. In addition, a first bonding pad 23 is provided on the outermost insulating layer of the first front insulating film 22.

[0064] For example, the first front insulating film 22 includes a metal wiring layer 222 and a first passivation film 224. The metal wiring layer 222 includes a plurality of wirings 223 therein. For example, the metal wiring layer 222 includes a metal wiring structure including a plurality of wirings 223 vertically stacked on a buffer film and an insulating film. The first bonding pad 23 is formed on the uppermost wiring of the plurality of wirings 223. For example, the wiring includes aluminum (Al), copper (Cu), tin (Sn), nickel (Ni), gold (Au), platinum (Pt), or an alloy thereof.

[0065] The first passivation film 224 is formed on the metal wiring layer 222 and exposes at least a portion of the first bonding pad 23. The first passivation film 224 includes a plurality of stacked insulating films. For example, the first passivation film 224 includes silicon oxide, silicon nitride, or silicon carbonitride. The first passivation film 224 has a single film or a multi-layer film structure.

[0066] A first bonding pad 23 is provided on the first passivation film 224. The first bonding pad 23 is exposed through the outer surface of the first passivation film 224. Although not shown in the drawings, an interlayer insulating film is provided on the first surface 212 of the first substrate 21 to cover the circuit pattern. The interlayer insulating film is formed to include, for example, silicon oxide or a low-k material. The interlayer insulating film includes an underlying wiring electrically connected to the circuit pattern. Thus, the circuit pattern is electrically connected to the first bonding pad 23 via the underlying wiring and the wiring.

[0067] A through silicon via (TSV) 24 vertically penetrates the interlayer insulating film and extends to a predetermined depth from the first surface 212 of the first substrate 21. The through electrode 24 contacts the lowest wiring of the metal wiring structure. Thus, the through electrode 24 is electrically connected to the first bonding pad 23 by a wiring 223.

[0068] A liner film (not shown) is provided on the outer surface of the through electrode 24. The liner film includes silicon oxide or carbon-doped silicon oxide. The liner film can electrically insulate the through electrode 24 from the first substrate 21 and the metal wiring layer 222.

[0069] The through electrode 24 and the first bonding pad 23 include the same metal, for example, copper (Cu), but are not limited thereto, and may include a material (e.g., gold (Au)) that is bonded by interdiffusion of metals through a high-temperature annealing process.

[0070] 8, the outer surface of the first semiconductor chip 20 is spaced apart from the inner surface of the recess (RC). The gap (G) between the outer surface of the first semiconductor chip 20 and the inner surface of the recess (RC) is in the range of 5 μm to 10 μm.

[0071] As shown in FIG. 9, the second surface 214 of the first substrate 21 is partially removed to expose one end of the through electrode 24 .

[0072] In one embodiment of the present invention, first, a back wrap After partially removing the second surface 214 of the first substrate 21 by a grinding process such as a silicon lap process, one end of the through electrode 24 is exposed by an etching process such as a silicon recess process. This allows the thickness of the first substrate 21 to be reduced to a desired thickness. For example, the first substrate 21 may have a thickness in the range of approximately 20 μm to 100 μm. Here, the second surface 214 of the first substrate 21 is at the same height as or higher than the second surface 14 of the silicon substrate 10.

[0073] The back-lapping process grinds the rear surface of the first substrate 21. The silicon recess process can selectively etch only the silicon on the rear surface of the first substrate 21. The etching process is an isotropic dry etching process. The etching process includes a plasma etching process. The plasma etching process can be performed using inductively coupled plasma, capacitively coupled plasma, microwave plasma, etc.

[0074] As a result, one end of the through electrode 24 protrudes from the second surface 214 of the first substrate 21 to have the same height.

[0075] As shown in FIG. 10, a first gap-fill filling film 30 is formed on the second surface 14 of the carrier substrate (C1) so as to cover the first semiconductor chip 20.

[0076] In one embodiment of the present invention, the first gap-fill filling film 30 is formed to fill the gap (G) between the outer surface of the first semiconductor chip 20 and the inner surface of the recess (RC). The first gap-fill filling film 30 is formed to cover the second surface 14 of the silicon substrate 10. The first gap-fill filling film 30 is formed on the second surface 214 of the first substrate 21 to fill the gap between the protruding ends of the through-electrodes 24. For example, the first gap-fill filling film 30 includes a silicon oxide such as TEOS.

[0077] As shown in FIGS. 11 to 13, a first rear insulating film 26 having second bonding pads 27 on its outer surface is formed on the second surface 214 of the first substrate 21.

[0078] 11, the upper portion of the first gap-fill filling film 30 is removed to expose one end of the through electrode 24. Here, the second surface 214 of the first substrate 21 can also be exposed.

[0079] In one embodiment of the present invention, a chemical mechanical polishing (CMP) process is performed using the second surface 14 of the silicon substrate 10 (or the passivation film on the second surface 14) for polishing endpoint detection, whereby the upper portion of the first gap-fill filling film 30 is removed to expose one end of the through electrode 24. The CMP process removes one end of the through electrode 24 and a portion of the first gap-fill filling film covering it, exposing the second surface 214 of the first substrate 21 (or the passivation film on the second surface 14). The second surface 14 of the silicon substrate 10 (or the passivation film on the second surface 14) is located on the same plane as the second surface 214 of the first substrate 21. The second surface 14 of the silicon substrate 10 (or the passivation film on the second surface 14) is located on the same plane as the upper surface of the first gap-fill filling film 30. The top surface of the first gap-fill film 30 is flush with the second surface 214 of the first substrate 21 .

[0080] Therefore, since no step is generated between the rear surface of the first substrate 21 of the first semiconductor chip 20 and the upper surface of the first gap fill film 30, it is possible to prevent voids from occurring during a subsequent wafer-to-wafer bonding process of the first semiconductor chip 20 and the second semiconductor chip. Furthermore, since no bevel step is generated between the second surface 14 of the silicon substrate 10 in the edge region of the carrier substrate C1 and the rear surface of the first substrate 21 of the first semiconductor chip 20, it is possible to prevent voids from occurring in the bevel region due to adhesion of both edge regions of the carrier substrate C1 during a subsequent wafer-to-wafer bonding process of the first semiconductor chip 20 and the second semiconductor chip.

[0081] As shown in Figures 12 and 13, a first rear insulating film 26 is formed on the second surface 214 of the first substrate 21 as a second passivation film having a second bonding pad 27 electrically connected to the through electrode 24.

[0082] For example, after forming the first rear insulating film 26 on the second surface 214 of the first substrate 21, an opening exposing the through electrode 24 is formed in the first rear insulating film 26, and the second bonding pad 27 is formed by a plating process. The second bonding pad 27 is disposed on the exposed surface of the through electrode 24. The first rear insulating film 26 includes silicon oxide, carbon-doped silicon oxide, silicon carbonitride (SiCN), etc. Thus, the first and second bonding pads 23, 27 are electrically connected to each other by the through electrode 24.

[0083] As shown in Figures 14 and 15, the carrier substrate (C1) of Figure 12 on which the first semiconductor chip 20 is formed is attached onto a second wafer (W2) on which the second semiconductor chip 40 is formed (wafer to wafer hybrid bonding process).

[0084] In one embodiment of the present invention, the structure of Figure 12 can be flipped upside down and the carrier substrate (C1) can be bonded onto a second wafer (W2) such that the rear surface of the first semiconductor chip 20 faces the front surface of the second semiconductor chip 40 of the second wafer (W2).

[0085] When the carrier substrate (C1) and the second wafer (W2) are bonded together by wafer-to-wafer bonding, the first semiconductor chip 20 of the carrier substrate (C1) and the second semiconductor chip 40 of the second wafer (W2) are bonded together by hybrid bonding through a thermocompression bonding process, i.e., the second front insulating film 42 on the front surface of the second semiconductor chip 40, i.e., the first surface 412 of the second substrate 41, is directly bonded to the first rear insulating film 26 on the rear surface of the first semiconductor chip 20, i.e., the second surface 214 of the first substrate 21.

[0086] When the carrier substrate (C1) and the second wafer (W2) are bonded to each other by wafer-to-wafer bonding, no step is generated between the rear surface of the first substrate 21 of the first semiconductor chip 20 and the upper surface of the first gap fill film 30, thereby preventing voids from occurring between the first rear insulating film 26 of the first semiconductor chip 20 and the second front insulating film 42 of the second semiconductor chip 40. In addition, when the carrier substrate (C1) and the second wafer (W2) are bonded to each other by wafer-to-wafer bonding, no bevel step is generated between the second surface 14 of the silicon substrate 10 at the edge region of the carrier substrate (C1) and the rear surface of the first substrate 21 of the first semiconductor chip 20, thereby preventing voids from occurring between the edge region of the carrier substrate (C1) and the edge region of the second wafer (W2).

[0087] 15, the second semiconductor chip 40 includes a second substrate 41 and a second front insulating film 42 having a third bonding pad 43 provided on its outer surface. The second substrate 41 has a first surface 412 and a second surface 414 opposite to the first surface 412. A circuit pattern is formed on the first surface 412 of the second substrate 41.

[0088] The second front insulating film 42 is an interlayer insulating film and is formed on the first surface 412, i.e., the front surface, of the second substrate 41. The second front insulating film 42 includes a plurality of insulating layers 422, 424 and wiring 423 within the insulating layers. In addition, a third bonding pad 43 is provided on the outermost insulating layer of the second front insulating film 42.

[0089] For example, the second front insulating film 42 includes a metal wiring layer 422 and a third passivation film 424. The metal wiring layer 422 includes a plurality of wirings 423 therein. For example, the metal wiring layer 422 includes a metal wiring structure including a plurality of wirings 423 vertically stacked on the buffer film and the insulating film. The third bonding pad 43 is formed on the uppermost wiring of the plurality of wirings 423. For example, the wiring includes aluminum (Al), copper (Cu), tin (Sn), nickel (Ni), gold (Au), platinum (Pt), or an alloy thereof.

[0090] The third passivation film 424 is formed on the metal wiring layer 422 and exposes at least a portion of the third bonding pad 43. The third passivation film 424 includes a plurality of stacked insulating films. For example, the third passivation film 424b includes silicon oxide, silicon nitride, or silicon carbonitride. The third passivation film 424b has a single film or a multi-layer film structure.

[0091] A third bonding pad 43 is provided on the third passivation film 424. The third bonding pad 43 is exposed through the outer surface of the third passivation film 424. Although not shown in the drawings, an interlayer insulating film is provided on the first surface 412 of the second substrate 41 to cover the circuit pattern. The interlayer insulating film is formed to include, for example, silicon oxide or a low-k material. The interlayer insulating film includes an underlying wiring electrically connected to the circuit pattern. Thus, the circuit pattern is electrically connected to the third bonding pad 43 via the underlying wiring and the wiring.

[0092] The second semiconductor chip 40 is a second chiplet die (upper chiplet die). The second semiconductor chip 40 is a small building block or IP block that constitutes a processor chip. The second chiplet die can constitute one chip together with the lower semiconductor chip as the first chiplet die.

[0093] As shown in FIG. 16, the first surface 12 of the carrier substrate (C1) is partially removed so that the front surface of the first semiconductor chip 20 is exposed.

[0094] In one embodiment of the present invention, a grinding process is performed to partially remove the first surface 12 of the carrier substrate (C1). The first surface 12 of the carrier substrate (C1) is removed to expose the bottom surface of the recess (RC), thereby forming a cavity 16 penetrating the silicon substrate 10. A first substrate 21 and a first front insulating film 22 are disposed in the cavity 16 of the silicon substrate 10. The first front insulating film 22 of the first semiconductor chip 20 is exposed by the cavity 16. Thus, the first bonding pads 23 are exposed from the first surface 12 of the silicon substrate 10.

[0095] This allows the first semiconductor chip 20 to be placed within the cavity 16 of the silicon substrate 10, and the first gap fill film 30 to fill the gap between the outer surface of the first semiconductor chip 20 and the inner surface of the cavity 16.

[0096] As shown in FIGS. 17 and 18, conductive bumps 50 are formed on the first bonding pads 23 of the first semiconductor chip 20.

[0097] As shown in FIG. 17, a seed film and a photoresist film are formed on the first front insulating film 22, and a photoresist pattern (PL) having openings (OP) that expose bump regions is formed by an exposure process.

[0098] 18, the openings (OR) of the photoresist pattern (PL) are filled with a conductive material, and then the photoresist pattern is removed and a reflow process is performed to form the conductive bumps 50. Alternatively, the conductive bumps can be formed by a screen printing method, a vapor deposition method, etc.

[0099] For example, pillar bumps 52 are formed on the first bonding pads 23 of the first semiconductor chip 20 in a first plating step, and solder bumps 54 are formed on the pillar bumps 52 in a second plating step.

[0100] As shown in FIG. 19, the carrier substrate (C1) and the second wafer (W2) are cut along the cutting region (CR) to form a stacked semiconductor chip 200 (see FIG. 1) as a chiplet package including a first semiconductor chip (chiplet die) 20 and a second semiconductor chip 40 bonded to each other.

[0101] When the first carrier substrate (C1) is cut along the cutting region (CR), a portion (cutting region) of the second wafer (W2) is also removed, so that the outer surface of the second semiconductor chip 40 is located on the same plane as the outer surface of the silicon substrate 10.

[0102] Fig. 20 is a cross-sectional view showing a semiconductor package according to one embodiment of the present invention. Fig. 21 is a cross-sectional view showing an intermediate core die stack of the semiconductor package in Fig. 20. The semiconductor package is substantially the same as the semiconductor package described in Fig. 1 except for the configuration of the buffer die and the first semiconductor chip. Therefore, the same components are denoted by the same reference numerals, and repeated description of the same components will be omitted.

[0103] As shown in FIGS. 20 and 21 , a semiconductor packaging device 500 includes stacked semiconductor chips (dies). The semiconductor packaging device 500 includes a buffer die 60, an intermediate core die stack stacked on the buffer die 60, and a top core die (TD) stacked on the intermediate core die stack. The intermediate core die stack includes multiple die structures (CD1, CD2, CD3) stacked sequentially. Each of the multiple die structures (CD1, CD2, CD3) includes a support substrate 10a, 10b, 10c having a cavity 16a, 16b, 16c, a core die 20a, 20b, 20c disposed in the cavity 16a, 16b, 16c, and a first gap fill film 30a, 30b, 30c filling a gap between the inner wall of the cavity and the core die. The semiconductor packaging device 500 also includes a conductive bump 70 provided on the outer surface of the buffer die 60.

[0104] The intermediate core die stack includes a plurality of vertically stacked semiconductor chips (dies) 20a, 20b, and 20c. In this embodiment, the semiconductor chips (dies) 20a, 20b, and 20c are substantially identical or similar to one another. Therefore, identical or similar components are denoted by identical or similar reference numerals, and repeated description of identical components will be omitted.

[0105] In this embodiment, the semiconductor package device as a multi-chip package is shown to include four stacked semiconductor chips 20a, 20b, 20c, and 40 on the buffer die 60. However, this is not limited thereto, and for example, the semiconductor package may include eight, twelve, sixteen, or more stacked semiconductor chips on the buffer die 60.

[0106] Each of the semiconductor chips 20a, 20b, 20c, and 40 includes an integrated circuit chip completed through a semiconductor manufacturing process. Each semiconductor chip includes, for example, a memory chip or a logic chip. The semiconductor package device 500 includes a memory device. The memory device includes a high bandwidth memory (HBM) device.

[0107] 21 , the intermediate core die stack includes first, second, and third die structures (DS1, DS2, DS3) stacked in sequence. The first die structure (DS1) includes a support substrate 10a having a cavity 16a, a first core die 20a disposed in the cavity 16a, and a first gap fill filling film 30a that fills a gap between the inner wall of the cavity 16a and the first core die 20a. The second die structure (DS2) includes a support substrate 10b having a cavity 16b, a second core die 20b disposed in the cavity 16b, and a first gap fill filling film 30b that fills a gap between the inner wall of the cavity 16b and the second core die 20b. The third die structure (DS3) includes a support substrate 10c having a cavity 16c, a third core die 20c disposed in the cavity 16c, and a first gap fill film 30c that fills a gap between the inner wall of the cavity 16c and the third core die 20c. The first, second, and third die structures (DS1, DS2, DS3) are substantially the same as or similar to the first die structure (CD1) of FIG. 1. Therefore, the same or similar components are denoted by the same or similar reference numerals, and repeated description of the same components will be omitted.

[0108] In one embodiment of the present invention, the buffer die 60 includes a substrate 61, a front insulating film 62, a plurality of first bonding pads 63, a plurality of through electrodes 64, a rear insulating film 66, and a plurality of second bonding pads 67. The buffer die 60 also includes conductive bumps 70 as conductive connecting members provided on the first bonding pads 63. The buffer die 60 is mounted on a package substrate or an interposer via the conductive bumps 70. For example, the conductive bumps 70 include pillar bumps 72 on the first bonding pads 63 and solder bumps 74 on the pillar bumps 72.

[0109] In one embodiment of the present invention, first, second, and third die structures (CD1, CD2, CD3) are stacked sequentially on buffer die 60. A top die (TD) is stacked on the third die structure (CD3).

[0110] The first die structure (CD1) is bonded to a wafer including the buffer die 60 by hybrid bonding. The second bonding pad 67 of the buffer die 60 and the first bonding pad 23a of the first core die 20a are bonded to each other by copper-copper hybrid bonding. The front surface of the first core die 20a, i.e., the front insulating film 23a on the first surface 212a of the first substrate 21a, is directly bonded to the back insulating film 66 of the substrate 61 of the buffer die 60.

[0111] The second die structure (CD2) is on the first die structure (CD1) and bonded to each other by hybrid bonding. The second bonding pad 27a of the first core die 20a and the first bonding pad 23b of the second core die 20b are bonded to each other by copper-copper hybrid bonding (Cu-Cu hybrid bonding).

[0112] The first front insulating film 22b on the front surface of the second core die 20b is directly bonded to the first rear insulating film 26a on the rear surface of the first core die 20a. The outermost insulating layers of the first rear insulating film 26a and the first front insulating film 22b are in contact with each other, providing a bonding structure including an insulating material that provides excellent bonding strength. The first rear insulating film 26a and the first front insulating film 22b are bonded to each other while in contact with each other through a high-temperature annealing process. Here, the bonding structure can have even stronger bonding strength due to the covalent bond.

[0113] Similarly, the third die structure (CD3) is bonded to the second die structure (CD2) by hybrid bonding. The second bonding pad 27b of the second core die 20b and the first bonding pad 23c of the third core die 20c are bonded to each other by copper-copper hybrid bonding. The first front insulating film 22c on the front surface of the third core die 20c is directly bonded to the first back insulating film 26b on the back surface of the second core die 20b.

[0114] The top die (TD) is bonded to the third die structure (CD3) by hybrid bonding. The second front insulating film 42 of the top die (TD) and the first back insulating film 26c of the third core die 20c are directly bonded to each other. Then, the second bonding pad 27c of the third core die 20c and the third bonding pad 43 of the top die (TD) are bonded to each other by Cu-Cu hybrid bonding (pad to pad direct bonding).

[0115] A method for manufacturing the packaged semiconductor device of FIG. 20 will be described below.

[0116] 22 to 28 are cross-sectional views illustrating a method for manufacturing a semiconductor package according to an embodiment of the present invention. FIG. 22 and FIGS. 24 to 28 are cross-sectional views illustrating a method for manufacturing a semiconductor package according to an embodiment of the present invention. FIG. 23 is an enlarged cross-sectional view of part H in FIG. 22.

[0117] 22 and 23, by the same or similar process as that described with reference to FIGS. 4 to 16, a first carrier substrate (C1) on which the third core die 20c is formed is attached onto a second wafer (W2) on which the top core die 40 is formed, and by the same or similar process as that described with reference to FIGS. 4 to 13, a second carrier substrate (C2) on which the second core die 20b is formed is formed, and the second carrier substrate (C2) is attached onto the first carrier substrate (C1) (wafer-to-wafer). to wafer) hybrid bonding process).

[0118] In one embodiment of the present invention, the first semiconductor chip 20 and the second semiconductor chip 40 in FIG. 16 correspond to the third core die 20c and the top core die 40 in FIG. 22, respectively.

[0119] As shown in FIG. 22, the second carrier substrate (C2) is stacked so that the rear surface of the second core die 20b faces the front surface of the third core die 20c of the first carrier substrate (C1).

[0120] When the second carrier substrate (C2) and the first carrier substrate (C1) are bonded together by wafer-to-wafer bonding, the second core die 20b of the second carrier substrate (C2) and the third core die 20c of the first carrier substrate (C1) are bonded together by hybrid bonding through a thermocompression bonding process, that is, the first front insulating film 22c on the front surface of the third core die 20c, i.e., the first surface 212c of the first substrate 21c, can be directly bonded to the first rear insulating film 26b on the rear surface of the second core die 20b, i.e., the second surface 214b of the first substrate 21b.

[0121] When the second carrier substrate (C2) and the first carrier substrate (C1) are bonded to each other by wafer-to-wafer bonding, a step does not occur between the rear surface of the first substrate 21b of the second core die 20b and the upper surface of the first gap fill film 30b, thereby preventing voids from occurring between the first rear insulating film 26b of the second core die 20b and the first front insulating film 22c of the third core die 20c. Also, when the second carrier substrate (C2) and the first carrier substrate (C1) are bonded to each other by wafer-to-wafer bonding, a bevel step does not occur between the second surface 14b of the silicon substrate 10b at the edge region of the second carrier substrate (C2) and the rear surface of the first substrate 21b of the second core die 20b, thereby preventing voids from occurring between the edge region of the second carrier substrate (C2) and the edge region of the first carrier substrate (C1).

[0122] As shown in FIG. 24, the first surface 12b of the second carrier substrate (C2) is partially removed so as to expose the front surface of the second core die 20b.

[0123] In one embodiment of the present invention, a grinding process is performed to partially remove the first surface 12b of the second carrier substrate (C2). The first surface 12b of the second carrier substrate (C2) is removed to expose the bottom surface of the recess (RC2), thereby forming a cavity 16b penetrating the silicon substrate 10b. The first substrate 21b and the first front insulating film 22b are disposed in the cavity 16b of the silicon substrate 10b. The first front insulating film 22b of the second core die 20b is exposed by the cavity 16b. Thus, the first bonding pads 23b can be exposed from the first surface 12b of the silicon substrate 10b.

[0124] This allows the second core die 20b to be placed in the cavity 16b of the silicon substrate 10b, and the first gap fill film 30b to fill the gap between the outer surface of the second core die 20b and the inner surface of the cavity 16b.

[0125] As shown in FIG. 25, a third carrier substrate (C3) on which the first core die 20a is formed is formed by the same or similar steps as those described in FIGS. 4 to 13, and the third carrier substrate (C3) is attached onto the second carrier substrate (C2) (wafer-to-wafer). to wafer) hybrid bonding process).

[0126] In one embodiment of the present invention, the third carrier substrate (C3) is stacked such that the rear surface of the first core die 20a faces the front surface of the second core die 20b of the second carrier substrate (C2).

[0127] When the third carrier substrate (C3) and the second carrier substrate (C2) are bonded to each other by wafer-to-wafer bonding, the first core die 20 a of the third carrier substrate (C3) and the second core die 20 b of the second carrier substrate (C2) are bonded to each other by hybrid bonding through a thermocompression bonding process, that is, the first front insulating film 22 b on the front surface of the second core die 20 b, i.e., the first surface 212 b of the first substrate 21 b, can be directly bonded to the first rear insulating film 26 a on the rear surface of the first core die 20 a, i.e., the second surface 214 a of the first substrate 21 a.

[0128] When the third carrier substrate (C3) and the second carrier substrate (C2) are bonded to each other by wafer-to-wafer bonding, a step does not occur between the rear surface of the first substrate 21a of the first core die 20a and the upper surface of the first gap fill film 30a, thereby preventing voids from occurring between the first rear insulating film 26a of the first core die 20a and the first front insulating film 22b of the second core die 20b. Also, when the third carrier substrate (C3) and the second carrier substrate (C2) are bonded to each other by wafer-to-wafer bonding, a bevel step does not occur between the second surface 14a of the silicon substrate 10a in the edge region of the third carrier substrate (C3) and the rear surface of the first substrate 21a of the first core die 20a, thereby preventing voids from occurring between the edge region of the third carrier substrate (C3) and the edge region of the second carrier substrate (C2).

[0129] As shown in FIG. 26, the first surface 12a of the third carrier substrate (C3) is partially removed so as to expose the front surface of the first core die 20a.

[0130] In one embodiment of the present invention, a grinding process is performed to partially remove the first surface 12a of the third carrier substrate (C3). The first surface 12a of the third carrier substrate (C3) is removed to expose the bottom surface of the recess (RC3), thereby forming a cavity 16a penetrating the silicon substrate 10a. The first substrate 21a and the first front insulating film 22a are disposed in the cavity 16a of the silicon substrate 10a. The first front insulating film 22a of the first core die 20a is exposed by the cavity 16a. Thus, the first bonding pad 23a can be exposed from the first surface 12a of the silicon substrate 10a.

[0131] This allows the first core die 20a to be placed within the cavity 16a of the silicon substrate 10a, and the first gap fill film 30a to fill the gap between the outer surface of the first core die 20a and the inner surface of the cavity 16a.

[0132] As shown in FIG. 27, the first to third carrier substrates (C1, C2, C3) of FIG. 26 on which the first to third core dies 20a, 20b, 20c are formed are attached onto the second wafer (W2) on which the buffer die 60 is formed (wafer-to-wafer). to wafer) hybrid bonding process).

[0133] 26 is turned upside down, and a third carrier substrate (C3) is bonded onto the buffer wafer (BW) on which the buffer die 60 is formed, with the front surface of the first core die 20a facing the rear surface of the buffer die 60 of the buffer wafer (BW).

[0134] When the third carrier substrate (C2) and the buffer wafer (BW) are bonded together by wafer-to-wafer bonding, the first core die 20a of the third carrier substrate (C3) and the buffer die 60 of the buffer wafer (BW) are bonded together by hybrid bonding through a thermocompression bonding process. That is, the rear insulating film 66 on the rear surface of the buffer die 60, i.e., the rear surface of the substrate 61, is directly bonded to the front surface of the first core die 20a, i.e., the first front insulating film 22a on the first surface 212a of the first substrate 21a. The first bonding pad 23a of the first core die 20a and the second bonding pad 17 of the buffer die 60 are bonded together by copper-copper hybrid bonding.

[0135] As shown in FIG. 28, the buffer wafer (BW), the first to third carrier substrates (C1), and the second wafer (W2) are cut along the cutting region (CR) to form the semiconductor package 5100 of FIG. 20.

[0136] 29 is a cross-sectional view showing a semiconductor package according to an embodiment of the present invention, which includes the semiconductor package device in FIGS. 1 and 20, but the present invention is not limited thereto.

[0137] 29, the semiconductor package 100 includes a package substrate 110, a first semiconductor device 200, and a second semiconductor device 500. The semiconductor package 100 further includes first and second underfill members 250 and 550, and an encapsulating member 600. The first semiconductor device 200 is substantially the same as or similar to the semiconductor package device described in FIG. 1. The second semiconductor device 500 is substantially the same as or similar to the semiconductor package device described in FIG. 20. Therefore, the same reference numerals are used to refer to the same components, and repeated description of the same components will be omitted.

[0138] In one embodiment of the present invention, the semiconductor package 100 is provided as part of a memory module having a 2.5D package structure, in which the package substrate 110 is an interposer for electrically connecting the first and second semiconductor devices 200, 500 to each other.

[0139] In one embodiment of the present invention, the first semiconductor device 200 includes a logic device, and the second semiconductor device 500 includes a memory device. The logic device is, for example, an application specific semiconductor (ASIC) chip including a graphics processing unit (GPU), a central processing unit (CPU), a microprocessor, a microcontroller, an application processor (AP), a digital signal processing core, etc. The memory device includes, for example, DRAM, flash, PRAM, ReRAM, FeRAM, or MRAM.

[0140] In one embodiment of the present invention, the package substrate 110 has opposing top and bottom surfaces and is, for example, a printed circuit board (PCB), a silicon interposer, or a rewiring interposer. The printed circuit board is a multi-layer circuit board having various circuit patterns therein.

[0141] The first semiconductor device 200 is mounted on a package substrate 110. The first semiconductor device 200 is mounted on the upper surface of the package substrate 110 by flip chip bonding. The first semiconductor device 200 is arranged so that the first front insulating film 22 on which the first bonding pads 23 are formed faces the package substrate 110. The first bonding pads 23 of the first semiconductor device 200 are electrically connected to substrate pads of the package substrate 110 by conductive bumps 50.

[0142] The second semiconductor device 500 is disposed on the package substrate 110 and spaced apart in the horizontal direction from the first semiconductor device 200. The second semiconductor device 500 is mounted on the upper surface of the package substrate 110 via conductive bumps 70.

[0143] The first semiconductor device 200 and the second semiconductor device 500 are electrically connected to each other by wiring within the package substrate 110. The package substrate 110 can provide high-density interconnection between the first and second semiconductor devices 200, 500.

[0144] In one embodiment of the present invention, the first and second underfill materials 250, 550 may include a material with relatively high fluidity so as to effectively fill small spaces between the first and second semiconductor devices 200, 500 and the package substrate 110. For example, the first and second underfill materials 250, 550 may include an adhesive containing an epoxy material.

[0145] The encapsulating member 600 is provided on the upper surface of the package substrate 110 so as to cover the first and second semiconductor devices 200 and 500. For example, the encapsulating member 600 includes an epoxy mold compound (EMC). The encapsulating member 600 includes UV resin, polyurethane resin, silicone resin, silica filler, etc.

[0146] Although not shown in the drawings, a heat slug covers the first and second semiconductor devices 200, 500 on the package substrate 110 so as to be in thermal contact with them. In this case, the encapsulation member 600 can be omitted. Alternatively, the encapsulation member 600 can expose the top surfaces of the first and second semiconductor devices 200, 500, and a heat dissipation member is disposed on the top surfaces of the first and second semiconductor package devices 200, 500 exposed by the encapsulation member 600. The heat dissipation member includes, for example, a thermal interface material (TIM). The heat slug is in thermal contact with the first and second semiconductor devices 200, 500 via the heat dissipation member.

[0147] The semiconductor device includes semiconductor elements such as logic elements and memory elements, such as logic elements like central processing units (CPUs, MPUs) and application processors (APs), volatile memory devices like SRAM devices and DRAM devices, and non-volatile memory devices like flash memory devices, PRAM devices, MRAM devices, and RRAM devices.

[0148] Although the present invention has been described above with reference to embodiments thereof, those skilled in the art will appreciate that various modifications and variations can be made to the present invention without departing from the spirit and scope of the invention as set forth in the claims below. [Explanation of symbols]

[0149] 10: Support substrate 16, 16a, 16b, 16c: Cavity 20, 20a, 20b, 20c: First semiconductor chip, core die 21, 21a, 21b, 21c: first substrate 22, 22a, 22b, 22c: first front insulating film 23, 23a, 23b, 23c: first bonding pads 24, 24a, 24b, 24c: Through electrode 26, 26a, 26b, 26c: first rear insulating film 27, 27a, 27b, 27c: Second bonding pads 30a: First gap fill film 40: Second semiconductor chip, top die 41: Second board 42: Second front insulating film 43: Third bonding pad 50, 70: Conductive bumps 52, 72: Pillar bump 54, 74: Solder bumps 100: Semiconductor packages 200, 500: Semiconductor package device, first semiconductor device, second semiconductor device 250, 550: Underfill material 600: Sealing member

Claims

1. a first die structure including a support substrate having a cavity, a first semiconductor chip disposed in the cavity, and a first gap fill film filling a gap between an inner wall of the cavity and the first semiconductor chip; a second die structure stacked on the first die structure and including a second semiconductor chip electrically connected to the first semiconductor chip; the first semiconductor chip includes a first substrate, a first front insulating film formed on a first surface of the first substrate and having a first bonding pad provided thereon, and a first rear insulating film formed on a second surface of the first substrate opposite to the first surface and having a second bonding pad provided thereon; the second semiconductor chip includes a second substrate and a second front insulating film formed on a first surface of the second substrate and having a third bonding pad provided thereon; The semiconductor package device, wherein the second bonding pad and the third bonding pad are directly bonded to each other.

2. 2. The semiconductor package device according to claim 1, wherein the first rear insulating film and the second front insulating film are directly bonded to each other.

3. 2. The semiconductor package device of claim 1, wherein the support substrate comprises a silicon substrate.

4. 2. The semiconductor package of claim 1, wherein the first gap-fill filling film comprises silicon dioxide.

5. 2. The semiconductor package of claim 1, wherein the first rear insulating film extends laterally from the second surface of the first substrate to cover the first gap-fill filling film.

6. 2. The packaged semiconductor device according to claim 1, wherein an outer surface of the second semiconductor chip is located on the same plane as an outer surface of the support substrate.

7. 2. The semiconductor package device of claim 1, wherein the second surface of the first substrate of the first semiconductor chip is flush with an upper surface of the first gap-fill filling film.

8. 2. The packaged semiconductor device according to claim 1, wherein the second surface of the first substrate of the first semiconductor chip is located on the same plane as an upper surface of the support substrate.

9. 2. The semiconductor package device of claim 1, wherein the support substrate has a first coefficient of thermal expansion, and the first gap-fill filling film has a second coefficient of thermal expansion greater than the first coefficient of thermal expansion.

10. 2. The semiconductor package device according to claim 1, further comprising conductive bumps respectively provided on the first bonding pads.

11. a first die structure including: a support substrate having a first surface and a second surface opposite to the first surface, the support substrate having a cavity extending from the first surface to the second surface; a first semiconductor chip disposed in the cavity; and a first gap fill film filling a gap between an inner wall of the cavity and the first semiconductor chip; a second die structure stacked on the first die structure and including a second semiconductor chip electrically connected to the first semiconductor chip; 2. A semiconductor package device, wherein an outer surface of the support substrate and an outer surface of the second semiconductor chip are located on the same plane.

12. the first semiconductor chip includes a first substrate, a plurality of through electrodes penetrating the first substrate, first bonding pads provided on a first surface of the first substrate and electrically connected to the plurality of through electrodes, and second bonding pads provided on a second surface of the first substrate opposite to the first surface and electrically connected to the plurality of through electrodes; the second semiconductor chip includes a second substrate and a third bonding pad provided on a first surface of the second substrate; 12. The semiconductor package device of claim 11, wherein the first bonding pad and the second bonding pad are directly bonded to each other.

13. the first semiconductor chip further includes a first rear insulating film provided on the second surface of the first substrate and exposing at least a portion of the second bonding pad; the second semiconductor chip further includes a second front insulating film provided on the first surface of the second substrate and exposing at least a portion of the third bonding pad; 13. The semiconductor package device of claim 12, wherein the first rear insulating film and the second front insulating film are directly bonded to each other.

14. 14. The semiconductor package of claim 13, wherein the first rear insulating film extends laterally from the second surface of the first substrate to cover the first gap-fill filling film.

15. 14. The semiconductor package of claim 13, wherein the second surface of the first substrate of the first semiconductor chip is flush with an upper surface of the first gap-fill filling film.

16. 14. The packaged semiconductor device according to claim 13, wherein the second surface of the first substrate of the first semiconductor chip is located on the same plane as an upper surface of the support substrate.

17. The semiconductor package device of claim 11 , wherein the support substrate comprises a silicon substrate.

18. 12. The semiconductor package of claim 11, wherein the first gap-fill filling film comprises silicon dioxide.

19. 12. The semiconductor package device of claim 11, wherein the support substrate has a first coefficient of thermal expansion, and the first gap-fill filling film has a second coefficient of thermal expansion greater than the first coefficient of thermal expansion.

20. a buffer die; a plurality of die structures stacked in sequence on the buffer die; a top core die stacked on a top die structure among the plurality of die structures, Each of the plurality of die structures comprises: a support substrate having a cavity; a core die disposed within the cavity; a first gap fill film that fills a gap between the inner wall of the cavity and the core die; 2. A semiconductor package device, wherein an outer surface of the support substrate of the top die structure and an outer surface of the top core die are located on the same plane.

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