Current detector

Abstract

To provide a current detector that can prevent current detection in two detection circuits from becoming impossible even when a short circuit occurs between adjacent input ports.SOLUTION: According to the current detector of the present invention, in one aspect, the upstream-side potential and the downstream-side potential of a shunt resistor 7 are input to respective input ports SP1, SN1, SP2, and SN2, the adjacent input ports, namely the input port SN1 connected to the inverting input terminal of a first detection circuit 4A and the input port SP2 connected to the non-inverting input terminal of a second detection circuit 4B, being set to the same potential.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a current detection device. [Background technology]

[0002] The control device for vehicle-mounted equipment in Patent Document 1 has a CPU that calculates a command signal to control a drive unit of the vehicle-mounted equipment, a state quantity detection unit that detects a state quantity of the vehicle-mounted equipment, an amplitude change unit that is provided between the CPU and the state quantity detection unit and changes the amplitude of a first signal that is an analog signal of the state quantity detected by the state quantity detection unit, and an abnormality judgment unit that is provided in the CPU and performs a comparison judgment to determine whether or not there is an abnormality in the device by comparing the first signal that has passed through the amplitude change unit with a second signal that is an analog signal of the state quantity detected by the state quantity detection unit. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2018-095221 Summary of the Invention [Problem to be solved by the invention]

[0004] Incidentally, when detecting the current flowing through the inverter circuit, the reliability of current detection can be improved by detecting the potential difference across the shunt resistor using a plurality of detection circuits (differential amplifiers). Here, when an IC (Integrated Circuit) equipped with multiple detection circuits is used, a pair of input ports (IC pins) of each current detection circuit are arranged side by side, and the input port of the first detection circuit to which the downstream potential of the shunt resistor is input and the input port of the second detection circuit to which the upstream potential of the shunt resistor is input may be adjacent to each other. In the case of such an IC, if a short circuit occurs between the input port of the adjacent first detection circuit and the input port of the second detection circuit, the first detection circuit and the second detection circuit will be unable to detect current.

[0005] Therefore, an object of the present invention is to provide a current detection device that can prevent current detection by two detection circuits from becoming impossible even if a short circuit occurs between adjacent input ports. [Means for solving the problem]

[0006] In one aspect of the current detection device of the present invention, the upstream potential and downstream potential of the shunt resistor are input to each input port so that the input port of the adjacent first detection circuit and the input port of the adjacent second detection circuit are at the same potential. [Effects of the Invention]

[0007] According to the present invention, even if a short circuit occurs between adjacent input ports, it is possible to prevent the two detection circuits from becoming unable to detect current. [Brief explanation of the drawings]

[0008] [Figure 1] 1 is a configuration diagram showing a first embodiment of a motor control system. [Figure 2] 10 is a flowchart showing an abnormality detection process of the detection circuit in the first embodiment. [Figure 3] 10 is a flowchart illustrating an offset correction process. [Figure 4] FIG. 10 is a diagram illustrating a voltage control state. [Figure 5] FIG. 10 is a configuration diagram showing a second embodiment of the motor control system. [Figure 6] 10 is a flowchart showing an abnormality detection process of the detection circuit in the second mode. [Figure 7] FIG. 10 is a configuration diagram showing a third embodiment of the motor control system. DETAILED DESCRIPTION OF THE INVENTION

[0009] Hereinafter, an embodiment of a current detection device according to the present invention will be described with reference to the drawings. FIG. 1 is a configuration diagram showing a motor control system 1 including a current detection device according to the present invention. The motor control system 1 is applied to the control of a motor that generates a steering force in an electric power steering device mounted on a vehicle, for example.

[0010] The motor control system 1 includes a motor 2, an inverter circuit 3, a pre-driver IC 4, and a CPU (Central Processing Unit) 5. The motor 2 is, for example, a three-phase brushless motor, and has a three-phase winding set consisting of a U-phase coil, a V-phase coil, and a W-phase coil.

[0011] The inverter circuit 3 is a three-phase bridge circuit made up of six switching elements 3a-3f, and converts the DC current of the battery 6 as a power source into AC current, and increases or decreases the frequency of the power source supplied to the motor 2. Each of the switching elements 3a-3f of the inverter circuit 3 is turned on and off in response to a PWM (Pulse Width Modulation) signal, in other words, a gate signal, output by the pre-driver IC 4.

[0012] A shunt resistor 7 for detecting a DC bus current of the inverter circuit 3 is connected in series on the ground GND side of the inverter circuit 3, more specifically, between the inverter circuit 3 and the ground GND. That is, the current detection device in the system of FIG. 1 is a low-side current detection device in which the shunt resistor 7 is connected in series to the ground side of the inverter circuit 3.

[0013] The pre-driver IC4 includes a first detection circuit 4A and a second detection circuit 4B as detection circuits that detect the DC bus current of the inverter circuit 3 by detecting the potential difference across the shunt resistor . That is, the current detection device that detects the DC bus current of the inverter circuit 3 includes the shunt resistor 7, the first detection circuit 4A, and the second detection circuit 4B.

[0014] The detection signals of the DC bus current outputted by the first detection circuit 4A and the second detection circuit 4B are taken into the CPU 5 as a motor control unit via filter circuits 8A and 8B. The CPU 5 obtains the current of each phase of the motor 2 from the detection signal of the DC bus current of the inverter circuit 3.

[0015] Then, the CPU 5 compares the current of each phase with the command current, executes feedback control to perform correction operations so as to bring the current of each phase closer to the command current, generates switch timing signals for the switching elements 3a-3f of the inverter circuit 3, and outputs the generated switch timing signals to the pre-driver IC 4. The pre-driver IC 4 generates a PWM signal based on the switch timing signal, and supplies the generated PWM signal to the switching elements 3 a to 3 f of the inverter circuit 3 .

[0016] The first detection circuit 4A includes a voltage follower 41A and a differential amplifier circuit 42A. Similarly, the second detection circuit 4B includes a voltage follower 41B and a differential amplifier circuit 42B. A reference voltage VREF is input to the non-inverting input terminals of the voltage followers 41A and 41B, the output terminal of the voltage follower 41A is connected to the non-inverting input terminal (+ terminal) of the differential amplifier circuit 42A, and the output terminal of the voltage follower 41B is connected to the non-inverting input terminal (+ terminal) of the differential amplifier circuit 42A.

[0017] The pre-driver IC4 also has input ports SP1 and SN1 respectively connected to a pair of input terminals of the differential amplifier circuit 42A, and input ports SP2 and SN2 respectively connected to a pair of input terminals of the differential amplifier circuit 42B. Specifically, the non-inverting input terminal (+ terminal) of the differential amplifier circuit 42A is connected to the input port SP1, and the inverting input terminal (- terminal) of the differential amplifier circuit 42A is connected to the input port SN1. The non-inverting input terminal (+ terminal) of the differential amplifier circuit 42B is connected to the input port SP2, and the inverting input terminal (- terminal) of the differential amplifier circuit 42B is connected to the input port SN2.

[0018] Here, the pair of input ports SP1, SN1 of the differential amplifier circuit 42A and the pair of input ports SP2, SN2 of the differential amplifier circuit 42B are formed as IC pins protruding from the IC body. The input ports SP1, SN1 and the input ports SP2, SN2 are arranged in parallel in the order SP1, SN1, SP2, SN2 at one side end of the IC body.

[0019] That is, the input ports are arranged in the following order: the non-inverting input port of the first detection circuit 4A, the inverting input port of the first detection circuit 4A, the non-inverting input port of the second detection circuit 4B, and the inverting input port of the second detection circuit 4B. Therefore, the input port SN1, which is the inverting input port of the first detection circuit 4A, and the input port SP2, which is the non-inverting input port of the second detection circuit 4B, are adjacent to each other.

[0020] An upstream input line UL for inputting the upstream potential of the shunt resistor 7 is branch-connected to an input port SP1, which is a non-inverting input port of the first detection circuit 4A. Furthermore, a downstream input line DL that inputs the downstream side potential (ground potential) of the shunt resistor 7 is branched and connected to the input port SN1 that is the inverting input port of the first detection circuit 4A.

[0021] An upstream input line UL for inputting the upstream potential of the shunt resistor 7 is branch-connected to an input port SN2 which is an inverting input port of the second detection circuit 4B. Furthermore, a downstream input line DL that inputs the downstream potential (ground potential) of the shunt resistor 7 is branched and connected to an input port SP2 that is a non-inverting input port of the second detection circuit 4B.

[0022] In other words, the upstream potential of the shunt resistor 7 is input to the input port SP1, the downstream potential of the shunt resistor 7 is input to the input port SN1, the downstream potential of the shunt resistor 7 is input to the input port SP2, and the upstream potential of the shunt resistor 7 is input to the input port SN2. Here, the input port SN1 (inverting input port) of the first detection circuit 4A and the input port SP2 (non-inverting input port) of the second detection circuit 4B are adjacent input ports, and the downstream potential of the shunt resistor 7 is input to both the input port SN1 and the input port SP2. In other words, the upstream input line UL and downstream input line DL are connected to the respective input ports so that the adjacent input port SN1 and input port SP2 are at the same potential.

[0023] As described above, since the input port SN1 of the first detection circuit 4A and the input port SP2 of the second detection circuit 4B are adjacent to each other, there is a possibility that a short circuit may occur between the input port SN1 and the input port SP2. However, since both input port SN1 and input port SP2 are input with the downstream potential (ground potential) of shunt resistor 7 and are at the same potential, even if a short circuit occurs between these input ports, it does not affect the outputs of the first detection circuit 4A and the second detection circuit 4B, and the current detection operation by the first detection circuit 4A and the second detection circuit 4B can continue normally. Therefore, the reliability and safety of the motor control system 1 that controls the motor 2 based on the current detection results by the first detection circuit 4A and the second detection circuit 4B is improved, and a reduction in the failure rate can be expected.

[0024] Moreover, the input lines connected to the input ports SP2 and SN2 are inverted relative to the input ports SP1 and SN1, so that the input ports SN1 and SP2 are at the same potential. Therefore, without changing the circuit configuration of the pre-driver IC4, it is possible to prevent a short circuit between adjacent input ports from causing the first detection circuit 4A and the second detection circuit 4B to be unable to detect current, and it is possible to prevent an increase in system costs due to changes to the pre-driver IC4.

[0025] Furthermore, when the downstream potential of the shunt resistor 7 is input to the input port SN1 and the upstream potential of the shunt resistor 7 is input to the input port SP2, even if a short circuit occurs between the input port SN1 and the input port SP2 and the first detection circuit 4A and the second detection circuit 4B are unable to detect current normally, the current detection values ​​of both will be at the same level, and the comparison process of the current detection values ​​will not be able to detect an abnormality in the current detection. In contrast, if the input ports SN1 and SP2 are at the same potential, the first detection circuit 4A and the second detection circuit 4B can detect the current normally even if a short circuit occurs between the input ports SN1 and SP2, and therefore the abnormality detection function by comparing the current detection values ​​can be maintained.

[0026] The flowchart in FIG. 2 shows the flow of the current detection diagnostic process executed by the CPU 5. The CPU 5 compares the current detection value by the first detection circuit 4A with the current detection value by the second detection circuit 4B to diagnose whether the current detection is normal or abnormal.

[0027] In step S101, the CPU 5 determines whether the current detection abnormality confirmation flag Fcde is 1 (High) indicating that an abnormality is confirmed, or 0 (Low) indicating that an abnormality is not confirmed. If the abnormality confirmation flag Fcde is 1 (High) and the current detection is in an abnormality confirmation state, the CPU 5 proceeds to step S102 and executes a fail-safe to operate the motor control system 1 on the safe side.

[0028] On the other hand, if the abnormality determination flag Fcde is 0 (Low), the CPU 5 proceeds to step S103 and subsequent steps to perform an abnormality diagnosis of the current detection. In step S103, the CPU 5 takes in the current Im1 (the DC bus current of the inverter circuit 3) detected based on the output of the first detection circuit 4A. In addition, in step S104, the CPU 5 takes in the current Im2 (the DC bus current of the inverter circuit 3) detected based on the output of the second detection circuit 4B.

[0029] Then, in step S105, the CPU 5 multiplies the current Im2 acquired in step S104 by −1 to invert the sign of the current Im2. This is because the input of the differential amplifier circuit 42B of the second detection circuit 4B is opposite to the input of the differential amplifier circuit 42A of the first detection circuit 4A, and the positive and negative signs of the current Im2 detected by the second detection circuit 4B are opposite to the positive and negative signs of the current Im1 detected by the first detection circuit 4A. That is, the CPU 5 multiplies the current Im2 by −1 to make the sign of the current Im2 the same as that of the current Im1.

[0030] Next, in step S106, the CPU 5 determines whether or not the absolute value of the deviation between the current Im1 and the current Im2 obtained by inverting the polarity of the current Im1 is less than the current threshold Ith. Here, if the absolute value of the deviation between the current Im1 and the current Im2 with its positive and negative polarities reversed is less than the current threshold value Ith, that is, if the current detection value by the first detection circuit 4A and the current detection value by the second detection circuit 4B are similar, the CPU 5 determines that the current detection by the first detection circuit 4A and the second detection circuit 4B is normal, and ends this routine while keeping the abnormality confirmation flag Fcde at 0 (Low).

[0031] On the other hand, if the absolute value of the deviation between the current Im1 and the current Im2 with its polarity reversed is greater than or equal to the current threshold Ith, that is, if the current detection value by the first detection circuit 4A and the current detection value by the second detection circuit 4B deviate by a predetermined amount or more, the CPU 5 determines that at least one of the first detection circuit 4A and the second detection circuit 4B is abnormal, and proceeds to step S107. In step S107, the CPU 5 sets the abnormality determination flag Fcde to 1 (High) to transition the motor control system 1 to a fail-safe state.

[0032] Here, assume that, in the adjacent input ports SN1 and SP2 shown in Figure 1, the downstream potential of the shunt resistor 7 is input to the input port SN1, and the upstream potential of the shunt resistor 7 is input to the input port SP2. In this case, if a short circuit occurs between the input port SN1 and the input port SP2, the current detection value by the first detection circuit 4A and the current detection value by the second detection circuit 4B will both be abnormal values. Furthermore, since the current detection value by the first detection circuit 4A and the current detection value by the second detection circuit 4B are both abnormal values, the CPU 5 is unable to detect the current detection abnormality in the diagnostic processing shown in the flowchart of Figure 2, and is unable to transition to fail-safe based on the abnormality detection.

[0033] In contrast, if the input ports SN1 and SP2 are set to the same potential, even if a short circuit occurs between the input ports SN1 and SP2, it will not affect the current detection and normal current detection can continue. Even if a short circuit occurs between the input port SN1 and the input port SP2, the CPU 5 can determine that the condition is normal in the diagnostic process shown in the flowchart of Figure 2, and can normally perform motor control based on the detected currents of the first detection circuit 4A and the second detection circuit 4B.

[0034] Furthermore, since the output of the second detection circuit 4B is opposite in sign to the output of the first detection circuit 4A, the CPU 5 can correct the offset error of the current detection value by adding the output of the first detection circuit 4A and the output of the second detection circuit 4B together. FIG. 3 is a flowchart showing the flow of the offset error correction process executed by the CPU 5.

[0035] In step S201, the CPU 5 acquires the output voltage value Vcs1 of the differential amplifier circuit 42A of the first detection circuit 4A, and in the next step S202, acquires the output voltage value Vcs2 of the differential amplifier circuit 42B of the second detection circuit 4B. Then, in step S203, the CPU 5 calculates the average value of the output voltage value Vcs1 and the output voltage value Vcs2 as the output voltage value Voc in which the offset error has been corrected. Voc=(Vcs1+Vcs2) / 2

[0036] FIG. 4 is a diagram illustrating the correlation between the output voltage value Vcs1 and the output voltage value Vcs2 when an offset error occurs. Below, we will explain with reference to FIG. 4 how the output voltage value Voc becomes an offset-corrected voltage value. In the example of Figure 4, the offset error is V offset and the offset error V offset If the true value in the absence of Vcs2 is A, the output voltage Vcs2 is Vcs2 = AV offset " and "V offset =A-Vcs2".

[0037] Similarly, the output voltage Vcs1 is calculated as follows: Vcs1=A+V offset " and "A=Vcs1-V offset " Here, "V offset =A-Vcs2", so A=Vcs1-V offset " can be rewritten as "A=Vcs1-(A-Vcs2)", which becomes "2A=Vcs1+Vcs2", and the true value A can be expressed as "A=(Vcs1+Vcs2) / 2". That is, the output voltage value Voc calculated as "Voc=(Vcs1+Vcs2) / 2" is the true value A with the offset error corrected.

[0038] In the embodiment shown in FIG. 1, the pre-driver IC 4 has two detection circuits 4A and 4B, but even if the pre-driver IC 4 has three detection circuits 4A, 4B, and 4C, the countermeasures against short circuits between adjacent input ports can be applied. FIG. 5 is a system diagram showing a motor control system 1 in which a pre-driver IC 4 includes three detection circuits 4A, 4B, and 4C, that is, a second embodiment of the motor control system 1. In FIG. In FIG. 5, the same elements as those in FIG. 1 are denoted by the same reference numerals, and detailed explanations thereof will be omitted.

[0039] The pre-driver IC 4 of FIG. 5 includes a third detection circuit 4C in addition to a first detection circuit 4A and a second detection circuit 4B. The third detection circuit 4C, like the first detection circuit 4A and the second detection circuit 4B, has a voltage follower 41C and a differential amplifier circuit 42C, and the detection signal of the DC bus current output by the third detection circuit 4C is acquired by the CPU 5 via the filter circuit 8C.

[0040] The non-inverting input terminal (+ terminal) of the differential amplifier circuit 42C of the third detection circuit 4C is connected to the input port SP3, and the inverting input terminal (- terminal) of the differential amplifier circuit 42C is connected to the input port SN3. The input ports SP1, SN1, SP2, SN2, SP3, and SN3 of the detection circuits 4A, 4B, and 4C are arranged in this order at one side end of the IC body.

[0041] That is, the input port SN1 (inverting input port) of the first detection circuit 4A and the input port SP2 (non-inverting input port) of the second detection circuit 4B are adjacent to each other, and the port SN2 (inverting input port) of the second detection circuit 4B and the input port SP3 (non-inverting input port) of the third detection circuit 4C are adjacent to each other. Here, an upstream input line UL for inputting an upstream potential of the shunt resistor 7 is branch-connected to the input ports SP1, SN2, and SP3. Further, a downstream input line DL for inputting a downstream side potential of the shunt resistor 7 is branch-connected to the input ports SN1, SP2, and SN3.

[0042] As a result, the downstream potential (ground potential) of the shunt resistor 7 is input to both the input port SN1 of the first detection circuit 4A and the input port SP2 of the second detection circuit 4B, which are adjacent to each other, and the two ports are set to the same potential. Moreover, the upstream potential of the shunt resistor 7 is input to the input port SN2 of the second detection circuit 4B and the input port SP3 of the third detection circuit 4C, which are adjacent to each other, and so the input port SN2 and the input port SP3 are at the same potential.

[0043] Therefore, even if a short circuit occurs between the input port SN1 of the first detection circuit 4A and the input port SP2 of the second detection circuit 4B, current detection by the first detection circuit 4A and the second detection circuit 4B continues normally. Furthermore, even if a short circuit occurs between the input port SN2 of the second detection circuit 4B and the input port SP3 of the third detection circuit 4C, the current detection by the second detection circuit 4B and the third detection circuit 4C continues normally.

[0044] Furthermore, in the system of Figure 5, the input to the central input ports SP2 and SN2 is inverted relative to the input to the input ports SP1 and SN1 and input ports SP3 and SN3, so that the input ports SN1 and SP2 are at the same potential, and the input ports SN2 and SP3 are at the same potential. Therefore, without changing the circuit of the pre-driver IC4, it is possible to prevent a short circuit between adjacent input ports from causing current detection by the first detection circuit 4A and the second detection circuit 4B, or current detection by the second detection circuit 4B and the third detection circuit 4C, to become impossible.

[0045] Furthermore, the CPU 5 can compare the detection results of the first detection circuit 4A, the second detection circuit 4B, and the third detection circuit 4C with each other to identify the normal current detection value by majority vote, and continue motor control based on the normal current detection value. FIG. 6 is a flowchart showing the flow of the current detection diagnostic process executed by the CPU 5.

[0046] In step S301, the CPU 5 determines whether the current detection abnormality confirmation flag Fcde is 1 (High) indicating that an abnormality is confirmed, or 0 (Low) indicating that an abnormality is not confirmed. If the abnormality confirmation flag Fcde is 1 (High) and the current detection is in an abnormality confirmation state, the CPU 5 proceeds to step S302 and executes a fail-safe to operate the motor control system 1 on the safe side.

[0047] On the other hand, if the abnormality determination flag Fcde is 0 (Low), the CPU 5 proceeds to step S303 and subsequent steps to perform an abnormality diagnosis of the current detection. In step S303, the CPU 5 takes in the current Im1 detected based on the output of the first detection circuit 4A.

[0048] In addition, in step S304, the CPU 5 takes in the current Im2 detected based on the output of the second detection circuit 4B. Furthermore, in step S305, the CPU 5 takes in the current Im3 detected based on the output of the third detection circuit 4C.

[0049] Next, in step S306, the CPU 5 multiplies the current Im2 acquired in step S304 by −1 to invert the sign of the current Im2. This is because the inputs of the differential amplifier circuit 42B of the second detection circuit 4B are opposite to the inputs of the differential amplifier circuit 42A of the first detection circuit 4A and the differential amplifier circuit 42C of the third detection circuit 4C, and the positive and negative signs of the current Im2 detected by the second detection circuit 4B are opposite to the positive and negative signs of the current Im1 detected by the first detection circuit 4A and the current Im3 detected by the third detection circuit 4C. Therefore, the CPU 5 multiplies the current Im2 by −1 to make the sign of the current Im2 the same as the signs of the currents Im1 and Im3.

[0050] Then, in step S307, the CPU 5 determines whether or not the absolute value of the deviation between the current Im1 and the current Im2 obtained by inverting the polarity of the current Im1 is less than the current threshold Ith. Here, if the absolute value of the deviation between the current Im1 and the current Im2 with its positive and negative polarities reversed is less than the current threshold Ith, that is, if the current detection value by the first detection circuit 4A and the current detection value by the second detection circuit 4B are similar, the CPU 5 proceeds to step S308.

[0051] In step S308, the CPU 5 determines that the current detection by at least the first detection circuit 4A and the second detection circuit 4B is normal, and then ends this routine while keeping the abnormality determination flag Fcde at 0 (Low). On the other hand, if the absolute value of the deviation between the current Im1 and the current Im2 with its polarity reversed is greater than or equal to the current threshold Ith, that is, if the current detection value by the first detection circuit 4A and the current detection value by the second detection circuit 4B deviate by a predetermined amount or more, the CPU 5 determines that at least one of the first detection circuit 4A and the second detection circuit 4B is abnormal, and proceeds to step S309.

[0052] In step S309, the CPU 5 determines whether or not the absolute value of the deviation between the current Im2, the polarity of which is reversed, and the current Im3 is less than the current threshold Ith. Here, if the absolute value of the deviation between the current Im2 with its sign reversed and the current Im3 is less than the current threshold Ith, that is, if the current detection value by the second detection circuit 4B and the current detection value by the third detection circuit 4C are similar, the CPU 5 proceeds to step S310.

[0053] In step S310, the CPU 5 determines that the first detection circuit 4A is abnormal, but that the current detection by the second detection circuit 4B and the third detection circuit 4C is normal, and then ends this routine while keeping the abnormality confirmation flag Fcde at 0 (Low). On the other hand, if the absolute value of the deviation between the current Im2 with its sign reversed and the current Im3 is greater than or equal to the current threshold Ith, that is, if the current detection value by the second detection circuit 4B and the current detection value by the third detection circuit 4C deviate by a predetermined amount or more, the CPU 5 determines that at least the second detection circuit 4B is abnormal and proceeds to step S311.

[0054] In step S311, the CPU 5 determines whether or not the absolute value of the deviation between the current Im1 and the current Im3 is less than the current threshold Ith. Here, if the absolute value of the deviation between the current Im1 and the current Im3 is less than the current threshold Ith, that is, if the current detection value by the first detection circuit 4A and the current detection value by the third detection circuit 4C are close to each other, the CPU 5 proceeds to step S312.

[0055] In step S312, the CPU 5 determines that although the second detection circuit 4B is abnormal, the current detection by the first detection circuit 4A and the third detection circuit 4C is normal, and then ends this routine while keeping the abnormality confirmation flag Fcde at 0 (Low). On the other hand, if the absolute value of the deviation between current Im1 and current Im3 is greater than or equal to current threshold value Ith, that is, if the current detection value by the first detection circuit 4A and the current detection value by the third detection circuit 4C deviate by a predetermined amount or more, CPU 5 determines that an abnormality has occurred in at least two of the first detection circuit 4A, the second detection circuit 4B, and the third detection circuit 4C, and proceeds to step S313. In step S313, the CPU 5 sets the abnormality determination flag Fcde to 1 (High) to transition the system to a fail-safe state.

[0056] Here, even if a short circuit occurs between the input port SN1 of the first detection circuit 4A and the input port SP2 of the second detection circuit 4B, or between the input port SN2 of the second detection circuit 4B and the input port SP3 of the third detection circuit 4C, the current detection of the first detection circuit 4A, the second detection circuit 4B, and the third detection circuit 4C continues normally. Therefore, even if a short circuit occurs between the adjacent input ports, the CPU 5 can identify the normal detected value by majority decision through mutual comparison of the current detection results.

[0057] Furthermore, if a short circuit occurs between input port SP1 and input port SN1 of the first detection circuit 4A and the first detection circuit 4A fails, the detection output of the first detection circuit 4A will diverge from the detection outputs of the second detection circuit 4B and the third detection circuit 4C, while the detection output of the second detection circuit 4B will approximately match the detection output of the third detection circuit 4C, allowing the CPU 5 to identify the failure of the first detection circuit 4A. Similarly, if a short circuit occurs between input port SP2 and input port SN2 of the second detection circuit 4B and the second detection circuit 4B fails, the detection output of the second detection circuit 4B will diverge from the detection outputs of the first detection circuit 4A and the third detection circuit 4C, while the detection output of the first detection circuit 4A will approximately match the detection output of the third detection circuit 4C, allowing the CPU 5 to identify the failure of the second detection circuit 4B. Similarly, if a short circuit occurs between input port SP3 and input port SN3 of the third detection circuit 4C and the third detection circuit 4C fails, the detection output of the third detection circuit 4C will diverge from the detection outputs of the first detection circuit 4A and the second detection circuit 4B, while the detection output of the first detection circuit 4A will approximately match the detection output of the second detection circuit 4B, allowing the CPU 5 to identify the failure of the third detection circuit 4C.

[0058] It should be noted that even when the pre-driver IC 4 includes the first detection circuit 4A, the second detection circuit 4B, and the third detection circuit 4C, the CPU 5 can perform the offset correction. In detail, the CPU 5 can obtain a detection value with the offset error corrected by adding together the detection output of the first detection circuit 4A and the detection output of the second detection circuit 4B to obtain an average value, or by adding together the detection output of the second detection circuit 4B and the detection output of the third detection circuit 4C to obtain an average value.

[0059] In addition, the shunt resistor 7 can be connected in series between the battery 6 and the inverter circuit 3 to form a current detection device that detects the DC bus current of the inverter circuit 3, that is, a high-side current detection device in which the shunt resistor 7 is connected in series to the power supply side of the inverter circuit 3. In this case, too, by connecting the upstream input line UL and the downstream input line DL to each input port so that adjacent input ports between different detection circuits are at the same potential, it is possible to prevent a short circuit between adjacent input ports from causing both detection circuits to be unable to detect current.

[0060] In addition, instead of detecting the DC bus current using the shunt resistor 7, a shunt resistor 7 can be connected to each winding of the motor 2, making it possible to create a current detection device that directly detects the phase current, which is the current flowing in each phase. FIG. 7 is a system diagram showing a motor control system 1 equipped with a current detection device that directly detects each phase current. In FIG. 7, the same elements as those in FIG. 1 or 5 are denoted by the same reference numerals, and detailed description thereof will be omitted.

[0061] In the motor control system 1 shown in Figure 7, a first shunt resistor 7A is connected in series to the ground side of the series connection circuit of switching element 3a and switching element 3b of the inverter circuit 3, a second shunt resistor 7B is connected in series to the ground side of the series connection circuit of switching element 3c and switching element 3d of the inverter circuit 3, and further, a third shunt resistor 7C is connected in series to the ground side of the series connection circuit of switching element 3e and switching element 3f of the inverter circuit 3. The first shunt resistor 7A, the second shunt resistor 7B, and the third shunt resistor 7C are connected in parallel with one another.

[0062] Similar to the system shown in FIG. 5, the pre-driver IC 4 includes a first detection circuit 4A, a second detection circuit 4B, and a third detection circuit 4C, and the input ports SP1, SN1, SP2, SN2, SP3, and SN3 of the detection circuits 4A, 4B, and 4C are arranged in this order at one side end of the IC body. A first upstream input line UL1 that inputs the upstream potential of the first shunt resistor 7A is connected to the input port SP1 of the first detection circuit 4A, and a first downstream input line DL1 that inputs the downstream potential (ground potential) of the first shunt resistor 7A is connected to the input port SN1 of the first detection circuit 4A.

[0063] In addition, a third upstream input line UL3 that inputs the upstream potential of the third shunt resistor 7C is connected to the input port SP3 of the third detection circuit 4C, and a third downstream input line DL3 that inputs the downstream potential (ground potential) of the third shunt resistor 7C is connected to the input port SN3 of the third detection circuit 4C. In contrast to these, a second downstream input line DL2 that inputs the downstream potential (ground potential) of the second shunt resistor 7B is connected to the input port SP2 of the second detection circuit 4B, and a second upstream input line UL2 that inputs the upstream potential of the second shunt resistor 7B is connected to the input port SN2 of the second detection circuit 4B.

[0064] Therefore, the downstream potential (ground potential) of the shunt resistors 7A, 7B is input to the input port SN1 of the first detection circuit 4A and the input port SP2 of the second detection circuit 4B, which are adjacent to each other, and these become the same potential. Furthermore, the upstream potentials of the shunt resistors 7B and 7C are input to the input port SN2 of the second detection circuit 4B and the input port SP3 of the third detection circuit 4C, which are adjacent to each other.

[0065] Here, since the input port SN1 of the first detection circuit 4A and the input port SP2 of the second detection circuit 4B are at the same potential (ground potential), even if a short circuit occurs between the input port SN1 and the input port SP2, the first detection circuit 4A and the second detection circuit 4B can continue to perform normal current detection operations. On the other hand, the input port SN2 of the second detection circuit 4B and the input port SP3 of the third detection circuit 4C are not at the same potential because the upstream potentials of the shunt resistors 7B and 7C for detecting different phase currents are input to them.

[0066] Therefore, if a short circuit occurs between the input port SN2 and the input port SP3, the second detection circuit 4B and the third detection circuit 4C will malfunction, making it impossible to determine a normal current detection value by majority vote. Therefore, compared to a system that uses a single shunt method to detect the DC bus current of the inverter circuit 3, the function of maintaining normal current detection operation in the event of a short circuit between adjacent input ports is limited, but normal operation can be continued in the event of a short circuit between input port SN1 and input port SP2, which contributes to improving the reliability of the system.

[0067] The technical ideas explained in the above embodiments can be used in appropriate combinations as long as no contradiction occurs. Furthermore, although the contents of the present invention have been specifically described with reference to preferred embodiments, it is obvious that a person skilled in the art can adopt various modified embodiments based on the basic technical idea and teachings of the present invention. [Explanation of symbols]

[0068] 1...motor control system, 2...motor, 3...inverter circuit, 4...pre-driver IC, 5...CPU, 7...shunt resistor, 4A...first detection circuit, 4B...second detection circuit, SP1, SN1, SP2, SN2...input ports, UL...upstream input line, DL...downstream input line

Claims

1. a shunt resistor connected in series to the power supply side or the ground side of the inverter circuit; a first detection circuit that detects a potential difference across the shunt resistor; a second detection circuit that detects a potential difference across the shunt resistor; an upstream input line that inputs an upstream potential of the shunt resistor to the first detection circuit and the second detection circuit; a downstream input line that inputs a downstream potential of the shunt resistor to the first detection circuit and the second detection circuit; and a pair of input ports of the first detection circuit and a pair of input ports of the second detection circuit are arranged in parallel, the upstream input line and the downstream input line are connected to each input port so that the input port of the first detection circuit and the input port of the second detection circuit adjacent to each other have the same potential; Current detection device.

2. 2. The current detection device according to claim 1, an inverting input port of the pair of input ports of the first detection circuit and a non-inverting input port of the pair of input ports of the second detection circuit are adjacent to each other; the upstream input line and the downstream input line are connected to the respective input ports so that the inverting input port of the first detection circuit and the non-inverting input port of the second detection circuit have the same potential, and the non-inverting input port of the first detection circuit and the inverting input port of the second detection circuit have the same potential; Current detection device.

3. 3. The current detection device according to claim 2, detecting a current based on an average of an output of the first detection circuit and an output of the second detection circuit; Current detection device.

4. 2. The current detection device according to claim 1, a third detection circuit that detects a potential difference between both ends of the shunt resistor in addition to the first detection circuit and the second detection circuit; a pair of input ports of the first detection circuit, a pair of input ports of the second detection circuit, and a pair of input ports of the third detection circuit are arranged in this order; an inverting input port of the first detection circuit and a non-inverting input port of the second detection circuit are adjacent to each other, and an inverting input port of the second detection circuit and a non-inverting input port of the third detection circuit are adjacent to each other; the upstream input line and the downstream input line are connected to the respective input ports so that the non-inverting input port of the second detection circuit has the same potential as the inverting input ports of the first detection circuit and the third detection circuit, and the inverting input port of the second detection circuit has the same potential as the non-inverting input ports of the first detection circuit and the third detection circuit; Current detection device.

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