Wiring board and manufacturing method of the same

Abstract

To provide a technique capable of suppressing an influence of warping or the like of a wiring board and improving reliability of connection with an electronic component to be surface-mounted.SOLUTION: A wiring board of the present embodiment includes: an insulating layer having a curved surface; a conductive layer stacked on the insulating layer and having a plurality of pads arranged in a grid pattern; a solder resist layer stacked on the conductive layer and having a plurality of connection openings exposing the plurality of pads; a plurality of solder bumps provided on the plurality of pads; and a bump upper surface formed on each of the plurality of solder bumps and included in a common imaginary flat surface. An opening area of the connection opening located in a region raised by the curvature is larger than an opening area of the connection opening located in a region lowered by the curvature.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to a wiring board in which a plurality of pads arranged in a grid pattern are exposed through a plurality of connection openings formed in a solder resist layer, and a method for manufacturing the same. [Background technology]

[0002] Conventionally, as this type of wiring board, one in which a plurality of solder bumps are provided on a plurality of pads is known (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2000-100863 A (paragraph

[0001] , Figure 4) Summary of the Invention [Problem to be solved by the invention]

[0004] However, with conventional wiring board structures, when the wiring board warps, there is a problem in that the connection state to the electronic components differs between the multiple solder bumps located in the area that is lower due to the warp and the multiple solder bumps located in the area that is higher due to the warp. In response to this, this application provides technology that can reduce the effects of warping of the wiring board and can increase the reliability of the connection with surface-mounted electronic components. [Means for solving the problem]

[0005] A wiring board according to one embodiment of the present disclosure is a wiring board having an insulating layer having a curved surface, a conductive layer laminated on the insulating layer and having a plurality of pads arranged in a grid pattern, a solder resist layer laminated on the conductive layer and having a plurality of connection openings exposing the plurality of pads, a plurality of solder bumps provided on the plurality of pads, and bump upper surfaces formed on each of the plurality of solder bumps and included in a common imaginary flat surface, wherein the opening area of ​​the connection openings located in an area that is higher due to the curvature is larger than the opening area of ​​the connection openings located in an area that is lower due to the curvature.

[0006] A method for manufacturing a wiring board according to one embodiment of the present disclosure includes stacking a conductive layer having a plurality of pads arranged in a grid pattern on an insulating layer having a curved surface, stacking a solder resist layer having a plurality of connection openings exposing the plurality of pads on the conductive layer, and forming a plurality of solder bumps on the plurality of pads, and flattening the plurality of solder bumps so that they have upper bump surfaces that are included in a common imaginary flat plane, wherein the connection openings located in areas that are higher due to the curvature are formed larger in opening area than the connection openings located in areas that are lower due to the curvature. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 is a cross-sectional view of a wiring board according to an embodiment of the present disclosure. [Figure 2] FIG. 2 is a plan view of a wiring board before a plurality of solder bumps are formed. [Figure 3] 3A and 3B are cross-sectional views showing a method for manufacturing a wiring board. [Figure 4] 4A and 4B are cross-sectional views showing a method for manufacturing a wiring board. [Figure 5] FIG. 5 is a cross-sectional view showing a method for manufacturing a wiring board. [Figure 6] 6A and 6B are cross-sectional views showing a method for manufacturing a wiring board. [Figure 7]FIG. 7 is a cross-sectional view showing a method for manufacturing a wiring board. [Figure 8] FIG. 8 is a cross-sectional view showing a method for manufacturing a wiring board. [Figure 9] FIG. 9 is a cross-sectional view of a wiring board according to a modified example. DETAILED DESCRIPTION OF THE INVENTION

[0008] An embodiment of the present disclosure will be described with reference to Figures 1 to 8. As shown in Figure 1, a wiring board 10 of this embodiment includes a core substrate 11 and first and second buildup layers 12A and 12B laminated on both the front and back surfaces of the core substrate 11.

[0009] Core substrate 11 includes, for example, insulating layer 11K, conductive layers 13 laminated on both the front and back surfaces of insulating layer 11K, and a plurality of through-hole conductors 14 for connecting these conductive layers 13. Although through-hole conductors 14 are constricted midway, they may also have a non-constricted shape.

[0010] The first and second buildup layers 12A and 12B include a plurality of insulating layers 15 and a plurality of conductive layers 16 that are alternately stacked, and a plurality of via conductors 17 for connecting the conductive layers 16. Note that the first and second buildup layers 12A and 12B include a plurality of conductive layers 16, but may include only one conductive layer 16.

[0011] A solder resist layer 20 is formed on the first and second buildup layers 12A and 12B. A plurality of connection openings 21A and 21B are formed in the solder resist layer 20, exposing a plurality of pads 18A and 18B provided on the outermost conductive layer 16.

[0012] The pads 18A on the outermost conductive layer 16 of the first buildup layer 12A are arranged in a grid pattern, and a plurality of solder bumps 30 for mounting an electronic component 90 are provided on the pads 18A. Each of the plurality of solder bumps 30 has a bump upper surface 31 that is included in a common imaginary flat surface at the top. As shown in Fig. 2, the wiring substrate 10 is, for example, rectangular in plan view, and has the pads 18A, connection openings 21A, and solder bumps 30 formed in the center thereof so that an electronic component 90 can be mounted thereon.

[0013] Although the plurality of solder bumps 30 are provided only on the plurality of pads 18A on the first buildup layer 12A side, they may be provided on both the plurality of pads 18A and 18B.

[0014] Incidentally, wiring board 10 may warp due to, for example, a difference in the amount of conductor between first buildup layer 12A and second buildup layer 12B. Therefore, in wiring board 10 of this embodiment, the opening area of ​​multiple connection openings 21A located in higher regions is made larger than the opening area of ​​multiple connection openings 21A located in regions that are lower due to warping, thereby reducing the height difference at the top of multiple solder bumps 30.

[0015] Specifically, as shown in Fig. 1, the surface of the outermost insulating layer 15 of the first buildup layer 12A of the wiring board 10 is curved so that it becomes lower, for example, as it approaches the center in a plan view, and the outermost conductive layer 16 and solder resist layer 20 laminated on the outermost insulating layer 15 are also curved in a similar manner. In this embodiment, the surface of the outermost insulating layer 15 is divided into multiple regions due to the height difference caused by the curvature, and the opening diameters of the multiple connection openings 21A are made different for each region. Note that Fig. 1 exaggerates the warpage of the wiring board 10.

[0016] Specifically, the surface of the outermost insulating layer 15 is divided into two regions: a lower region R1 including the lowest central portion, and an upper region R2 that is higher than the lower region R1. Of the plurality of connection openings 21A, the opening diameter D2 of the plurality of connection openings 21A2 located in the upper region R2 is larger than the opening diameter D1 of the plurality of connection openings 21A1 located in the lower region R1.

[0017] 2, in the plurality of connection openings 21A in which a plurality of solder bumps 30 are formed in seven vertical rows and seven horizontal rows, two outer rows of a plurality of connection openings 21A2 are included in the upper region R2, and the inner three vertical rows and three horizontal rows of a plurality of connection openings 21A1 surrounded by these are included in the lower region R1. However, the manner of dividing the regions is not limited to this, and they may be divided appropriately according to the difference in height caused by the curvature of the surface of the outermost insulating layer 15. The arrangement and number of the plurality of connection openings 21A1 included in the lower region R1 and the plurality of connection openings 21A2 included in the upper region R2 may be changed accordingly. In addition, the opening diameter D1 of the connection opening 21A1 and the opening diameter D2 of the connection opening 21A2 are opening diameters on the top sides of the connection openings 21A1 and 21A2. The opening diameters of these connection openings 21A1 and 21A2 are preferably 100 μm or more and 400 μm or less, and in this embodiment, for example, the opening diameter D1 of connection opening 21A1 is 190 μm, and the opening diameter D2 of connection opening 21A2 is 250 μm.

[0018] The wiring board 10 of the present disclosure is manufactured as follows. (1) As shown in FIG. 3A, a laminate 11S is prepared in which metal foils 11D are laminated on both sides of an insulating layer 11K.

[0019] (2) Next, the laminate 11S is subjected to, for example, drilling or laser light irradiation to form through holes at the positions where the plurality of through-hole conductors 14 are to be formed. Then, after electroless plating and electrolytic plating, a conductive layer 13 having a predetermined pattern is formed by a subtractive method, and the core substrate 11 is obtained as shown in FIG.

[0020] (3) As shown in FIG. 4A, first and second buildup layers 12A and 12B are formed on both sides of core substrate 11 by a semi-additive method.

[0021] (4) As shown in FIG. 4B, a solder resist film 20A is laminated on the first and second buildup layers 12A and 12B.

[0022] (5) Next, as shown in FIG. 5, the solder resist film 20A of the first buildup layer 12A is irradiated with ultraviolet light through an exposure mask 80. The exposure mask 80 has a plurality of light-shielding portions 81, 82 (black portions in FIG. 5) with different outer diameters, where the light-shielding portions 81 correspond to the plurality of connection openings 21A1 and the light-shielding portions 82 correspond to the plurality of connection openings 21A2. This hardens the solder resist film 20A in the portions other than the light-shielding portions 81, 82 that are irradiated with light. Then, after the unexposed portions of the solder resist film 20A are removed by the light-shielding portions 81, 82, the solder resist film 20A is hardened by heat. This results in a solder resist layer 20 having a plurality of connection openings 21A1, 21A2 with different opening diameters (see FIG. 6A).

[0023] The same process is performed on the solder resist film 20A on the second buildup layer 12B side, forming a solder resist layer 20 having a plurality of connection openings 21B as shown in Fig. 6A. The outer diameters of the plurality of light-shielding portions 84A of the exposure mask 84 used when forming the solder resist layer 20 of the second buildup layer 12B are all the same size.

[0024] (6) Flux F (see FIG. 6B) is applied onto the pads 18A exposed from the connection openings 21A1 and 21A2 of the solder resist layer 20 of the first buildup layer 12A.

[0025] (7) Next, as shown in FIG. 6B, a ball mounting mask 83 is overlaid on the solder resist layer 20 of the first buildup layer 12A. The ball mounting mask 83 has a plurality of openings 83K formed in positions corresponding to the plurality of connection openings 21A1 and 21A2. The diameter of the plurality of openings 83K in the ball mounting mask 83 is, for example, substantially the same as the diameter of the connection opening 21A1. Then, one solder ball 32 is mounted in each opening 83K of the ball mounting mask 83. At this time, the solder balls 32 used have substantially the same diameter, regardless of the difference in the diameters of the connection openings 21A1 and 21A2. Note that FIG. 6B only shows the first buildup layer 12A side.

[0026] (8) After the ball mounting mask 83 is removed, reflow is performed to form multiple solder bumps 30 on the multiple pads 18A. At this time, the solder bumps 30 in the connection opening 21A2, which has a larger opening diameter, use more solder to fill the connection opening 21A2 than the solder bumps 30 in the connection opening 21A1. In this embodiment, the multiple solder bumps 30 are made up of multiple solder balls 32 of approximately the same diameter, so as shown in FIG. 7, the multiple solder bumps 30 on the multiple pads 18A in the upper region R2 are lower than the multiple bumps 30 on the multiple pads 18A in the lower region R1. As a result, the height difference at the top of the multiple solder bumps 30 is reduced.

[0027] 7, the warping of wiring board 10 and the curvature of the surface of outermost insulating layer 15 occur in this step, but the warping of wiring board 10 and the curvature of the surface of outermost insulating layer 15 are not limited to occurring in this step and may occur in any step, or the warping of wiring board 10 and the curvature of the surface of insulating layer 15 may gradually increase as the manufacturing steps proceed. Furthermore, the method of mounting multiple solder balls 32 on wiring board 10 is not limited to the method of dropping solder balls 32 into openings 83K of ball mounting mask 83 as described above in (7), but may also be a method of lifting multiple solder balls 32 by suction and placing them on multiple pads 18A, for example.

[0028] (9) Next, as shown in Fig. 8, the plurality of solder bumps 30 are pressed by a pressure plate P having a flat press surface, and upper bump surfaces 31 are formed on the upper portions of the plurality of solder bumps 30. Here, in this embodiment, the plurality of solder bumps 30 are pressed by the pressure plate P while minimizing the height difference at the top of the plurality of solder bumps 30, so the difference in area between the upper bump surfaces 31 of the solder bumps 30 on the plurality of pads 18A in the lower region R1 and the upper bump surfaces 31 of the solder bumps 30 on the plurality of pads 18A in the upper region R2 is minimized. In this way, the wiring substrate 10 is completed.

[0029] The structure of the wiring board 10 and the manufacturing method thereof according to this embodiment have been described above. Next, the effects of the wiring board 10 will be described. As described above, in the wiring board 10 according to this embodiment, the opening area of ​​the plurality of connection openings 21A2 located in a higher region (specifically, the upper region R2) is larger than the opening area of ​​the plurality of connection openings 21A1 located in a lower region (specifically, the lower region R1) of the surface of the outermost insulating layer 15 due to warping. This makes the solder bumps 30 on the plurality of pads 18A located higher lower than the solder bumps 30 on the plurality of pads 18A located lower, thereby minimizing the height difference at the top of the plurality of solder bumps 30. Furthermore, the plurality of solder bumps 30 are formed with upper bump surfaces 31 that are included in a common imaginary flat surface, thereby minimizing the difference in area between the upper bump surfaces 31 of the plurality of solder bumps 30.

[0030] Furthermore, if the opening area of ​​the plurality of connection openings 21A2 located in the higher region (upper region R2) were the same as the opening area of ​​the plurality of connection openings 21A1 located in the lower region (lower region R1), a large amount of solder would protrude from the solder resist layer 20, making it more likely for short circuits to occur between the solder bumps 30. However, according to the configuration of this embodiment, the opening area of ​​the plurality of connection openings 21A2 located in higher positions is increased, so that more solder is used to fill the connection openings 21A, making it less likely for short circuits to occur. Thus, according to the wiring board 10 of this embodiment, the effects of warping and the like of the wiring board 10 are suppressed, making it possible to improve the reliability of connections with surface-mounted electronic components 90.

[0031] In addition, in this embodiment, the amount of solder required to form the plurality of solder bumps 30 is approximately the same, which stabilizes the quality of the solder bumps 30. Furthermore, in this embodiment, the surface of the outermost insulating layer 15 of the first buildup layer 12A is divided into two regions: a lower region R1 including the lowest portion, and an upper region R2 that is higher than the lower region R1, and the opening diameters of the plurality of connection openings 21A are made different for each of the regions R1 and R2, so that the plurality of solder bumps 30 can be formed according to the difference in height of the plurality of pads 18A due to the curvature of the surface of the outermost insulating layer 15 (warpage of the wiring substrate 10).

[0032] [Other embodiments] In the above embodiment, the surface of the curved outermost insulating layer 15 is divided into two regions, a lower region R1 and an upper region R2, and the multiple connection openings 21A are composed of two types: multiple connection openings 21A1 for the lower region R1 and multiple connection openings 21A2 for the upper region R2. However, the surface may be divided into three or more regions and have three or more types of multiple connection openings 21A with different opening diameters.

[0033] In the above embodiment, an example has been shown in which wiring board 10 is warped so that it is lower as it approaches the center in a plan view, but wiring board 10 may be warped so that any position in a plan view is the lowest. It is sufficient that the surface of outermost insulating layer 15 is divided into a plurality of regions according to the height differences of the plurality of pads 18A caused by the warping.

[0034] 1, in the above embodiment, an example has been described in which the plurality of solder bumps 30 are provided on the solder resist layer 20 side that is recessed inward, but conversely, as shown in Fig. 9, they may be provided on the solder resist layer 20 side that bulges outward. In the example of Fig. 9, the outer edge of the outermost insulating layer 15 forms the lower region R1, and the central portion of the outermost insulating layer 15 forms the upper region R2, and the plurality of connection openings 21A2 located in the upper region R2 have larger opening areas than the plurality of connection openings 21A1 located in the lower region R1.

[0035] In the above embodiment, the pads 18A, the connection openings 21A, and the solder bumps 30 are provided so that the center of the wiring board 10 and the center of the electronic component 90 are substantially aligned, but the arrangement of the electronic component 90 is not limited to this and the electronic component 90 may be arranged at any position on the wiring board 10. Furthermore, the number of electronic components 90 mounted is not limited to one, and may be multiple.

[0036] In the above embodiment, an example was described in which multiple solder bumps 30 were formed using solder balls 32, but this is not limited to this. For example, the solder bumps 30 may be formed by printing and applying solder paste in approximately constant amounts using a screen printing method.

[0037] The curvature of the surface of the outermost insulating layer 15 is not limited to the arched curvature shown in FIGS. 1 and 9, but may be, for example, a wavy curvature in which the curve undulates up and down.

[0038] Although the present specification and drawings disclose specific examples of the technology included in the scope of the claims, the technology described in the claims is not limited to these specific examples, but also includes various modifications and variations of the specific examples, and also includes parts of the specific examples taken out alone. [Explanation of symbols]

[0039] 10. Wiring board 15 Insulating layer 16 Conductive layer 18A, 18B pads 20 Solder resist layer 20A solder resist film 21A, 21A1, 21A2, 21B Connection opening 30 Solder bumps 31 Top of bump 32 solder balls R1 Lower area R2 upper area

Claims

1. an insulating layer having a curved surface; a conductive layer laminated on the insulating layer and having a plurality of pads arranged in a grid pattern; a solder resist layer laminated on the conductive layer and having a plurality of connection openings exposing the plurality of pads; a plurality of solder bumps provided on the plurality of pads; a bump upper surface formed on each of the plurality of solder bumps and included in a common imaginary flat surface, The opening area of ​​the connection opening located in the region that is higher due to the curvature is larger than the opening area of ​​the connection opening located in the region that is lower due to the curvature.

2. 2. The wiring board according to claim 1, The volume of the plurality of solder bumps is substantially uniform.

3. 2. The wiring board according to claim 1, The plurality of solder bumps are made up of a plurality of solder balls having approximately the same diameter.

4. 4. The wiring board according to claim 1, The surface of the insulating layer is divided into a plurality of regions including a lower region having the lowest portion and an upper region having the highest portion, and the opening area of ​​the connection opening varies in stages for each of the regions.

5. 5. The wiring board according to claim 4, the plurality of regions are composed of two regions, the lower region and the upper region, The plurality of connection openings are configured in two types, large and small, for the lower region and the upper region.

6. 4. The wiring board according to claim 1, The surface of the insulating layer is curved so that it becomes lower as it approaches the center in a plan view.

7. a conductive layer having a plurality of pads arranged in a grid pattern is laminated on an insulating layer having a curved surface; a solder resist layer having a plurality of connection openings exposing the plurality of pads is laminated on the conductive layer; forming a plurality of solder bumps on the plurality of pads exposed from the plurality of connection openings, and planarizing the plurality of solder bumps so that they have upper bump surfaces included in a common imaginary flat plane; The connecting openings located in the regions that are higher due to the curvature are formed to have larger opening areas than the connecting openings located in the regions that are lower due to the curvature.

8. 8. The method for manufacturing a wiring board according to claim 7, The plurality of solder bumps are formed by a plurality of solder balls having approximately the same diameter.

9. 9. The method for manufacturing a wiring board according to claim 7 or 8, The surface of the insulating layer is divided into a plurality of regions including a lower region having the lowest portion and an upper region having the highest portion, and the opening area of ​​the connection opening varies in stages for each of the regions.

10. 10. The method for manufacturing a wiring board according to claim 9, the plurality of regions are composed of two regions, the lower region and the upper region, The plurality of connection openings are configured in two types, large and small, for the lower region and the upper region.

11. 9. The method for manufacturing a wiring board according to claim 7 or 8, The surface of the insulating layer is curved so that it becomes lower as it approaches the center in a plan view.

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