Magnetic storage device

Abstract

To provide a magnetic storage device capable of improving operating performance.SOLUTION: A magnetic storage device of an embodiment includes: a comparator CP that compares a voltage Vm of a memory cell with a voltage Va lower than a precharge voltage Vpc and outputs a first signal when the voltage of the memory cell is lower than the voltage Va; and a delay circuit 53 that outputs a second signal delayed by a first delay time of the first signal outputted from the comparator. During a read operation, a switch S1 is set to a connected state, a switch S2 is set to a disconnected state, and the memory cell is charged to the voltage Vpc. After the memory cell is charged to the voltage Vpc, the switch S1 is set to the disconnected state, the switch S2 is set to the connected state, and the charge of the memory cell is discharged. Then, a switch S3 is set to the disconnected state according to the second signal, the sense amplifier compares the voltage Vm of the memory cell with a voltage Vref, and the data stored in the memory cell is determined.SELECTED DRAWING: Figure 5

Description

[Technical Field]

[0001] FIELD OF THE INVENTION The present invention relates to a magnetic storage device. [Background technology]

[0002] 2. Description of the Related Art Magnetic storage devices using magnetoresistive elements as storage elements (Magnetoresistive Random Access Memories (MRAMs)) are known. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] US Patent Application Publication No. 2018 / 0342273 Summary of the Invention [Problem to be solved by the invention]

[0004] A magnetic storage device capable of improving operating performance is provided. [Means for solving the problem]

[0005] a first switch connected between the memory cell and the first power supply circuit and configured to connect or disconnect the memory cell from the first power supply circuit; a second switch connected between the memory cell and a ground voltage node to which a ground voltage is supplied and configured to connect or disconnect the memory cell from the ground voltage node; a comparator that compares the voltage of the memory cell with a second voltage lower than the first voltage and outputs a first signal when the voltage of the memory cell drops below the second voltage; a delay circuit that delays the first signal output from the comparator by a first delay time and outputs a second signal; a sense amplifier that compares the voltage of the memory cell with a third voltage; and a third switch connected between the memory cell and the sense amplifier and configured to connect or disconnect the memory cell from the sense amplifier. In a read operation, the first switch is set to a connected state, the second switch is set to a disconnected state, the memory cell is charged to the first voltage, after the memory cell is charged to the first voltage, the first switch is set to a disconnected state, the second switch is set to a connected state, the charge stored in the memory cell is discharged, the third switch is set to a disconnected state in response to the second signal, the voltage of the memory cell is compared with the third voltage by the sense amplifier, and the data stored in the memory cell is determined. [Brief explanation of the drawings]

[0006] [Figure 1] 1 is a block diagram showing a configuration of a memory system including a magnetic memory device according to an embodiment. [Figure 2] 1 is a circuit diagram showing the configuration of a memory cell array included in a magnetic memory device according to an embodiment. [Figure 3] 1 is a perspective view showing the structure of a memory cell array included in a magnetic memory device according to an embodiment. [Figure 4]1 is a cross-sectional view of a memory cell in a memory cell array according to an embodiment. [Figure 5] FIG. 2 is a circuit diagram showing the configuration of a read circuit included in the magnetic memory device according to the embodiment. [Figure 6] FIG. 2 is a diagram illustrating an example of the configuration of a delay circuit in a readout circuit according to the embodiment. [Figure 7] 10A and 10B are diagrams showing changes in the voltage of a memory cell during a read operation of the magnetic memory device according to the embodiment. [Figure 8] 10 is a flowchart showing the flow of a read operation of the magnetic memory device according to the embodiment. [Figure 9] 10A and 10B are diagrams illustrating switch states and current flows during a read operation according to an embodiment. [Figure 10] 10A and 10B are diagrams illustrating switch states and current flows during a read operation according to an embodiment. [Figure 11] 10A and 10B are diagrams illustrating switch states and current flows during a read operation according to an embodiment. [Figure 12] 10A and 10B are diagrams illustrating switch states and current flows during a read operation according to an embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0007] Hereinafter, embodiments will be described with reference to the drawings. In the following description, components having the same function and configuration will be assigned the same reference numerals. Furthermore, the embodiments shown below are merely examples of devices and methods for embodying the technical ideas of the embodiments, and do not specify the materials, shapes, structures, arrangements, etc. of the components as described below.

[0008] (Embodiment) First, an example of a memory system including the magnetic storage device of the embodiment will be described. Fig. 1 is a block diagram showing the configuration of a memory system MS including the magnetic storage device of the embodiment.

[0009] 1, the memory system MS includes a magnetic storage device 1 and a memory controller 2. The magnetic storage device 1 operates under the control of the memory controller 2. The memory controller 2 can instruct the magnetic storage device 1 to perform read operations, write operations, etc. in response to a request (or command) from an external host device.

[0010] 1. Magnetic Storage Device Configuration Next, the configuration of the magnetic storage device 1 according to the embodiment will be described with reference to FIG.

[0011] The magnetic memory device 1 is a type of resistance change memory. The magnetic memory device 1 is a memory device that uses MTJ (Magnetic Tunnel Junction) elements as memory cells. The MTJ elements utilize the magnetoresistance effect caused by a magnetic tunnel junction. The MTJ elements are also called magnetoresistance effect elements.

[0012] The magnetic memory device 1 includes, for example, a memory cell array 11, an input / output circuit 12, a control circuit 13, a row selection circuit 14, a column selection circuit 15, a write circuit 16, and a read circuit 17.

[0013] The memory cell array 11 includes a plurality of memory cells MC, a plurality of word lines WL, and a plurality of bit lines BL. FIG. 1 shows a set of memory cells MC, word lines WL, and bit lines BL. The memory cells MC can store data in a non-volatile manner. The memory cells MC are connected between one word line WL and one bit line BL, and correspond to a set of a row and a column. A row address is assigned to the word line WL. A column address is assigned to the bit line BL. One or more memory cells MC can be specified by selecting one row and one or more columns.

[0014] The input / output circuit 12 is connected to the memory controller 2 and controls communication between the magnetic storage device 1 and the memory controller 2. The input / output circuit 12 transfers the control signal CNT and command CMD received from the memory controller 2 to the control circuit 13. The input / output circuit 12 also transfers the row address and column address included in the address signal ADD received from the memory controller 2 to the row selection circuit 14 and the column selection circuit 15, respectively. The input / output circuit 12 transfers the data DAT (write data) received from the memory controller 2 to the write circuit 16. The input / output circuit 12 transfers the data DAT (read data) received from the read circuit 17 to the memory controller 2.

[0015] The control circuit 13 controls the overall operation of the magnetic memory device 1. For example, the control circuit 13 executes read operations, write operations, etc. based on the control indicated by the control signal CNT and the command CMD. For example, in a write operation, the control circuit 13 supplies the write circuit 16 with a voltage and control signal used for writing data. In a read operation, the control circuit 13 supplies the read circuit 17 with a voltage and control signal used for reading data.

[0016] The row selection circuit 14 is connected to a plurality of word lines WL. The row selection circuit 14 selects one word line WL specified by a row address. The selected word line WL is electrically connected to, for example, a driver circuit (not shown).

[0017] The column selection circuit 15 is connected to a plurality of bit lines BL. The column selection circuit 15 selects one or more bit lines BL specified by a column address. The selected bit lines BL are electrically connected to, for example, a driver circuit (not shown).

[0018] The write circuit 16 supplies a voltage used for writing data to the column selection circuit 15 based on the control of the control circuit 13 and the data DAT (write data) received from the input / output circuit 12. When a current based on the write data flows through the memory cell MC, the desired data is written to the memory cell MC.

[0019] The read circuit 17 includes a sense amplifier. Based on the control of the control circuit 13, the read circuit 17 supplies a voltage used for reading data to the row selection circuit 14 and the column selection circuit 15. The sense amplifier determines the data stored in the memory cell MC based on the voltage or current of the selected memory cell MC and word line WL. Furthermore, the read circuit 17 transfers data DAT (read data) corresponding to the determination result to the input / output circuit 12. Details of the read circuit 17 will be described later.

[0020] 1.1 Memory cell array circuit configuration An example of the circuit configuration of the memory cell array 11 included in the magnetic memory device 1 of the embodiment will be described with reference to Fig. 2. Fig. 2 is a circuit diagram showing the configuration of the memory cell array 11 included in the magnetic memory device 1. Fig. 2 shows WL0 and WL1 extracted from the multiple word lines WL and BL0 and BL1 extracted from the multiple bit lines BL.

[0021] 2, one memory cell MC is connected between WL0 and BL0, between WL0 and BL1, between WL1 and BL0, and between WL1 and BL1, respectively. The memory cells MC are arranged in the memory cell array 11, for example, in a matrix.

[0022] Each memory cell MC includes a variable resistance element VR and a selector element SE. The variable resistance element VR and the selector element SE are connected in series between the associated bit line BL and word line WL. For example, one end of the variable resistance element VR is connected to the bit line BL. The other end of the variable resistance element VR is connected to one end of the selector element SE. The other end of the selector element SE is connected to the word line WL. Note that the connection relationship between the variable resistance element VR and the selector element SE between the bit line BL and the word line WL may be reversed. That is, one end of the variable resistance element VR may be connected to the word line WL, and the other end of the variable resistance element VR may be connected to one end of the selector element SE. The other end of the selector element SE may be connected to the bit line BL.

[0023] The variable resistance element VR corresponds to an MTJ element (i.e., a magnetoresistive element). The variable resistance element VR can store data nonvolatilely based on its resistance value. For example, a memory cell MC including a variable resistance element VR in a high resistance state stores data "1." A memory cell MC including a variable resistance element VR in a low resistance state stores data "0." The assignment of data associated with the resistance value of the variable resistance element VR may be other settings. The resistance state of the variable resistance element VR can change depending on the current flowing through the variable resistance element VR.

[0024] The selector element SE is, for example, a bidirectional diode. The selector element SE functions as a selector that controls the supply of current to the associated variable resistance element VR. Specifically, the selector element SE included in a memory cell MC is turned off when the voltage applied to the memory cell MC is lower than the threshold voltage of the selector element SE, and is turned on when the voltage is equal to or higher than the threshold voltage of the selector element SE. The selector element SE in the off state functions as an insulator with a high resistance. When the selector element SE is in the off state, current flow between the word line WL and bit line BL connected to the memory cell MC is suppressed. When the selector element SE is in the on state, current flows between the word line WL and bit line BL connected to the memory cell MC. In other words, the selector element SE can switch whether to pass current depending on the magnitude of the voltage applied to the memory cell MC, regardless of the direction of current flow. Note that other elements, such as a transistor, may also be used as the selector element SE.

[0025] 1.2 Memory cell array structure An example of the structure of the memory cell array 11 included in the magnetic memory device 1 of the embodiment will be described with reference to FIG. 3. FIG. 3 is a perspective view showing the structure of the memory cell array 11 included in the magnetic memory device 1. In the following description, an XYZ Cartesian coordinate system is used. The X direction corresponds to the extension direction of the word lines WL. The Y direction corresponds to the extension direction of the bit lines BL. The Z direction corresponds to the vertical direction with respect to the surface of the semiconductor substrate used to form the magnetic memory device 1. The term "bottom" and its derivatives and related terms indicate a position with a smaller coordinate on the Z axis. The term "top" and its derivatives and related terms indicate a position with a larger coordinate on the Z axis. Hatching is added appropriately to the perspective views. The hatching added to the perspective views does not necessarily relate to the materials or properties of the components to which the hatching is added. In the perspective views and cross-sectional views, illustrations of components such as interlayer insulating films are omitted.

[0026] As shown in FIG. 3, the memory cell array 11 includes a plurality of conductor layers 20, a plurality of conductor layers 21, and a plurality of memory cells MC.

[0027] Each of the plurality of conductive layers 20 has a portion extending in the X direction. The plurality of conductive layers 20 are arranged side by side in the Y direction and spaced apart from one another. Each conductive layer 20 is used as a word line WL.

[0028] Each of the plurality of conductive layers 21 has a portion extending in the Y direction. The plurality of conductive layers 21 are arranged side by side in the X direction and spaced apart from one another. Each conductive layer 21 is used as a bit line BL.

[0029] A wiring layer including a plurality of conductor layers 21 is provided above a wiring layer including a plurality of conductor layers 20. One memory cell MC is provided at each intersection of the plurality of conductor layers 20 and the plurality of conductor layers 21. In other words, each memory cell MC is provided between an associated word line WL and bit line BL. Each memory cell MC has a columnar structure. In this example, a selector element SE is provided on the conductor layer 20. A variable resistance element VR is provided on the selector element SE. A conductor layer 21 is provided on the variable resistance element VR.

[0030] Although the variable resistance element VR is provided above the selector element SE in the above example, the present invention is not limited to this. Depending on the circuit configuration of the memory cell array 11, the variable resistance element VR may be provided below the selector element SE. Furthermore, other elements or conductive layers may be inserted between the memory cell MC and the conductive layer 20. Similarly, other elements or conductive layers may be inserted between the memory cell MC and the conductive layer 21. Each of the conductive layers 20 and 21 may be referred to as "wiring."

[0031] 1.3 Cross-sectional structure of memory cell An example of a memory cell MC included in the memory cell array 11 of the magnetic storage device 1 of the embodiment will be described with reference to Fig. 4. Fig. 4 is a cross-sectional view of a memory cell MC included in the memory cell array 11.

[0032] As shown in FIG. 4, the memory cell MC has a structure in which, for example, a lower electrode 30, a selector material layer 31, an upper electrode 32, a ferromagnetic layer 40, a non-magnetic layer 41, and a ferromagnetic layer 42 are stacked in this order from the conductor layer 20 upward (in the Z direction).

[0033] That is, the lower electrode 30 is provided above the conductor layer 20 (in the Z direction). The selector material layer 31 is provided above the lower electrode 30. The upper electrode 32 is provided above the selector material layer 31. The ferromagnetic layer 40 is provided above the upper electrode 32. The non-magnetic layer 41 is provided above the ferromagnetic layer 40. The ferromagnetic layer 42 is provided above the non-magnetic layer 41. The conductor layer 21 is provided above the ferromagnetic layer 42.

[0034] In other words, the nonmagnetic layer 41 is provided between the ferromagnetic layer 40 and the ferromagnetic layer 42. The ferromagnetic layer 40 is provided between the nonmagnetic layer 41 and the upper electrode 32. The upper electrode 32 is provided between the ferromagnetic layer 40 and the selector material layer 31. The selector material layer 31 is provided between the upper electrode 32 and the lower electrode 30. The lower electrode 30 is provided between the selector material layer 31 and the conductor layer 20. Furthermore, the ferromagnetic layer 42 is provided between the nonmagnetic layer 41 and the conductor layer 21.

[0035] A set of the lower electrode 30, the selector material layer 31, and the upper electrode 32 corresponds to the selector element SE. A set of the ferromagnetic layer 40, the non-magnetic layer 41, and the ferromagnetic layer 42 corresponds to the variable resistance element VR.

[0036] Each of the ferromagnetic layers 40 and 42 is made of a ferromagnetic material and has a magnetization direction perpendicular to the film surface. In the magnetic memory device 1, for example, the magnetization direction of the ferromagnetic layer 40 is fixed, and the magnetization direction of the ferromagnetic layer 42 is variable. In this case, the ferromagnetic layer 40 functions as a reference layer of the MTJ element, and the ferromagnetic layer 42 functions as a storage layer of the MTJ element. The nonmagnetic layer 41 is made of an insulator such as MgO and functions as a tunnel barrier layer. The ferromagnetic layers 40 and 42, together with the nonmagnetic layer 41, form a magnetic tunnel junction. This variable resistance element VR functions as a perpendicular magnetization MTJ element utilizing the TMR (tunneling magnetoresistive) effect.

[0037] The ferromagnetic layer 40 contains at least one element selected from the group consisting of, for example, iron (Fe), cobalt (Co), and nickel (Ni). The non-magnetic layer 41 contains at least one oxide of an element or compound selected from the group consisting of, for example, magnesium (Mg), aluminum (Al), zinc (Zn), titanium (Ti), and LSM (Lanthanum-strontium-manganese). The ferromagnetic layer 42 contains at least one element selected from the group consisting of, for example, iron (Fe), cobalt (Co), and nickel (Ni).

[0038] The variable resistance element VR can be in either a low resistance state or a high resistance state depending on the relative relationship between the magnetization directions of the ferromagnetic layers 40 and 42. The variable resistance element VR stores data depending on the magnetization direction of the ferromagnetic layer 42 (memory layer). For example, a variable resistance element VR in which the magnetization directions of the reference layer and memory layer are antiparallel (AP state) is in a high resistance state (data "1"). On the other hand, a variable resistance element VR in which the magnetization directions of the reference layer and memory layer are parallel (P state) is in a low resistance state (data "0").

[0039] In this example, the variable resistance element VR is in the AP state when a write current is passed in the direction from the ferromagnetic layer 40 to the ferromagnetic layer 42, and is in the P state when a write current is passed in the direction from the ferromagnetic layer 42 to the ferromagnetic layer 40. This write method, in which a write current is passed through the variable resistance element VR to inject spin torque into the memory layer and reference layer and control the magnetization direction of the memory layer, is called a spin injection write method. The variable resistance element VR is configured so that the magnetization direction of the ferromagnetic layer 40 does not change when a current of a magnitude sufficient to reverse the magnetization direction of the ferromagnetic layer 42 is passed through the variable resistance element VR.

[0040] In this specification, "the magnetization direction is variable" means that the magnetization direction changes depending on the write current. "The magnetization direction is fixed" means that the magnetization direction does not change depending on the write current. In the variable resistance element VR, the memory layer and the reference layer may be interchanged. The variable resistance element VR may also include other layers. For example, the variable resistance element VR may include a shift cancellation layer that suppresses the influence of the leakage magnetic field from the reference layer, an SAF (Synthetic Anti-Ferromagnetic) structure, or the like. Hereinafter, a memory cell MC including a variable resistance element VR in the AP state will be referred to as a memory cell MC in the AP state, and a memory cell MC including a variable resistance element VR in the P state will be referred to as a memory cell MC in the P state.

[0041] 1.4 Readout circuit configuration An example of the circuit configuration of the read circuit 17 included in the magnetic memory device 1 of the embodiment will be described with reference to Fig. 5. Fig. 5 is a circuit diagram showing the configuration of the read circuit 17. Fig. 5 shows the read circuit 17, a pair of bit lines BL and word lines WL included in the memory cell array 11, and memory cells MC.

[0042] As shown in FIG. 5, the read circuit 17 includes a sense amplifier SA, a comparator CP, a power supply circuit 51, a power supply circuit 52, a delay circuit 53, a precharge switch S1, a sink switch S2, and a sense amplifier switch S3.

[0043] The power supply circuit 51 is connected to the word line WL via the precharge switch S1. A node to which a ground voltage VSS is supplied is connected to the power supply circuit 51. Hereinafter, the node to which the ground voltage VSS is supplied is referred to as a ground voltage VSS node.

[0044] The word line WL is connected to a sense amplifier SA via a sense amplifier switch S3, which is supplied with a reference voltage Vref.

[0045] The word line WL is also connected to the negative input terminal (or inverting input terminal) of a comparator CP. A positive input terminal (or non-inverting input terminal) of the comparator CP is connected to a power supply circuit 52. A ground voltage VSS node is connected to the power supply circuit 52.

[0046] The output terminal of the comparator CP is connected to the input terminal of the delay circuit 53. The output terminal of the delay circuit 53 is connected to the control terminal of the sink switch S2 and the control terminal of the sense amplifier switch S3.

[0047] The bit line BL is connected to the ground voltage VSS node via the sink switch S2.

[0048] A memory cell MC is connected between a word line WL and a bit line BL. The memory cell MC includes a selector element SE and a variable resistance element VR connected in series. That is, one end of the selector element SE is connected to the word line WL, and one end of the variable resistance element VR is connected to the other end of the selector element SE. Furthermore, the other end of the variable resistance element VR is connected to the bit line BL.

[0049] The sense amplifier SA is configured to compare the voltage Vm of the memory cell MC with a reference voltage Vref when reading data stored in the memory cell MC, and determine the data stored in the memory cell MC based on the comparison result. Here, the voltage Vm of the memory cell MC can be regarded as, for example, a voltage due to the charge stored in the memory cell MC (or a selector element), or as a voltage due to the charge stored in the memory cell MC (or a selector element) and the word line WL. Hereinafter, either case will be referred to as the voltage of the memory cell MC.

[0050] The reference voltage Vref is a voltage used as a threshold value in determining whether data is "0" or "1." For example, when the voltage Vm of the memory cell MC is equal to or higher than Vref, the sense amplifier SA outputs a voltage corresponding to data "1." On the other hand, when the voltage Vm of the memory cell MC is lower than Vref, the sense amplifier SA outputs a voltage corresponding to data "0." Note that a sense amplifier SA is provided, for example, for each word line WL.

[0051] The comparator CP is configured to compare the voltage Vm of the memory cell MC with a comparison voltage Va during a read operation and determine the timing at which discharge from the memory cell MC begins (hereinafter referred to as discharge start timing) based on the comparison result. The comparison voltage Va is a voltage used as a threshold in determining the discharge start timing. For example, when the voltage Vm of the memory cell MC is equal to or higher than Va, the comparator CP outputs a signal indicating that discharge has not begun, such as a low-level voltage (hereinafter referred to as "L"). On the other hand, when the voltage Vm of the memory cell MC is lower than Va, the comparator CP outputs a signal indicating that discharge has begun, i.e., that it is the discharge start timing, such as a high-level voltage (hereinafter referred to as "H") higher than "L". Note that the comparator CP is provided, for example, for each word line WL.

[0052] The power supply circuit 51 supplies a precharge voltage Vpc to the memory cell MC, and charges the memory cell MC, that is, the selector element SE and the word line WL, to the precharge voltage Vpc. The precharge voltage Vpc is a voltage that is charged to the memory cell MC in a read operation.

[0053] The power supply circuit 52 supplies the comparator CP with a comparison voltage Va. The comparison voltage Va is lower than the precharge voltage Vpc and is as close as possible to the precharge voltage Vpc. That is, Va=k·Vpc, where k<1 and k is a value as close to 1 as possible.

[0054] Furthermore, after the memory cell MC is charged to the precharge voltage Vpc, the charge stored in the memory cell MC is discharged, and the voltage held by the memory cell MC when the discharge current stops flowing is defined as the hold voltage Vh. Then, with respect to the comparison voltage Va, Vpc>Va>Vh holds.

[0055] The delay circuit 53 delays an input voltage by a predetermined delay time and outputs the delayed voltage. Fig. 6 shows an example of the configuration of the delay circuit 53. For example, as shown in Fig. 6(a), the delay circuit 53 has a configuration in which an even number of inverters IV are connected in series. As shown in Fig. 6(b), the delay circuit 53 has a configuration including two inverters IV, and a resistive element R1 and a capacitive element C1 connected between these inverters.

[0056] The delay time by the delay circuit 53 is set to be shorter than the time from the timing when the memory cell MC starts discharging until the memory cell MC drops to the hold voltage Vh due to the discharge.

[0057] Furthermore, the delay time by the delay circuit 53 is set to three times or less the time constant that can be expressed by RC, where R is the resistance component of the memory cell MC (or selector element SE) and C is the capacitance component. Furthermore, the delay time by the delay circuit 53 may be set to three times or less the time constant that can be expressed by RC, where R is the resistance component of the memory cell MC (or selector element SE) and the word line WL, and C is the capacitance component.

[0058] The precharge switch S1 is a switch that switches between supplying and stopping the supply of a precharge voltage Vpc to the memory cell MC under the control of the control circuit 13. The precharge switch S1 is connected between the word line WL (or memory cell MC) and the power supply circuit 51. Under the control of the control circuit 13, the precharge switch S1 sets the state between the word line WL and the power supply circuit 51 to either a connected state (or a closed state) or a disconnected state (or an open state). For example, when the precharge switch S1 is set to a connected state, the precharge voltage Vpc is supplied from the power supply circuit 51 to the memory cell MC. On the other hand, when the precharge switch S1 is set to a disconnected state, the supply of the precharge voltage Vpc from the power supply circuit 51 to the memory cell MC is stopped. The precharge switch S1 includes, for example, an n-type MOS field effect transistor.

[0059] The sink switch S2 is a switch that switches between discharging and stopping the discharge of charge from the memory cell MC based on the output signal of the delay circuit 53. The sink switch S2 is connected between the bit line BL (or the memory cell MC) and the ground voltage VSS node. The sink switch S2 sets the state between the bit line BL and the ground voltage VSS node to either a connected state or a cut-off state based on the output signal of the delay circuit 53. For example, when the sink switch S2 is set to a connected state, a discharge current flows from the memory cell MC to the ground voltage VSS node, and the charge stored in the memory cell MC is discharged. On the other hand, when the sink switch S2 is set to a cut-off state, no discharge current flows from the memory cell MC to the ground voltage VSS node, and the discharge of the charge stored in the memory cell MC is stopped. The sink switch S2 includes, for example, an n-type MOS field effect transistor.

[0060] The sense amplifier switch S3 is set to a cut-off state when data is read from the memory cell MC based on the output signal of the delay circuit 53. On the other hand, it is set to a connected state when data is not read from the memory cell MC. The sense amplifier switch S3 is connected between the word line WL (or memory cell MC) and the sense amplifier SA. The sense amplifier switch S3 sets the state between the word line WL and the sense amplifier SA to either a connected state or a cut-off state based on the output signal of the delay circuit 53. The sense amplifier switch S3 includes, for example, an n-type MOS field effect transistor.

[0061] The relationship between the input and output of the positive and negative input terminals of the comparator CP, the number of inverter stages included in the delay circuit 53, and the polarity of the voltages that set the precharge switch S1, sink switch S2, and sense amplifier switch S3 to the connected or disconnected state can be set arbitrarily as long as the configuration is such that operation is established. For example, if the relationship between the input and output of the positive and negative input terminals of the comparator CP is reversed, the number of inverter stages in the delay circuit 53 is set to an odd number.

[0062] 2. Magnetic storage device read operation The read operation of the magnetic memory device 1 of the embodiment will be described with reference to Fig. 7. Fig. 7 is a diagram showing changes in the voltage of the memory cell MC during the read operation of the magnetic memory device 1. In Fig. 7, the horizontal axis represents time, and the vertical axis represents the voltage Vm of the memory cell MC. The voltage Vm of the memory cell MC is the voltage charged (or held) in the memory cell MC (or the selector element SE) and the word line WL, and is the voltage obtained by subtracting the voltage of the bit line BL from the voltage of the word line WL.

[0063] Here, we will explain the case where data stored in two memory cells MCa and MCb is read. Memory cells MCa and MCb may be the same memory cell that is read in different read cycles, or may be different memory cells connected to different word lines. The read operation is controlled by the control circuit 13 or the read circuit 17.

[0064] When reading from the memory cell MCa, the read circuit 17 charges the memory cell MCa to a precharge voltage Vpc and then discharges the charge stored in the memory cell MCa. The time when the voltage Vm of the memory cell MCa drops from voltage Vpc to voltage Va (i.e., time t2a) is detected as the time when discharge starts (i.e., discharge start timing). The read circuit 17 reads from the memory cell MCa after a predetermined delay time (or discharge time) A has elapsed from the discharge start timing (i.e., time t3a).

[0065] When reading from memory cell MCb, read circuit 17 charges memory cell MCb to precharge voltage Vpc and then discharges the charge stored in memory cell MCb. Here, the time when voltage Vm of memory cell MCb drops from voltage Vpc to voltage Va (i.e., time t2b) is detected as the discharge start timing. Read circuit 17 reads memory cell MCb after a predetermined delay time (or discharge time) B has elapsed from the discharge start timing (i.e., time t3b). Delay time B is the same as delay time A.

[0066] The read circuit 17 adjusts the read execution time t3a or t3b so that the time from the start of discharge to the execution of read is the same, in accordance with the time t2a when discharge starts from memory cell MCa or the time t2b when discharge starts from memory cell MCb. This reduces the variation in the interval (or time) from the discharge start timing to the execution of read (hereinafter referred to as read execution timing) caused by the variation in discharge start timing, and makes the interval from the discharge start timing to the read execution timing the same (or constant). This makes it possible to make the amount of discharge current from memory cells in the same resistance state (high resistance state or low resistance state) approximately the same, thereby reducing read errors for memory cells in the same resistance state.

[0067] 7, the voltages of the memory cells MCa and MCb at times t4a and t4b are the hold voltage Vh described above. The hold voltage Vh is the voltage when the sink switch S2 is kept connected until the discharge current stops flowing during discharging after the memory cell MCa or MCb has been charged to the precharge voltage Vpc. The hold voltages Vh of the memory cells MCa and MCb are approximately equal.

[0068] Furthermore, delay time A is set to a time (or interval) shorter than time t2a-t4a. As described above, time t2a is the timing at which discharge begins in memory cell MCa. Time t4a is the time at which voltage Vm of memory cell MCa reaches hold voltage Vh.

[0069] Similarly, delay time B is set to a time shorter than time t2b-t4b. Time t2b is the timing at which memory cell MCb starts discharging. Time t4b is the time at which voltage Vm of memory cell MCb reaches hold voltage Vh.

[0070] The read operation of the magnetic memory device 1 of the embodiment will be described in detail below with reference to Figures 7 to 12. Figure 8 is a flowchart showing the flow of the read operation of the magnetic memory device 1. Figures 9 to 12 are diagrams showing the states of the switches and the flow of current during the read operation.

[0071] First, the read operation for the memory cell MCa will be described.

[0072] The read circuit 17 charges the memory cell MCa (and the word line WL) to the precharge voltage Vpc (S1). Specifically, at time t0, as shown in FIG. 9, the control circuit 13 sets the precharge switch S1 and the sense amplifier switch S3 to a connected state (i.e., a closed state) and sets the sink switch S2 to a disconnected state (i.e., an open state). As a result, the precharge voltage Vpc is supplied from the power supply circuit 51 to the memory cell MCa (and the word line WL), and the memory cell MCa (and the word line WL) is charged to the precharge voltage Vpc.

[0073] Next, the read circuit 17 starts discharging the precharge voltage Vpc charged in the memory cell MCa (and the word line WL) (S2). Specifically, at time t1, as shown in FIG. 10, the read circuit 17 sets the precharge switch S1 to a cut-off state and sets the sink switch S2 to a connect state. The sense amplifier switch S3 remains connected. This stops the supply of the precharge voltage Vpc to the memory cell MCa (and the word line WL). Thereafter, as shown in FIG. 11, a discharge current Id starts flowing from the memory cell MCa (and the word line WL), and the voltage Vm of the memory cell MCa gradually drops from the precharge voltage Vpc.

[0074] Next, the read circuit 17 detects the timing when the voltage Vm of the memory cell MCa becomes lower than the voltage Va (i.e., the discharge start timing) (S3). Specifically, as shown in FIG. 11, a discharge current Id flows from the memory cell (and the word line WL) to the ground voltage VSS node via the bit line BL. Then, at time t2a, the comparator CP detects the discharge start timing when the voltage Vm of the memory cell MCa becomes lower than the voltage Va. When the voltage Vm of the memory cell MCa becomes lower than the voltage Va, the comparator CP switches its output signal from "L" to "H" and outputs "H."

[0075] Next, the read circuit 17 stops discharging from the memory cell MCa (and the word line WL) after a predetermined delay time A has elapsed since the discharge start timing of the memory cell MCa (S4). Specifically, the output signal "H" of the comparator CP is input to the delay circuit 53. The delay circuit 53 delays the received signal "H" by the predetermined delay time A and outputs it to the control terminals of the sink switch S2 and the sense amplifier switch S3. As shown in FIG. 12, when the sink switch S2 receives "H", it transitions from the connected state to the disconnected state. Similarly, when the sense amplifier switch S3 receives "H", it transitions from the connected state to the disconnected state. As a result, at time t3a, discharging from the memory cell MCa (and the word line WL) is stopped, and the voltage Vm of the memory cell MCa at this time is held in the sense amplifier SA.

[0076] Furthermore, the read circuit 17 executes a read operation on the memory cell MCa (S5). Specifically, the sense amplifier SA compares the voltage Vm of the memory cell MCa at time t3a with the reference voltage Vref, and determines the data stored in the memory cell MCa based on the comparison result.

[0077] Next, the read operation for the memory cell MCb will be described.

[0078] The read circuit 17 charges the memory cell MCb (and the word line WL) to the precharge voltage Vpc (S1). Specifically, at time t0, as shown in FIG. 9, the control circuit 13 sets the precharge switch S1 and the sense amplifier switch S3 to a connected state and sets the sink switch S2 to a disconnected state. As a result, the precharge voltage Vpc is supplied from the power supply circuit 51 to the memory cell MCb (and the word line WL), and the memory cell MCb (and the word line WL) is charged to the precharge voltage Vpc.

[0079] Next, the read circuit 17 starts discharging the precharge voltage Vpc charged in the memory cell MCb (and the word line WL) (S2). Specifically, at time t1, as shown in FIG. 10, the read circuit 17 sets the precharge switch S1 to a cut-off state and sets the sink switch S2 to a connect state. The sense amplifier switch S3 remains connected. This stops the supply of the precharge voltage Vpc to the memory cell MCb (and the word line WL). Thereafter, as shown in FIG. 11, a discharge current Id starts flowing from the memory cell MCb (and the word line WL), and the voltage Vm of the memory cell MCb gradually drops from the precharge voltage Vpc.

[0080] Next, the read circuit 17 detects the discharge start timing when the voltage Vm of the memory cell MCb becomes lower than the voltage Va (S3). Specifically, as shown in FIG. 11, a discharge current Id flows from the memory cell (and word line WL) through the bit line BL to the ground voltage VSS node. Then, at time t2b, the comparator CP detects the discharge start timing when the voltage Vm of the memory cell MCb becomes lower than the voltage Va. When the voltage Vm of the memory cell MCb becomes lower than the voltage Va, the comparator CP switches its output signal from "L" to "H" and outputs "H."

[0081] Next, the read circuit 17 stops discharging from the memory cell MCb (and the word line WL) after a predetermined delay time B has elapsed since the discharge start timing of the memory cell MCb (S4). Specifically, the output signal "H" of the comparator CP is input to the delay circuit 53. The delay circuit 53 delays the received signal "H" by the predetermined delay time B and outputs it to the control terminals of the sink switch S2 and the sense amplifier switch S3. As shown in FIG. 12, when the sink switch S2 receives "H", it transitions from the connected state to the disconnected state. Similarly, when the sense amplifier switch S3 receives "H", it transitions from the connected state to the disconnected state. As a result, at time t3b, discharging from the memory cell MCb (and the word line WL) is stopped, and the voltage Vm of the memory cell MCb at this time is held in the sense amplifier SA.

[0082] Furthermore, the read circuit 17 executes a read operation on the memory cell MCb (S5). Specifically, the sense amplifier SA compares the voltage Vm of the memory cell MCb at time t3b with the reference voltage Vref, and determines the data stored in the memory cell MCb based on the comparison result.

[0083] As described above, the read circuit 17 adjusts the read execution timing to time t3a or t3b according to the discharge start timing (time t2a) in memory cell MCa or the discharge start timing (time t2b) in memory cell MCb. This reduces the variation in the delay time (or discharge time) from the discharge start timing to the read execution timing caused by the variation in discharge start timing. This makes it possible to make the discharge times from the discharge start timing to the read execution timing in memory cells MCa and MCb approximately equal.

[0084] 3. Effects of the embodiment According to the magnetic storage device 1 of the embodiment, it is possible to reduce read errors in read operations and improve operational performance.

[0085] The effects of the embodiment will be described below.

[0086] For example, when reading a memory cell in a magnetic storage device, when a command is issued to start discharging the voltage charged in the memory cell, the time from the command to start discharging to the memory cell actually starting to discharge may vary depending on the read cycle or the memory cell being read. On the other hand, the time from the command to start discharging to the execution of the read is set to a constant. Therefore, even if the state of the variable resistance element is the same resistance state (high resistance state or low resistance state), the read voltage of the memory cell will vary depending on the timing when the memory cell actually starts to discharge. This may result in a read error.

[0087] In contrast, the embodiment includes a circuit that detects the discharge start timing in the memory cell MC (and word line WL), such as a comparator CP and a power supply circuit 52, and a delay circuit 53 that delays the detection signal of the discharge start timing by a predetermined delay time (or discharge time). This makes it possible to set the timing at which reading is performed to be after the predetermined delay time has elapsed from the timing at which the memory cell MC to be read actually starts discharging. Therefore, even if the discharge start timing in the memory cell MC varies, the discharge time from the actual discharge start timing to the timing at which reading is performed can be set to a constant. This makes it possible to reduce read errors in the read operation and improve operating performance.

[0088] Furthermore, in the embodiment, since the integrated amount of current flowing through the variable resistance element (for example, MTJ element) VR of the memory cell MC in the read operation can be reduced, read disturb can be suppressed.

[0089] Furthermore, in the embodiment, as described above, the amount of current accumulated in the variable resistance element VR can be reduced, thereby reducing the current load on the variable resistance element VR during a read operation and lengthening the lifespan of the variable resistance element VR before it becomes worn out.

[0090] Furthermore, in the embodiment, in the read operation, when discharging the memory cell MC (and word line WL) after charging it to the precharge voltage Vpc, the discharge current Id is stopped midway and reading is performed, so the time required for the read operation can be shortened compared to when reading is performed after the voltage of the memory cell MC reaches the hold voltage Vh without stopping the discharge current.

[0091] As described above, the magnetic storage device 1 of the embodiment can improve the operating performance.

[0092] 4.Other In this specification, "connected" refers to being electrically connected and does not exclude the presence of another element therebetween. The nonmagnetic layer 41 may also be called an "oxide layer." The elements contained in each layer of the MTJ element can be measured, for example, by using electron energy loss spectroscopy (EELS) using a scanning transmission electron microscope (STEM).

[0093] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, as well as within the scope of the invention described in the claims and their equivalents. [Explanation of symbols]

[0094] 1...magnetic memory device, 2...memory controller, 11...memory cell array, 12...input / output circuit, 13...control circuit, 14...row selection circuit, 15...column selection circuit, 16...write circuit, 17...read circuit, 20...conductor layer, 21...conductor layer, 30...lower electrode, 31...selector material layer, 32...upper electrode, 40...ferromagnetic layer, 41...non-magnetic layer, 42...ferromagnetic layer, 51...power supply circuit, 52...power supply circuit, 53...delay circuit, C1...capacitive element, R1...resistive element, S1...precharge switch, S2...sink switch, S3...sense amplifier switch

Claims

1. a memory cell including a variable resistance element and a selector element; a first power supply circuit that supplies a first voltage to the memory cell; a first switch connected between the memory cell and the first power supply circuit, for setting the state between the memory cell and the first power supply circuit to either a connected state or a disconnected state; a second switch connected between a ground voltage node to which a ground voltage is supplied and the memory cell, the second switch setting the state between the ground voltage node and the memory cell to either a connected state or a disconnected state; a comparator that compares the voltage of the memory cell with a second voltage that is lower than the first voltage, and outputs a first signal when the voltage of the memory cell drops below the second voltage; a delay circuit that delays the first signal output from the comparator by a first delay time and outputs a second signal; a sense amplifier that compares the voltage of the memory cell with a third voltage; a third switch connected between the memory cell and the sense amplifier, for setting the state between the memory cell and the sense amplifier to either a connected state or a disconnected state; In a read operation, The first switch is set to a connected state, the second switch is set to a disconnected state, and the memory cell is charged to the first voltage; After the memory cell is charged to the first voltage, the first switch is set to a cut-off state and the second switch is set to a connect state, thereby discharging the charge stored in the memory cell; In response to the second signal, the third switch is set to a cut-off state, and the sense amplifier compares the voltage of the memory cell with the third voltage to determine the data stored in the memory cell. Magnetic storage device.

2. In response to the second signal, the second switch is set to a cut-off state, and discharging of the charge stored in the memory cell is stopped.

2. The magnetic storage device according to claim 1.

3. After the memory cell is charged to the first voltage, the second switch is set to a connected state, the charge stored in the memory cell is discharged, and when the discharge stops, the voltage held by the memory cell is a fourth voltage. the second voltage is lower than the first voltage and higher than the fourth voltage; 2. The magnetic storage device according to claim 1.

4. the first delay time by the delay circuit is shorter than the time from when the comparator outputs the first signal to when the memory cell drops to the fourth voltage due to the discharge; 4. The magnetic storage device according to claim 3.

5. If the resistance component of the memory cell is R and the capacitance component is C, then the first delay time by the delay circuit is three times or less of a time constant that can be expressed by RC; 2. The magnetic storage device according to claim 1.

6. Further comprising a first wiring and a second wiring, the memory cell is connected between the first wiring and the second wiring; the first wiring is connected to the first switch, and the second wiring is connected to the second switch; the voltage of the memory cell includes a voltage held by the first wiring; 2. The magnetic storage device according to claim 1.

7. When the resistance component of the memory cell and the first wiring is R and the capacitance component is C, the first delay time by the delay circuit is three times or less of a time constant that can be expressed by RC; 7. The magnetic storage device according to claim 6.

8. In a read operation on the first memory cell and the second memory cell, a first time is a time period from when the comparator compares the voltage of the first memory cell with the second voltage and outputs a first signal to when the third switch is set to a cut-off state; When the time from when the comparator compares the voltage of the second memory cell with the second voltage and outputs a first signal to when the third switch is set to a cut-off state is a second time, the first time and the second time are equal; 2. The magnetic storage device according to claim 1.

9. a first wiring extending in a first direction and connected to the selector element; a second wiring extending in a second direction intersecting the first direction and connected to the variable resistance element; Furthermore, the first switch is connected between the first wiring and the first power supply circuit; the second switch is connected between the second wiring and the ground voltage node; When the first switch is set to a connected state, the first voltage is supplied from the first power supply circuit to the selector element and the first wiring, and the selector element and the first wiring are charged to the first voltage; When the second switch is set to a connected state, the charges stored in the selector element and the first wiring are discharged via the second wiring.

2. The magnetic storage device according to claim 1.

10. the selector element includes a bidirectional diode; 2. The magnetic storage device according to claim 1.

11. the first switch, the second switch, and the third switch include MOS field effect transistors; 2. The magnetic storage device according to claim 1.

12. the delay circuit includes an even number of inverters connected in series; 2. The magnetic storage device according to claim 1.

13. the delay circuit includes a first inverter, a second inverter, and a resistive element and a capacitive element connected between the first inverter and the second inverter; 2. The magnetic storage device according to claim 1.

14. the variable resistance element includes an MTJ (Magnetic Tunnel Junction) element, 2. The magnetic storage device according to claim 1.

15. the MTJ element includes a first ferromagnetic layer, a second ferromagnetic layer, and a nonmagnetic layer provided between the first ferromagnetic layer and the second ferromagnetic layer; 15. The magnetic storage device according to claim 14.

16. the first ferromagnetic layer contains at least one element selected from the group consisting of iron (Fe), cobalt (Co), and nickel (Ni); the nonmagnetic layer contains an oxide of at least one element or compound selected from the group consisting of magnesium (Mg), aluminum (Al), zinc (Zn), titanium (Ti), and LSM (Lanthanum-strontium-manganese); the second ferromagnetic layer contains at least one element selected from the group consisting of iron (Fe), cobalt (Co), and nickel (Ni); 16. The magnetic storage device according to claim 15.

17. each of the first ferromagnetic layer and the second ferromagnetic layer has an easy axis of magnetization in a direction perpendicular to a film surface; the magnetization direction of the first ferromagnetic layer is fixed; The magnetization direction of the second ferromagnetic layer is configured to be easily reversed compared to the magnetization direction of the first ferromagnetic layer.

16. The magnetic storage device according to claim 15.

18. a first conductive layer extending in a first direction; a second conductive layer extending in a second direction intersecting the first direction and spaced apart from the first conductive layer; the memory cell is provided between the first conductive layer and the second conductive layer; 2. The magnetic storage device according to claim 1.

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