Capacity calculation method for semiconductor circuit and capacity calculation program for semiconductor circuit

Abstract

To provide a method for calculating a capacity value of an LSI including a CMOS circuit in a state where a power supply voltage is applied to the LSI by modeling a capacity of the LSI between a power source and a GND.SOLUTION: In a capacity calculation method for a semiconductor circuit, a computer executes: calculating a charge curve during charging of a CR (Capacitor Resistance) charge circuit including a resistor, to which a voltage of a first power source is applied, and a CMOS (Complementary Metal Oxide Semiconductor) circuit connected in series to the resistor by charging the CR charge circuit until a voltage of a second power source applied between the resistor and the CMOS circuit becomes equal to the voltage of the first power source; and calculating a capacity between the first power source and a ground of the CMOS circuit at the time when the voltage of the first power source is applied, in a case where the CMOS circuit is regarded as a single capacitive element based on the charge curve.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present disclosure relates to a method for calculating the capacitance of a semiconductor circuit and a program for calculating the capacitance of a semiconductor circuit. [Background technology]

[0002] In semiconductor integrated circuits, measures are taken to bypass and block noise components by placing capacitors and inductors between the power supply and GND. Patent Document 1 discloses a technology for efficiently placing decoupling capacitors required to suppress power supply noise in semiconductor integrated circuits within a predetermined allowable range. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent No. 5161035 Summary of the Invention [Problem to be solved by the invention]

[0004] However, in semiconductor integrated circuits, particularly CMOS (Complementary Metal Oxide Semiconductor) circuits, the capacitance between the power supply and ground can change significantly depending on whether or not a power supply voltage is applied. Conventional technology does not take into account changes in capacitance between the power supply and ground when a power supply voltage is applied, and therefore may not be able to properly bypass noise components. As such, conventional technology has room for improvement in terms of properly calculating the capacitance between the power supply and ground of semiconductor circuits when a power supply voltage is applied, i.e., when the circuit is operational.

[0005] In view of the above circumstances, the present disclosure aims to provide an invention for appropriately calculating the capacitance between the power supply and GND of a semiconductor circuit. [Means for solving the problem]

[0006] In order to solve the above problem, the capacitance calculation method for a semiconductor circuit according to the present disclosure is executed by a computer, which calculates a charging curve of the CR charging circuit when charging, by charging a CR (Capacitor Resistance) charging circuit including a resistor to which a voltage of a first power supply is applied and a CMOS (Complementary Metal Oxide Semiconductor) circuit connected in series with the resistor, until a voltage of a second power supply applied between the resistor and the CMOS circuit becomes equal to the voltage of the first power supply, and calculates, based on the charging curve, the capacitance between the first power supply and the ground of the CMOS circuit when the voltage of the first power supply is applied, when the CMOS circuit is considered to be a single capacitive element.

[0007] In order to solve the above problem, the capacitance calculation program for a semiconductor circuit according to the present disclosure causes a computer to execute the following steps: charge a CR charging circuit including a resistor to which a voltage of a first power supply is applied and a CMOS circuit connected in series with the resistor until a voltage of a second power supply applied between the resistor and the CMOS circuit becomes equal to the voltage of the first power supply; calculate a charging curve of the CR charging circuit when charging; and calculate, based on the charging curve, the capacitance between the first power supply and the ground of the CMOS circuit when the voltage of the first power supply is applied, when the CMOS circuit is considered to be a single capacitive element. [Brief explanation of the drawings]

[0008] [Figure 1A] FIG. 1A is a diagram for explaining the premise for explaining an embodiment of the present disclosure. [Figure 1B] FIG. 1B is a diagram for explaining the premise for explaining the embodiment of the present disclosure. [Figure 2] FIG. 2 is a diagram for explaining the premise for explaining the embodiment of the present disclosure. [Figure 3] FIG. 3 is a diagram showing an example of the configuration of a simulation circuit 100 to which a capacitance calculation method for a semiconductor circuit according to an embodiment of the present disclosure is applied. [Figure 4A]FIG. 4A is a diagram for explaining a method for calculating the capacitance of the semiconductor circuit 200 according to an embodiment of the present disclosure. [Figure 4B] FIG. 4B is a diagram for explaining a method for calculating the capacitance of the semiconductor circuit 200 according to an embodiment of the present disclosure. [Figure 4C] FIG. 4C is a diagram for explaining a method for calculating the capacitance of the semiconductor circuit 200 according to an embodiment of the present disclosure. [Figure 5] FIG. 5 is a diagram for explaining a method for calculating the capacitance of the semiconductor circuit 200 according to an embodiment of the present disclosure. [Figure 6] FIG. 6 is a diagram for explaining the charging characteristics of the CR charging circuit 202 obtained by the capacitance calculation method (simulation) of the present disclosure. [Figure 7] FIG. 7 is a diagram for explaining the charging characteristics of the CR charging circuit 202 obtained by the capacitance calculation method (simulation) of the present disclosure. [Figure 8] FIG. 8 is a diagram showing an example of the configuration of a circuit to which a capacitance calculation method for a semiconductor circuit 200A according to a modification of the present disclosure is applied. [Figure 9] FIG. 9 is a diagram for explaining a method for calculating the capacitance of a semiconductor circuit 200A according to a modification of the present disclosure. [Figure 10] FIG. 10 is a block diagram showing the hardware configuration of the information processing device 10. As shown in FIG. DETAILED DESCRIPTION OF THE INVENTION

[0009] Hereinafter, embodiments will be described with reference to the drawings. Note that the same or similar reference numerals are used to designate the same functions or configurations, and descriptions thereof will be omitted as appropriate.

[0010] (Embodiment) The present disclosure relates to a method for modeling the capacitance between a power supply and a GND of a semiconductor integrated circuit (LSI: Large Scale Integration) mounted on an electronic device, particularly a CMOS (Complementary Metal Oxide Semiconductor) LSI, and calculating the capacitance value of the LSI when a power supply voltage is applied to the LSI including the CMOS circuit. Premise for describing embodiments of the present disclosure will be described with reference to FIGS. 1A, 1B, and 2.

[0011] Electronic devices are increasingly adopting and incorporating LSIs that are becoming increasingly miniaturized and highly integrated. As the main functions of electronic devices are increasingly concentrated in LSIs, noise performance is also becoming increasingly dependent on LSIs. To improve the noise performance of LSIs, the following circuit measures are being applied within the LSI. (1) Filter measures to remove noise even if it is injected into the input signal or power supply. (2) A countermeasure using a synchronous circuit design that does not pick up even momentary noise. (3) A majority voting circuit that compares multiple circuit states and estimates the correct state.

[0012] Outside the LSI, there is a measure to bypass and block noise components by installing a capacitor or inductor between the power supply and GND terminals.

[0013] Generally, LSIs are treated as an LCR equivalent circuit when it comes to noise. Here, L is the package inductance, C is the terminal capacitance of the LSI, and R is the resistance of the package lead frame, wires, and the power supply main line of the LSI.

[0014] Here, L and R are proportional to the length of the package lead, and L is set to 0.7nH / mm to 1.0nH / mm according to Ampere's law. R is calculated from the sheet resistance ρ of the lead frame, wire, etc., as ρ / cross-sectional area [Ω / mm].

[0015] However, the conventional capacitance calculation method disclosed in Patent Document 1 has the following problems. (A) The difference in capacitance value due to whether or not voltage is applied to the gate of a CMOS transistor is not taken into consideration. (B) The junction capacitance between the power supply and output, and between the output and GND in CMOS transistor circuits, especially in basic logic elements such as inverters and NAND gates, is not taken into consideration. (C) It is not taken into consideration that the capacitance value changes depending on the voltage applied to each input terminal of each logic element.

[0016] In particular, there are cases where the capacitance value of (C) changes significantly depending on whether or not voltage is applied. This is shown in Figures 1A and 1B using an NMOS capacitor circuit in which the source and drain are connected to the same GND and the gate is connected to the power supply VDD. When no voltage is applied to the gate, the gate-bulk capacitance, i.e., the VDD-GND capacitance, is equal to the gate capacitance C G and the depletion layer capacitance C dep When a voltage is applied to the gate, the depletion layer becomes an inversion layer, and C G (See Figure 1B.)

[0017] VDD-GND capacitance C when no voltage is applied off is 1 / C off =1 / C G +1 / C dep From C off =(C G ×C dep ) / (C G +C dep ) and the VDD-GND capacitance C on is C on ≒C G In general, C dep Since is small, C off ≒C dep and C on ≫C off This becomes:

[0018] Therefore, if the circuit configuration and whether or not voltage is applied are not taken into account when estimating, large differences will occur. Even for basic gates, large differences can occur depending on the circuit configuration and the state of each terminal. In addition, the source-drain junction capacitance also changes depending on the state of the drain.

[0019] When C is treated as an LRC equivalent circuit of an LSI, the desired noise can be removed near the cutoff frequency fc. In the case of an LSI, the cutoff frequency fc can be calculated from the inductance L of the package lead frame and the chip capacitance C (see Figure 2).

[0020] However, even if a capacitance C is inserted with fc=30MHz, when the applied voltage is taken into consideration, C' actually becomes 2C, so the cutoff frequency f'c drops to 20MHz as shown in equation (1).

[0021]

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[0022] Furthermore, when trying to achieve the initial target value, an extra capacitance C' of 30% is actually placed when voltage is applied compared to the capacitance C calculated in the conventional example, which wastes area and leads to increased costs.

[0023] However, there are few examples of estimating capacitance taking into consideration whether or not a voltage is applied to each element, and even if there are such examples, they have been carried out through complex calculations and simulations.

[0024] Based on this premise, in this disclosure, we model the capacitance between the power supply and GND of an LSI, particularly a CMOS LSI, and calculate the VDD-GND capacitance C of the LSI when a power supply voltage is applied to the LSI including a CMOS circuit. on A method for calculating the above will be explained.

[0025] FIG. 3 is a diagram showing an example of the configuration of a simulation circuit 100 to which a capacitance calculation method for a semiconductor circuit according to an embodiment of the present disclosure is applied.

[0026] The simulation circuit 100 may include a switch SW, a resistor R to which the voltage of the first power supply VDD is applied via the switch SW, and a semiconductor circuit 200.

[0027] The semiconductor circuit 200 may be interpreted as an LSI. The semiconductor circuit 200 may include a CMOS circuit 201.

[0028] The CMOS circuit 201 and the resistor R may be connected in series between the first power supply VDD and the GND of the semiconductor circuit 200 to form a CR charging circuit 202.

[0029] The voltage of the second power supply VDDC is generated between the resistor R and the CMOS circuit 201. The second power supply VDDC may be interpreted as a charging voltage generated when the CR charging circuit 202 is charging.

[0030] The logic elements and capacitance circuits that make up the semiconductor circuit 200 are equivalent to the capacitance C on Therefore, the simulation circuit 100 is configured with a first power supply VDD, a resistor R, and a capacitor C on Therefore, based on the resistance value of the resistor R and the charging time of the CR charging circuit 202, the capacitance C on can be obtained.

[0031] Therefore, in the capacitance calculation method for the semiconductor circuit 200 according to the embodiment of the present disclosure, the CR charging circuit 202 is charged until the voltage of the second power supply VDDC applied between the resistor and the CMOS circuit 201 becomes equal to the voltage of the first power supply VDD, thereby calculating a charging curve of the CR charging circuit 202 when it is being charged, and based on this charging curve, the capacitance C between the first power supply VDD and the GND (ground) of the CMOS circuit 201 when the voltage of the first power supply VDD is applied is calculated when the CMOS circuit is considered as a single capacitive element. on Calculate.

[0032] Next, a method for calculating the capacitance of the semiconductor circuit 200 according to an embodiment of the present disclosure will be described in detail with reference to FIGS. 4A to 5. FIGS. 4A to 5 are diagrams for explaining the method for calculating the capacitance of the semiconductor circuit 200 according to an embodiment of the present disclosure. FIG. 5 shows a charging curve (charging characteristics) during charging of the CR charging circuit 202. The vertical axis of FIG. 5 represents the charging voltage, i.e., the voltage of the second power supply VDDC. The horizontal axis of FIG. 5 represents time.

[0033] After the first power supply VDD starts up, a charging current i flows through resistor R (see Figure 4A), causing the voltage of the second power supply VDDC of the LSI to rise. When the voltage of the second power supply VDDC rises to a certain potential, the LSI, particularly the circuits that form inverters and logic gates using PMOS and NMOS, enter the ON state, and a through current ip flows between the second power supply VDDC and GND (see Figure 4B). At this time, the current from the first power supply VDD cannot charge the second power supply VDDC, and the voltage of the second power supply VDDC stagnates at the midpoint potential of the first power supply VDD.

[0034] As shown in Figure 5, the charging time τ1 from the start of charging until the through current ip starts to flow is the same as the capacitance C on does not represent the capacitance when voltage is applied to the LSI.

[0035] As shown in Figure 5, during the period τ2 when the through current ip flows, the LSI is not a capacitance component but a resistance component, so during this period too, the capacitance C on It cannot be applied to calculate

[0036] If the charging current i continues to flow from this state (see Figure 4C), the voltage of the first power supply VDD will gradually increase, and the transistors in the LSI will transition to a stable state in which they are either in the ON state or the OFF state. The time (time) at which this stable state is reached is defined as t@VDD START Let's say.

[0037] After that, charging continues and eventually VDD becomes approximately equal to VDDC. The time (time) when the voltage of the first power supply VDD becomes 90% of the voltage of the second power supply VDDC is called t@VDD. 90% Then, the charging time τ3 is calculated using equation (2).

[0038]

number

[0039] Once the charging time τ3 is obtained, the voltage of the second power supply VDDC is calculated using equation (3), that is, according to the charging time equation of the RC charging circuit.

[0040]

number

[0041] From equation (3), if the time (point in time) when the voltage of the second power supply VDDC is 10% of the voltage of the first power supply VDD is defined as t10, and the time (point in time) when the voltage of the second power supply VDDC is 90% of the voltage of the first power supply VDD is defined as t90, then the results shown in equations (4) and (5) can be obtained.

[0042]

number

[0043]

number

[0044] Therefore, if t90-t10≒τ, the capacitance C on can be calculated according to equations (6) and (7).

[0045]

number

[0046]

number

[0047] This is the case when the voltage of the first power supply VDD is 10% to 90%. In this case, the time immediately after the through current ip flows and the start of recharging is t START , and voltage VDD START In this case, the voltage ratio between the first power supply VDD and the second power supply VDDC is: ratio=VDD START If / VDDC, the capacitance C oncan be calculated using equation (8). Note that whether or not the battery is being recharged can be determined automatically by checking that the value of the through current ip has changed from an increase to a decrease.

[0048]

number

[0049] By using the above method, the capacitance C between the power supply and GND when power is applied to an LSI circuit using a CMOS transistor on can be calculated.

[0050] 6 and 7, a capacitance C on The simulation netlist may be interpreted as a simulation circuit diagram.

[0051] 6 and 7 are diagrams for explaining the charging characteristics of the CR charging circuit 202 obtained by the capacity calculation method (simulation) of the present disclosure.

[0052] Fig. 6 shows a simulation netlist of the SRAM circuit. Fig. 7 shows the charging characteristics of the CR charging circuit 202 obtained by the capacitance calculation method (simulation) of the present disclosure using the simulation netlist of Fig. 6. Specifically, Fig. 7 shows the charging characteristics of the CR charging circuit 202 obtained by the capacitance calculation method (simulation) of the present disclosure using the simulation netlist of Fig. 6. on Calculate the resulting capacity C on 7, the charging curve (charging characteristics) of the CR charging circuit 202 calculated by the method described above is superimposed on the charging curve of the actual CR charging circuit 202. The solid line is the charging curve calculated by the capacity calculation method of the present disclosure, and the dashed line is the charging curve of the actual CR charging circuit 202. As shown in FIG. 7, the capacitance C on It can be seen that the charging curve of the CR charging circuit 202 obtained by the simulation is substantially consistent with the actual one.

[0053] In this way, in the capacitance calculation method of the present disclosure, when a period τ2 appears in the charging curve in which the through current ip flows through the CMOS circuit 201 after a certain time from the start of charging, the capacitance C on may be calculated.

[0054] In addition, in the capacitance calculation method of the present disclosure, the capacitance C is calculated based on the charging time τ3 after the through current ip has finished flowing and the resistance value of the resistor R. on may be calculated.

[0055] (Variation) For circuits with a relatively small circuit scale, such as SRAM circuits and analog circuits, the capacitance C on However, with the advancement of miniaturization and high functionality in current LSIs, where the logic scale has reached several million gates, it is difficult to calculate the capacitance of all elements that exist between the same power supply and ground.

[0056] Therefore, in the modified example, a method for estimating the capacitance of the LSI logic section is disclosed. Since the logic scale of the LSI is calculated in terms of two-input NAND gates, the capacitance C between the power supply and GND of the two-input NAND gate is calculated as follows: NAND Calculate the capacity C NAND By multiplying this by the number of logic gates N, the capacitance C Logic =C NAND Get ×N.

[0057] Capacity C Logic In calculating the capacitance C, a 2NAND gate circuit (a simulation circuit 100A in FIG. 8 described later) may be used instead of the simulation circuit 100 that was the calculation target in the above-described embodiment. In order to obtain a certain degree of current accuracy, the simulation circuit 100 may be configured by connecting a plurality of 2NAND gate circuits in parallel. In addition, the state of the two input terminals is calculated for all states (=4 ways) of the 2NAND gate. Logic The load of the 2NAND gate is the average wiring length capacitance load C Wire It may also be possible to use the following.

[0058] FIG. 8 is a diagram illustrating an example of a circuit configuration to which a capacitance calculation method for a semiconductor circuit 200A according to a modified example of the present disclosure is applied. The simulation circuit 100A illustrated in FIG. 8 may include a switch SW, a resistor R to which a voltage of a first power supply VDD is applied via the switch SW, and a semiconductor circuit 200A. The semiconductor circuit 200A may be interpreted as an LSI. The semiconductor circuit 200A may include a CMOS circuit 201A. The CMOS circuit 201A and the resistor R may be connected in series between the first power supply VDD and the GND of the semiconductor circuit 200A to form a CR charging circuit 202A. The CMOS circuit 201A may be interpreted as a basic element of an LSI logic unit, or as a two-input NAND gate.

[0059] A capacitance calculation method for the semiconductor circuit 200A according to the modified example will be specifically described below. In the capacitance calculation method (simulation) according to the modified example of the present disclosure, a two-input NAND gate, which is a basic element of an LSI logic unit including the CMOS circuit 201A, is used as one unit, and the capacitance of the two-input NAND gate (the capacitance C between the power supply and GND of the two-input NAND gate) is calculated. NAND ) and calculate the capacity C NAND is multiplied by the gate size N (capacity C Logic ) can be treated as the capacity of the LSI logic section.

[0060] Specifically, in a capacitance calculation method (simulation) according to a modified example of the present disclosure, the capacitance for each of four input patterns for the first and second inputs of a two-input NAND gate is calculated, and the sum of the calculated capacitances for the four input patterns is divided by four, which can be treated as the capacitance of one NAND gate.

[0061] The capacitance calculation method according to the modified example of the present disclosure will be described more specifically with reference to Fig. 9. Fig. 9 is a diagram for explaining the capacitance calculation method of the semiconductor circuit 200A according to the modified example of the present disclosure.

[0062] As described above, after the first power supply VDD is activated, a charging current i flows through the resistor R.

[0063] However, the capacitance of a NAND gate differs depending on the voltage applied to input terminals A and B. For example, when A=B=L, that is, when the voltage applied to input terminals A and B is low level L (GND), the capacitance of the PMOS included in the NAND gate is the capacitance when the power is ON, but the capacitance of the NMOS included in the NAND gate is the same as the capacitance when the power is OFF.

[0064] As a result, Y=H (=VDDC), that is, the voltage of the output terminal Y becomes high level L, and the source-drain capacitance of the PMOS is not visible, but the source-drain capacitance of the NMOS is indirectly visible. Furthermore, as a charge capacitance, the load wiring C of the output terminal Y wire Includes:

[0065] On the other hand, when A=B=H (=VDDC), that is, when the applied voltage to input terminal A and input terminal B is high level L, the capacitance of the PMOS is the capacitance when the power is OFF, but the capacitance of the NMOS is the same as the capacitance when the power is ON.

[0066] This results in Y=L (=GND), and the charge capacity is the load wiring C of the output terminal Y. wire Also, the source-drain capacitance of the PMOS is visible, but the source-drain capacitance of the NMOS is not.

[0067] In a large-scale LSI, it is completely unknown which state each gate can take, so the capacitance for each of the four input patterns for the first and second inputs of a two-input NAND gate is calculated as the probability that capacitance will appear equally for these four states. Then, as shown in equation (9), the capacitances of the four input patterns (C1 to C4) are added together and the total value is divided by 4. This value is used as the capacitance C of one NAND gate. NAND It may be treated as such.

[0068]

number

[0069] LSI logic capacity CLogic As shown in equation (10), the capacitance C of one NAND gate obtained in equation (9) NAND This is obtained by multiplying by the logic scale N[Gate].

[0070]

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[0071] If the capacitances of the SRAM, analog, and MOS capacitors other than the LSI logic section are obtained by the simulation according to the above-described embodiment, the capacitance C chip can be calculated using equation (11).

[0072]

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[0073] Fig. 10 is a block diagram showing the hardware configuration of the information processing device 10. Fig. 10 is a block diagram showing the hardware configuration of the information processing device 10. The information processing device 10 is, for example, a smartphone, a tablet terminal, or a personal computer. The information processing device 10 is an example of a "computer."

[0074] The information processing device 10 includes a CPU (Central Processing Unit) 11, a ROM (Read Only Memory) 12, a RAM (Random Access Memory) 13, a storage 14, a display 15, a speaker 16, an external I / F (Interface) 17, a communication I / F 18, and an input I / F 19. Each component is connected to each other via a bus 20 so as to be able to communicate with each other.

[0075] The CPU 11 is a central processing unit that executes various programs and controls each part.

[0076] The ROM 12 stores various programs and various data. The RAM 13 serves as a working area for temporarily storing programs or data.

[0077] The storage 14 is configured by a storage device such as a hard disk drive (HDD), a solid state drive (SSD), or a flash memory, and stores various programs and various data.

[0078] The display 15 is, for example, a liquid crystal display, and displays various types of information. In the embodiment of the present disclosure, the display 15 is integrated with the information processing device 10. However, this is not a limitation, and the display 15 may be separate from the information processing device 10. Also, in the embodiment of the present disclosure, the display 15 does not have a touch panel. However, this is not a limitation, and the display 15 may have a touch panel integrally. The display 15 is an example of a display unit.

[0079] The speaker 16 outputs various sounds. The external I / F 17 is an interface for connecting an external device to the information processing device 10. The external device is a recording medium 30, for example.

[0080] The recording medium 30 may be a CD-ROM (Compact Disk Read Only Memory), a DVD-ROM (Digital Versatile Disk Read Only Memory), a USB (Universal Serial Bus) memory, an SD memory card, or the like. The recording medium 30 stores a program 30A (a capacity calculation program) for executing the above simulation in the information processing device 10. The CPU 11 reads the program 30A from the recording medium 30 via the external I / F 17 and executes the program 30A using the RAM 13 as a working area. Note that the program 30A is not limited to being stored on the recording medium 30, and may be stored in advance in the storage 14 of the information processing device 10, or may be downloadable to the information processing device 10 via a network.

[0081] The communication I / F 18 is an interface for connecting the information processing device 10 to a network. The communication I / F 18 uses, for example, a wired communication standard such as Ethernet (registered trademark) or FDDI, or a wireless communication standard such as 4G, 5G, or Wi-Fi (registered trademark).

[0082] The input I / F 19 is an interface for connecting to the input device 40. The input device 40 is a controller having operation buttons and directional keys, a mouse, a keyboard, etc., and is used to perform various inputs. Operation information indicating the content of the input operation performed by the user using the input device 40 is stored in the RAM 13. The input device 40 may be separate from the information processing device 10, or may be integrated with the information processing device 10. The input device 40 may be detachable from the information processing device 10. The number of input devices 40 may be one or more.

[0083] In the above embodiment, the control processing executed by the CPU 11 after reading the software (program) may be executed by various processors other than a CPU. Examples of such processors include programmable logic devices (PLDs) such as field-programmable gate arrays (FPGAs), whose circuit configuration can be changed after fabrication, and dedicated electrical circuits such as application-specific integrated circuits (ASICs), which are processors with circuit configurations specifically designed to execute specific processing. The control processing may be executed by one of these processors, or by a combination of two or more processors of the same or different types (e.g., multiple FPGAs, or a combination of a CPU and an FPGA). The hardware structure of these processors is, more specifically, an electrical circuit that combines circuit elements such as semiconductor devices.

[0084] (Action, effect) As described above, the capacitance calculation method for the semiconductor circuit 200 of the present disclosure calculates a charging curve when the CR charging circuit 202 is charged by charging the CR charging circuit 202 until the voltage of the second power supply VDDC becomes equal to the voltage of the first power supply VDD, and calculates the capacitance C between the first power supply VDD and the GND (ground) of the CMOS circuit 201 when the voltage of the first power supply VDD is applied, when the CMOS circuit 201 is considered as a single capacitive element, based on the charging curve. on The computer executes the calculation.

[0085] This makes it possible to estimate the capacitance of the logic part of the LSI. Furthermore, by estimating SRAM and analog in the same way, it is possible to estimate the capacitance of the entire LSI circuit connected to the same power supply. If one were to try to obtain the capacitance of the entire LSI through simulation, it would take an enormous amount of time (on the order of days to weeks) to extract the silicon circuit and perform the simulation, but with this method, once the element capacitance is obtained, it becomes easy to estimate the capacitance of the entire LSI by simply preparing the scale of each circuit.

[0086] Furthermore, with regard to the step of calculating the capacitance value from recharging after the through current ip has stopped flowing, a mechanism can be easily applied that automatically calculates the value as a program after determining the operation of the through current ip.

[0087] For elements that do not allow through current to flow, such as MOS capacitors, if the circuit operation is predicted in advance and it is specified that no through current will flow, the same method can be used to calculate the transition time from 10% to 90% of the power supply voltage VDD.

[0088] The capacitance C of the entire LSI compared to the target capacitance value chip If the capacitance C of the entire LSI is insufficient, it is possible to determine how much MOS capacitance should be added and to program and implement CAD (Computer Aided Design) to automatically place the MOS capacitance on the chip layout. chip This can be interpreted as a CAD program that automatically estimates the capacitance C of the entire LSI when calculating logic gates based on RLT.chip The capacitance calculation program of the present disclosure can be interpreted as a CAD program for estimating the capacitance C of the entire LSI when the number of gates is estimated in the overall LSI design. chip It can be interpreted as a CAD program that automatically calculates the required capacitance. For example, when programming a target capacitance value during LSI design, the number of elements corresponding to the required function of the entire LSI is known at the element level, and once the number of elements is known, the capacitance corresponding to the number of elements is known, so the capacitance required to improve the noise resistance of the LSI can be determined. This required capacitance can be compensated for.

[0089] In this way, the capacitance calculation program for a semiconductor circuit of the present disclosure charges the CR charging circuit 202 until the voltage of the second power supply VDDC becomes equal to the voltage of the first power supply VDD, thereby calculating a charging curve when the CR charging circuit 202 is being charged, and based on the charging curve, calculating the capacitance C between the first power supply VDD and the GND (ground) of the CMOS circuit 201 when the voltage of the first power supply VDD is applied, when the CMOS circuit 201 is considered as a single capacitive element. on The computer may be caused to calculate:

[0090] Furthermore, the capacitance calculation program for the semiconductor circuit of the present disclosure calculates the calculated capacitance C on If the capacitance is insufficient for the target capacitance, MOS capacitors may be automatically placed in the chip layout.

[0091] In addition, the following supplementary notes are provided in relation to the above description.

[0092] (Appendix 1) A CR (Capacitor Resistance) charging circuit including a resistor to which a voltage of a first power supply is applied and a CMOS (Complementary Metal Oxide Semiconductor) circuit connected in series with the resistor is charged until a voltage of a second power supply applied between the resistor and the CMOS circuit becomes equal to the voltage of the first power supply, thereby calculating a charging curve during charging of the CR charging circuit; Calculating a capacitance between the first power supply and a ground of the CMOS circuit when the voltage of the first power supply is applied, based on the charging curve, when the CMOS circuit is regarded as a single capacitive element; A computer-implemented method for calculating the capacitance of a semiconductor circuit. (Appendix 2) The method for calculating the capacitance of a semiconductor circuit according to claim 1, wherein, in the charging curve, if a period in which a through current flows through the CMOS circuit appears after a certain time from the start of charging, the period is excluded and the capacitance is calculated from the time when the voltage of the first power supply starts to rise again after the through current has stopped flowing. (Appendix 3) 3. The method for calculating the capacitance of a semiconductor circuit according to claim 2, wherein the capacitance is calculated based on the charging time after the through current has stopped flowing and the resistance value of the resistor. (Appendix 4) Calculating the capacitance of a two-input NAND gate, which is a basic element of an LSI (Large Scale Integration) logic unit including the CMOS circuit, as one unit; 4. The capacitance calculation method for a semiconductor circuit according to any one of appendices 1 to 3, wherein a value obtained by multiplying the capacitance of the two-input NAND gate by a gate scale is treated as the capacitance of the LSI logic section. (Appendix 5) 5. The capacitance calculation method for a semiconductor circuit according to claim 4, wherein the capacitance is calculated for each of four input patterns for the first input and the second input of the two-input NAND gate, and the sum of the calculated capacitances for the four input patterns is divided by 4, and the resulting value is treated as the capacitance of one NAND gate. (Appendix 6) A CR (Capacitor Resistance) charging circuit including a resistor to which a voltage of a first power supply is applied and a CMOS (Complementary Metal Oxide Semiconductor) circuit connected in series with the resistor is charged until a voltage of a second power supply applied between the resistor and the CMOS circuit becomes equal to the voltage of the first power supply, thereby calculating a charging curve during charging of the CR charging circuit; Calculating a capacitance between the first power supply and a ground of the CMOS circuit when the voltage of the first power supply is applied, based on the charging curve, when the CMOS circuit is regarded as a single capacitive element; A semiconductor circuit capacitance calculation program that causes a computer to execute this. (Appendix 7) 7. The semiconductor circuit capacitance calculation program according to claim 6, wherein, if the calculated capacitance is insufficient for a target capacitance, a MOS (Metal Oxide Semiconductor) capacitance is automatically placed in a chip layout. [Explanation of symbols]

[0093] 10. Information processing equipment 14. Storage 15 Display 16 speakers 17 External I / F 18 Communication I / F 19 Input I / F 20 Bus 30 Recording media 30A Program 40 Input Devices 100 Simulation Circuit 100A simulation circuit 200 Semiconductor Circuits 200A semiconductor circuit 201 CMOS Circuits 201A CMOS circuit 202 Charging circuit 202A charging circuit

Claims

1. a CR (Capacitor Resistance) charging circuit including a resistor to which a voltage of a first power supply is applied and a CMOS (Complementary Metal Oxide Semiconductor) circuit connected in series with the resistor, is charged until a voltage of a second power supply applied between the resistor and the CMOS circuit becomes equal to the voltage of the first power supply, thereby calculating a charging curve of the CR charging circuit during charging; Calculating a capacitance between the first power supply and a ground of the CMOS circuit when the voltage of the first power supply is applied, based on the charging curve, when the CMOS circuit is regarded as a single capacitive element; A computer-implemented method for calculating the capacitance of a semiconductor circuit.

2. 2. The method for calculating the capacitance of a semiconductor circuit according to claim 1, wherein, in the charging curve, if a period in which a through current flows through the CMOS circuit appears after a certain time from the start of charging, the period is excluded and the capacitance is calculated from the time when the voltage of the first power supply starts to rise again after the through current has stopped flowing.

3. 3. The method for calculating the capacitance of a semiconductor circuit according to claim 2, wherein the capacitance is calculated based on the charging time after the through current has stopped flowing and the resistance value of the resistor.

4. A two-input NAND gate, which is a basic element of an LSI (Large Scale Integration) logic unit including the CMOS circuit, is taken as one unit, and the capacitance of the two-input NAND gate is calculated; 2. The method for calculating capacitance of a semiconductor circuit according to claim 1, wherein a value obtained by multiplying the capacitance of the two-input NAND gate by a gate scale is treated as the capacitance of the LSI logic section.

5. 5. The capacitance calculation method for a semiconductor circuit according to claim 4, wherein the capacitance for each of four input patterns for the first input and the second input of the two-input NAND gate is calculated, and the sum of the calculated capacitances for the four input patterns is divided by 4, and the resulting value is treated as the capacitance of one NAND gate.

6. a CR (Capacitor Resistance) charging circuit including a resistor to which a voltage of a first power supply is applied and a CMOS (Complementary Metal Oxide Semiconductor) circuit connected in series with the resistor, is charged until a voltage of a second power supply applied between the resistor and the CMOS circuit becomes equal to the voltage of the first power supply, thereby calculating a charging curve of the CR charging circuit during charging; Calculating a capacitance between the first power supply and a ground of the CMOS circuit when the voltage of the first power supply is applied, based on the charging curve, when the CMOS circuit is regarded as a single capacitive element; A semiconductor circuit capacitance calculation program that causes a computer to execute this.

7. 7. The semiconductor circuit capacitance calculation program according to claim 6, wherein when the calculated capacitance is insufficient for a target capacitance, a MOS (Metal Oxide Semiconductor) capacitance is automatically placed in the chip layout.

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