Semiconductor storage device

Abstract

To provide a memory capable of reducing power consumption.SOLUTION: A memory includes a first data line and a first control line for writing, and a second data line and a second control line for reading. A memory cell includes a first transistor having a gate connected to the first control line and one end connected to the first data line, a second transistor having a gate connected to the second control line and one end connected to the second data line, and a third transistor having a gate connected to the other end of the first transistor and one end connected to the other end of the second transistor. A detection circuit is connected to the first and second data lines. When writing or reading data, a control unit activates the second control line, and after the detection circuit detects the first data based on the voltage of the second data line, the control unit activates the first control line. After receiving a writing command, the detection circuit transmits second data to the gate of the third transistor when latching the second data from the outside.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present embodiment relates to a semiconductor memory device. [Background technology]

[0002] In a gain cell memory, data is read by amplifying the charge stored in the sense node using a transistor, and it is desirable to reduce the power consumption of such a gain cell memory. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2018-073453 [Patent Document 2] Japanese Patent Application Publication No. 2018-081736 [Patent Document 3] Japanese Patent Application Laid-Open No. 2008-053288 Summary of the Invention [Problem to be solved by the invention]

[0004] A semiconductor memory device capable of reducing power consumption is provided. [Means for solving the problem]

[0005] The semiconductor memory device according to this embodiment includes a first data line and a first control line used for writing data, and a second data line and a second control line used for reading data. The memory cells include a first transistor having a gate connected to the first control line and one end connected to the first data line, a second transistor having a gate connected to the second control line and one end connected to the second data line, and a third transistor having a gate connected to the other end of the first transistor, holding data from the first data line, and one end connected to the other end of the second transistor, and having a conductive state corresponding to the data. The detection circuit is connected to the first and second data lines, latches data from an external source, applies a voltage corresponding to the latched data to the first data line, or detects data based on the voltage on the second data line. The control unit controls the first control line and the second control line. When writing or reading data, the control unit activates the second control line, and the detection circuit detects first data based on the voltage of the second data line, and then the control unit activates the first control line, and the detection circuit transmits the first data to the gate of the third transistor. After receiving a write command instructing writing, the detection circuit latches second data from the outside and transmits the second data to the gate of the third transistor. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 2 is a circuit diagram showing an example of the configuration of a memory cell of a gain cell memory according to the first embodiment. [Figure 2] FIG. 2 is a block diagram showing an example of the configuration of a gain cell memory according to the first embodiment. [Figure 3] FIG. 10 is a state transition diagram showing an example of a case where the gain cell memory is operated in a DRAM mode. [Figure 4] FIG. 10 is a timing chart showing an example of a case where the gain cell memory is operated in a DRAM mode. [Figure 5] FIG. 10 is a diagram showing the state of a sense amplifier in a DRAM mode. [Figure 6] FIG. 10 is a diagram showing the state of a sense amplifier in a DRAM mode. [Figure 7]FIG. 10 is a diagram showing the state of a sense amplifier in a DRAM mode. [Figure 8] FIG. 10 is a diagram showing the state of a sense amplifier in a DRAM mode. [Figure 9] FIG. 10 is a state transition diagram showing an example of a case where the gain cell memory is operated in a first gain cell mode. [Figure 10] FIG. 10 is a timing chart showing an example of a case where the gain cell memory is operated in a first gain cell mode. [Figure 11] FIG. 10 is a diagram showing the state of a sense amplifier in a first gain cell mode. [Figure 12] FIG. 10 is a diagram showing the state of a sense amplifier in a first gain cell mode. [Figure 13] FIG. 10 is a diagram showing the state of a sense amplifier in a first gain cell mode. [Figure 14] FIG. 10 is a timing chart showing an example of a case where the gain cell memory is operated in a second gain cell mode. [Figure 15] FIG. 10 is a diagram showing the state of a sense amplifier in a second gain cell mode. [Figure 16] FIG. 10 is a diagram showing the state of a sense amplifier in a second gain cell mode. [Figure 17] FIG. 10 is a timing chart showing an example of random access in the first gain cell mode. [Figure 18] FIG. 10 is a timing chart showing an example of page access in the first gain cell mode. [Figure 19] FIG. 10 is a timing chart showing an example of random access in the second gain cell mode. [Figure 20] FIG. 10 is a timing chart showing an example of page access in the second gain cell mode. [Figure 21] FIG. 10 is a state transition diagram showing the operation of the gain cell memory according to the second embodiment. [Figure 22] FIG. 10 is a timing chart showing the operation of the gain cell memory according to the third embodiment. [Figure 23] FIG. 10 is a timing chart showing the operation of the gain cell memory according to the third embodiment. [Figure 24]FIG. 10 is a timing chart showing the operation of the gain cell memory according to the fourth embodiment. [Figure 25] FIG. 10 is a timing chart showing the operation of the gain cell memory according to the fourth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0007] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. The present invention is not limited to the embodiment. The drawings are schematic or conceptual. In the specification and drawings, the same elements are designated by the same reference numerals.

[0008] (First embodiment) 1 is a circuit diagram showing an example of the configuration of a memory cell of a gain cell memory according to the first embodiment. A memory cell MC of the gain cell memory is composed of three transistors MW1, MR1, and MR2. The transistors MW1, MR1, and MR2 are, for example, n-type Oxide Semiconductor Field Effect Transistors (OSFETs).

[0009] The gate of transistor MW1, which serves as a first transistor, is connected to a write word line WWL, which serves as a first control line. One electrode of transistor MW1 is connected to a write bit line WBL, which serves as a first data line. The other electrode of transistor MW1 is connected to the gate of transistor MR1. The one and other electrodes of transistor MW1 function as source electrodes or drain electrodes depending on the voltage supplied to transistor MW1. Under the control of the write word line WWL, transistor MW1 connects the write bit line WBL to the gate of transistor MR1, which functions as a sense node SN (hereinafter also referred to as sense node SN). When transistor MW1 is in a conductive state, it transmits the voltage of the write bit line WBL to the sense node SN. When transistor MW1 is in a non-conductive state, it holds the voltage of the sense node SN. In this way, transistor MW1 can write a voltage (data) from the write bit line WBL to the sense node SN or hold a voltage (data) written to the sense node SN.

[0010] The gate of the transistor MR1, which serves as a third transistor, is connected to the other electrode of the transistor MW1 and functions as a sense node SN. One electrode (source) of the transistor MR1 is connected to a low voltage supply VSS. The other electrode (drain) of the transistor MR1 is connected to one electrode of the transistor MR2. The transistor MR1 is turned on according to the voltage (i.e., data) of the sense node SN. For example, when the sense node SN is held at a high-level voltage (e.g., data "1"), the transistor MR1 is turned on. When the sense node SN is held at a low-level voltage (e.g., data "0"), the transistor MR1 is turned off.

[0011] The gate of the transistor MR2, which serves as a second transistor, is connected to a read word line RWL, which serves as a second control line. One electrode of the transistor MR2 is connected to the drain of the transistor MR1. The other electrode of the transistor MR2 is connected to a read bit line RBL, which serves as a second data line. The one and other electrodes of the transistor MR2 can function as source or drain electrodes depending on the voltage supplied to the transistor MR2. The transistor MR2 connects the read bit line RBL to the drain of the transistor MR1 under the control of the read word line RWL. The transistor MR1 is in a state (conductive or non-conductive) depending on the voltage (data) held at the sense node SN. When the transistor MR2 is in a conductive state, if the read bit line RBL is connected to the transistor MR1, charge from the read bit line RBL flows to the low voltage source VSS depending on the state of the transistor MR1. When the transistor MR1 is in a conductive state, charge from the read bit line RBL flows to the low voltage source VSS, and the voltage of the read bit line RBL becomes low. When the transistor MR1 is in a non-conductive state, almost no charge flows from the read bit line RBL to the low voltage supply VSS, and the voltage of the read bit line RBL is maintained high, so that a voltage based on the data held in the sense node SN is transmitted to the read bit line RBL.

[0012] The sense amplifier SA, which serves as a detection circuit, is connected to the write bit line WBL and the read bit line RBL. The sense amplifier SA latches write data from the outside and applies a voltage corresponding to the write data to the write bit line WBL. The sense amplifier SA also detects read data based on the voltage of the read bit line RBL and latches the read data. The read data latched by the sense amplifier SA is transmitted to the outside. The sense amplifier SA also precharges the write bit line WBL and the read bit line RBL.

[0013] The control unit CTL is connected to the write word line WWL and the read word line RWL, and controls the voltages of the write word line WWL and the read word line RWL.

[0014] The write word line WWL and write bit line WBL are wirings used for writing data. The read word line RWL and read bit line RBL are wirings used for reading data. In this way, the gain cell memory uses different word lines and bit lines for writing and reading data. This allows the gain cell memory to read data while maintaining the data in the sense node SN (non-destructive read). Furthermore, one memory cell MC is composed of three transistors MW1, MR1, and MR2, and does not have a capacitor, which is difficult to miniaturize, as in a DRAM (Dynamic Random Access Memory). Therefore, the gain cell memory is excellent for miniaturization.

[0015] FIG. 2 is a block diagram showing an example of the configuration of a gain cell memory according to the first embodiment. The gain cell memory according to this embodiment has a three-dimensional memory cell array in which a plurality of memory cells MC are arranged three-dimensionally. The plurality of memory cells MC are arranged in a matrix form consisting of a plurality of rows and a plurality of columns. The rows are the arrangement of the memory cells MC in the X direction. The columns are the arrangement of the memory cells MC in the Z direction. Furthermore, the memory cells MC are arranged in rows and columns in the Y direction. As a result, the memory cell array MCA is a three-dimensional array in which a plurality of memory cells MC are arranged three-dimensionally. The number of rows, columns, and rows and columns of the memory cells MC is not particularly limited.

[0016] A plurality of write word lines WWL are provided corresponding to the plurality of rows of memory cells MC, and a plurality of read word lines RWL are also provided corresponding to the plurality of rows of memory cells MC.

[0017] A plurality of write bit lines WBL are provided corresponding to the plurality of columns of memory cells MC, a plurality of read bit lines RBL are also provided corresponding to the plurality of columns of memory cells MC, a plurality of sense amplifiers SA are also provided corresponding to the plurality of columns of memory cells MC, and a plurality of source lines SL are also provided corresponding to the plurality of columns of memory cells MC.

[0018] Next, the operation of the gain cell memory according to this embodiment will be described.

[0019] (DRAM mode: 1st mode) FIG. 3 is a state transition diagram showing an example of a gain cell memory operating in DRAM mode. In FIG. 3, the arrow next to each command indicates an active state or an inactive state. An upward arrow indicates activation, and a downward arrow indicates inactivation. The same applies to FIGS. 9, 13, and 21. FIG. 4 is a timing diagram showing an example of a gain cell memory operating in DRAM mode. Note that FIG. 4 shows a specific example in which data "1" is stored in a memory cell MC and data "0" is written to that memory cell MC.

[0020] Each memory cell MC of the gain cell memory holds data in the idle state. The gain cell memory periodically performs a restore operation (refresh) of the data in each memory cell MC. The restore operation will be described later.

[0021] The memory cell array MCA is divided into multiple banks, and each bank is set to an active state (Bank active) for operation. At t1 in FIG. 4, when the gain cell memory receives an active command ACT, a bank is selectively set to the active state. In the active state, the read bit lines RBL of multiple columns in the selected bank are charged. Next, at t2, the read word line RWL corresponding to a selected row among multiple rows in the bank is activated. As a result, at t3 to t4, data from the multiple memory cells MC corresponding to the selected row is detected and latched by the sense amplifiers SA of the multiple columns.

[0022] At t4, the read word line RWL of the selected row is deactivated and the write word line WWL of the selected row is activated. This puts the memory cells MC of the selected row into a state in which data can be written. Between t4 and t5, the data latched by the sense amplifier SA (the data originally stored in the memory cells MC of the selected row) is returned to the sense nodes SN of the memory cells MC of the selected row via the write bit lines WBL of each column.

[0023] Next, at t5, when the gain cell memory receives a write command WRITE or a read command READ, the gain cell memory transitions from the active state (Bank active) in Fig. 3 to a write state (Writing) or a read state (Reading). Here, it is assumed that a write command WRITE is issued at t5, as shown in Fig. 4. In this case, the gain cell memory transitions from the active state to the write state.

[0024] At t6, when the column select line CSL is raised, write data is transferred to and latched in the sense amplifier SA corresponding to the selected column among the multiple columns. In the example of FIG. 4, data “0” is transferred to the sense amplifier SA of the selected column as the write data. At this time, the write word line WWL is activated, so the write data is written to the memory cell MC corresponding to the selected column in the selected row via the write bit line WBL. In the example of FIG. 4, data “0” is written to the memory cell MC of the selected column in the selected row via the write bit line WBL. Therefore, the data at the sense node SN is inverted from “1” to “0.” Note that the original data stored in the memory cell MC is written back to the memory cell MC corresponding to the unselected column in the selected row. Furthermore, even in the selected column, if the write data has the same logic as the original data stored in the memory cell MC, the original data stored in the memory cell MC is written without logic inversion.

[0025] At t7, the column select line CSL is pulled down, and at t8, a precharge command PRE is issued. This causes the gain cell memory to transition from the write state of FIG. 3 to the precharge state (Precharging). At this time, at t9, the write word line WWL is deactivated. This causes the multiple memory cells MC in the selected row to be electrically disconnected from the write bit lines WBL, and the sense nodes SN retain the write data. Furthermore, at t10, the sense amplifiers SA of multiple columns precharge the write bit lines WBL to, for example, VDD / 2. Thereafter, the write bit lines WBL are disconnected from the sense amplifiers SA. VDD is, for example, the voltage of a high voltage supply. This completes the precharge, and the gain cell memory returns to the standby state.

[0026] On the other hand, at t5, when the gain cell memory receives a read command READ, the gain cell memory transitions from the active state (Bank active) in FIG. 3 to the read state (Reading). In this case, although not shown, at t6, when the column select line CSL is raised, the sense amplifier SA transmits the latched data to the outside as read data. The data latched in the sense amplifier SA is not inverted, but is written back to the multiple memory cells MC in the selected row via the write bit line WBL. Therefore, in the precharge operation, the data at the sense nodes SN of the multiple memory cells MC in the selected row is not inverted and is maintained as is. The other read operations (t1 to t5, t8 to t10) may be the same as the corresponding write operations.

[0027] Thus, in DRAM mode, when writing or reading data, the read word line RWL is activated, and the sense amplifier SA detects the data based on the voltage of the read bit line RBL. Then, in a write operation, the write word line WWL is activated, and the sense amplifier SA transmits the write data to the sense node SN of the memory cell MC at the timing when the column select line CSL is raised to latch the external write data. The memory cell MC retains the data written to the sense node SN. Meanwhile, in a read operation, the write word line WWL is activated, and the sense amplifier SA outputs the read data to the external device at the timing when the column select line CSL is raised to return the read data to the sense node SN of the memory cell MC. The memory cell MC retains the data returned to the sense node SN.

[0028] Therefore, in DRAM mode, when reading data, the read word line RWL is activated and the sense amplifier SA detects the read data based on the voltage of the read bit line RBL. Then, the write word line WWL is activated and the sense amplifier SA outputs the read data to the outside by raising the column select line CSL, and returns the same data to the sense node SN of the memory cell MC. The memory cell MC holds the read data returned to the sense node SN.

[0029] In a restore operation, the gain cell memory first reads the data stored in each memory cell MC and then writes the same data back. In this case, after the gain cell memory transitions from the standby state to the active state in FIG. 3, when a precharge command PRE is issued, the memory directly transitions to the precharge state and returns to the standby state. At this time, the column select line CSL is not raised. The sense amplifier SA does not output data from the memory cell MC to the outside, nor does it import data from the outside. Therefore, data is not written to or read from the sense amplifier SA, and the data detected by the sense amplifier SA in the active state is written back to the original memory cell MC. That is, the control unit CTL activates the write word line WWL, and the sense amplifier SA transmits the latched data from the memory cell MC to the sense node SN of the original memory cell MC, thereby restoring (refreshing) the data in the memory cell MC. The restore operation can be performed by sequentially selecting multiple rows.

[0030] 3, when a read command READ is received after a write command WRITE is received, the gain cell memory may transition from a writing state (Writing) to a reading state (Reading). Conversely, when a write command WRITE is received after a read command READ is received, the gain cell memory may transition from a reading state (Reading) to a writing state (Writing).

[0031] 5 to 8 are diagrams showing the state of the sense amplifier in DRAM mode. The sense amplifier SA includes a latch circuit consisting of two n-type MOSFETs and two p-type MOSFETs. This latch circuit holds either the high voltage supply VDD or the low voltage supply VSS at node N1 depending on the data to be latched. For example, when the read bit line RBL is at a low level voltage (data "1"), node N1 holds a low level voltage based on the low voltage supply VSS. For example, when the read bit line RBL is at a high level voltage (data "0"), node N1 holds a high level voltage based on the high voltage supply VDD. Node N1_b holds an inverted signal relative to node N1. RBL_b denotes the inverted signal of the read bit line RBL. WBL_b denotes the inverted signal of the write bit line WBL. LIO_b denotes the inverted signal of the input / output line LIO.

[0032] First, in the active state from t1 to t2, the read bit lines RBL and RBL_b are connected to the sense amplifier SA and charged, as shown in Figure 5. This charging is based on the precharge potential. Note that the write bit lines WBL and WBL_b are not connected to the sense amplifier SA.

[0033] During t2 to t4, as shown in FIG. 6, data from the memory cell MC is detected and latched by the sense amplifier SA via the read bit line RBL.

[0034] Between t4 and t6, as shown in Figure 7, the write state is entered, and the write bit lines WBL and WBL_b are connected to the sense amplifier SA. This allows the data latched in the sense amplifier SA to be written to the memory cell MC. After the read word line RWL is deactivated, the read bit lines RBL and RBL_b are each disconnected from the sense amplifier SA.

[0035] 8, the column selection line CSL is activated, and the input / output lines LIO and LIO_b are connected to the nodes N1 and N1_b, respectively. As a result, external write data (data "0") is latched at the nodes N1 and N1_b and transmitted to the sense node SN of the memory cell MC via the write bit line WBL.

[0036] In this way, the sense amplifier SA can detect data stored in the memory cells MC and output the data to the outside as read data, or can latch write data from the outside and write the write data to the memory cells MC.

[0037] In DRAM mode, when the gain cell memory is activated, the read word line RWL is activated once, and after the sense amplifier SA detects data based on the voltage of the read bit line RBL, the write word line WWL is activated before receiving the write command WRITE or the read command READ.

[0038] When a write command WRITE is received after the gain cell memory has been activated, the sense amplifier SA transmits the write data from the outside to the sense node SN of the memory cell MC at the timing when the write data is latched.

[0039] When a read command READ is received, the sense amplifier SA outputs the latched data to the outside.

[0040] In DRAM mode, the gain cell memory can randomly access any memory cell MC in a block of the memory cell array MCA at high speed. The gain cell memory has separate word lines and bit lines for writing and reading, allowing it to operate in a manner similar to DRAM. Meanwhile, in DRAM mode, the gain cell memory activates the write word line WWL each time it enters the active state, regardless of whether a write command WRITE is issued. Therefore, power consumption increases when read operations are repeated. Furthermore, in DRAM mode, the write word line WWL is activated each time it enters the active state, so precharging is required even for read operations. Therefore, power consumption also increases when read operations are repeated.

[0041] (1st gain cell mode: 1st submode of 2nd mode) Fig. 9 is a state transition diagram showing an example of a case where the gain cell memory is operated in the first gain cell mode. Fig. 10 is a timing diagram showing an example of a case where the gain cell memory is operated in the first gain cell mode. Note that Fig. 10 shows a specific example in which data "1" is stored in a memory cell MC and data "0" is written to the memory cell MC.

[0042] In the first gain cell mode, when transitioning from the standby state to the active state, the write word line WWL is not activated. The write word line WWL is activated after issuing the write command WRITE. For example, as shown in FIG. 10, the write word line WWL is activated at the same time as the column select line CSL is activated.

[0043] In addition, in the first gain cell mode, as shown in Figure 9, a path P1 is set that directly transitions from the read state (Reading) to the idle state (Idle) without going through precharge. As described above, the gain cell memory is capable of non-destructive reading, and it is not necessary to write back the original data to the memory cell MC during a read operation. Therefore, if restore is not required, the gain cell memory may directly transition to the idle state after a read operation, as shown by path P1.

[0044] 10, the operations from t1 to t4 may be the same as those from t1 to t4 in FIG. 4. However, in the first gain cell mode, the write word line WWL is not activated at t4, and the data latched in the sense amplifier SA is not transmitted to the write bit line WBL.

[0045] At t6, the control unit CTL activates the column selection line CSL. This transfers and latches the write data to the sense amplifier SA corresponding to the selected column among the multiple columns. In the example of FIG. 10, data “0” is transferred to the sense amplifier SA of the selected column as the write data. At the same time, the control unit CTL activates the write word line WWL of the selected row. Furthermore, the write bit lines WBL and WBL_b are connected to the sense amplifier SA. This causes the write data to be written to the memory cells MC corresponding to the selected column in the selected row via the write bit line WBL. In the example of FIG. 10, data “0” is written to the memory cells MC of the selected column in the selected row via the write bit line WBL. Therefore, the data at the sense node SN is inverted from “1” to “0.” The original data stored in the memory cells MC are written back to the memory cells MC corresponding to the unselected columns in the selected row. Furthermore, even in the selected column, if the write data has the same logic as the original data stored in the memory cells MC, the original data stored in the memory cells MC is written without logic inversion.

[0046] Thereafter, the operations from t7 to t10 in FIG. 10 may be the same as the operations from t7 to t10 in FIG.

[0047] 11 and 12 are diagrams showing the state of the sense amplifier in the first gain cell mode. The state of the sense amplifier SA from t1 to t4 is the same as that described with reference to FIGS.

[0048] During t4 to t6, the sense amplifier SA shown in FIG. 11 holds the data read from the memory cell MC.

[0049] Between t6 and t7, as shown in FIG. 12, the column select line CSL is activated, and the input / output lines LIO and LIO_b are connected to the nodes N1 and N1_b, respectively. As a result, external write data (data "0") is latched to the nodes N1 and N1_b. At the same time as the rise of the column select line CSL, the write word line WWL is activated. As a result, the external write data is transmitted to the nodes N1 and N1_b and also transmitted to the sense node SN of the memory cell MC via the write bit line WBL.

[0050] In this way, the sense amplifier SA can detect data stored in the memory cells MC and output the data to the outside as read data, or can latch write data from the outside and write the write data to the memory cells MC.

[0051] In this way, in the first gain cell mode, when the gain cell memory is activated, the read word line RWL is temporarily activated and the sense amplifier SA detects the read data based on the voltage of the read bit line RBL, while the write word line WWL is kept inactive.

[0052] After entering the active state, the gain cell memory activates the write word line WWL when it receives a write command WRITE. The sense amplifier SA latches external write data in response to the rising edge of the column select line CSL, and transmits the latched data to the sense node SN of the memory cell MC at the timing of activating the write word line WWL. In the first gain cell mode, the column select line CSL and the write word line WWL are activated almost simultaneously, so the sense amplifier SA transmits the external write data to the sense node SN of the memory cell MC at the timing of latching the external write data.

[0053] When a read command READ is received, the write word line WWL is kept inactive, and the sense amplifier SA outputs the read data to the outside at the timing of activating the column select line CSL. As described above, the gain cell memory is capable of non-destructive reading, so in the first gain cell mode, after the read operation, it directly transitions to the standby state.

[0054] (Second gain cell mode: Second sub-mode of second mode) Fig. 13 is a state transition diagram showing an example of a case where the gain cell memory is operated in the second gain cell mode. Fig. 14 is a timing chart showing an example of a case where the gain cell memory is operated in the second gain cell mode. Fig. 14 shows a specific example in which data "1" is stored in a memory cell MC and data "0" is written to the memory cell MC.

[0055] In the second gain cell mode, the write word line WWL is activated after the write command WRITE is issued, which is the same as in the first gain cell mode. However, in the second gain cell mode, the write word line WWL is activated when the precharge command PRE is received after the column select line CSL is activated, as shown in FIG.

[0056] Also, in the second gain cell mode, a path P1 is set that transitions directly from the read state to the standby state without going through precharge, as shown in Fig. 13. This is because the gain cell memory is capable of non-destructive readout.

[0057] In FIG. 14, the operations from t1 to t5 may be the same as those from t1 to t5 in FIG.

[0058] Between t6 and t7, the control unit CTL activates the column selection line CSL. This transfers and latches the write data to the sense amplifier SA corresponding to the selected column among the multiple columns. However, at this time, in the second gain cell mode, the write word line WWL is not yet activated. The write word line WWL is activated at t8 upon receiving the precharge command PRE after issuing the write command WRITE. Furthermore, the write bit lines WBL and WBL_b are connected to the sense amplifier SA. Therefore, in the example of FIG. 14, the write word line WWL is activated upon issuing the precharge command PRE, and the write data latched in the sense amplifier SA is written to the memory cell MC corresponding to the selected column in the selected row via the write bit line WBL. In the example of FIG. 14, data “0” is written to the memory cell MC of the selected column in the selected row via the write bit line WBL. Therefore, the data at the sense node SN is inverted from “1” to “0.”

[0059] Thereafter, at t9, the write word line WWL is deactivated, and at t10, the write bit line WBL is set to a precharge state. The write bit lines WBL and WBL_b are disconnected from the sense amplifier SA.

[0060] Other operations in the second gain cell mode may be the same as those in the first gain cell mode.

[0061] 15 and 16 are diagrams showing the state of the sense amplifier in the second gain cell mode. The state of the sense amplifier SA from t1 to t4 is the same as that described with reference to Figures 5 and 6. The state of the sense amplifier SA from t4 to t6 is the same as that described with reference to Figure 11.

[0062] Between t6 and t7, as shown in FIG. 15, the column selection line CSL is activated, and the input / output lines LIO and LIO_b are connected to the nodes N1 and N1_b, respectively. This causes external write data (data "0") to be latched at the nodes N1 and N1_b. At this time, the write word line WWL is not yet activated.

[0063] 16, at the timing of issuing a precharge command PRE, the write word line WWL is activated. The write bit lines WBL and WBL_b are connected to the sense amplifier SA. As a result, the sense amplifier SA writes the latched write data to the memory cell MC.

[0064] In this way, in the second gain cell mode, even when the gain cell memory receives a write command WRITE after being activated, the write word line WWL remains inactive. Furthermore, the sense amplifier SA latches write data from the outside in response to the rising edge of the column select line CSL, but the write word line WWL remains inactive. Then, when a precharge command PRE is issued, the sense amplifier SA transmits the write data to the sense node SN of the memory cell MC.

[0065] When a read command READ is received, the write word line WWL is kept inactive, and the sense amplifier SA outputs the read data to the outside at the timing of activating the column select line CSL. As described above, the gain cell memory is capable of non-destructive reading, so after the read operation, it directly transitions to the standby state.

[0066] The gain cell memory according to this embodiment can selectively execute one of the DRAM mode, the first gain cell mode, and the second gain cell mode. A mode selection signal indicating whether to execute the DRAM mode, the first gain cell mode, or the second gain cell mode may be preset in a program executed by the control unit CTL. In this case, the gain cell memory repeatedly executes the same mode specified by the mode selection signal. Alternatively, when the control unit CTL operates, the control unit CTL may receive the mode selection signal from an external device. In this case, the gain cell memory receives a mode selection signal from an external device each time it receives an active command ACT, and selects or switches modes according to the mode selection signal.

[0067] In the first and second gain cell modes, the gain cell memory can randomly access any memory cell in the memory cell array MCA, or can access (page access) a selected block of the memory cell array MCA in page units (row units, write word lines WWL or read word lines RWL).

[0068] (Random access in 1st gain cell mode) 17 is a timing diagram showing an example of random access in the first gain cell mode. In the case of writing by random access, the gain cell memory activates the read word line RWL[i] of the selected row [i] for the selected row address (RA) (t2 to t4). The sense amplifier SA detects and latches data from the selected memory cell MC of the selected column among the multiple memory cells MC of the selected row.

[0069] Next, the control unit CTL activates the column select line CSL of the selected column and raises the write word line WWL[i] of the selected row. The sense amplifier SA of the selected column latches the write data from the outside and applies the write data to the sense node SN[i] of the selected memory cell via the write bit line WBL (t6).

[0070] After that, after a precharge command PRE is issued, the write word line WWL[i] is deactivated (t9), and the write bit line WBL is precharged (t10).

[0071] This write cycle CYCL can be selectively executed for any of the rows [j] to [l].

[0072] In this case, the write word line WWL is activated and writing to the memory cell MC is performed before issuing the precharge command PRE. Therefore, high-speed random access can be maintained. Note that the read operation can be easily understood from the write operation described above, so its explanation will be omitted here.

[0073] (Page access in 1st gain cell mode) For example, Figure 18 is a timing diagram showing an example of page access in the first gain cell mode. In the case of writing by page access, the gain cell memory charges the read bit lines RBL[a] to RBL[d] for multiple columns [a] to [d] in the row address (RA), and then activates the read word line RWL of the selected row (t1 to t4). Multiple sense amplifiers SA[a] to SA[d] each detect and latch data from multiple memory cells MC in the selected row.

[0074] Next, upon receiving a write command WRITE, the control unit CTL activates the write word line WWL[i] of the selected row and activates the column select lines CSL[a]-CSL[d] of each column according to the column address (CA) received with the write command. For example, when the column select line CSL[a] is activated, the sense amplifier SA[a] of the selected column latches the corresponding write data from the outside and applies the write data to the sense node SN[a] of the selected memory cell via the write bit line WBL (t6a-t7a). Similarly, when the column select lines CSL[b]-CSL[d] are activated in sequence, the sense amplifiers SA[b]-SA[d] of the corresponding selected columns latch the corresponding write data from the outside and apply the write data to the sense nodes SN[b]-SN[d] of the selected memory cell via the write bit line WBL (t6b-t7d).

[0075] Thereafter, after a precharge command PRE is issued, the write word line WWL is deactivated (t9), and the write bit line WBL is precharged (t10).

[0076] This write cycle CYCL can be selectively executed for any row.

[0077] In page access, random access to any memory cell MC is not possible, but all data in a selected row (one page of data) can be written by driving one write word line WWL at a time. Therefore, page access can be performed with low power consumption. Furthermore, since non-destructive read is possible in read operations, a write command WRITE is not issued. Therefore, since the write bit line WBL is already precharged, a precharge operation is not required. Therefore, the gain cell memory directly transitions to a standby state after a read operation. This can further reduce power consumption. In particular, when read operations are frequently repeated, the power consumption reduction effect is significant.

[0078] (Random access in 2nd gain cell mode) For example, Figure 19 is a timing diagram showing an example of random access in the second gain cell mode. The write operation of random access in the second gain cell mode differs from that in the first gain cell mode in the rise timing of the write word lines WWL[i] to WWL[l] of the selected row. In the second gain cell mode, the write word lines WWL[i] to WWL[l] of the selected row are activated when a precharge command PRE is received. Other operations of random access in the second gain cell mode may be the same as those of random access in the first gain cell mode.

[0079] In the second gain cell mode, the write cycle CYCL is relatively long because the write from the sense amplifier SA to the sense node occurs after the issuance of the precharge command PRE. Therefore, in terms of high-speed random access, the DRAM mode or the first gain cell mode is more preferable.

[0080] (Page access in 2nd gain cell mode) For example, Figure 20 is a timing diagram showing an example of page access in the second gain cell mode. In the case of writing by page access, the gain cell memory charges the read bit lines RBL[a] to RBL[d] for multiple columns [a] to [d] in the row address (RA), and then activates the read word line RWL of the selected row (t1 to t4). Multiple sense amplifiers SA[a] to SA[d] each detect and latch data from multiple memory cells MC in the selected row.

[0081] In the second gain cell mode, the write word line WWL of the selected row is activated when a precharge command PRE is received. Therefore, in page access in the second gain cell mode, when the precharge command PRE is issued and the write word line WWL of the selected row is activated, the data latched in the sense amplifiers SA[a] to SA[d] is written to the sense nodes SN[a] to SN[d] via the write bit lines WBL[a] to WBL[d], respectively (t8). Other operations of page access in the second gain cell mode may be the same as those of page access in the first gain cell mode.

[0082] This write cycle CYCL can also be selectively executed for any row.

[0083] The page access in the second gain cell mode can achieve the same effect as the page access in the first gain cell mode. Moreover, in the second gain cell mode, the time during which the write word line WWL is in an active state is relatively short. Therefore, the power consumption is effectively reduced.

[0084] In the first or second gain cell mode, the timing of activating the write word line WWL may be any timing between the timing of activating the column select line CSL and the timing of receiving the precharge command PRE.

[0085] (Second embodiment) 21 is a state transition diagram showing the operation of the gain cell memory according to the second embodiment. The gain cell memory according to the second embodiment can receive a write command WRITE from the active state, and after the write operation, can also receive a read command READ for the same page (Reading after Writing). In this case, precharging can be performed after the read operation of the page.

[0086] It is also possible to receive a read command READ from the active state and then receive a write command WRITE for the same page after the read operation. In this case, precharge should be performed after the write operation for that page.

[0087] (Third embodiment) 22 and 23 are timing diagrams showing the operation of the gain cell memory according to the third embodiment. Fig. 22 shows the case where the read data is "1" and the write data is "0". Fig. 23 shows the case where the read data is "0" and the write data is "1".

[0088] In the third embodiment, the control unit CTL activates the read word line RWL at t2 and then maintains the read word line RWL in an active state until the write word line WWL is deactivated at t8 (the end of the write operation). As a result, the drain voltage MR1_d of the transistor MR1 does not become floating during the write state, but is fixed to the voltage of the read bit line RBL. As a result, due to the presence of parasitic capacitance between the drain of the transistor MR1 and the sense node SN, the voltage difference (sense merge) between data "0" and data "1" can be widened.

[0089] Other operations of the third embodiment may be the same as those of the second gain cell mode of the first embodiment. The third embodiment may also be applied to the DRAM mode or the first gain cell mode. This allows the voltage difference (sense merge) between data "0" and data "1" in the DRAM mode or the first gain cell mode to be widened.

[0090] (Fourth embodiment) 24 and 25 are timing diagrams showing the operation of the gain cell memory according to the fourth embodiment. Fig. 24 shows the case where the read data is "1" and the write data is "0". Fig. 25 shows the case where the read data is "0" and the write data is "1".

[0091] In the fourth embodiment, the voltage of the source line SL is lowered from VSS to the negative side (e.g., VSS-ΔVsl) from the activation of the write word line WWL at t8 (the start of the write operation) to the deactivation of the write word line WWL at t9 (the end of the write operation). In the standby state after precharge, the voltage of the source line SL is returned to VSS. In both the write operation of data "0" and data "1", the voltage of the source line SL is lowered from VSS to the negative side during the activation period of the write word line WWL (during the write operation). This somewhat increases the voltage of the sense node SN in the standby state after precharge without changing the sense margin. This reduces the source-drain voltage difference Vgs of the transistor MW1 in the standby state, improving the data retention characteristics of the memory cell MC. This allows the period of the restore operation to be extended, leading to reduced power consumption.

[0092] When the memory cell MC holds data "0", the source-drain voltage difference Vgs of the transistor MW1 is the voltage difference between the sense node SN and the gate of the transistor MW1. When the memory cell MC holds data "1", the source-drain voltage difference Vgs of the transistor MW1 is the voltage difference between the write bit line WBL and the gate of the transistor MW1.

[0093] Other operations of the fourth embodiment may be the same as those of the second gain cell mode of the first embodiment. The fourth embodiment may also be applied to the DRAM mode or the first gain cell mode. This can also improve the data retention characteristics of the DRAM mode or the first gain cell mode.

[0094] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, as well as the inventions described in the claims and their equivalents. [Explanation of symbols]

[0095] MC memory cell MW1, MR1, MR2 transistors WWL Write Word Line RWL Read Word Line WBL Write Bit Line RBL Read Bit Line SA Sense Amplifier SL Source Line CTL control unit

Claims

1. a first data line and a first control line used for writing data; a second data line and a second control line used for reading data; a plurality of memory cells each including a first transistor having a gate connected to the first control line and one end connected to the first data line, a second transistor having a gate connected to the second control line and one end connected to the second data line, and a third transistor having a gate connected to the other end of the first transistor, holding data from the first data line, and one end connected to the other end of the second transistor, having a conductive state according to the data; a detection circuit connected to the first and second data lines, which latches data from an external source and applies a voltage corresponding to the latched data to the first data line, or detects data based on a voltage on the second data line; a control unit that controls the first control line and the second control line, When writing or reading data, the control unit activates the second control line, and the detection circuit detects first data based on a voltage of the second data line, and then the control unit activates the first control line, and the detection circuit transmits the first data to the gate of the third transistor; After receiving a write command instructing writing, the detection circuit latches second data from the outside and then transmits the second data to the gate of the third transistor.

2. the plurality of memory cells are arranged in a plurality of rows and a plurality of columns; a plurality of the first control lines and a plurality of the second control lines are provided corresponding to the plurality of rows, a plurality of the first data lines, a plurality of the second data lines, and a plurality of the detection circuits are provided corresponding to the plurality of columns, respectively; When writing or reading data, the control unit activates the second control line corresponding to a selected row selected from the plurality of rows, and the plurality of detection circuits corresponding to the plurality of columns detect the first data based on voltages of the plurality of second data lines corresponding thereto, and then the control unit activates the first control line corresponding to the selected row, and the detection circuit transmits the first data to the gate of the third transistor; 2. The semiconductor memory device according to claim 1, wherein after receiving the write command, when the detection circuit corresponding to a selected column selected from among the plurality of columns latches second data from the outside, the detection circuit transmits the second data to the gate of the third transistor of the memory cell corresponding to the selected row and the selected column.

3. 3. The semiconductor memory device according to claim 2, wherein after said control section inactivates said first control line corresponding to said selected row, said detection circuit executes a precharge to set said first data line to a predetermined voltage.

4. 4. The semiconductor memory device according to claim 3, wherein when neither the write command nor the read command is issued but a precharge command instructing the precharge is issued, the detection circuit transmits the first data to the gate of the third transistor.

5. a first data line and a first control line used for writing data; a second data line and a second control line used for reading data; a plurality of memory cells each including a first transistor having a gate connected to the first control line and one end connected to the first data line, a second transistor having a gate connected to the second control line and one end connected to the second data line, and a third transistor having a gate connected to the other end of the first transistor, holding data from the first data line, and one end connected to the other end of the second transistor, having a conductive state according to the data; a detection circuit connected to the first and second data lines, which latches data from an external source and applies a voltage corresponding to the latched data to the first data line, or detects data based on a voltage on the second data line; a control unit that controls the first control line and the second control line, When writing or reading data, the control unit activates the second control line, and the detection circuit detects first data based on the voltage of the second data line; the control unit is in a first mode, in which after detecting the first data, the control unit activates the first control line, the detection circuit transmits the first data to the gate of the third transistor, and after receiving a write command instructing writing, when the detection circuit latches second data from an external source, transmits the second data to the gate of the third transistor; a second mode in which, after detecting the first data, the detection circuit outputs the first data to an external device or latches second data from an external device, and when the control unit activates the first control line, the detection circuit transmits the first or second data to the gate of the third transistor; A semiconductor memory device that selectively executes one of the above.

6. 6. The semiconductor memory device according to claim 5, wherein said control section selects said first mode or said second mode based on a mode selection signal which selects said first mode or said second mode.

7. The second mode is a first sub-mode in which the control unit activates the first control line at a timing when the detection circuit outputs the first data to the outside or latches the second data from the outside; and a second sub-mode in which the control unit activates the first control line at a timing when a precharge command for setting the first data line to a predetermined voltage is issued after the detection circuit outputs the first data to the outside or latches the second data from the outside.

8. 8. The semiconductor memory device according to claim 7, wherein said control section selects said first sub-mode or said second sub-mode based on a mode selection signal that selects said first sub-mode or said second sub-mode.

9. 6. The semiconductor memory device according to claim 1, wherein said control section activates said second control line during a period in which said first control line is activated.

10. a source line connected to the other end of the third transistor; 6. The semiconductor memory device according to claim 1, wherein said control section changes the voltage of said source line during a period in which said first control line is activated.

11. a first data line and a first control line used for writing data; a second data line and a second control line used for reading data; a plurality of memory cells each including a first transistor having a gate connected to the first control line and one end connected to the first data line, a second transistor having a gate connected to the second control line and one end connected to the second data line, and a third transistor having a gate connected to the other end of the first transistor, holding data from the first data line, and one end connected to the other end of the second transistor, having a conductive state according to the data; a detection circuit connected to the first and second data lines, which latches data from an external source and applies a voltage corresponding to the latched data to the first data line, or detects data based on a voltage on the second data line; a control unit that controls the first control line and the second control line, When writing or reading data, the control unit activates the second control line, and the detection circuit detects first data based on the voltage of the second data line; When a read command instructing reading is received, the control unit does not activate the first control line, and the detection circuit outputs the first data to the outside; a detection circuit that latches second data from the outside when a write command instructing writing is received, and that transmits the second data to the gate of the third transistor when the control unit activates the first control line.

12. the plurality of memory cells are arranged in a plurality of rows and a plurality of columns; a plurality of the first control lines and a plurality of the second control lines are provided corresponding to the plurality of rows, a plurality of the first data lines, a plurality of the second data lines, and a plurality of the detection circuits are provided corresponding to the plurality of columns, respectively; When writing or reading data, the second control line corresponding to a selected row selected from the plurality of rows is activated, and the plurality of detection circuits corresponding to the plurality of columns detect the first data based on voltages of the plurality of second data lines corresponding thereto; 12. The semiconductor memory device according to claim 11, wherein when the write command is received, the plurality of detection circuits latch second data from the outside, and when the control unit activates the first control line corresponding to the selected row, the plurality of detection circuits transmit the second data to gates of the third transistors of the plurality of memory cells corresponding to the selected row and the plurality of columns.

13. 13. The semiconductor memory device according to claim 12, wherein, when the write command is received, after transmitting the second data, the control unit inactivates the first control line corresponding to the selected row, and then the detection circuit performs a precharge to set the first data line to a predetermined voltage.

14. 14. The semiconductor memory device according to claim 13, wherein when the write command and the read command are not issued and a precharge command instructing the precharge is issued, the control unit activates the first control line and the detection circuit transmits the first data to the gate of the third transistor.

15. a first sub-mode in which the control unit activates the first control line at a timing when the detection circuit outputs the first data to the outside or latches the second data from the outside; 13. The semiconductor memory device according to claim 11, further comprising at least one of a first sub-mode in which the control unit activates the first control line at a timing when a precharge command for setting the first data line to a predetermined voltage is issued after the detection circuit outputs the first data to the outside or latches the second data from the outside.

16. 16. The semiconductor memory device according to claim 15, wherein said control section selects said first sub-mode or said second sub-mode based on a mode selection signal that selects said first sub-mode or said second sub-mode.

17. 12. The semiconductor memory device according to claim 11, wherein the control unit activates the first control line at any timing between the timing when the detection circuit outputs the first data to the outside or latches the second data from the outside and the timing when a precharge command is issued to set the first data line to a predetermined voltage.

18. 12. The semiconductor memory device according to claim 11, wherein said control section activates said second control line during a period in which said first control line is activated.

19. a source line connected to the other end of the third transistor; 12. The semiconductor memory device according to claim 11, wherein said control section changes the voltage of said source line during a period in which said first control line is activated.

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