Level shift circuit, semiconductor device including level shift circuit, and electronic apparatus including semiconductor device

Abstract

To solve the problem that a level shift circuit has room for further study regarding generation of a clock.SOLUTION: A level shift circuit (4x) includes: an input-stage (N1) configured to generate a triangular wave signal (V1); an output-stage (IV20) configured to generate a second pulse signal (CLK1) whose logic level is inverted between high level and low level according to power-supply voltage (Vcc); and a current limiting circuit (DN1) connected between an application terminal of the power-supply voltage (Vcc) and an output-terminal of the second pulse signal (CLK1) and configured to limit current flowing from the power-supply voltage (Vcc) into the output-stage (IV20).SELECTED DRAWING: Figure 5

Description

[Technical Field]

[0001] The invention disclosed in this specification relates to a level shift circuit, a semiconductor device including a level shift circuit, and an electronic device including the semiconductor device. [Background technology]

[0002] Conventionally, there is a semiconductor device for realizing an automatic write function to a nonvolatile memory. Such a semiconductor device includes an oscillator circuit and a level shift circuit. The level shift circuit level-shifts the internal clock generated by the oscillator circuit to generate a clock for counting the write time to the nonvolatile memory.

[0003] As an example of the related prior art, Patent Document 1 can be mentioned. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Publication No. 2018-037125

[0005] [overview] The level shift circuit disclosed in Patent Document 1 leaves room for further consideration regarding clock generation.

[0006] The level shift circuit disclosed herein includes an input stage, an output stage, and a current limiting circuit. The input stage is configured to generate a triangular wave signal that alternately rises and falls in response to a first pulse signal. The output stage is configured to generate a second pulse signal whose logic level inverts between a high level and a low level in response to a power supply voltage when the triangular wave signal matches an inversion threshold. The current limiting circuit is connected between an application terminal of the power supply voltage and an output terminal of the second pulse signal, and is configured to limit a current flowing from the power supply voltage to the output stage. The output stage is configured so that the inversion threshold is determined in response to the current.

[0007] The semiconductor device disclosed in this specification includes the level shift circuit configured as described above, and a count circuit configured to count time in response to the second pulse signal.

[0008] The electronic device disclosed in this specification includes the semiconductor device having the above-described configuration. [Brief explanation of the drawings]

[0009] [Figure 1] FIG. 1 is a circuit diagram showing a semiconductor device 50 of a comparative example. [Figure 2] FIG. 2 is a diagram showing the internal configuration of the count circuit 5. As shown in FIG. [Figure 3] FIG. 3 is a timing chart showing the input voltage V1, the first clock signal CLK1, the second clock signal CLK2, and the third clock signal CLK3. [Figure 4] FIG. 4 is a timing chart showing the input voltage V1, the first clock signal CLK1, the second clock signal CLK2, and the third clock signal CLK3 when the power supply voltage Vcc is set relatively high. [Figure 5] FIG. 5 is a diagram showing a semiconductor device 100 according to the present disclosure. [Figure 6] FIG. 6 is a diagram showing a modified example of the semiconductor device 100. In FIG. [Figure 7] FIG. 7 is a diagram showing a further modified example of the semiconductor device 100. In FIG.

[0010] [Detailed explanation] First, a semiconductor device 50, which is a comparative example of the semiconductor device 100 of the present disclosure, will be described, and then the semiconductor device 100 of the present disclosure will be described. The semiconductor device 50 has a basic configuration in common with the semiconductor device 100. Therefore, the following description of the semiconductor device 100 will focus on the components that differ from the semiconductor device 50.

[0011] <Regarding the semiconductor device 50 of the comparative example> 1 is a circuit diagram showing a comparative example of a semiconductor device 50. As shown in FIG. 1, the semiconductor device 50 includes an oscillator circuit 1, a charge pump circuit 2, a memory circuit 3, a level shift circuit 4y, a count circuit 5, and an enable signal generation circuit 6.

[0012] The oscillation circuit 1 generates an internal clock signal PCLK that is pulse-driven at a predetermined cycle. The oscillation circuit 1 can be, for example, a ring oscillator (not shown) configured to include multiple inverter stages.

[0013] The charge pump circuit 2 receives the internal clock signal PCLK and generates a write voltage VPP by boosting the power supply voltage Vcc. Specifically, this is as follows.

[0014] The charge pump circuit 2 includes a boost clock generation circuit 2a and a boost circuit 2b. The boost clock generation circuit 2a receives the internal clock signal PCLK and generates a pulse signal in phase with the internal clock signal PCLK and a pulse signal opposite in phase to the internal clock signal PCLK (not shown). The boost circuit 2b includes a plurality of transistors and a plurality of capacitors (not shown). The boost circuit 2b boosts the write voltage VPP to a desired voltage value while charging and discharging the capacitors in accordance with the in-phase and opposite in-phase pulse signals generated by the boost clock generation circuit 2a.

[0015] The memory circuit 3 is a nonvolatile memory (e.g., an EEPROM [Electrically Erasable Programmable Read-Only Memory]) that can be electrically written and erased. The memory circuit 3 includes a memory cell array MCA, a row decoder RD, and a column decoder CD. Data is written to the memory circuit 3 by applying a write voltage VPP to the row decoder RD, the column decoder CD, and the memory cell array MCA.

[0016] The level shift circuit 4y receives the internal clock signal PCLK and generates a first clock signal CLK1 that pulses at a predetermined frequency. The detailed configuration of the level shift circuit 4y is as follows.

[0017] The level shift circuit 4y includes a transistor N1, a constant current source CC1, an inverter IV10, and a buffer circuit Bf.

[0018] The transistor N1 is an N-channel MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor). The gate terminal of the transistor N1 is connected to the output terminal of the oscillator circuit 1. The drain terminal of the transistor N1 is connected to the output terminal of the constant current source CC1. The source terminal of the transistor N1 is connected to the ground terminal GND. The constant current source CC1 generates a constant current Iref.

[0019] The inverter IV10 includes a transistor P1 and a transistor N2. The transistor P1 is a P-channel MOSFET. The transistor N2 is an N-channel MOSFET.

[0020] The gate terminal of transistor P1, together with the gate terminal of transistor N2, constitutes the input terminal of inverter IV10. The gate terminals of transistors P1 and N2 (=input terminal of inverter IV10) are connected to the drain terminal of transistor N1. The drain terminal of transistor P1, together with the drain terminal of transistor N2, constitutes the output terminal of inverter IV10. The drain terminals of transistors P1 and N2 (=output terminal of inverter IV10) are connected to the input terminal of buffer circuit Bf. The source terminal of transistor P1 is connected to the application terminal of power supply voltage Vcc. The source terminal of transistor N2 is connected to ground terminal GND.

[0021] For ease of explanation, the connection node between the gate terminals of transistors P1 and N2 (= the input terminal of inverter IV10) is referred to as node n1. The connection node between the drain terminals of transistors P1 and N2 (= the output terminal of inverter IV10) is referred to as node n2. The voltage generated at node n1 is referred to as input voltage V1, and the voltage generated at node n2 is referred to as output voltage V2.

[0022] The inverter IV10 has a predetermined inversion threshold Vth (see FIG. 3). The inversion threshold Vth is the voltage value of the input voltage V1 when the logic level of the output voltage V2 switches to a high level (based on the power supply voltage Vcc) or a low level (based on the ground voltage GND). In other words, when the input voltage V1 is below the inversion threshold Vth, the output voltage V2 is at a high level, and when the input voltage V1 is above the inversion threshold Vth, the output voltage V2 is at a low level. More specifically, this is as follows.

[0023] When the input voltage V1 is sufficiently low compared to the inversion threshold Vth, the transistor P1 enters a saturated state and the transistor N2 turns off. As the input voltage V1 increases from this state and remains within a certain range, both the transistors P1 and N2 enter a saturated state. The inversion threshold Vth is the center value of this certain range of the input voltage V1. The inversion threshold Vth is proportional to the power supply voltage Vcc. More specifically, it is as follows.

[0024] The inversion threshold Vth is determined according to the driving power of the high-side transistor (here, transistor P1) and the low-side transistor (here, transistor N2). Driving power can also be described as the magnitude of the current flowing through it when it is saturated. If the driving power of transistors P1 and N2 is equal and other conditions are ideal, the inversion threshold Vth is half the power supply voltage Vcc. In the semiconductor device 50 according to the comparative example, the driving power of transistors P1 and N2 is set equal, and the inversion threshold Vth of inverter IV10 is approximately half the power supply voltage Vcc.

[0025] The input terminal of the buffer circuit Bf is connected to the node n2. The output terminal of the buffer circuit Bf is connected to the count circuit 5. The buffer circuit Bf receives the output voltage V2, performs a predetermined buffering process on the output voltage V2, and outputs the first clock signal CLK1.

[0026] The count circuit 5 receives the first clock signal CLK1 and sets the time for writing data to the memory circuit 3. Data is written to the memory circuit 3 within the write time. The specific configuration of the count circuit 5 is as follows.

[0027] Fig. 2 is a diagram showing the internal configuration of the count circuit 5. As shown in Fig. 2, the count circuit 5 includes a plurality of D flip-flops and inverters. Note that Fig. 2 only shows D flip-flops D1 and D2 and inverters IV1 and IV2.

[0028] The clock input terminal of the D flip-flop D1 is connected to the output terminal of the level shift circuit 4y (more specifically, the output terminal of the buffer circuit Bf). The D input terminal (D) of the D flip-flop D1 is connected to the output terminal of the inverter IV1. The output terminal (Q) of the D flip-flop D1 is connected to the input terminal of the inverter IV1 and the clock input terminal of the D flip-flop D2.

[0029] The D input terminal (D) of the D flip-flop D2 is connected to the output terminal of the inverter IV2. The output terminal (Q) of the D flip-flop D2 is connected to the input terminal of the inverter IV2. Although not shown in Figure 2, the output terminal (Q) of the D flip-flop D2 is also connected to the clock input terminal of another adjacent D flip-flop.

[0030] The D flip-flops D1 and D2 are edge-triggered. Specifically, the D flip-flops D1 and D2 set the logic level of their D input terminals (D) using the edge (more specifically, the rising edge) of the signal input to their own clock input terminals as a trigger.

[0031] The count circuit 5 receives the first clock signal CLK1 and counts the write time using a plurality of D flip-flops. An output signal S1 is output from the output terminal of the last D flip-flop (not shown). The output signal S1 goes high when the count value has not reached a predetermined value. Conversely, the output signal S1 goes low when the count value has exceeded the predetermined value.

[0032] The enable signal generation circuit 6 generates the enable signal EN in response to the output signal S1. Specifically, the enable signal generation circuit 6 keeps the logic level of the enable signal EN at a high level until the count value of the count circuit 5 reaches a predetermined value (i.e., until the output signal S1 rises from a low level to a high level). When the count value exceeds the predetermined value (i.e., when the output signal S1 rises to a high level), the enable signal generation circuit 6 drops the logic level of the enable signal EN to a low level.

[0033] Returning to Fig. 1, the enable signal EN is input to the oscillator circuit 1. When the enable signal EN is at a high level, the oscillator circuit 1 pulses the internal clock signal PCLK. Conversely, when the enable signal EN is at a low level, the oscillator circuit 1 stops pulsing the internal clock signal PCLK and maintains the internal clock signal PCLK at a low level.

[0034] In other words, during the write time (until the count value reaches a predetermined value), the oscillator circuit 1 pulses the internal clock signal PCLK to generate the write voltage VPP. In this way, the write voltage VPP is generated during the write time and applied to the memory circuit 3, thereby automatically writing data.

[0035] <Operations of the Level Shift Circuit 4y and the Count Circuit 5> The transistor N1 turns on / off in response to the internal clock signal PCLK input to its gate terminal. When the transistor N1 is on, a current Iref flows from the constant current source CC1 to the ground terminal GND via the transistor N1.

[0036] An input voltage V1 is generated at node n1 according to the gate capacitances of transistors P1 and N2. Specifically, when transistor N1 is off, the constant current source CC1 supplies current Iref, charging the gate capacitances of transistors P1 and N2. At this time, the input voltage V1 rises.

[0037] Conversely, when transistor N1 is on, the gate capacitances of transistors P1 and N2 are discharged. At this time, the input voltage V1 drops. In this way, the input voltage V1 fluctuates in a triangular wave pattern, repeatedly rising and falling, depending on whether transistor N1 is on or off, and ultimately on the internal clock signal PCLK.

[0038] 3 is a timing chart showing the input voltage V1, the first clock signal CLK1, the second clock signal CLK2, and the third clock signal CLK3. When the input voltage V1 is below the inversion threshold Vth, the transistor P1 is turned off and the transistor N2 is turned on. At this time, the output voltage V2 is at a low level (based on the ground voltage GND). Therefore, as shown in FIG. 3, when the input voltage V1 is below the inversion threshold Vth, the first clock signal CLK1 is also at a low level.

[0039] On the other hand, when the input voltage V1 exceeds the inversion threshold Vth, the transistor P1 is turned on and the transistor N2 is turned off. At this time, the output voltage V2 becomes high level (= power supply voltage Vcc reference). Therefore, the first clock signal CLK1 also becomes high level.

[0040] As described above, the D flip-flops D1 and D2 are edge-triggered flip-flops. Therefore, the logic level of the second clock signal CLK2 switches at the timing of the rising edge of the first clock signal CLK1. The cycle of the second clock signal CLK2 is twice that of the first clock signal CLK1.

[0041] Similarly, the logic level of the third clock signal CLK3 switches at the timing of the rising edge of the second clock signal CLK2. The third clock signal CLK3 has a period twice that of the second clock signal CLK2 and four times that of the first clock signal CLK1.

[0042] In this way, the count circuit 5 is configured such that the pulse period of the pulse signal output from the output terminal (Q) increases as the stage of the D flip-flop increases.

[0043] <Considerations regarding the duty ratio of the first clock signal CLK1> FIG. 4 is a timing chart showing the input voltage V1, the first clock signal CLK1, the second clock signal CLK2, and the third clock signal CLK3 when the power supply voltage Vcc is set relatively high.

[0044] 3 and 4, the logic level of the first clock signal CLK1 switches when the input voltage V1 matches the inversion threshold Vth. Therefore, as the inversion threshold Vth increases, the on-duty of the first clock signal CLK1 decreases. Therefore, as shown in FIG. 4, if the power supply voltage Vcc is set to a relatively high value, the value of the inversion threshold Vth becomes relatively high, and the on-duty of the first clock signal CLK1 becomes relatively small.

[0045] If the on-duty of the first clock signal CLK1 becomes smaller, there is a risk that the D flip-flop D1 will not be able to set the logic level of its input terminal (D) while the first clock signal CLK1 is at a high level. As a result, the logic level of the second clock signal CLK2 will not switch correctly at the rising edge of the first clock signal CLK1. This prevents the count circuit 5 from counting the write time correctly. This causes the time it takes to write data to the memory circuit 3 to exceed the intended write time.

[0046] To address this problem, the semiconductor device 100 of the present disclosure is capable of suppressing overrunning of the time required to write data to the memory circuit 3. The semiconductor device 100 according to the embodiment of the present disclosure will be described in detail below. As described above, the semiconductor device 100 according to the embodiment of the present disclosure includes components in common with the semiconductor device 50 described above. For this reason, the same reference numerals are used to designate the common components, and descriptions thereof will be omitted.

[0047] <Regarding the semiconductor device 100 according to the embodiment of the present disclosure> Fig. 5 is a diagram showing a semiconductor device 100 according to the present disclosure. As shown in Fig. 5, the semiconductor device 100 includes the oscillator circuit 1, charge pump circuit 2, memory circuit 3, count circuit 5, and enable signal generation circuit 6, which are similar to those described above. In addition to these, the semiconductor device 100 also includes a level shift circuit 4x.

[0048] The level shift circuit 4x receives the internal clock signal PCLK and generates a first clock signal CLK1 that pulses at a predetermined frequency. The detailed configuration of the level shift circuit 4x is as follows.

[0049] The level shift circuit 4x includes a transistor N1, an inverter IV20, a constant current source CC1, and a buffer circuit Bf.

[0050] The inverter IV20 includes a transistor P1, a transistor N2, and a current limiting element DN1, which is a depletion-mode N-channel MOSFET.

[0051] The gate terminal of the current limiting element DN1 is connected to the drain terminal of the transistor N2 together with its source terminal, and the drain terminal of the current limiting element DN1 is connected to the drain terminal of the transistor P1.

[0052] The gate terminal of transistor P1, together with the gate terminal of transistor N2, constitutes the input terminal of inverter IV20. The drain terminal of transistor N2, together with the gate terminal and source terminal of current limiting element DN1, constitutes the output terminal of inverter IV20. The drain terminal of transistor N2 and the gate terminal and source terminal of current limiting element DN1 (= output terminal of inverter IV20) are connected to the input terminal of buffer circuit Bf.

[0053] Here, the connection node between the source terminal of the current limiting element DN1 and the drain terminal of the transistor N2 is referred to as node n3. The voltage generated at node n3 is referred to as output voltage V3 of the inverter IV20. Note that node n3 corresponds to the aforementioned node n2.

[0054] As mentioned above, the current limiting element DN1 has its gate and source terminals connected, and the gate-source voltage difference is zero. As also mentioned above, the current limiting element DN1 is a depletion-type N-channel transistor. Therefore, the current limiting element DN1 is always on and functions as a resistance component due to its own on-resistance.

[0055] When transistor P1 is on, current flows from the power supply voltage Vcc application terminal to node n3 via transistor P1 and current limiting element DN1. At this time, current limiting element DN1 limits the current flowing through itself by an amount proportional to its own on-resistance. This can also be expressed as follows:

[0056] The output voltage V3 when transistor P1 is on and transistor N2 is off is the product of the combined resistance of the on-resistances of transistor P1 and current limiting element DN1 and the current flowing through transistor P1 and current limiting element DN1. Therefore, the output voltage V3 when transistor P1 is on is lower by the on-resistance of current limiting element DN1 compared to a configuration without current limiting element DN1 (for example, the output voltage V2 of the inverter IV10 mentioned above).

[0057] The inverter IV20 has a predetermined inversion threshold Vth. When the input voltage V1 is below the inversion threshold Vth, the output voltage V3 is at a high level, and when the input voltage V1 is above the inversion threshold Vth, the output voltage V3 is at a low level.

[0058] As described above, the inversion threshold Vth is determined by the drive strength of the high-side transistor (here, transistor P1) and the low-side transistor (here, transistor N2). As described above, the amount of current that flows when transistor P1 is saturated is limited by current limiting element DN1. Therefore, when both transistors P1 and N2 are saturated, the drive strength of transistor N2 becomes dominant, and the inversion threshold Vth shifts to the low side. In other words, the drive strength of transistor N2 becomes dominant due to the current limiting element DN1, and the inversion threshold Vth becomes lower than that of a configuration without current limiting element DN1 (e.g., the inversion threshold Vth of inverter IV10).

[0059] Therefore, even if the power supply voltage Vcc is set to a relatively high voltage, the inversion threshold Vth is unlikely to become high. This prevents the on-duty of the first clock signal CLK1 from decreasing. This ensures that the logic level of the second clock signal CLK2 switches correctly at the rising edge of the first clock signal CLK1. This prevents the time required to write data to the memory circuit 3 from exceeding the target write time.

[0060] <Modification> The present disclosure is not limited to the above-described embodiments, and various modifications are possible without departing from the spirit of the present disclosure. For example, although the current limiting element DN1 described above is a depression-type N-channel MOSFET, this is not limiting. For example, a resistor can also be used as the current limiting element DN1. Compared to using a resistor, using a depression-type N-channel MOSFET reduces the influence of the temperature characteristics of the current limiting element DN1, and further suppresses an increase in circuit area.

[0061] Also, for example, as shown in FIG. 6, the current limiting element DN1 may be disposed between the application terminal of the power supply voltage Vcc and the source terminal of the transistor P1.

[0062] 7, a constant current source CC2 may be disposed between the application terminal of the power supply voltage Vcc and the source terminal of the transistor P1. In this case, the constant current source CC2 is configured to pass a current through the transistor P1 while limiting the current value to a predetermined value or less.

[0063] The semiconductor device 100 can be mounted on an electronic device 200 that is an in-vehicle device.

[0064] <Additional Notes> The level shift circuit (4x) disclosed in the specification includes an input stage (N1) configured to generate a triangular wave signal (V1) that alternately rises and falls in response to a first pulse signal (PCLK), an output stage (IV20) configured to generate a second pulse signal (CLK1) whose logic level inverts between a high level and a low level in response to a power supply voltage (Vcc) when the triangular wave signal (V1) matches an inversion threshold (Vth), and a current limiting circuit (DN1) connected between an application terminal of the power supply voltage (Vcc) and an output terminal of the second pulse signal (CLK1) and configured to limit a current flowing from the power supply voltage (Vcc) to the output stage (IV20), and the output stage (IV20) is configured so that the inversion threshold (Vth) is determined in response to the current (first configuration).

[0065] In the level shift circuit (4x) according to the first configuration, the output stage (IV20) includes a high-side switch (P1) and a low-side switch (N2) connected in series between an application terminal of a power supply voltage (Vcc) and an application terminal of a low-level voltage, and the current limiting circuit (DN1) is connected between the high-side switch (P1) and the application terminal of the power supply voltage (Vcc) to limit the current (second configuration).

[0066] In the level shift circuit (4x) according to the first or second configuration, the current limiting circuit (DN1) is a depletion type transistor (third configuration).

[0067] The semiconductor device (100) disclosed in the specification may be configured to include a level shift circuit (4x) according to any one of the first to third configurations, and a count circuit (5) configured to count time in response to the second pulse signal (CLK1) (fourth configuration).

[0068] A semiconductor device (100) according to a fourth configuration may be configured to include an oscillator circuit (1) configured to generate a first pulse signal (PCLK), a nonvolatile memory (3) configured to be able to write data, and a charge pump circuit (2) configured to generate a write voltage (VPP) by boosting a power supply voltage (Vcc) and apply the write voltage (VPP) to the nonvolatile memory (3) for a time counted by a count circuit (5), thereby writing data to the nonvolatile memory (3) (fifth configuration).

[0069] The electronic device (200) disclosed in the specification includes the semiconductor device (100) according to the fifth configuration (sixth configuration). [Explanation of symbols]

[0070] 1. Oscillator circuit 2. Charge pump circuit 2a Boost clock generation circuit 2b Boost circuit 3 Memory Circuit 4x, 4y level shift circuit 5 Counting circuit 6 Enable signal generation circuit 50 Semiconductor devices 100 Semiconductor device 200 Electronic equipment Bf buffer circuit CC1 constant current source CC2 constant current source CD Column Decoder CLK1 First clock signal CLK2 Second clock signal CLK3 Third clock signal D1, D2 D flip-flops DN1 Current limiting element EN Enable signal GND grounding end IV1, IV2 inverter IV10 Inverter IV20 Inverter Iref current MCA Memory Cell Array P1, N1, N2 transistors PCLK Internal clock signal RD Row Decoder S1 output signal V1 input voltage V2, V3 output voltage VPP write voltage Vcc power supply voltage Vth inversion threshold n1~n3 nodes

Claims

1. an input stage configured to generate a triangular wave signal that alternately rises and falls in response to a first pulse signal; an output stage configured to generate a second pulse signal whose logic level inverts between a high level and a low level according to a power supply voltage when the triangular wave signal matches an inversion threshold; a current limiting circuit connected between an application terminal of the power supply voltage and an output terminal of the second pulse signal, and configured to limit a current flowing from the power supply voltage to the output stage; Including, The output stage is a level shift circuit configured so that the inversion threshold is determined in accordance with the current.

2. the output stage includes a high-side switch and a low-side switch connected in series between an application terminal of the power supply voltage and an application terminal of the low-level voltage, 2. The level shift circuit according to claim 1, wherein the current limiting circuit is connected between the high-side switch and an application terminal of the power supply voltage to limit the current.

3. 2. The level shift circuit according to claim 1, wherein the current limiting circuit is a depletion-type transistor.

4. a level shift circuit according to claim 1; a counting circuit configured to count time in response to the second pulse signal; A semiconductor device comprising:

5. an oscillator circuit configured to generate the first pulse signal; a non-volatile memory configured to be able to write data; a charge pump circuit configured to generate a write voltage by boosting the power supply voltage, and to apply the write voltage to the nonvolatile memory for the time counted by the count circuit, thereby writing the data to the nonvolatile memory; The semiconductor device according to claim 4 , comprising:

6. An electronic device comprising the semiconductor device according to claim 5 .

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