Semiconductor storage device, memory system, and method

Abstract

To provide a semiconductor storage device capable of appropriately storing parameter data in a feature register group of an interface chip, a memory system, and a method.SOLUTION: A semiconductor storage device comprises a first device (memory chips CP0-0 to CP0-3, CP1-0 to CP1-3) and a second device (interface chip). The first device comprises a first register group (feature register group 203) to which a first address space is mapped, and a memory cell array. The second device comprises a second register group (feature register group 112) including a plurality of pages to which a common second address space, exclusive of the first address space, is mapped. When it receives a command sequence of a setting command, the second device identifies a page in which parameter data is to be stored among the plurality of pages if the address included in the command sequence is a first value on the basis of the command sequence of the setting command.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present embodiment relates to a semiconductor memory device, a memory system, and a method. [Background technology]

[0002] There is a semiconductor memory device that has a semiconductor integrated circuit called an interface chip arranged between multiple memory chips and a group of external terminals connected to an external controller (hereinafter referred to as a memory controller). In this semiconductor memory device, data transfer between the memory controller and multiple memory chips is performed via the interface chip. The interface chip distributes the load on the transmission lines, allowing the memory system to operate at high speed even when a large number of memory chips are installed.

[0003] The interface chip, like the memory chip, has a group of feature registers for setting functions. Storing parameter data in the feature registers of the memory chip and the interface chip is performed using a common specific command. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] U.S. Patent No. 1,537,537 Summary of the Invention [Problem to be solved by the invention]

[0005] An object of one embodiment is to provide a semiconductor memory device, a memory system, and a method that can suitably store parameter data in a group of feature registers provided in an interface chip. [Means for solving the problem]

[0006] According to one embodiment, a semiconductor memory device includes a terminal group, a first device, and a second device. A command sequence of a setting command including an address is input to the terminal group. The first device includes a first register group to which a first address space is mapped, and a memory cell array. The first device stores parameter data in the first register group when the address is included in the first address space. The first device does not store parameter data in the first register group when the address is not included in the first address space. The second device is disposed between the terminal group and the first device. The second device includes a second register group including multiple pages to which a common second address space exclusive to the first address space is mapped. The second device is configured to identify a page among the multiple pages in which the parameter data is to be stored based on the command sequence when the address is a first value. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 is a schematic diagram showing an example of the configuration of a memory system according to a first embodiment. [Figure 2] FIG. 3 is a schematic diagram for explaining a more detailed connection relationship between the interface chip and each memory chip according to the first embodiment. [Figure 3] FIG. 2 is a diagram for explaining an example of the configuration of an interface chip and each memory chip according to the first embodiment. [Figure 4] FIG. 4 is a diagram showing the configuration of a command sequence for transferring a SetFeature command according to the first embodiment. [Figure 5] FIG. 4 is a diagram for explaining a parameter data setting method according to the first embodiment using the first sequence. [Figure 6] 5 is a flowchart showing an example of the operation of the interface chip according to the first embodiment. [Figure 7] 5 is a flowchart showing an example of the operation of the memory chip according to the first embodiment. [Figure 8]FIG. 10 is a diagram showing the configuration of a second sequence, which is another command sequence for transferring a SetFeature command according to the first embodiment. [Figure 9] FIG. 10 is a diagram for explaining an example of the configuration of an interface chip and each memory chip according to a second embodiment. [Figure 10] FIG. 10 is a diagram showing the configuration of a second sequence according to the second embodiment. [Figure 11] FIG. 10 is a diagram for explaining a parameter data setting method according to the second embodiment using a second sequence. [Figure 12] 10 is a flowchart showing an example of the operation of the interface chip according to the second embodiment. [Figure 13] 10 is a flowchart showing an example of the operation of the memory chip according to the second embodiment. [Figure 14] FIG. 11 is a diagram showing the configuration of a second sequence according to the third embodiment. [Figure 15] FIG. 10 is a diagram for explaining an example of the configuration of an interface chip and each memory chip according to the third embodiment. [Figure 16] FIG. 11 is a diagram showing an example of the configuration of a conversion table according to the third embodiment. [Figure 17] 10 is a flowchart showing an example of the operation of the interface chip according to the third embodiment. [Figure 18] 10 is a flowchart showing an example of the operation of the memory chip according to the third embodiment. [Figure 19] FIG. 10 is a diagram for explaining an example of the configuration of an interface chip and each memory chip according to the fourth embodiment. [Figure 20] FIG. 13 is a diagram showing an example of the configuration of a conversion table according to the fourth embodiment. [Figure 21] FIG. 10 is a diagram for explaining a parameter data setting method according to the fourth embodiment using the first sequence. [Figure 22] 10 is a flowchart showing an example of the operation of the interface chip according to the fourth embodiment. [Figure 23] 10 is a flowchart showing an example of the operation of the memory chip according to the fourth embodiment. [Figure 24] FIG. 13 is a diagram for explaining an example of the configuration of an interface chip and each memory chip according to the fifth embodiment. [Figure 25] FIG. 13 is a diagram showing an example of the configuration of a conversion table according to the fifth embodiment. [Figure 26] FIG. 13 is a diagram showing the configuration of a first sequence according to the fifth embodiment. [Figure 27] FIG. 10 is a diagram for explaining a parameter data setting method according to the fifth embodiment using the first sequence. [Figure 28] FIG. 13 is another diagram for explaining the parameter data setting method of the fifth embodiment using the first sequence. [Figure 29] 13 is a flowchart showing an example of the operation of the interface chip according to the fifth embodiment. [Figure 30] 10 is a flowchart showing an example of the operation of the memory chip according to the fifth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0008] A semiconductor memory device, a memory system, and a method according to embodiments will be described in detail below with reference to the accompanying drawings. However, the present invention is not limited to these embodiments.

[0009] (First embodiment) FIG. 1 is a schematic diagram showing an example of the configuration of a memory system SYS according to the first embodiment.

[0010] The memory system SYS can be connected to a host HS. The communication path connecting the host HS and the memory system SYS and the standard to which communication via the communication path conforms are not limited to a specific standard. The host HS is, for example, a personal computer, a portable information terminal, or a server. When accessing the memory system SYS, the host HS transmits an access command to the memory system SYS. The access command includes a write command, a read command, or the like.

[0011] The memory system SYS includes a semiconductor memory device 1, a memory controller MC, and a RAM (Random Access Memory) 2.

[0012] The memory controller MC is a control device that controls the semiconductor memory device 1. As part of the control of the semiconductor memory device 1, the memory controller MC executes data transfer between the host HS and the semiconductor memory device 1 in response to an access command from the host HS.

[0013] The RAM2 provides the memory controller MC with functions such as a buffer area, a cache area, and an area into which programs are loaded. For example, the memory controller MC can buffer data transferred between the host HS and the semiconductor memory device 1 in the RAM2. The memory controller MC also loads firmware programs into the RAM2 for use, and buffers or caches various management data in the RAM2. In the example shown in FIG. 1, the RAM2 is located outside the memory controller MC. The RAM2 may also be built into the memory controller MC.

[0014] The semiconductor memory device 1 includes a terminal group T, an interface chip IFC, and a plurality of memory chips CP0-0 to CP0-3 and CP1-0 to CP1-3. The interface chip IFC is arranged between the terminal group T and the plurality of memory chips CP0-0 to CP0-3 and CP1-0 to CP1-3.

[0015] Each of the plurality of memory chips CP0-0 to CP0-3, CP1-0 to CP1-3 is, for example, a memory chip of a nonvolatile memory such as a NAND type flash memory. Here, each of the plurality of memory chips CP0-0 to CP0-3, CP1-0 to CP1-3 is assumed to be a memory chip of a NAND type flash memory.

[0016] The semiconductor memory device 1 may be implemented as an MCP (Multi Chip Package) in which the memory chips CP0-0 to CP0-3 and the memory chips CP1-0 to CP1-3 are stacked. When the semiconductor memory device 1 is implemented as an MCP, the interface chip IFC and the memory chips CP0-0 to CP0-3 and CP1-0 to CP1-3 may be sealed with a molding resin.

[0017] The semiconductor memory device 1 also includes a plurality of channels that connect the plurality of memory chips CP0-0 to CP0-3, CP1-0 to CP1-3 to the interface chip IFC. Each of these channels is referred to as a memory channel MCH, meaning a channel that connects a NAND flash memory.

[0018] 1, the semiconductor memory device 1 includes memory channels MCH0 and MCH1 as the multiple memory channels MCH. Four memory chips CP0-0 to CP0-3 are connected to the interface chip IFC via memory channel MCH0, and four memory chips CP1-0 to CP1-3 are connected to the interface chip IFC via memory channel MCH1.

[0019] Each memory channel MCH is configured based on a predetermined standard. When each of the memory chips CP0-0 to CP0-3 and CP1-0 to CP1-3 is a NAND flash memory, the predetermined standard is, for example, the toggle DDR standard.

[0020] The number of memory chips CP included in the semiconductor memory device 1 is not limited to eight. Furthermore, the number of memory channels MCH connecting the interface chip IFC and the plurality of memory chips CP is not limited to two.

[0021] Each of the memory chips CP0-0 to CP0-3 and CP1-0 to CP1-3 is an example of a first device, and the interface chip IFC is an example of a second device.

[0022] Hereinafter, each of the memory chips CP0-0 to CP0-3 and CP1-0 to CP1-3 may be referred to as a memory chip CP.

[0023] The semiconductor memory device 1 is connected to the memory controller MC via one channel. This one channel is referred to as a host channel HCH, meaning a channel on the host side as seen from the interface chip IFC.

[0024] The host channel HCH is configured based on a predetermined standard. When each memory chip CP is a NAND flash memory, the predetermined standard is, for example, the toggle DDR standard.

[0025] The host channel HCH includes a signal line for transferring a chip enable signal CEn, a signal line for transferring a command latch enable signal CLE, a signal line for transferring an address latch enable signal ALE, a signal line for transferring a write enable signal WEn, a signal line for transferring a read enable signal RE / REn, a signal line for transferring a data strobe signal DQS / DQSn, a signal line for transferring a data signal DQ[7:0] having a predetermined bit width (here, 8 bits as an example), a signal line for transferring a ready / busy signal R / Bn_1, and a signal line for transferring a ready / busy signal R / Bn_2. Note that the "n" at the end of the symbol representing a signal indicates that the signal operates in negative logic. Whether each signal operates in negative logic or positive logic can be designed arbitrarily.

[0026] The chip enable signal CEn is a signal for enabling the memory chip CP to be accessed. The data strobe signal DQS / DQSn is a signal that instructs the other device to take in the data transmitted by the data signal DQ[7:0]. The data strobe signal DQS / DQSn is a differential signal composed of the data strobe signal DQS and the data strobe signal DQSn. The command latch enable signal CLE is a signal that indicates that the data signal DQ[7:0] is a command. The address latch enable signal ALE is a signal that indicates that the data signal DQ[7:0] is an address. The write enable signal WEn is a signal that instructs the other device to take in the command or address transmitted by the data signal DQ[7:0]. The read enable signal RE / REn is a signal that instructs the other device to output the data signal DQ[7:0]. The read enable signal RE / REn is a differential signal composed of the read enable signal RE and the read enable signal REn. The ready-busy signals R / Bn_1 and R / Bn_2 are signals that indicate whether the host channel HCH is in a ready state, in which it is waiting to receive a command, or in a busy state, in which it cannot execute a received command. The configuration of the signal lines that the host channel HCH includes to transfer the ready-busy signal R / Bn is not limited to the example described above. For example, the host channel HCH may include a single signal line for transferring a single ready-busy signal R / Bn generated by a wired-OR connection or the like from the ready-busy signal R / Bn associated with memory channel MCH0 and the ready-busy signal R / Bn associated with memory channel MCH1.

[0027] Each of the memory channels MCH0 and MCH1 can transmit and receive the same types of signals as those of the host channel HCH. That is, each of the memory channels MCH0 and MCH1 includes a signal line for transferring a chip enable signal CEn, a signal line for transferring a command latch enable signal CLE, a signal line for transferring an address latch enable signal ALE, a signal line for transferring a write enable signal WEn, a signal line for transferring a read enable signal RE / REn, a signal line for transferring a data strobe signal DQS / DQSn, a signal line group for transferring a data signal DQ[7:0], and a signal line for transferring a ready / busy signal R / Bn.

[0028] FIG. 2 is a schematic diagram for explaining in more detail the connection relationship between the interface chip IFC and each memory chip CP of the first embodiment.

[0029] 2, the four memory chips CP0-0 to CP0-3 are commonly connected to a memory channel MCH0. Similarly, the four memory chips CP1-0 to CP1-3 are commonly connected to a memory channel MCH1.

[0030] The memory chips CP0-0 to CP0-3 and CP1-0 to CP1-3 do not necessarily have to be commonly connected to all of the signal lines that make up the corresponding memory channels MCH. The memory chips CP0-0 to CP0-3 and CP1-0 to CP1-3 may be configured so that some of the signal lines that make up the corresponding memory channels MCH, except for the signal lines that transfer data signals DQ[7:0], connect the interface chip IFC to the individual memory chips CP one-to-one.

[0031] The interface chip IFC can execute data transfers via memory channel MCH0 and memory channel MCH1 independently. The host channel HCH, which connects the memory controller MC and the interface chip IFC, is controlled to prevent data transfers from being delayed in the interface chip IFC even when data transfers via memory channel MCH0 and memory channel MCH1 are executed in parallel. Therefore, the host channel HCH can transfer data at a transfer rate that is the sum of the transfer rates of memory channel MCH0 and memory channel MCH1. In other words, the host channel HCH can transfer data at a transfer rate that is twice that of the memory channel MCH.

[0032] Each memory chip CP is assigned a LUN (Logical Unit Number), which is an identification number unique within the semiconductor memory device 1. The memory controller MC stores in advance the relationship between the LUN assigned to each memory chip CP and the memory channel MCH to which the memory chip CP is connected. In the example shown in Fig. 2, the memory controller MC stores in advance that memory chip CP0-0 is assigned LUN0, memory chip CP0-1 is assigned LUN1, memory chip CP0-2 is assigned LUN2, memory chip CP0-3 is assigned LUN3, memory chip CP1-0 is assigned LUN4, memory chip CP1-1 is assigned LUN5, memory chip CP1-2 is assigned LUN6, and memory chip CP1-3 is assigned LUN7.

[0033] 3 is a diagram for explaining an example of the configuration of the interface chip IFC and each memory chip CP according to the first embodiment. The memory chips CP0-0 to CP0-3 and CP1-0 to CP1-3 have a common configuration. In this diagram, the configuration of the memory chips CP0-0 and CP1-0 is shown as representative of the memory chips CP0-0 to CP0-3 and CP1-0 to CP1-3, and the configurations of the other memory chips CP are not shown.

[0034] The interface chip IFC includes a host interface 101 , two memory interfaces 102 , and a controller 103 .

[0035] The host interface 101 is a PHY circuit that transmits and receives electrical signals to and from the host HA via the host channel HCH.

[0036] Of the two memory interfaces 102, memory interface 102-0 is a PHY circuit that transmits and receives electrical signals to and from four memory chips CP0-1 to CP0-3 via memory channel MCH0. Of the two memory interfaces 102, memory interface 102-1 is a PHY circuit that transmits and receives electrical signals to and from four memory chips CP1-0 to CPU1-3 via memory channel MCH1.

[0037] The controller 103 is disposed between the host interface 101 and the two memory interfaces 102. The controller 103 controls the transmission and reception of signals between the host interface 101 and the two memory interfaces 102.

[0038] The controller 103 includes a command decoder 111 and a set of feature registers 112 .

[0039] The command decoder 111 analyzes signals such as commands received from the host HA via the host channel HCH. The command decoder 111 can transfer signals to the memory chip CP according to the analysis results. If the command is an operation instruction for the interface chip IFC, the command decoder 111 can operate in accordance with the command.

[0040] The feature register group 112 is a group of registers for setting functions of the interface chip IFC. The feature register group 112 stores parameter data for one or more functions provided in the interface chip IFC.

[0041] Each memory chip CP includes a memory interface 201 , an access circuit 202 , a feature register group 203 , and a memory cell array 204 .

[0042] The memory interface 201 is a PHY circuit that transmits and receives electrical signals to and from the interface chip IFC via the memory channel MCH.

[0043] The memory cell array 204 has a plurality of memory cell transistors. Each memory cell transistor is associated with a row and a column. The memory cell array 204 stores data specified by a write command from the memory controller MC via the interface chip IFC.

[0044] The feature register group 203 is a register for setting functions of the memory chip CP. The feature register group 203 stores parameter data for one or more functions provided in the memory chip CP.

[0045] The access circuit 202 includes, for example, a signal processing circuit, a row decoder, a column decoder, a sense amplifier, a latch circuit, and a voltage generation circuit. The access circuit 202 performs operations such as accessing the memory cell array 204 or storing parameter data in the feature register group 203 in response to commands received from the memory controller MC via the interface chip IFC.

[0046] The feature register set 203 is an example of a first register set, and the feature register set 112 is an example of a second register set.

[0047] The memory controller MC uses a common setting command to store parameter data in the feature register group 112 included in the interface chip IFC and in the feature register group 203 included in each memory chip CP. This setting command is called a SetFeature command.

[0048] The size of the address space (referred to as the feature register space) that can be specified as the storage destination for parameter data using the SetFeature command is defined by the standard. For example, for semiconductor memory devices with NAND-type flash memory, the Joint Electron Device Engineering Councils (JEDEC) defines a feature register space consisting of 256 addresses. Each memory vendor can assign the functions they need to this feature register space.

[0049] The semiconductor memory device 1 includes feature register sets 112 and 203. Therefore, the feature register sets 112 and 203 need to share a finite feature register space.

[0050] As an example of a technique for sharing a feature register space, a technique to be compared with the embodiment will be described. The technique to be compared with the embodiment will be referred to as a comparative example. According to the comparative example, a part of the feature register space is mapped to the feature register group of each memory chip, and another part is mapped to the feature register group of the interface chip. In other words, the feature register space is simply divided into a partial space for each memory chip and a partial space for the interface chip.

[0051] In recent years, there has been an increasing demand for faster interface chips. This has created a need for interface chips to have many registers that can set various communication functions, such as training and equalizer functions. This means that the amount of parameter data that needs to be set for interface chips (and memory chips) is on the rise.

[0052] In contrast, in the comparative example, the feature register space is simply divided into a partial space for each memory chip and a partial space for the interface chip, making it difficult to allocate a large space to the partial space for the interface chip, and there is a risk that the partial space for the interface chip will be insufficient to accommodate the increasing amount of parameter data.

[0053] In the first embodiment, the feature register group 112 has multiple pages, and a common partial space is mapped to the multiple pages. The interface chip IFC is configured to interpret the command sequence of the SetFeature command as a command for specifying a page when the address included in the command sequence of the SetFeature command is a specific value. This allows the partial space for the interface chip IFC to be expanded without reducing the partial space for each memory chip CP.

[0054] 3, the feature register set 203 of each memory chip CP has 240 storage areas each assigned with a different address in the range of 00h to EFh. In other words, the feature register space in the range of 00h to EFh is mapped onto the feature register set 203. Each of the 240 storage areas has a storage capacity of 32 bits.

[0055] The feature register group 112 included in the interface chip IFC includes multiple sets of 16 memory areas, each assigned a different address in the range of F0h to FFh. Each set of 16 memory areas is considered to be a different page. In other words, a feature register space in the range of F0h to FFh is mapped to each of the multiple pages included in the feature register group 112. A unique value is associated with each page as an identification number. The value associated with each page is referred to as a page number. Each of the 16 memory areas included in each page has a storage capacity of 32 bits.

[0056] Each of the addresses (addresses 00h to EFh in the example shown in FIG. 1) given to the feature register group 203 of the memory chip CP is referred to as a memory feature address. Each of the addresses (addresses F0h to FFh in the example shown in FIG. 1) given to the feature register group 112 of the interface chip IFC is referred to as an interface feature address. Addresses included in the feature register space may also be referred to as feature addresses.

[0057] The command decoder 111 is configured to interpret address F0h of the interface feature addresses as a command for page designation (referred to as a page designation identifier).

[0058] The SetFeature command is transferred in a command sequence of a predetermined format. The command sequence for transferring the SetFeature command includes an address field and a data field, and the page specification identifier is transferred using the address field.

[0059] FIG. 4 is a diagram showing the configuration of a command sequence for transferring a SetFeature command according to the first embodiment.

[0060] The SetFeature command includes a first SetFeature command and a second SetFeature command. The first SetFeature command is a SetFeature command for setting parameter data commonly to multiple memory chips CP. The second SetFeature command is a SetFeature command for specifying one memory chip CP using a LUN and setting parameter data for the specified memory chip CP. Figure 4 shows the configuration of a command sequence for transferring the first SetFeature command. The command sequence for transferring the first SetFeature command will be referred to as the first sequence hereinafter.

[0061] The first sequence is configured to transfer a first SetFeature command C1, a first address, and setting data in this order. The first SetFeature command C1, the first address, and setting data are transferred through a group of signal lines that transfer the data signal DQ[7:0]. The first SetFeature command C1 is transferred in one command transfer cycle. The first address is transferred in one address transfer cycle. The setting data is transferred in four data transfer cycles. The command transfer cycle is a cycle in which the data signal DQ[7:0] is transferred as a command using the command latch enable signal CLE. The address transfer cycle is a cycle in which the data signal DQ[7:0] is transferred as an address using the address latch enable signal ALE. The data transfer cycle is a cycle in which the data signal DQ[7:0] is transferred as data.

[0062] The data signal DQ[7:0] is transferred with a width of 8 bits. Since the first address is transferred in one address transfer cycle, the first address can be an address in the range of 00h to FFh, i.e., an address in the range of the feature register space.

[0063] The setting data is transferred in four data transfer cycles. Therefore, 32 bits (= 8 bits × 4) of setting data can be transferred in one first sequence.

[0064] In the first embodiment, the first sequence is configured to be able to transfer, as the first address, any of an address corresponding to a memory feature address, an address corresponding to an interface feature address, and an address corresponding to a page specification identifier.

[0065] The first sequence is configured to be able to transfer not only parameter data but also information specifying a page (hereinafter, page specification) as setting data. When transferring a page specification as setting data, the memory controller MC can specify any one of the multiple pages included in the feature register group 112 by transferring a page number as setting data.

[0066] FIG. 5 is a diagram for explaining a parameter data setting method according to the first embodiment using the first sequence.

[0067] In the example shown in FIG. 5, the memory controller MC transfers the first sequence SQ1, the first sequence SQ2, the first sequence SQ3, and the first sequence SQ4 to the semiconductor memory device 1 in this order.

[0068] The first sequence SQ1 includes an address F0h that is a page designation identifier as the first address, and a value 01h that is a page designation that designates page #1 as setting data. When the interface chip IFC receives the first sequence SQ1, the command decoder 111 recognizes that the first sequence SQ1 is a command sequence for page designation because the first sequence SQ1 includes the page designation identifier. The command decoder 111 recognizes that page #1 has been designated because the first sequence SQ1 includes the value 01h as setting data.

[0069] The first sequence SQ2 includes an address F1h corresponding to an interface feature address as a first address, and parameter data as setting data. When the interface chip IFC receives the first sequence SQ2 following the first sequence SQ1, the command decoder 111 stores the parameter data included in the first sequence SQ2 at a location indicated by the address F1h of page #1, which is the already specified page, in the feature register group 112.

[0070] The first sequence SQ3 includes an address F0h, which is a page designation identifier, as the first address, and a value 02h, which is a page designation designating page #2, as setting data. When the interface chip IFC receives the first sequence SQ3, the command decoder 111 recognizes that the first sequence SQ3 is a command sequence for page designation because the first sequence SQ3 includes the page designation identifier. The command decoder 111 recognizes that page #2 has been designated because the first sequence SQ3 includes the value 02h as setting data.

[0071] The first sequence SQ4 includes address FFh, which corresponds to the interface feature address, as the first address, and parameter data as the setting data. When the interface chip IFC receives the first sequence SQ4 following the first sequence SQ3, the command decoder 111 stores the parameter data included in the first sequence SQ4 at the location indicated by address FFh on page #2 in the feature register group 112.

[0072] In this way, the feature register group 112 of the interface chip IFC has multiple pages to which a total of 16 addresses, F0h to FFh, are assigned. The first sequence is configured to enable switching of the page in which parameter data is stored from multiple pages. Therefore, the address space available for setting parameter data in the interface chip IFC is expanded according to the number of pages provided in the feature register group 112. This makes it possible to increase the capacity of the feature register group 112 of the interface chip IFC that can store parameter data. In other words, it is possible to increase the amount of parameter data that can be stored in the feature register group 112 compared to the comparative example.

[0073] FIG. 6 is a flowchart showing an example of the operation of the interface chip IFC according to the first embodiment.

[0074] When the interface chip IFC receives a first sequence from the memory controller MC via the terminal group T (S101), the controller 103 transfers the received first sequence to the memory chips CP group (S102).

[0075] The command decoder 111 determines whether the first address included in the received first sequence corresponds to a page designation identifier (S103). In the example shown in Figures 3 and 5, address F0h corresponds to the page designation identifier.

[0076] If the first address corresponds to the page designation identifier (S103: Yes), the command decoder 111 identifies the designated page based on the setting data included in the first sequence, and then stores the designated page (S104).

[0077] If the first address does not correspond to the page specification identifier (S103: No), the command decoder 111 determines whether the first address corresponds to an interface feature address (S105).

[0078] 3 and 5, addresses F0h to FFh correspond to interface feature addresses. Note that address F0h is used as a page designation identifier. Therefore, in S105, if the first address is one of addresses F1h to FFh, the command decoder 111 determines that the first address corresponds to an interface feature address.

[0079] If the first address corresponds to an interface feature address (S105: Yes), the command decoder 111 stores the parameter data included as setting data in the first sequence at the location indicated by the first address of the specified page in the feature register group 112 (S106).

[0080] If the first address does not correspond to the interface feature address (S105: No), or after S104, or after S106, the interface chip IFC ends the operation.

[0081] The interface chip IFC executes the operations of S102 to S106 every time it receives the first sequence, thereby realizing the operation shown in FIG.

[0082] 7 is a flowchart showing an example of the operation of the memory chip CP according to the first embodiment. All memory chips CP included in the semiconductor memory device 1 execute a common operation. Here, the operation of one memory chip CP will be described as a representative of all memory chips CP.

[0083] When the memory chip CP receives a first sequence via the interface chip IFC (S201), the access circuit 202 determines whether or not a first address included in the received first sequence corresponds to a memory feature address (S202).

[0084] 3 and 5, addresses 00h to EFh correspond to memory feature addresses. Therefore, in S202, the access circuit 202 determines that the first address corresponds to a memory feature address when the first address is one of addresses 00h to EFh.

[0085] If the first address corresponds to a memory feature address (S202: Yes), the access circuit 202 stores the parameter data included in the first sequence as setting data at the location indicated by the first address in the feature register group 203 (S203).

[0086] If the first address does not correspond to the memory feature address (S202: No), or after S203, the memory chip CP ends the operation.

[0087] In the above, an example has been described in which the first sequence is used as a command sequence for transferring a SetFeature command. Even when the semiconductor memory device 1 receives a command sequence for transferring a second SetFeature command (referred to as the second sequence), the semiconductor memory device 1 can perform the same operations as when it receives the first sequence (for example, the operations shown in FIGS. 5 and 6).

[0088] FIG. 8 is a diagram showing the configuration of a second sequence, which is another command sequence for transferring a SetFeature command according to the first embodiment.

[0089] The second sequence is configured so that the second SetFeature command C2, the second address, the first address, and the setting data are transferred in this order. The second SetFeature command C2 is transferred in one command transfer cycle. The first address and the second address are each transferred in one address transfer cycle. The setting data is transferred in four data transfer cycles.

[0090] The second address is an address at which a LUN can be specified.

[0091] In the interface chip IFC, the command decoder 111 executes the series of operations shown in FIG. 6 based on the first address and setting data, regardless of the second address.

[0092] The access circuit 202 of each memory chip CP executes the series of operations shown in FIG. 7 when the second address corresponds to the LUN given to the memory chip CP that includes it.

[0093] As described above, according to the first embodiment, a command sequence of a SetFeature command including a first address is input to the terminal group T. The memory chip CP includes a feature register group 203 to which a partial space (e.g., a space ranging from 00h to EFh) of the feature register space is mapped, and a memory cell array 204. The memory chip CP stores parameter data in the feature register group 203 when the first address is included in the partial space mapped to the feature register group 203, and does not store parameter data in the feature register group 203 when the first address is not included in the partial space mapped to the feature register group 203. The interface chip IFC includes a feature register group 112. The feature register group 112 includes multiple pages to which a common partial space (e.g., a space ranging from F0h to FFh) exclusive to the partial space mapped to the feature register group 203 is mapped. When the first address included in the received command sequence corresponds to a page specification identifier, the interface chip IFC identifies a page in which the parameter data is to be stored based on the setting data included in the command sequence.

[0094] Therefore, the partial space available for setting parameter data for the interface chip IFC is expanded according to the number of pages provided in the feature register group 112. It is possible to increase the capacity of the feature register group 112 of the interface chip IFC that can store parameter data. It is possible to increase the amount of parameter data that can be stored in the feature register group 112 compared to the comparative example. In other words, it becomes possible to suitably store parameter data in the feature register group 112 provided in the interface chip IFC.

[0095] Furthermore, according to the first embodiment, when the interface chip IFC receives a command sequence containing a value corresponding to the page designation identifier as the first address, it identifies one of the multiple pages included in the feature register group 112 based on the setting data included in the command sequence. After that, when the interface chip IFC receives a command sequence containing an interface feature address that does not correspond to the page designation identifier as the first address, it stores the parameter data included as setting data in the command sequence in the identified one of the multiple pages included in the feature register group 112.

[0096] Therefore, it is possible to increase the amount of parameter data that can be stored in the feature register group 112 compared to the comparative example. In other words, it is possible to suitably store parameter data in the feature register group 112 provided in the interface chip IFC.

[0097] (Second embodiment) In the second embodiment, differences from the first embodiment will be described. Explanations of the same matters as in the first embodiment will be omitted or will be given in a simplified manner.

[0098] FIG. 9 is a diagram for explaining an example of the configuration of the interface chip IFC and each memory chip CP according to the second embodiment.

[0099] In the second embodiment, the controller 103 of the interface chip IFC includes a command decoder 111a instead of the command decoder 111. The command decoder 111a is configured to be able to specify a page based on the second sequence.

[0100] Each memory chip CP includes an access circuit 202a instead of the access circuit 202.

[0101] FIG. 10 is a diagram illustrating a configuration of the second sequence according to the second embodiment.

[0102] The second sequence is configured so that a second SetFeature command C2, a second address, a first address, and setting data are transferred in this order.

[0103] The second sequence is configured to allow the transfer of both an address corresponding to a memory feature address and an address corresponding to an interface feature address as the first address. In other words, the first address is an address included in either the partial space of the feature register space mapped to the feature register set 203 (here, the space in the range of 00h to EFh) or the partial space mapped to the feature register set 112 (for example, the space in the range of F0h to FFh).

[0104] The second sequence is configured to allow transfer of both a LUN and a page designation as the second address. More specifically, if the first address is included in the subspace mapped to the interface feature address, i.e., the feature register group 112, the command decoder 111a interprets the second address as a page designation.

[0105] 2 and 9, the semiconductor memory device 1 includes eight memory chips CP assigned with LUNs 0 to 7. Therefore, the memory controller MC can designate one LUN of the eight memory chips CP by transferring a value in the range of 00h to 07h as the second address.

[0106] Furthermore, when transferring a page designation as the second address, the memory controller MC can designate any page by transferring a page number as the second address.

[0107] The second sequence is configured so that parameter data can be transferred as setting data.

[0108] FIG. 11 is a diagram for explaining a parameter data setting method according to the second embodiment using the second sequence.

[0109] In the example shown in FIG. 11, the memory controller MC transfers the second sequence SQ11 and the second sequence SQ21 to the semiconductor memory device 1 in this order.

[0110] The second sequence SQ11 includes an address F1h corresponding to the interface feature address and a value 01h as the second address. When the interface chip IFC receives the second sequence SQ11, the command decoder 111a recognizes that the second sequence SQ11 is a command sequence for a SetFeature command targeting the interface chip IFC because the first address corresponds to the interface feature address. With regard to the second sequence targeting the interface chip IFC, the command decoder 111a interprets the second address as a page designation. In the example shown in FIG. 11, the second sequence SQ11 includes a value 01h as the second address, so the command decoder 111a recognizes that page #1 is designated. Therefore, the command decoder 111a stores the parameter data included in the second sequence SQ11 as setting data at the location indicated by the address F1h of page #1 in the feature register group 112.

[0111] The second sequence SQ21 includes an address FFh corresponding to the interface feature address and a value 02h as the second address. Because the first address corresponds to the interface feature address, the command decoder 111a recognizes that the second sequence SQ21 is a command sequence for a SetFeature command targeting the interface chip IFC, and interprets the second address as a page designation. In the example shown in FIG. 11, because the second sequence SQ21 includes a value 02h as the second address, the command decoder 111a recognizes that page #2 is designated. Therefore, the command decoder 111a stores the parameter data included in the second sequence SQ21 as setting data at the location indicated by address FFh of page #2 in the feature register group 112.

[0112] FIG. 12 is a flowchart showing an example of the operation of the interface chip IFC according to the second embodiment.

[0113] When the interface chip IFC receives the second sequence from the memory controller MC (S301), the controller 103 transfers the received second sequence to the group of memory chips CP (S302).

[0114] The command decoder 111a determines whether the first address included in the received second sequence corresponds to an interface feature address (S303).

[0115] According to the examples shown in FIGS. 9 and 11, addresses F0h to FFh correspond to interface feature addresses.

[0116] If the first address corresponds to an interface feature address (S303: Yes), the command decoder 111a identifies the specified page based on the value included as the second address in the second sequence (S304).Then, the command decoder 111a stores the parameter data included as setting data in the second sequence at the location indicated by the first address of the specified page in the feature register group 112 (S305).

[0117] If the first address does not correspond to the interface feature address (S303: No), or after S305, the interface chip IFC ends the operation.

[0118] The interface chip IFC executes the operations of S302 to S305 every time it receives the second sequence, thereby realizing the operation shown in FIG.

[0119] 13 is a flowchart showing an example of the operation of the memory chip CP according to the second embodiment. As in the first embodiment, all memory chips CP included in the semiconductor memory device 1 execute a common operation. Here, the operation of one memory chip CP will be described as a representative of all memory chips CP.

[0120] When the memory chip CP receives the second sequence via the interface chip IFC (S401), the access circuit 202 determines whether the second address included in the received second sequence corresponds to the LUN assigned to the memory chip CP that includes the access circuit 202 (S402).

[0121] If the second address corresponds to the LUN assigned to the memory chip CP that includes it (S402: Yes), the access circuit 202 determines whether the second address included in the received second sequence corresponds to a memory feature address (S403).

[0122] 9 and 11, addresses 00h to EFh correspond to memory feature addresses. Therefore, in S403, the access circuit 202 determines that the first address corresponds to a memory feature address when the first address is any of addresses 00h to EFh.

[0123] If the first address corresponds to a memory feature address (S403: Yes), the access circuit 202 stores the parameter data included in the first sequence as setting data at the location indicated by the first address in the feature register group 203 (S404).

[0124] If the second address does not correspond to the LUN given to the memory chip CP having its own access circuit 202 (S402: No), or if the first address does not correspond to the memory feature address (S403: No), or after S404, the memory chip CP terminates the operation.

[0125] Thus, according to the second embodiment, the second sequence is configured to be transferable using a LUN or a page number as the second address. If the first address is included in the partial space mapped to the feature register set 112, the interface chip IFC interprets the second address as a page designation, i.e., a page number. Then, the interface chip IFC stores the parameter data at a location indicated by the first address in one of the multiple pages included in the feature register set 112 that corresponds to the page number.

[0126] Since a page can be specified using the second address of the second sequence, the memory controller MC can instruct both the page specification and the parameter data storage using one second sequence.

[0127] (Third embodiment) In the third embodiment, differences from the second embodiment will be described. Explanations of the same matters as in the second embodiment will be omitted or will be given in a simplified manner.

[0128] In the third embodiment, similar to the second embodiment, the memory controller MC can store parameter data in the feature registers of the interface chip IFC using the second sequence. However, the method of specifying the page differs from that of the second embodiment.

[0129] The second address is transferred in one address transfer cycle with an 8-bit width, so 256 different values ​​can be transferred as the second address. However, if the number of memory chips CP included in the semiconductor memory device 1 is less than 256, 256 different values ​​are not necessary to specify the LUN. For example, in the example shown in Figure 1, the number of memory chips CP included in the semiconductor memory device 1 is eight, so eight different values ​​are sufficient to specify the LUN.

[0130] In the third embodiment, a plurality of values ​​that are not used to specify a LUN out of the 256 values ​​that can be transferred as the second address are used to specify a page.

[0131] FIG. 14 is a diagram illustrating a configuration of the second sequence according to the third embodiment.

[0132] The second sequence is configured so that a second SetFeature command C2, a second address, a first address, and setting data are transferred in this order.

[0133] The second sequence is configured to allow both LUN and page designation to be transferred as the second address. Of the 256 possible values ​​that can be transferred as the second address, at least the value corresponding to the number of memory chips CP included in the semiconductor memory device 1 is used to designate the LUN, and the remaining values ​​are used to designate the page. According to the example shown in Figure 14, values ​​in the range from 00h to 0Fh are used to designate the LUN, and values ​​in the range from 10h to FFh are used to designate the page.

[0134] If the second address is any value in the range from 00h to 0Fh (case 1), the interface chip IFC interprets the first address as corresponding to a memory feature address. If the second address is any value in the range from 10h to FFh (case 2), the interface chip IFC interprets the first address as corresponding to an interface feature address.

[0135] FIG. 15 is a diagram for explaining an example of the configuration of the interface chip IFC and each memory chip CP according to the third embodiment.

[0136] In the third embodiment, the controller 103 of the interface chip IFC includes a command decoder 111b instead of the command decoder 111a. The controller 103 also includes a feature register group 112b instead of the feature register group 112. The controller 103 also includes a memory 113.

[0137] The feature register group 112b includes multiple sets of 256 memory areas, each assigned a different address in the range of 00h to FFh. Each set of 256 memory areas is considered a different page and is assigned a unique page number. Each of the 256 memory areas in each set has a storage capacity of 32 bits.

[0138] The memory 113 is a non-volatile memory that stores the conversion table 120. The memory 113 is, for example, an eFuse or a ROM (Read Only Memory). The conversion table 120 is stored in the memory 113 when the semiconductor memory device 1 is manufactured. Note that the type of memory 113 and the timing of storing the conversion table 120 are not limited to these.

[0139] Each memory chip CP has a feature register group 203b instead of the feature register group 203. The feature register group 203b has 256 storage areas each assigned a different address in the range of 00h to FFh. Each of the 256 storage areas provided in the feature register group 203 has a storage capacity of 32 bits.

[0140] Each memory chip CP includes an access circuit 202b instead of the access circuit 202.

[0141] FIG. 16 is a diagram showing an example of the configuration of the conversion table 120 according to the third embodiment.

[0142] The conversion table 120 records, for each page number, the correspondence between a value for specifying a page that can be transferred as a second address and the page number. According to the example shown in FIG. 14, the value for specifying a page that can be transferred as a second address is a value in the range from 10h to FFh. In the third embodiment, because a LUN can be transferred as a second address, a page number cannot be used as the second address as is. The conversion table 120 associates a value that is exclusive to values ​​that can be used as a LUN with the page number, thereby making it possible to use a value in the range that cannot be used as a LUN as a page designation.

[0143] From the example of the conversion table 120 shown in FIG. 16, it can be seen that the value 10h transferred as the second address corresponds to page number 1, and the value 11h transferred as the second address corresponds to page number 2.

[0144] The command decoder 111b can refer to the conversion table 120 to identify the specified page from the page specification transferred as the second address.

[0145] FIG. 17 is a flowchart showing an example of the operation of the interface chip IFC according to the third embodiment.

[0146] When the interface chip IFC receives the second sequence from the memory controller MC (S501), the controller 103 transfers the received second sequence to the group of memory chips CP (S502).

[0147] The command decoder 111b determines whether the second address included in the received second sequence corresponds to a page designation (S503).

[0148] 14, a value in the address range of 10h to FFh is used as a page designation. The command decoder 111b determines whether the second address corresponds to a page designation based on whether the second address is a value in the address range of 10h to FFh.

[0149] Note that the method for determining whether the second address corresponds to a page designation is not limited to this. For example, the command decoder 111b may determine whether the second address corresponds to a page designation by referring to the conversion table 120. The value of the page designation is associated with any page number by the conversion table 120. The command decoder 111b may determine whether the second address corresponds to a page designation based on whether the second address corresponds to any page number by the conversion table 120.

[0150] If the second address corresponds to a page designation (S503: Yes), the command decoder 111b identifies the designated page (S504) based on the second address and the conversion table 120. The command decoder 111b acquires the page number associated with the second address from the conversion table 120 to identify the designated page.

[0151] The command decoder 111b stores the parameter data included as setting data in the second sequence at the location indicated by the first address of the specified page in the feature register group 112 (S505).

[0152] If the second address does not correspond to the page designation (S503: No), or after S505, the interface chip IFC ends the operation.

[0153] 18 is a flowchart showing an example of the operation of the memory chip CP according to the third embodiment. In this figure, too, the operation of one memory chip CP will be explained as a representative of all memory chips CP.

[0154] When the memory chip CP receives the second sequence via the interface chip IFC (S601), the access circuit 202b determines whether the second address included in the received second sequence corresponds to the LUN assigned to the memory chip CP that includes the access circuit 202b (S602).

[0155] If the second address corresponds to the LUN assigned to the memory chip CP that includes it (S602: Yes), the access circuit 202b stores the parameter data included as setting data in the second sequence at the location indicated by the first address in the feature register group 203b (S603).

[0156] If the second address does not correspond to the LUN given to the memory chip CP that includes its own access circuit 202b (S602: No), or after S603, the memory chip CP ends the operation.

[0157] As described above, according to the third embodiment, the second sequence is configured to be able to transfer, as the second address, a value associated with each of a plurality of pages included in the feature register group 112b, which is exclusive of values ​​that can be used as LUNs (in the above example, a value associated with a page number in the range from 10h to FFh). When the second address is a value associated with any of the pages, the interface chip IFC stores the parameter data at the location indicated by the first address of the page associated with the second address.

[0158] In the first and second embodiments, the command sequence of the SetFeature command is configured so that whether the target of the SetFeature command is the interface chip IFC or each memory chip CP can be determined based on whether the first address corresponds to an interface feature address or a memory feature address. Therefore, overlapping values ​​between the interface feature address and the memory feature address are prohibited.

[0159] In contrast, in the third embodiment, the second sequence is configured to be able to determine whether the target is the interface chip IFC or each memory chip CP based on the second address, and therefore values ​​are allowed to overlap between the interface feature address and the memory feature address. Therefore, a common address space (a space ranging from 00h to FFh in the above example) can be mapped to each page of the feature register set 112b and the feature register set 203b. This not only makes it possible to increase the capacity of the feature register set 112b of the interface chip IFC that can store parameter data, but also makes it possible to map the full-size feature register space defined by the standard to the feature register set 203b.

[0160] (Fourth embodiment) A memory vendor does not necessarily assign the memory chip CP function to all of the 256 addresses included in the feature register space. The 256 addresses included in the feature register space include addresses to which the memory chip CP function is not assigned, that is, addresses that are not used by the memory chip CP.

[0161] In the fourth embodiment, addresses not used by the memory chip CP among the 256 addresses included in the feature register space are used by the interface chip IFC.

[0162] The fourth embodiment will be described below. In the fourth embodiment, differences from the first embodiment will be described. Explanations of the same matters as in the first embodiment will be omitted or will be explained briefly.

[0163] FIG. 19 is a diagram for explaining an example of the configuration of the interface chip IFC and each memory chip CP according to the fourth embodiment.

[0164] The controller 103 of the interface chip IFC includes a command decoder 111c instead of the command decoder 111. Furthermore, the controller 103 includes a feature register group 112c instead of the feature register group 112.

[0165] The feature register set 112c has 32 storage areas each assigned a different address in the range of 00h to 1Fh. Each of the 32 storage areas has a storage capacity of 32 bits. In the fourth embodiment, the 32 addresses in the range of 00h to 1Fh assigned to the feature register set 112c are referred to as interface feature addresses.

[0166] The controller 103 further includes a memory 113c. The memory 113c is a non-volatile memory in which the conversion table 120c is stored. The memory 113c is, for example, an eFuse or a ROM (Read Only Memory). The conversion table 120c is stored in the memory 113c when the semiconductor memory device 1 is manufactured. Note that the type of memory 113c and the timing of storing the conversion table 120c are not limited to these.

[0167] Each memory chip CP includes an access circuit 202c instead of the access circuit 202. Also, each memory chip CP includes a feature register group 203c instead of the feature register group 203.

[0168] The feature register set 203c has 256 storage areas each assigned a different address in the range of 00h to FFh. Each of the 256 storage areas in the feature register set 203c has a storage capacity of 32 bits. Note that, for the feature register set 203c, 32 addresses in the range of 00h to FFh have no function assigned. In other words, the 32 addresses in the feature register space are unused by the memory chip CP.

[0169] The 32 addresses in the feature register space that are unused in the memory chip CP are associated with the 32 storage areas of the feature register group 112c of the interface chip IFC. The conversion table 120c is a table that records the correspondence between the 32 addresses that are unused in the memory chip CP and the 32 storage areas of the feature register group 112c.

[0170] FIG. 20 is a diagram showing an example of the configuration of the conversion table 120c according to the fourth embodiment.

[0171] The conversion table 120c records the correspondence between the addresses unused by the memory chip CP among the 256 addresses that can be transferred as the first address and the interface feature addresses.

[0172] In the example shown in FIG. 20, it can be read from the conversion table 120c that the value 80h transferred as the first address corresponds to the interface feature address 00h, and the value A2h transferred as the first address corresponds to the interface feature address 01h.

[0173] This configuration can be considered as follows: That is, the feature register space (an example of a first access space) includes a space (an example of a first space) used to access the feature register group 203c and a space (an example of a second space) used to access the feature register group 112c. The space used to access the feature register group 203c and the space used to access the feature register group 112c are mutually exclusive. The translation table 120c records the correspondence between the address groups included in the space used to access the feature register group 112c and the feature register group 112c.

[0174] FIG. 21 is a diagram for explaining a parameter data setting method according to the fourth embodiment using the first sequence.

[0175] In the example shown in FIG. 21, the memory controller MC transfers the first sequence SQ31 and the first sequence SQ32 to the semiconductor memory device 1 in this order.

[0176] The first sequence SQ31 includes, as a first address, address 80h, which is an address unused in the memory chip CP. When the interface chip IFC receives the first sequence SQ31, the command decoder 111c refers to the conversion table 120c to determine whether the first address is associated with any interface feature address. In the example shown in FIG. 20, address 80h is associated with interface feature address 00h. Therefore, the command decoder 111c stores the parameter data included in the first sequence SQ31 at the location indicated by interface feature address 00h in the feature register group 112c.

[0177] The first sequence SQ32 includes, as a first address, address A2h, which is an address unused in the memory chip CP. When the interface chip IFC receives the first sequence SQ31, the command decoder 111c refers to the conversion table 120c to determine whether the first address is associated with any interface feature address. In the example shown in FIG. 20, address A2h is associated with interface feature address 01h. Therefore, the command decoder 111c stores the parameter data included in the first sequence SQ32 at the location indicated by interface feature address 01h in the feature register group 112c.

[0178] FIG. 22 is a flowchart showing an example of the operation of the interface chip IFC according to the fourth embodiment.

[0179] When the interface chip IFC receives the first sequence from the memory controller MC (S701), the controller 103 transfers the received first sequence to the group of memory chips CP (S702).

[0180] The command decoder 111c determines whether the first address included in the received first sequence is associated with an interface feature address by the conversion table 120c (S703).

[0181] If the first address is associated with an interface feature address (S703: Yes), the command decoder 111c converts the first address into an interface feature address (S704). In S704, the command decoder 111c identifies the interface feature address corresponding to the first address by referring to the conversion table 120c.

[0182] The command decoder 111c stores the parameter data included in the first sequence as setting data at the position indicated by the interface feature address obtained by the conversion in the feature register group 112c (S705). The command decoder 111c stores the parameter data in the storage area indicated by the interface feature address obtained by the conversion, among the 32 storage areas provided in the feature register group 112c.

[0183] If the first address is not associated with the interface feature address (S703: No), or after S705, the interface chip IFC ends the operation.

[0184] 23 is a flowchart showing an example of the operation of the memory chip CP according to the fourth embodiment. In this figure, too, the operation of one memory chip CP will be explained as a representative of all memory chips CP.

[0185] When the memory chip CP receives a first sequence via the interface chip IFC (S801), the access circuit 202c determines whether or not the first address included in the received first sequence corresponds to an unused address (S802).

[0186] If the first address does not correspond to an unused address (S802: No), the access circuit 202c stores the parameter data included in the first sequence as setting data at the location indicated by the first address in the feature register group 203c (S803).

[0187] If the first address corresponds to an unused address (S802: Yes), or after S803, the memory chip CP ends the operation.

[0188] In the fourth embodiment, the first sequence is used as a command sequence for transferring the SetFeature command. Even when the second sequence is received, the semiconductor memory device 1 can perform the same operation as when the first sequence is received (for example, the operation shown in FIG. 22).

[0189] As described above, according to the fourth embodiment, the first address included in the command sequence of the SetFeature command is included in either the space used to access the feature register group 203c (referred to as the first space) or the space used to access the feature register group 112c (referred to as the second space), which is exclusive of the first space. The conversion table 120c records the correspondence between the address group included in the second space and the feature register group 112c. If the first address is included in the first space, the memory chip CP stores the parameter data included in the command sequence in the feature register group 203c. If the first address is not included in the first space, the memory chip CP does not store the parameter data in the feature register group 203c. If the first address is included in the second space, the interface chip IFC stores the parameter data included in the command sequence in the feature register group 112c. If the first address is not included in the second space, the interface chip IFC does not store the parameter data in the feature register group 112c.

[0190] Since addresses in the feature register space that are not used by the memory chip CP can be used by the interface chip IFC, it is possible to maximize the number of addresses available for the interface chip IFC without reducing the number of addresses used by the memory chip CP. In other words, parameter data can be suitably stored in the feature register group 112c provided in the interface chip IFC.

[0191] Furthermore, according to the fourth embodiment, the feature register set 112c includes a plurality of storage areas (32 storage areas in the example shown in FIG. 19), and the second space includes a plurality of addresses (32 addresses in the example shown in FIG. 19). The conversion table 120c records correspondence between the plurality of addresses included in the second space and the plurality of storage areas included in the feature register set 112c. When the first address is included in the second space, the interface chip IFC stores parameter data included in the command sequence in the storage area that is associated with the first address by the conversion table 120c, among the plurality of storage areas included in the feature register set 112c.

[0192] Therefore, addresses in the feature register space that are not used by the memory chip CP can be used by the interface chip IFC.

[0193] (Fifth embodiment) In the command sequence of the SetFeature command, the setting data is transferred in four data transfer cycles. That is, the command sequence of the SetFeature command has four 8-bit data transfer fields (data transfer fields B0 to B3 described below), and the memory controller MC can transfer parameter data in 8-bit (=1 byte) units per address. The feature register group of the memory chip CP has multiple storage areas, each with a storage capacity of 32 bits (=4 bytes), which can be considered to have four byte areas, each capable of storing 1 byte of parameter data transferred in one data transfer field. Furthermore, each of the 256 addresses included in the feature register space can be considered to include four segments corresponding to the four byte areas.

[0194] The plurality of storage areas provided in the feature register group of the memory chip CP may include a storage area having an unused byte area.

[0195] In the fifth embodiment, a space corresponding to an unused byte area in the feature register space can be used in the interface chip IFC. That is, a group of segments that are not used in the memory chip CP among 1024 segments (=256 addresses×4 segments) included in the feature register space can be used in the interface chip IFC.

[0196] The fifth embodiment will be described below. In the fifth embodiment, differences from the fourth embodiment will be described. Explanations of the same matters as in the fourth embodiment will be omitted or will be explained briefly.

[0197] FIG. 24 is a diagram for explaining an example of the configuration of the interface chip IFC and each memory chip CP according to the fifth embodiment.

[0198] The controller 103 of the interface chip IFC includes a command decoder 111d instead of the command decoder 111c, and a feature register group 112d instead of the feature register group 112c.

[0199] The feature register set 112d has 32 storage areas each assigned a different address in the range of 00h to 1Fh. Each of the 32 storage areas has a storage capacity of 32 bits (=4 bytes). In the fifth embodiment, the 32 addresses in the range of 00h to 1Fh assigned to the feature register set 112d are referred to as interface feature addresses.

[0200] The controller 103 further includes a memory 113d. The memory 113d is a non-volatile memory in which the conversion table 120d is stored. The memory 113d is, for example, an eFuse or a ROM. The conversion table 120d is stored in the memory 113d when the semiconductor memory device 1 is manufactured. Note that the type of the memory 113d and the timing of storing the conversion table 120d are not limited to these.

[0201] Each memory chip CP includes an access circuit 202d instead of the access circuit 202c, and a feature register group 203d instead of the feature register group 203c.

[0202] The feature register set 203d has 256 storage areas each assigned a different address in the range of 00h to FFh. Each of the 256 storage areas included in the feature register set 203d has a storage capacity of 32 bits (=4 bytes).

[0203] 24, 32 of the 256 storage areas in the feature register set 203d each include one or more unused byte areas. The total capacity of the unused byte areas in the feature register set 203d is 64 bytes.

[0204] The 32 addresses assigned to the 32 storage areas each containing one or more unused byte areas are associated with the 32 storage areas of the feature register group 112d of the interface chip IFC by a conversion table 120d. The conversion table 120d also records the location of each unused byte area.

[0205] FIG. 25 is a diagram showing an example of the configuration of the conversion table 120d according to the fifth embodiment.

[0206] The conversion table 120d records the correspondence between the interface feature address and an address assigned to a storage area including an unused byte area among 256 addresses that can be transferred as the first address.

[0207] Furthermore, the conversion table 120d records the position of the unused byte area for each address assigned to a storage area including an unused byte area among the 256 addresses that can be transferred as the first address.

[0208] As described above, the command sequence of the SetFeature command includes four data transfer fields B0 to B3, each of which transfers one byte of parameter data. In Figure 25, the location of unused byte areas in the 32-bit storage area is represented by a flag for each data transfer field. A flag value of "1" indicates an unused byte area, and a flag value of "0" indicates a used byte area.

[0209] 25, address 80h is associated with interface feature address 00h, and the flags for data transfer fields B2 and B3 among data transfer fields B0 to B3 are set to "1." This means that of the four byte areas included in the storage area to which address 80h is assigned in the feature register group 203d, the third and fourth byte areas are unused byte areas.

[0210] Address A2h is associated with interface feature address 01h, and the flag for data transfer field B1 of data transfer fields B0 to B3 is set to "1." This means that the first byte area of ​​the four byte areas in the storage area to which address A2h is assigned in the feature register group 203d is unused.

[0211] In this way, the conversion table 120d records the correspondence between the unused space in the feature register space of the memory chip CP and the feature register group 112d in units of byte areas, in other words, in units of segments, which are the address space corresponding to the byte areas.

[0212] FIG. 26 is a diagram illustrating a configuration of a first sequence according to the fifth embodiment.

[0213] The first sequence is configured to transfer a first SetFeature command C1, a first address, and setting data in that order. The first sequence includes data transfer fields B0 to B3, and the setting data is transferred in 1-byte units by the data transfer fields B0 to B3.

[0214] As the first address, either a feature address or an address corresponding to a field designation identifier can be transferred. The field setting identifier is a specific address among 256 feature addresses. The command decoder 111d interprets the field setting identifier as a command for setting the target of the 4-byte parameter data transferred by the data transfer fields B0 to B3.

[0215] As the setting data, in addition to the parameter data, a field setting value can be transferred for each data transfer field. The field setting value indicates the target of the parameter data and whether the parameter data is valid or invalid.

[0216] In the example shown in FIG. 26, the field setting values ​​can be 00h, 01h, 10h, and 11h.

[0217] A field setting value of 00h means invalid data for the memory chip CP. When a field setting value of 00h is transferred in a certain data transfer field, parameter data transferred thereafter in that data transfer field is parameter data targeted at the memory chip CP and is invalid data.

[0218] A field setting value of 01h means valid data for the memory chip CP. When a field setting value of 01h is transferred in a certain data transfer field, parameter data transferred thereafter in that data transfer field is parameter data targeted at the memory chip CP and is valid data.

[0219] A field setting value of 10h means invalid data for the interface chip IFC. When a field setting value of 10h is transferred in a certain data transfer field, the parameter data transferred in that data transfer field thereafter is parameter data targeted at the interface chip IFC and is invalid data.

[0220] The field setting value 11h means valid data for the interface chip IFC. When the field setting value 11h is transferred in a certain data transfer field, the parameter data transferred in that data transfer field thereafter is parameter data targeted at the interface chip IFC and is valid data.

[0221] 27 and 28 are diagrams for explaining a parameter data setting method according to the fifth embodiment using the first sequence.

[0222] In the example shown in FIG. 27, the memory controller MC transfers the first sequence SQ41 and the first sequence SQ42 to the semiconductor memory device 1 in this order.

[0223] The first sequence SQ41 includes a field setting identifier as a first address. In this example, address 55h is used as the field setting identifier. When the interface chip IFC and each memory chip CP receive the first sequence SQ41, they recognize that a field setting value will be transferred in each of the data transfer fields B0 to B3 because the first sequence SQ41 includes a field setting identifier.

[0224] In the first sequence SQ41, a field setting value of 00h is transferred in each of the data transfer fields B0 and B1. Therefore, the interface chip IFC and each memory chip CP recognize that the parameter data subsequently transferred in the data transfer fields B0 and B1 is parameter data targeted at the memory chip CP and is invalid data.

[0225] In the first sequence SQ41, a field setting value of 11h is transferred in each of the data transfer fields B2 and B3. Therefore, the interface chip IFC and each memory chip CP recognize that the parameter data subsequently transferred in the data transfer fields B2 and B3 is parameter data targeted at the interface chip IFC and is valid data.

[0226] The first sequence SQ42 includes feature address 80h as the first address. The interface chip IFC and each memory chip CP perform the following operations based on the field settings included in the previously transferred first sequence SQ41. That is, the interface chip IFC and each memory chip CP do not store the parameter data transferred in data transfer fields B0 and B1 included in the first sequence SQ42 in the feature register groups 112d and 203d. Furthermore, the parameter data transferred in data transfer fields B2 and B3 included in the first sequence SQ42 is stored in the feature register group 112d by the interface chip IFC. The feature address 80h is associated with interface feature address 00h by the conversion table 120d. Therefore, the parameter data transferred in data transfer fields B2 and B3 included in the first sequence SQ42 is stored in the memory area assigned interface feature address 00h in the feature register group 112d. In each memory chip CP, the parameter data transferred in the data transfer fields B2 and B3 included in the first sequence SQ42 is not stored in the feature register group 203d.

[0227] In the example shown in FIG. 28, the memory controller MC transfers the first sequence SQ51 and the first sequence SQ52 to the semiconductor memory device 1 in this order.

[0228] The first sequence SQ51 includes a field setting identifier as a first address. When the interface chip IFC and each memory chip CP receive the first sequence SQ51, they recognize that a field setting value will be transferred in each of the data transfer fields B0 to B3 because the first sequence SQ51 includes a field setting identifier.

[0229] In each of the data transfer fields B0 and B1 of the first sequence SQ51, a field setting value of 01h is transferred, so that the interface chip IFC and each memory chip CP recognize that the parameter data subsequently transferred in the data transfer fields B0 and B1 is parameter data targeted at the memory chip CP and is valid data.

[0230] In each of the data transfer fields B2 and B3 of the first sequence SQ51, a field setting value of 10h is transferred. Therefore, the interface chip IFC and each memory chip CP recognize that the parameter data subsequently transferred in the data transfer fields B2 and B3 is parameter data targeted at the interface chip IFC and is invalid data.

[0231] The first sequence SQ52 includes feature address 80h as the first address. The interface chip IFC and each memory chip CP perform the following operations based on the field settings included in the previously transferred first sequence SQ51. That is, the interface chip IFC does not store the parameter data transferred in data transfer fields B0 and B1 included in the first sequence SQ52 in the feature register group 112d. In each memory chip CP, the parameter data transferred in fields B0 and B1 is stored in the storage area assigned feature address 80h in the feature register group 203d. Furthermore, the interface chip IFC and each memory chip CP do not store the parameter data transferred in data transfer fields B2 and B3 included in the first sequence SQ52 in the feature register groups 112d and 203d.

[0232] FIG. 29 is a flowchart showing an example of the operation of the interface chip IFC according to the fifth embodiment.

[0233] When the interface chip IFC receives a first sequence from the memory controller MC (S901), the controller 103 transfers the received first sequence to the group of memory chips CP (S902).

[0234] The command decoder 111d determines whether the first address included in the received first sequence corresponds to the field setting identifier (S903). If the first address corresponds to the field setting identifier (S903: Yes), the command decoder 111d stores the field setting values ​​of the data transfer fields B0 to B3 included in the received first sequence (S904).

[0235] If the first address included in the received first sequence does not correspond to the field setting identifier (S903: No), the command decoder 111d determines whether there is a data transfer field among the data transfer fields B0 to B3 in which the stored field setting value is "11h" (S905).

[0236] If there is a data transfer field whose field setting value is "11h" (S905: Yes), the command decoder 111d converts the first address into an interface feature (S906). The command decoder 111d identifies the interface feature address associated with the first address by referring to the conversion table 120d.

[0237] The command decoder 111d stores the data in the data transfer field, which has the stored field setting value "11h", in the location indicated by the interface feature address obtained by the conversion in the feature register group 112d (S907).

[0238] After S904, or if there is no data transfer field with the field setting value "11h" (S905: No), or after S907, the interface chip IFC ends the operation.

[0239] 30 is a flowchart showing an example of the operation of the memory chip CP according to the fifth embodiment. In this figure, too, the operation of one memory chip CP will be explained as a representative of all memory chips CP.

[0240] When the memory chip CP receives a first sequence via the interface chip IFC (S1001), the access circuit 202d determines whether the first address included in the received first sequence corresponds to the field setting identifier (S1002). If the first address corresponds to the field setting identifier (S1002: Yes), the access circuit 202d stores the field setting values ​​of the data transfer fields B0 to B3 included in the received first sequence (S1003).

[0241] If the first address included in the received first sequence does not correspond to the field setting identifier (S1002: No), the access circuit 202d determines whether there is a data transfer field among the data transfer fields B0 to B3 in which the stored field setting value is "01h" (S1004).

[0242] If there is a data transfer field whose field setting value is "01h" (S1004: Yes), the access circuit 202d stores the data of the stored data transfer field whose field setting value is "01h" at the location indicated by the first address in the feature register group 203d (S1005).

[0243] After S1003, or if there is no data transfer field with a field setting value of "01h" (S1004: No), or after S1005, the memory chip CP ends the operation.

[0244] In the above description, the field setting values ​​and parameter data are transferred using the first sequence. The fifth embodiment can also be realized by using the second sequence instead of or in addition to the first sequence.

[0245] Furthermore, the semiconductor memory device 1 is configured so that the target of data transferred in each data transfer field is set to either the interface chip IFC or each memory chip CP using a field setting value. The method for switching the storage destination of parameter data in units of data transfer fields is not limited to this.

[0246] For example, the memory controller MC may use the GetFeature command to read parameter data in units of 32-bit storage areas, and then use the SetFeature command to transfer the parameter data in a read-modify-write format.

[0247] As described above, according to the fifth embodiment, each feature address includes multiple segments (four segments in the above example), and the interface chip IFC can use the space unused by the memory chip CP in segment units. In other words, the interface chip IFC uses a group of segments that is exclusive to the group of segments used by the memory chip CP.

[0248] The segment of the feature register space that is not used by the memory chip CP can be used by the interface chip IFC. This makes it possible to secure as much space as possible for the interface chip IFC without reducing the space of the feature register space used by the memory chip CP. In other words, parameter data can be suitably stored in the feature register group 112d provided in the interface chip IFC.

[0249] The fourth and fifth embodiments can be applied together with the first or second embodiment.

[0250] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as defined in the claims. [Explanation of symbols]

[0251] 1 semiconductor memory device, 101 host interface, 102, 102-0, 102-1, 201 memory interface, 103 controller, 111, 111a, 111b, 111c, 111d command decoder, 112, 112b, 112c, 112d, 203, 203b, 203c, 203d feature register group, 113, 113c, 113d memory, 120, 120c, 120d conversion table, 202, 202a, 202b, 202c, 202d access circuit, 204 memory cell array, IFC interface chip, CP memory chip, SYS memory system, T terminal group.

Claims

1. a group of terminals to which a command sequence of a setting command including an address is input; a first device comprising a first register group to which a first address space is mapped and a memory cell array, wherein parameter data is stored in the first register group when the address is included in the first address space, and parameter data is not stored in the first register group when the address is not included in the first address space; a second device disposed between the terminal group and the first device, the second device including a second register group including a plurality of pages to which a common second address space exclusive to the first address space is mapped, the second device being configured to identify, based on the command sequence, a page among the plurality of pages in which parameter data is to be stored when the address is a first value; A semiconductor memory device comprising:

2. the command sequence of the setting command includes data in addition to the address, the first value is contained in the second address space; The second device is when a first command sequence that is a command sequence of the setting command including the address of the first value is received via the terminal group, identifying one page of the plurality of pages based on data included in the first command sequence; when a second command sequence, which is a command sequence of the setting command including an address of a second value included in the second address space and which is different from the first value, is received via the terminal group after the first command sequence, storing data included in the second command sequence as parameter data at a position indicated by the second value within the identified one page; 2. The semiconductor memory device according to claim 1.

3. The first device is assigned a LUN (Logical Unit Number); the command sequence of the setting command includes parameter data in addition to the address; the addresses include a first address included in either the first address space or the second address space, and a second address to which the LUN can be designated; the first value is any one of a group of values ​​associated with different pages of the plurality of pages, When the first address is included in the second address space, the second device interprets the second address as the first value and stores the parameter data at a position indicated by the first address in one page of the plurality of pages that corresponds to the first value.

2. The semiconductor memory device according to claim 1.

4. a LUN is provided to the first device; the first value is any one of a group of values ​​associated with different pages of the plurality of pages, the values ​​being exclusive of the LUN; the command sequence of the setting command includes parameter data in addition to the address; the addresses include a first address included in either the first address space or the second address space, and a second address to which the LUN or the first value can be assigned; when the second address is the first value, the second device stores the parameter data at a position indicated by the first address in one page of the plurality of pages that corresponds to the first value; 2. The semiconductor memory device according to claim 1.

5. a group of terminals to which a command sequence of a setting command including an address included in the first address space is input; a first device including a first set of registers and a memory cell array; a second device disposed between the terminal group and the first device, the second device including a second register group and a memory storing first information; Equipped with the first address space includes a first space used to access the first register group and a second space used to access the second register group, the second space being exclusive from the first space; the first information is information in which a correspondence between the second space and the second register group is recorded; the first device stores parameter data in the first register group when the address is included in the first space, and does not store parameter data in the first register group when the address is not included in the first space; the second device stores parameter data in the second register group when the address is included in the second space, and does not store parameter data in the second register group when the address is not included in the second space; Semiconductor memory device.

6. the second register group includes a plurality of storage areas; the second space includes a plurality of first addresses; the first information records correspondence between the plurality of first addresses and the plurality of storage areas; the second device stores parameter data in a storage area associated with the address by the first information among the plurality of storage areas when the address is one of the plurality of first addresses; 6. The semiconductor memory device according to claim 5.

7. the first address space includes a plurality of third spaces to which a plurality of second addresses are associated, and each of the plurality of third spaces includes a plurality of segments; the first space and the second space are made up of mutually exclusive segments; 7. The semiconductor memory device according to claim 6.

8. The setting command is a SetFeature command.

6. The semiconductor memory device according to claim 1.

9. A semiconductor memory device according to any one of claims 1 to 7, a memory controller that transmits a command sequence of the setting command to the semiconductor memory device; A memory system comprising:

10. A method for controlling a semiconductor memory device comprising: a first device including a group of terminals to which a command sequence of a setting command including an address is input, a first group of registers to which a first address space is mapped, and a memory cell array; and a second device disposed between the group of terminals and the first device, and including a second group of registers including a plurality of pages to which a common second address space exclusive to the first address space is mapped, the method comprising: identifying a page of the plurality of pages in which parameter data is to be stored based on the command sequence when the address included in the command sequence received by the second device is a first value; A method comprising:

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