Memory device

Abstract

To provide a three-dimensional memory device with improved integration density.SOLUTION: A memory cell MC according to the present technique includes: a bit line 101 and a plate line 102 disposed apart from each other and oriented vertically along a first direction D1; a transistor TR oriented horizontally in a second direction D2 intersecting with the bit line 101 and including an active region 105 including a first cylinder 105A, a second cylinder 105B, and at least one channel part 105C1 and 105C2 oriented horizontally between the first cylinder 105A and the second cylinder 105B; a word line 103 extending along a third direction D3 while surrounding the at least one channel part 105C1 and 105C2 in the active region 105; and a capacitor 104 oriented horizontally along the second direction D2 between the active region 105 and the plate line 102.SELECTED DRAWING: Figure 6B

Description

[Technical Field]

[0001] The present invention relates to semiconductor devices, and more particularly to three-dimensional memory devices with improved integration density. [Background technology]

[0002] The integration level of a two-dimensional (2D) or planar semiconductor device is primarily determined by the area occupied by a unit memory cell, and is therefore greatly influenced by the level of fine pattern formation technology. However, because extremely expensive equipment is required for pattern miniaturization, the integration level of two-dimensional semiconductor devices is still limited, even though it has increased. For this reason, three-dimensional memory devices with memory cells arranged three-dimensionally have been proposed. Summary of the Invention [Problem to be solved by the invention]

[0003] Embodiments of the present invention provide a three-dimensional memory device with increased integration density. [Means for solving the problem]

[0004] A semiconductor device according to an embodiment of the present invention may include an active region including a first cylinder, a second cylinder, and at least one channel portion horizontally oriented between the first cylinder and the second cylinder, a surround gate electrode surrounding the at least one channel portion, a first buried gate electrode extending from one side of the surround gate electrode and buried within the first cylinder, and a second buried gate electrode extending from the other side of the surround gate electrode and buried within the second cylinder.

[0005] A memory cell according to an embodiment of the present invention may include a bit line and a plate line spaced apart from each other and vertically oriented along a first direction, a transistor horizontally oriented in a second direction intersecting the bit line and including an active region having a first cylinder, a second cylinder, and at least one channel portion horizontally oriented between the first cylinder and the second cylinder, a word line extending along a third direction while surrounding at least one channel portion of the active region, and a capacitor horizontally oriented along the second direction between the active region and the plate line.

[0006] A memory device according to an embodiment of the present invention may include a memory cell array including a plurality of memory cells arranged vertically along a first direction, each of the memory cells including: bit lines and plate lines spaced apart from each other and vertically oriented along the first direction; a transistor oriented horizontally in a second direction intersecting the bit lines, the transistor including an active region having a first cylinder, a second cylinder, and at least one channel portion oriented horizontally between the first cylinder and the second cylinder; a word line extending along a third direction while surrounding at least one channel portion of the active region; and a capacitor oriented horizontally along the second direction between the active region and the plate line.

[0007] A memory cell according to an embodiment of the present invention includes a substrate, a first recess, a second recess, and at least one nanowire channel oriented horizontally between the first recess and the second recess, the memory cell including an active layer spaced from the substrate, a word line surrounding the at least one nanowire channel, a bit line oriented vertically from the substrate and connected to one side of the active layer, and a bit line oriented horizontally from the active layer and connected to the other side of the active layer. and a capacitor connected to the capacitor. [Effects of the Invention]

[0008] In the three-dimensional memory device according to the present technology, transistors and capacitors can be stacked three-dimensionally on a substrate, thereby improving the integration density of the memory device. [Brief explanation of the drawings]

[0009] [Figure 1] 2 is a diagram illustrating a transistor TR according to an embodiment. FIG. [Figure 2A] FIG. [Figure 2B] FIG. 1 is a detailed view of the source region. [Figure 2C] FIG. 2 is a detailed view of the drain region. [Figure 2D] FIG. 2 is a cross-sectional view illustrating a first channel portion, a source region, and a drain region. [Figure 2E] FIG. 4 is a cross-sectional view illustrating a second channel portion, a source region, and a drain region. [Figure 3A] FIG. 10 is a cross-sectional view illustrating an active region according to another embodiment. [Figure 3B] FIG. 10 is a cross-sectional view illustrating an active region according to another embodiment. [Figure 4A] FIG. 2 is a perspective view for explaining a gate electrode GAA of FIG. [Figure 4B] 4B is a cross-sectional view taken along a second direction D2 of FIG. 4A. [Figure 4C] 10 is a perspective view for explaining a surround portion, a first channel portion, and a second channel portion of a gate electrode GAA. FIG. [Figure 4D] FIG. 2 is a cross-sectional view for explaining a gate electrode GAA, a first cylinder, and a second cylinder. [Figure 5] 1 is a diagram illustrating a schematic configuration of a memory device according to an embodiment; [Figure 6A] FIG. 6 is a schematic perspective view for explaining an individual memory cell MC of FIG. 5. [Figure 6B] FIG. 6B is a detailed perspective view for explaining an individual memory cell MC of FIG. 6A. [Figure 6C]FIG. 6C is a cross-sectional view taken along the direction AA′ of FIG. 6B. [Figure 6D] FIG. 6D is a cross-sectional view taken along line BB′ in FIG. 6C. [Figure 6E] FIG. 6D is a cross-sectional view taken along line CC′ in FIG. 6C. [Figure 6F] FIG. 6D is a cross-sectional view taken along line DD′ in FIG. 6C. [Figure 6G] FIG. 6D is a cross-sectional view taken along line EE′ of FIG. 6C. [Figure 6H] FIG. [Figure 7A] FIG. 2 is a diagram for explaining a memory cell array MCA according to an embodiment. [Figure 7B] FIG. 2 is a diagram for explaining a memory cell array MCA according to an embodiment. [Figure 8] 1 is a diagram illustrating a mirror-type memory cell array sharing a bit line; [Figure 9] FIG. 10 is a diagram for explaining a mirror type memory cell array sharing a plate line. [Figure 10A] 10A and 10B are diagrams illustrating a memory device according to another embodiment; [Figure 10B] 10A and 10B are diagrams illustrating a memory device according to another embodiment; [Figure 11A] FIG. 10 is a diagram illustrating an individual memory cell according to another embodiment. [Figure 11B] FIG. 10 is a diagram illustrating an individual memory cell according to another embodiment. [Figure 12A] 10A and 10B are diagrams illustrating a capacitor according to another embodiment. [Figure 12B] FIG. 12B is a detailed view of the plate node of the capacitor of FIG. 12A. DETAILED DESCRIPTION OF THE INVENTION

[0010] The embodiments and the like described in this specification will be described with reference to cross-sectional views, plan views, and block diagrams that are idealized schematic views of the present invention. Therefore, the shapes of the illustrative views may be modified due to manufacturing techniques and / or tolerances. Therefore, the embodiments and the like of the present invention are not limited to the specific shapes shown in the drawings, but may be modified in accordance with the shapes produced by the manufacturing process. Therefore, the regions illustrated in the drawings have schematic attributes, and the shapes of the regions illustrated in the drawings are intended to illustrate specific forms of regions of elements, and are not intended to limit the scope of the invention.

[0011] FIG. 1 is a diagram illustrating a semiconductor device according to an embodiment.

[0012] As shown in FIG. 1, the semiconductor device 100 is a gate all around (Gate All Around) The semiconductor device 100 may include a transistor TR. The transistor TR may be a lateral transistor (lateral around). The transistor TR may comprise a gate-all-around transistor.

[0013] The transistor TR may include a first doping region SR, a second doping region DR, an active region (ACT) between the first doping region SR and the second doping region DR, and a gate electrode (GAA) surrounding a portion of the active region ACT.

[0014] The first doping region SR and the second doping region DR may each extend along a first direction D1. The first doping region SR and the second doping region DR may each be vertically planar. The first doping region SR and the second doping region DR may be spaced apart from each other along a second direction D2. The first doping region SR and the second doping region DR may be electrically connected to each other via an active region ACT. The first doping region SR and the second doping region DR may be part of the active region ACT. The first doping region SR and the second doping region DR may include a silicon-containing material. The first doping region SR and the second doping region DR may include a single-crystal silicon layer, a polysilicon layer, a doped silicon layer, a doped polysilicon layer, or a combination thereof. The first doping region SR and the second doping region DR may include N-type impurities or P-type impurities. The first doped region SR and the second doped region DR may include phosphorus (P), arsenic (As), boron (B), indium (In), or a combination thereof. The first doped region SR and the second doped region DR may be doped with the same impurity. The first doped region SR and the second doped region DR may be referred to as first and second source / drain regions. The first doped region SR may be formed on a first edge of the active region ACT, and the second doped region DR may be formed on a second edge of the active region ACT. In another embodiment, the first doped region SR may provide a first edge of the active region ACT, and the second doped region DR may provide a second edge of the active region ACT. That is, the first doped region SR and the second doped region DR may be formed within the first and second edges of the active region ACT, respectively. The first doping region SR and the second doping region DR may each be a vertical structure extending along a first direction D1.

[0015] The active region ACT may be located between the first doping region SR and the second doping region DR. The active region ACT may extend along a second direction D2 between the first doping region SR and the second doping region DR. The second direction D2 may be perpendicular to the first direction D1. The active region ACT may be referred to as a horizontal active layer or a horizontal active region. The active region ACT may include a first cylinder (AC1), a second cylinder (AC2), and at least one channel portion CH1, CH2 oriented horizontally between the first cylinder AC1 and the second cylinder AC2. The first cylinder AC1 may be connected to the first doping region SR, and the second cylinder AC2 may be connected to the second doping region SR. It can be connected to a DR.

[0016] The gate electrode GAA may include a surround portion (GS) surrounding at least one channel portion CH1, CH2 of the active region ACT. The gate electrode GAA may further include a first buried portion (GB1) extending from one side of the surround portion GS and buried within the first cylinder AC1. The gate electrode GAA may further include a second buried portion (GB2) extending from the other side of the surround portion GS and buried within the second cylinder AC2. The surround portion GS may extend in a third direction D3. The third direction D3 may be perpendicular to the first direction D1 and the second direction D2. The surround portion GS may be referred to as a surround gate electrode, and the first and second buried portions GB1, GB2 may be referred to as a first buried gate electrode and a second buried gate electrode, respectively.

[0017] Fig. 2A is a detailed view of the active region ACT. Fig. 2B is a detailed view of the first cylinder AC1, Fig. 2C is a detailed view of the second cylinder AC2, Fig. 2D is a cross-sectional view for explaining the first channel portion, the first cylinder, and the second cylinder, and Fig. 2E is a cross-sectional view for explaining the second channel portion, the first cylinder, and the second cylinder.

[0018] As shown in FIGS. 2A to 2E, the active region ACT may include a first cylinder AC1, a second cylinder AC2, and at least one channel portion CH1, CH2 between the first cylinder AC1 and the second cylinder AC2. The first cylinder AC1 and the second cylinder AC2 may be spaced apart from each other along a second direction D2. The at least one channel portion CH1, CH2 may be formed horizontally and elongated along the second direction D2 between the first cylinder AC1 and the second cylinder AC2. The at least one channel portion CH1, CH2 may include a first channel portion CH1 and a second channel portion CH2. The first channel portion CH1 and the second channel portion CH2 may be spaced apart from each other and parallel to each other along a third direction D3. The first channel portion CH1 and the second channel portion CR2 may each be referred to as a nanowire channel. The first cylinder AC1 and the second cylinder AC2 may be referred to as the first active cylinder and the second active cylinder, respectively.

[0019] The active region ACT may further include a first recess portion R1 and a second recess portion R2. The first recess portion R1 may be formed in the first cylinder AC1, and the second recess portion R2 may be formed in the second cylinder AC2. The first recess portion R1 and the second recess portion R2 may be horizontal recesses recessed along the second direction D2. The first recess portion R1 may not penetrate the first cylinder AC1, and the second recess portion R2 may not penetrate the second cylinder AC2.

[0020] The first cylinder AC1 may include a pair of first side walls SW1, a pair of second side walls SW2, and one third side wall SW3. The pair of first side walls SW1 may extend along a first direction D1 and may face each other. The pair of second side walls SW2 may extend along a second direction D2 and may face each other. The first side walls SW1 and the second side walls SW2 may be connected to each other. The one third side wall SW3 may extend along the third direction D3 and may connect one side edge of the first side wall SW1 to one side edge of the second side wall SW2. A first recess R1 may be defined inside the first cylinder AC1 by a combination of the pair of first side walls SW1, the pair of second side walls SW2, and the one third side wall SW3. The first recess R1 may extend along the direction D2 of the first cylinder AC1. The first recess R1 may not penetrate the first cylinder AC1 due to the third sidewall SW3. The third sidewall SW3 may be connected to the first doping region SR and provide a first edge of the active region ACT. The third sidewall SW3 may also be the first doping region SR. The active region ACT may include the first doping region SR, whereby the first edge of the active region ACT may be provided by the first doping region SR. The pair of first sidewalls SW1 and the pair of second sidewalls SW2 may be horizontal sidewalls, and the third sidewall SW3 may be vertical sidewalls. As shown in FIGS. 2B, 2D, and 2E, a first channel portion CH1 may be connected to the other edge of one of the first sidewalls SW1, and a second channel portion CH2 may be connected to the other edge of the other of the first sidewalls SW1. The height of the first sidewall SW1 may be greater than the first channel portion CH1 and the second channel portion CH2. The first channel portion CH1 and the second channel portion CH2 may be at a level located between the second sidewalls SW2. For example, the first channel portion CH1 and the second channel portion CH2 may be located at a lower level than the upper second sidewall SW2, and the first channel portion CH1 and the second channel portion CH2 may be located at a higher level than the lower second sidewall SW2.

[0021] As shown in FIG. 2C , the second cylinder AC2 may include a pair of first side walls SW11, a pair of second side walls SW12, and one third side wall SW13. The pair of first side walls SW11 may extend along a first direction D1 and may face each other. The pair of second side walls SW12 may extend along a second direction D2 and may face each other. The first side walls SW11 and the second side walls SW12 may be connected to each other. The one third side wall SW13 may extend along a third direction D3 and may connect one side edge of the first side wall SW11 to one side edge of the second side wall SW12. A second recess R2 may be defined within the second cylinder AC2 by a combination of the pair of first sidewalls SW11, the pair of second sidewalls SW12, and one third sidewall SW13, and the second recess R2 may extend along the second direction D2. The second recess R2 may not penetrate the second cylinder AC2 due to the third sidewall SW13. The third sidewall SW13 may be connected to the second doping region DR and provide a second edge of the active region ACT. The third sidewall SW13 may also be the second doping region DR. The active region ACT may include the second doping region DR, and thereby the second edge of the active region ACT may be provided by the second doping region DR. The pair of first sidewalls SW11 and the pair of second sidewalls SW12 may be horizontal sidewalls, and the third sidewall SW13 may be vertical sidewalls. 2C, 2D, and 2E, a first channel portion CH1 may be connected to the other edge of one of the first side walls SW11, and a second channel portion CH2 may be connected to the other edge of the other of the first side walls SW11. The height of the first side wall SW11 may be greater than the heights of the first channel portion CH1 and the second channel portion CH2. The first channel portion CH11 and the second channel portion CH12 may be at a level located between the second side walls SW12.For example, the first channel portion CH1 and the second channel portion CH2 may be located at a level lower than the upper second sidewall SW12, and the first channel portion CH1 and the second channel portion CH2 may be located at a level higher than the lower second sidewall SW12. The first channel portion CH1 and the second channel portion CH2 may have the same size and the same threshold value.

[0022] As described above, the active region ACT may include the first channel portion CH1 and the second channel portion CH2. The first cylinder AC1 may be connected to one side edge of the first and second channel portions CH1 and CH2, and the other side edge of the first and second channel portions CH1 and CH2 may be connected to the first cylinder AC1. A second cylinder AC2 may be connected to the edge. The first cylinder AC1 and the second cylinder AC2 may face each other along the second direction D2. The first cylinder AC1 and the second cylinder AC2 may be symmetrical to each other along the second direction D2. The first recess R1 and the second recess R2 may be symmetrical to each other. The shape, size, depth, width, and height of the first recess R1 and the second recess R2 may be identical to each other. The first cylinder AC1 and the second cylinder AC2 may have a horizontal cylindrical shape.

[0023] 3A and 3B are cross-sectional views illustrating an active region according to another embodiment, in which Fig. 3A is a cross-sectional view illustrating a first channel portion, a first cylinder, and a second cylinder, and Fig. 3B is a cross-sectional view illustrating a second channel portion, a first cylinder, and a second cylinder.

[0024] As shown in FIG. 3A , a first cylinder AC1 may be connected to one side edge (hereinafter, the first edge) of a first channel portion CH11, and a second cylinder AC2 may be connected to the other side edge (hereinafter, the second edge) of the first channel portion CH11. The first channel portion CH11 may include a channel body CHB11, a first edge CHE11, and a second edge CHE12. The first edge CHE11 of the first channel portion CH11 may be connected to a first side wall SW1 of the first cylinder AC1, and the second edge CHE12 of the first channel portion CH11 may be connected to a first side wall SW11 of the second cylinder AC2. A contact surface CT1 between the channel body CHB11 and the first edge CHE11 may be smaller than a contact surface CT2 between the first side wall SW1 of the first cylinder AC1 and the first edge CHE11. A contact surface CT1 between the channel body CHB11 and the second edge CHE12 may be smaller than a contact surface CT2 between the first side wall SW11 of the second cylinder AC2 and the second edge CHE12. The first edge CHE11 and the second edge CHE12 of the first channel portion CH11 may each have a rounded profile. The first edge CHE11 may have a shape that gradually decreases in width from the first side wall SW1 of the first cylinder AC1 toward the channel body CHB11. The second edge CHE12 may have a shape that gradually decreases in width from the first side wall SW11 of the second cylinder AC2 toward the channel body CHB11.

[0025] As shown in FIG. 3B , a first cylinder AC1 may be connected to one side edge (hereinafter referred to as the first edge) of the second channel portion CH21, and a second cylinder AC2 may be connected to the other side edge (hereinafter referred to as the second edge) of the second channel portion CH21. The second channel portion CH21 may include a channel body CHB21, a first edge CHE21, and a second edge CHE22. The first edge CHE21 of the second channel portion CH21 may be connected to a first side wall SW1 of the first cylinder AC1, and the second edge CHE22 of the second channel portion CH21 may be connected to a first side wall SW11 of the second cylinder AC2. A contact surface CT1 between the channel body CHB21 and the first edge CHE21 may be smaller than a contact surface CT2 between the first side wall SW1 of the first cylinder AC1 and the first edge CHE21. A contact surface CT1 between the channel body CHB21 and the second edge CHE22 may be smaller than a contact surface CT2 between the first side wall SW11 of the second cylinder AC2 and the second edge CHE22. The first edge CHE21 and the second edge CH22 of the second channel portion CH21 may each have a rounded profile. The first edge CHE21 may have a shape that gradually decreases in width from the first side wall SW1 of the first cylinder AC1 toward the channel body CHB21. The second edge CHE22 may have a shape that gradually decreases in width from the first side wall SW11 of the second cylinder AC2 toward the channel body CHB21.

[0026] 4A is a perspective view for explaining the gate electrode GAA of FIG. 1, and FIG. 4B is a perspective view for explaining the gate electrode GAA of FIG. FIG. 2 is a cross-sectional view taken along the second direction D2.

[0027] As shown in FIGS. 4A and 4B , the gate electrode GAA may include a surround portion GS, a first buried portion GB1, and a second buried portion GB2. The surround portion GS may extend longitudinally along a third direction D3. The surround portion GS may be located between the first buried portion GB1 and the second buried portion GB2. The first buried portion GB1 and the second buried portion GB2 may extend along a second direction D2. The first buried portion GB1 and the second buried portion GB2 may be connected to both sides of the surround portion GS. The first buried portion GB1 may extend horizontally from the surround portion GS along the second direction D2. The second buried portion GB2 may extend horizontally from the surround portion GS along the second direction D2. The height of the surround portion GS in the first direction D1 may be greater than the first and second buried portions GB1 and GB2.

[0028] Fig. 4C is a perspective view illustrating the surround portion, the first channel portion, and the second channel portion of the gate electrode GAA, and Fig. 4D is a cross-sectional view illustrating the gate electrode GAA, the first cylinder, and the second cylinder.

[0029] As shown in FIGS. 4C and 4D , the surround portion GS of the gate electrode GAA may be shaped to surround the first channel portion CH1 and the second channel portion CH2. The first buried portion GB1 and the second buried portion GB2 may not surround the first and second channel portions CH1 and CH2. The first buried portion GB1 and the second buried portion GB2 may be spaced apart from the first and second channel portions CH1 and CH2. The first buried portion GB1 may extend to be located within the first recess portion R1 of the first cylinder AC1. The first buried portion GB1 may fill the first recess portion R1 of the first cylinder AC1. The second buried portion GB2 may extend to be located within the second recess portion R2 of the second cylinder AC2. The second buried portion GB2 may fill the second recess portion R2 of the second cylinder AC2.

[0030] 2A to 4D, the surround portion GS of the gate electrode GAA may define horizontal channels (see reference symbol "LC" in FIGS. 2D and 2E) in the first channel portion CH1 and the second channel portion CH2. The first buried portion GB1 of the gate electrode GAA may define a first buried channel (BC1) in the cylinder surface of the first cylinder AC1. The second buried portion GB2 of the gate electrode GAA may define a second buried channel (BC2) in the cylinder surface of the second cylinder AC2. The first buried channel BC1 and the second buried channel BC2 are shown in FIG. 4D.

[0031] As described above, the transistor TR may include a gate-all-around (GAA) structure and a hybrid channel, which may refer to a structure in which a horizontal channel LC formed by a surround region GS and first and second buried channels BC1 and BC2 formed by first and second buried regions GB1 and GB2 are mixed.

[0032] Although not shown, a gate insulating layer may be formed between the gate electrode GAA and the first channel portions CH1, CH11 and between the gate electrode GAA and the second channel portions CH2, CH21. The gate insulating layer may be formed between the first buried portion GB1 of the gate electrode GAA and the first cylinder AC1. The gate insulating layer may be formed between the second buried portion GB2 of the gate electrode GAA and the second cylinder AC2. The gate insulating layer may conformally cover the surface of the first recess portion R1 of the first cylinder AC1 and the surface of the second recess portion R2 of the second cylinder AC2. The gate insulating layer may conformally cover the surface of the gate electrode GAA. A gate insulating layer may be formed between the surround portion GS of the gate electrode GAA and the first channel portion CH1, CH11. A gate insulating layer may be formed between the surround portion GS of the gate electrode GAA and the second channel portion CH2, CH21. The gate insulating layer may have a surround shape conformally surrounding the first channel portion CH1, CH11 and the second channel portion CH2, CH21. The gate insulating layer may include silicon oxide, silicon nitride, silicon oxynitride, a high-k material, or a combination thereof.

[0033] The active region ACT may include a semiconductor material such as polysilicon. The active region ACT may include doped polysilicon, undoped polysilicon, or amorphous silicon. The first cylinder AC1 and the second cylinder AC2 may be doped with N-type impurities or P-type impurities. The first cylinder AC1 and the second cylinder AC2 may be doped with the same conductivity type impurities. The first cylinder AC1 and the second cylinder AC2 may include at least one impurity selected from arsenic (As), phosphorus (P), boron (B), indium (In), and combinations thereof. The first channel portions CH1 and CH11 and the second channel portions CH2 and CH21 may be doped with conductivity type impurities. The first channel portions CH1 and CH11 and the second channel portions CH2 and CH21 may each include a silicon nanowire doped with impurities.

[0034] The gate electrode GAA may include a metal, a metal mixture, a metal alloy, a semiconductor material, a work function material, a barrier material, or a combination thereof.

[0035] FIG. 5 is a diagram illustrating a schematic configuration of a memory device according to an embodiment.

[0036] As shown in FIG. 5 , the memory device 200 may include a substrate structure (LS), and a memory cell array MCA may be formed on the substrate structure LS. The memory cell array MCA may be vertically oriented VA along a first direction D1 from the substrate structure LS. The memory cell array MCA may include a plurality of memory cells MC, and each individual memory cell MC may include a bit line BL, a transistor TR, a capacitor CAP, and a plate line PL. Each individual memory cell MC may further include a word line WL, and the word line WL may extend elongatedly along a third direction D3. In each individual memory cell MC, the bit line BL, the transistor TR, the capacitor CAP, and the plate line PL may be arranged in a horizontal array LA along a second direction D2.

[0037] The substrate structure LS may be made of a material suitable for semiconductor processing. The substrate structure LS may include at least one of a conductive material, a dielectric material, and a semiconductive material. Various materials may be formed on the substrate structure LS. The substrate structure LS may include a semiconductor substrate, which may be made of a silicon-containing material. For example, the substrate structure LS may include silicon, single-crystal silicon, polysilicon, amorphous silicon, silicon germanium, single-crystal silicon germanium, polycrystalline silicon germanium, carbon-doped silicon, a combination thereof, or a multilayer thereof. The substrate structure LS may also include other semiconductor materials, such as germanium. The substrate structure LS may also include a III / V semiconductor substrate, e.g., a compound semiconductor substrate such as GaAs. The substrate structure LS may also include a silicon-on-insulator (SOI) substrate.

[0038] In another embodiment, the substrate structure LS may include a semiconductor substrate and a plurality of integrated circuits, a multi-level metal wiring (MLM), or a combination thereof formed on the semiconductor substrate. For example, the substrate structure LS may include a peripheral circuit unit (see drawing reference symbol "PC"), and the peripheral circuit unit PC may include a plurality of control circuits for controlling the memory cell arrays MCA. At least one control circuit in the peripheral circuit unit PC may include an N-channel transistor, a P-channel transistor, a CMOS circuit, or a combination thereof. At least one control circuit in the peripheral circuit unit PC may include an address decoder circuit, a read circuit, a write circuit, etc. At least one control circuit in the peripheral circuit unit PC may include a planar channel transistor, a recess channel transistor, a buried gate transistor, a fin channel transistor (FinFET), etc. The peripheral circuit unit PC may include a sense amplifier (SA), and the sense amplifier SA may be connected to the multi-level metal wiring (MLM).

[0039] The memory cell array MCA may include a stack of memory cells MC, which may be stacked vertically along a first direction D1 on top of a substrate structure LS.

[0040] Each individual memory cell MC may include a bit line BL, a transistor TR, a capacitor CAP, and a plate line PL. The transistor TR may include the transistor TR of FIG. 1. A gate electrode GAA of the transistor TR may be referred to as a word line WL. The transistor TR may be located between the bit line BL and the capacitor CAP. The transistors TR may be located in a horizontal array LA along a second direction D2 parallel to the surface of the substrate structure LS. That is, the transistor TR may be located horizontally between the bit line BL and the capacitor CAP.

[0041] The bit lines BL may extend elongately from the substrate structure LS along a first direction D1. The plane of the substrate structure LS may be defined by a second direction D2 and a third direction D3. The bit lines BL may be vertically oriented from the substrate structure LS. Here, vertical orientation may refer to the bit lines BL being vertically oriented in direct contact with the substrate structure LS. For example, the bottom portions of the bit lines BL may be directly connected to the peripheral circuit unit PC. The bit lines BL may have a vertically elevated pillar shape. The bit lines BL may be referred to as vertically oriented bit lines or pillar-type bit lines. Vertically stacked memory cells MC may share one bit line BL.

[0042] FIG. 6A is a schematic perspective view for explaining an individual memory cell MC of FIG. 5. FIG. 6B is a detailed perspective view for explaining an individual memory cell MC of FIG. 6A. FIG. 6C is a cross-sectional view along the AA′ direction of FIG. 6B. FIG. 6D is a cross-sectional view along the BB′ line of FIG. 6C. FIG. 6E is a cross-sectional view along the CC′ line of FIG. 6C. FIG. 6F is a cross-sectional view along the DD′ line of FIG. 6C. FIG. 6G is a cross-sectional view along the EE′ line of FIG. 6C.

[0043] As shown in FIGS. 6A to 6G, each individual memory cell MC includes a transistor TR and a capacitor 104, which are connected to a bit line 101, a plate line 102, and a word line 103. The transistor TR may further include an active region 105, and the word line 103 may have a gate-all-around (GAA) structure surrounding a portion of the active region 105. The active region 105 and the word line 103 may correspond to the active region ACT and gate electrode GAA described in the above-mentioned embodiments. A gate insulating layer GD may be formed between the word line 103 and the active region 105. The gate insulating layer GD may have a shape surrounding the active region 105.

[0044] The bit lines 101 may extend vertically along a first direction D1. The plate lines 102 may extend vertically along the first direction D1. The capacitors 104 may extend horizontally along a second direction D2 between the bit lines 101 and the plate lines 102. The active areas 105 may extend horizontally along the second direction D2 between the bit lines 101 and the capacitors 104. The word lines 103 may extend longitudinally along a third direction D3.

[0045] The transistor TR may be located between the bit line 101 and the plate line 102. The capacitors 104, the transistors TR, and the word lines 103 may be located in a horizontal array LA along a second direction D2.

[0046] The bit line 101 may include a silicon-based material, a metal-based material, or a combination thereof. The bit line 101 may include polysilicon, titanium nitride, tungsten, or a combination thereof. For example, the bit line 101 may include polysilicon or titanium nitride (TiN) doped with N-type impurities. The bit line BL may include a stack of titanium nitride and tungsten (TiN / W). The bit line 101 may further include an ohmic contact layer such as a metal silicide.

[0047] The plate line 102 may include a silicon-based material, a metal-based material, or a combination thereof. The plate line 102 may include polysilicon, titanium nitride, tungsten, or a combination thereof. For example, the plate line 102 may include titanium nitride (TiN). The plate line 102 may include a stack of titanium nitride and tungsten (TiN / W).

[0048] The active region 105 may include a first cylinder 105A, a second cylinder 105B, and at least one channel portion 105C1, 105C2. A source region 105S may be formed at one edge of the active region 105, and a drain region 105D may be formed at the other edge of the active region 105. The drain region 105D may be connected to the bit line 101, and the source region 105S may be connected to a storage node SN of the capacitor 104. The source region 105S and the drain region 105D may be doped with N-type impurities. The source region 105S and the drain region 105D may have a vertical structure. The active region 105 and the source / drain regions 105S, 105D may be integral. That is, the source region 105S may be formed by impurity doping at one edge of the active region 105, and the drain region 105D may be formed by impurity doping at the other edge of the active region 105. 1 to 4B for a detailed description of the active region 105. The source region 105S and the drain region 105D may have a vertical structure.

[0049] The word line 103 may include a surround portion 103S surrounding the channel portions 105C1 and 105C2, and first and second buried portions 103B1 and 103B2 extending from both sides of the surround portion 103S. The surround portion 103S may be shaped to surround the channel portions 105C1 and 105C2. A gate insulating layer GD may be formed between the surround portion 103S and the channel portions 105C1 and 105C2, and the gate insulating layer GD may be shaped to surround the channel portions 105C1 and 105C2. The first buried portion 103B1 of the word line 103 may be buried in the first cylinder 105A of the active region 105. The second buried portion 103B2 of the word line 103 may be buried in the second cylinder 105B of the active region 105. A gate insulating layer GD may be formed between the first buried portion 103B1 and the first cylinder 105A, and the gate insulating layer GD may conformally cover the interior of the first cylinder 105A. A gate insulating layer GD may be formed between the second buried portion 103B2 and the second cylinder 105B, and the gate insulating layer GD may conformally cover the interior of the second cylinder 105B.

[0050] The capacitor 104 may be disposed horizontally from the transistor TR. The capacitor 104 may extend horizontally along the second direction D2. The capacitor 104 may include a storage node SN, a dielectric layer DE, and a plate node PN. The storage node SN, the dielectric layer DE, and the plate node PN may be arranged horizontally along the second direction D2. The storage node SN may have a horizontally oriented cylindrical shape, and the plate node PN may have a shape surrounding the cylinder of the storage node SN. The dielectric layer DE may have a shape covering the cylinder surface of the storage node SN. The plate node PN may be connected to the plate line 102. In another embodiment, the plate node PN and the plate line 102 may be integrated, and the plate node PN may be part of the plate line 102.

[0051] The storage node SN may have a three-dimensional structure, and the three-dimensional storage node SN may be a horizontal three-dimensional structure parallel to the second direction D2. As an example of the three-dimensional structure, the storage node SN may have a cylinder shape, a pillar shape, or a pylinder shape in which a pillar shape and a cylinder shape are merged. In the illustrated embodiment, the storage node SN may be a cylinder shape. A dielectric layer DE may be formed between the storage node SN and the plate node PN. The dielectric layer DE may be in direct contact with the plate node PN.

[0052] The capacitor 104 may comprise a metal-insulator-metal (MIM) capacitor. The storage node SN and the plate node PN may include a metal-based material. The dielectric layer DE may include silicon oxide, silicon nitride, a high-k material, or a combination thereof. The high-k material may have a higher dielectric constant than silicon oxide. Silicon oxide (SiO2) may have a dielectric constant of about 3.9, and the dielectric layer DE may include a high-k material having a dielectric constant of 4 or greater. The high-k material may have a dielectric constant of about 20 or greater. The high-k material may include hafnium oxide (HfO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), lanthanum oxide (La2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), niobium oxide (Nb2O5), or strontium titanium oxide (SrTiO3). In other embodiments, the dielectric layer DE may be a composite layer including two or more layers of the high dielectric constant materials described above.

[0053] The dielectric layer DE is made of zirconium-based oxide. The dielectric layer DE may be a stack structure including zirconium oxide (ZrO2). The stack structure including zirconium oxide (ZrO2) may include a ZA (ZrO2 / Al2O3) stack or a ZAZ (ZrO2 / Al2O3 / ZrO2) stack. The ZA stack may be a structure in which aluminum oxide (Al2O3) is stacked on zirconium oxide (ZrO2). The ZAZ stack may be a structure in which zirconium oxide (ZrO2), aluminum oxide (Al2O3), and zirconium oxide (ZrO2) are sequentially stacked. The ZA stack and the ZAZ stack may be referred to as a zirconium oxide-based layer. In another embodiment, the dielectric layer DE may be formed of a hafnium-based oxide. The dielectric layer DE may be a stack structure including hafnium oxide (HfO2). Stack structures including hafnium oxide (HfO2) may include HA (HfO2 / Al2O3) stacks or HAH (HfO2 / Al2O3 / HfO2) stacks. HA stacks may have a structure in which aluminum oxide (Al2O3) is stacked on hafnium oxide (HfO2). HAH stacks may have a structure in which hafnium oxide (HfO2), aluminum oxide (Al2O3), and hafnium oxide (HfO2) are sequentially stacked. HA stacks and HAH stacks may be referred to as hafnium oxide-base layers. In ZA stacks, ZAZ stacks, HA stacks, and HAH stacks, aluminum oxide (Al2O3) may have a larger band gap than zirconium oxide (ZrO2) and hafnium oxide (HfO2). Aluminum oxide (AlO) may have a lower dielectric constant than zirconium oxide (ZrO) and hafnium oxide (HfO). Therefore, the dielectric layer DE may include a stack of a high dielectric constant material and a high band gap material having a larger band gap than the high dielectric constant material.In addition to aluminum oxide (Al2O3), the dielectric layer DE can also include silicon oxide (SiO2) as another high bandgap material. The dielectric layer DE can suppress leakage current by including a high bandgap material. The high bandgap material can be extremely thin. The high bandgap material can be thinner than the high-k material. In other embodiments, the dielectric layer DE can include a laminated structure in which high-k materials and high-bandgap materials are alternately stacked. For example, the dielectric layer DE can include ZAZA (ZrO2 / Al2O3 / ZrO2 / Al2O3), ZAZAZ (ZrO2 / Al2O3 / ZrO2 / Al2O3 / ZrO2), HAHA (HfO2 / Al2O3 / HfO2 / Al2O3), or HAHAH (HfO2 / Al2O3 / HfO2 / Al2O3 / HfO2 / Al2O3 / HfO2). In such a laminated structure, the aluminum oxide (Al2O3) can be extremely thin.

[0054] In other embodiments, the dielectric layer DE may include a stack structure, a laminate structure, or an intermixing structure including zirconium oxide, hafnium oxide, and aluminum oxide.

[0055] In another embodiment, an interface control layer for improving leakage current may be further formed between the storage node SN and the dielectric layer DE. The interface control layer may include titanium oxide (TiO2). The interface control layer may also be formed between the plate node PN and the dielectric layer DE.

[0056] The storage node SN and the plate node PN may include a metal, a noble metal, a metal nitride, a conductive metal oxide, a conductive noble metal oxide, a metal carbide, a metal silicide, or a combination thereof. For example, the storage node SN and the plate node PN may include titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), ruthenium (Ru), ruthenium (Ru), or a combination thereof. The plate node PN may include titanium nitride (RuO), iridium germanium (Ir), iridium oxide (IrO), platinum (Pt), molybdenum (Mo), molybdenum oxide (MoO), titanium nitride / tungsten (TiN / W) stack, or tungsten nitride / tungsten (WN / W) stack. The plate node PN may also include a combination of a metal-based material and a silicon-based material. For example, the plate node PN may be a titanium nitride / silicon germanium / tungsten nitride (TiN / SiGe / WN) stack. In the titanium nitride / silicon germanium / tungsten nitride (TiN / SiGe / WN) stack, silicon germanium may be a gap fill material filling the cylinder interior of the storage node SN, titanium nitride (TiN) may function as the plate node of the actual capacitor 104, and tungsten nitride may be a low-resistance material.

[0057] The plate node PN of the capacitor 104 may have a branch shape extending in a second direction D2 parallel to the plate line 102. The plate node PN may be located inside the cylinder of the storage node SN, and may be electrically connected to the plate line 102.

[0058] FIG. 6H is a detailed view of a capacitor, and the plate node PN of the capacitor 104 may include an internal node N2 and external nodes N21, N22, N23, and N24. The internal node N2 and the external nodes N21, N22, N23, and N24 may be interconnected. The internal node N2 may be located inside the cylinder of the storage node SN. The external nodes N21, N22, N23, and N24 may be located outside the storage node SN with a dielectric layer DE sandwiched therebetween. The internal node N2 may be located inside the cylinder of the storage node SN with a dielectric layer DE sandwiched therebetween. The external nodes N21, N22, N23, and N24 may be located to surround the outer wall of the cylinder of the storage node SN. The external nodes N21, N22, N23, and N24 may be continuous with each other.

[0059] 7A and 7B are diagrams for explaining a memory cell array MCA according to an embodiment.

[0060] As shown in FIG. 7A , the memory cell array MCA may include a plurality of memory cells MC. The memory cells MC may be stacked vertically along a first direction D1. Each individual memory cell MC may include a bit line 101, a transistor TR, a capacitor 104, and a plate line 102. In each individual memory cell MC, the bit line 101, the transistor TR, the capacitor 104, and the plate line 102 may be arranged in a horizontal array along a second direction D2. The bit line 101 and the plate line 102 may be oriented vertically along the first direction D1. Each individual memory cell MC may further include a word line 103, which may extend longitudinally along a third direction D3. The transistor TR may be horizontally positioned between the bit line 101 and the capacitor 104.

[0061] The individual memory cells MC may be the same as the memory cells MC of FIG. 6A.

[0062] The memory cells MC stacked along the first direction D1 can share a bit line 101. The memory cells MC stacked along the first direction D1 can share a plate line 102.

[0063] As shown in FIG. 7B, the memory cell array MCA may include a plurality of memory cells MC1 to MC6. The memory cells MC1 to MC3 may be stacked vertically along the first direction D1. The memory cells MC4 to MC6 may be stacked vertically along the first direction D1. The memory cells MC1, MC4, MC2, MC5, and MC3, MC6 may each be horizontally arranged along the third direction D3 and share one word line 103. Each of the individual memory cells MC1 to MC6 may include a bit line 101, a transistor TR, a capacitor 104, and a plate line 102. In each of the individual memory cells MC1 to MC6, the bit line 101, the transistor TR, the capacitor 104, and the plate line 102 may be arranged in a horizontal arrangement along the second direction D2. The bit line 101 and the plate line 102 may be oriented vertically along the first direction D1. Each of the individual memory cells MC1 to MC6 may further include a word line 103, which may extend longitudinally along the third direction D3. The transistor TR may be horizontally arranged between the bit line 101 and the capacitor 104.

[0064] The individual memory cells MC1 to MC6 may be the same as the memory cells MC in FIG. 6A.

[0065] The memory cells MC1 to MC3 and MC4 to MC6 stacked along the first direction D1 can share one bit line 101. The memory cells MC1 to MC3 and MC4 to MC6 stacked along the first direction D1 can share one plate line 102. The plate line 102 of the memory cells MC1 to MC3 and the plate line 102 of the memory cells MC4 to MC6 can be interconnected. Therefore, the memory cells MC1 to MC6 can share the plate line 102.

[0066] 8 is a diagram illustrating a mirror type memory cell array sharing a bit line, and FIG 9 is a diagram illustrating a mirror type memory cell array sharing a plate line.

[0067] Referring to FIG. 8, a mirrored memory cell array 200 sharing a bit line 101 will be described.

[0068] The memory cells MC arranged horizontally along the second direction D2 may be arranged in a mirror structure in which they are connected to different plate lines 102 but share one bit line 101.

[0069] Referring to FIG. 9, a mirror type memory cell array 210 sharing a plate line 102 will be described.

[0070] The memory cells MC arranged along the second direction D2 may be arranged in a mirror structure in which they are connected to different bit lines 101 but share one plate line 102 .

[0071] In another embodiment, the memory device may include both a mirrored memory cell array 200 that shares bit lines 101 and a mirrored memory cell array 210 that shares plate lines 102 .

[0072] 10A and 10B are diagrams illustrating a memory device according to another embodiment.

[0073] 10A and 10B, the memory devices 301 and 302 may include a peripheral circuit unit 310 and a memory cell array 320. The memory cell array 320 may include at least one of the memory cell arrays (MCA, 200, 210) shown in FIGS. 7A to 9. The memory cell array 320 may include a DRAM memory cell array.

[0074] 10A, the memory cell array 320 may be located above the peripheral circuit unit 310. Therefore, the memory device 301 may have a PUC (Peri under Cell) structure.

[0075] 10B, the memory cell array 320 may be located below the peripheral circuit section 310. Therefore, the memory device 302 may have a CUP (Cell under Peri) structure.

[0076] The peripheral circuit unit 310 may refer to a circuit for driving the memory cell array 320 during read / write operations. The peripheral circuit unit 310 may include an N-channel transistor, a P-channel transistor, a CMOS circuit, or a combination thereof. The peripheral circuit unit 310 may include an address decoder circuit, a read circuit, a write circuit, etc. The peripheral circuit unit 310 may have a structure in which a semiconductor substrate 312 and sense amplifiers 313 are arranged on the semiconductor substrate 312. The sense amplifiers 313 may include transistors whose channels are in the semiconductor substrate 312, and the transistors may be planar channel transistors whose channels are parallel to the surface of the semiconductor substrate 312. The transistor structure in the sense amplifier 313 may include a recess channel transistor, a buried gate transistor, a fin channel transistor (FinFET), etc. in addition to a planar channel transistor.

[0077] The bit lines BL of the memory cell array 320 can be electrically connected to the transistors of the sense amplifier 313. Although not shown, the bit lines BL and the transistors of the sense amplifier 313 can also be interconnected via multi-level metal wiring MLM, which can be formed by a damascene process.

[0078] Although not shown, in yet another embodiment, the memory devices 301 and 302 may include a first semiconductor substrate and a second semiconductor substrate bonded to the first semiconductor substrate. The memory cell array 320 may be formed on the first semiconductor substrate, and the peripheral circuit unit 310 may be formed on the second semiconductor substrate. The first semiconductor substrate and the second semiconductor substrate may each include a conductive bonding pad, and the first semiconductor substrate and the second semiconductor substrate may be bonded to each other via the conductive bonding pad. This allows the memory cell array 320 and the peripheral circuit unit 310 to be electrically connected to each other.

[0079] 11A and 11B are diagrams illustrating an individual memory cell according to another embodiment, and the individual memory cell in Fig. 11A and 11B may be similar to those in Fig. 6A to Fig. 6H.

[0080] 11A and 11B, each individual memory cell MC100, MC101 may include a transistor TR including a bit line 101, a plate line 102, and a word line 103, and a capacitor 104. The transistor TR may further include an active region 105′, and the word line 103 may have a gate-all-around (GAA) structure surrounding a portion of the active region 105′. A gate insulating layer GD may be formed between the word line 103 and the active region 105′.

[0081] The active area 105' includes a first cylinder 105A', a second cylinder 105B', and at least one horizontally oriented cylinder 105A' between the first cylinder 105A' and the second cylinder 105B'. The first cylinder 105A' can be connected to the first doping region 105S, and the second cylinder 105B' can be connected to the second doping region 105D.

[0082] The first cylinder 105A' and the second cylinder 105B' may be asymmetric with respect to each other. As shown in FIG. 11A, the horizontal length of the first cylinder 105A' may be smaller than the horizontal length of the second cylinder 105B'. As shown in FIG. 11B, the horizontal length of the first cylinder 105A' may be larger than the horizontal length of the second cylinder 105B'.

[0083] As described above, the active region 105' comprising the asymmetric first and second cylinders 105A' and 105B' can be applied to the active region ACT of FIGS. 1 to 4B.

[0084] Fig. 12A is a diagram illustrating a capacitor according to another embodiment. Fig. 12B is a detailed diagram of a plate node of the capacitor in Fig. 12A. The capacitor in Fig. 12A may be similar to those in Figs. 6A to 6H.

[0085] 12A and 12B, the capacitor 104' may include a storage node SN, a dielectric layer DE, and a plate node PN'. The plate node PN' may be connected to a plate line 102. The plate node PN' may be connected to an internal node Node N2 and external nodes N21', N22', N23', N24'.

[0086] The external nodes N21′, N22′, N23′, and N24′ may include a first external node N21′, a second external node N22′, a third external node N23′, and a fourth external node N24′. The first external node N21′ and the second external node N22′ may be located on the upper and lower sides of the storage node SN along the first direction D1, and the third external node N23′ and the fourth external node N24′ may be located on the lateral sides of the storage node SN along the third direction D3.

[0087] The horizontal lengths of the first external node N21′ and the second external node N22′ may be the same as each other. The horizontal lengths of the third external node N23′ and the fourth external node N24′ may be the same as each other. The horizontal lengths of the first external node N21′ and the second external node N22′ may be smaller than the horizontal lengths of the third external node N23′ and the fourth external node N24′.

[0088] The third external node N23' and the fourth external node N24' have large horizontal lengths, so that they can support the storage node SN more stably.

[0089] According to the above-described embodiments, overlap control of source and drain regions is possible in a 3D DRAM. Since the overlap control is not affected by variations in etching profile due to transistor dimensions, such as channel size and word line dimensions, a 3D DRAM with excellent mass productivity can be realized.

[0090] The present invention is not limited to the above-described embodiments and the accompanying drawings, and it will be apparent to those skilled in the art that various substitutions, modifications, and alterations are possible within the scope of the technical idea of ​​the present invention. [Explanation of symbols]

[0091] MC memory cell 101 bit lines 102 Plate Line 103 Word Line TR transistor 104 Capacitor 105 Active region

Claims

1. an active region comprising a first cylinder, a second cylinder, and at least one channel portion horizontally oriented between the first cylinder and the second cylinder; a surround gate electrode surrounding the at least one channel portion; a first buried gate electrode extending from one side of the surround gate electrode and buried within the first cylinder; a second buried gate electrode extending from the other side of the surround gate electrode and buried within the second cylinder; A semiconductor device comprising:

2. The semiconductor device according to claim 1 , wherein the at least one channel portion comprises a pair of channel portions that are spaced apart and parallel to each other.

3. The at least one channel portion is a first channel portion; a second channel portion spaced apart from the first channel portion; The semiconductor device according to claim 1 , comprising:

4. The semiconductor device of claim 1 , wherein the at least one channel portion comprises a semiconductor material.

5. The semiconductor device according to claim 1 , wherein the surround gate electrode, the first buried gate electrode, and the second buried gate electrode contain the same material.

6. The semiconductor device according to claim 1 , wherein the surround gate electrode, the first buried gate electrode, and the second buried gate electrode contain a metal-containing material.

7. 2. The semiconductor device of claim 1, further comprising a first doped region connected to the first cylinder and a second doped region connected to the second cylinder.

8. a horizontal channel defined by the surround gate electrode in the at least one channel portion; a buried channel defined in the first and second cylinders by the first and second buried gate electrodes; The semiconductor device according to claim 1 , further comprising:

9. bit lines and plate lines spaced apart from each other and vertically oriented along a first direction; a transistor having an active region horizontally oriented in a second direction intersecting the bit line, the active region comprising a first cylinder, a second cylinder, and at least one channel portion horizontally oriented between the first cylinder and the second cylinder; a word line extending in a third direction while surrounding at least one channel portion of the active region; a capacitor oriented horizontally along the second direction between the active region and a plate line; A memory cell comprising:

10. The memory cell of claim 9 , wherein the first cylinder, the second cylinder, and the at least one channel portion are positioned in a horizontal arrangement along the second direction.

11. The word line is a surround gate electrode surrounding the at least one channel portion; a first buried gate electrode extending from one side of the surround gate electrode and buried within the first cylinder; a second buried gate electrode extending from the other side of the surround gate electrode and buried within the second cylinder; The memory cell of claim 9 comprising:

12. The memory cell of claim 11 , wherein the active region comprises a buried channel defined by the first buried gate electrode and the second buried gate electrode.

13. a vertical source region between the capacitor and the first cylinder; a vertical drain region between the second cylinder and the bit line; The memory cell of claim 9 further comprising:

14. The memory cell of claim 9 , further comprising a gate insulating layer formed between the word line and the active region.

15. The capacitor is a cylindrical storage node connected to a first cylinder of the active region; a plate node connected to the plate line; a dielectric material between the storage node and the plate node; Equipped with The memory cell of claim 9 , wherein the storage node, the dielectric material, and the plate node are positioned in a horizontal array along the second direction.

16. The plate node is an inner node oriented horizontally from the plate line and extending into the cylinder of the storage node; a plurality of outer nodes oriented horizontally from the plate line and surrounding an outer cylinder of the storage node; The memory cell of claim 15 comprising:

17. The plurality of external nodes: first and second external nodes located outside the cylinder of the storage node along the first direction; third and fourth external nodes located outside the cylinder of the storage node along the third direction; Equipped with 17. The memory cell of claim 16, wherein the horizontal lengths of the first and second external nodes are smaller than the horizontal lengths of the third and fourth external nodes.

18. 18. The memory cell of claim 17, wherein the horizontal length of the first external node and the horizontal length of the second external node are the same, and the horizontal length of the third external node and the horizontal length of the fourth external node are the same.

19. The memory cell of claim 9 , wherein the first cylinder and the second cylinder have horizontally oriented cylindrical shapes located at the same level and facing each other along the second direction.

20. a horizontal length of the first cylinder along the second direction and a horizontal length of the second cylinder along the second direction 10. The memory cell of claim 9, wherein the horizontal lengths along the

21. The at least one channel portion is The memory cell of claim 9 , comprising an edge contacted by the first cylinder and the second cylinder and a channel body between the edges, wherein the contact area between the channel body and the edge is smaller than the contact area between the first and second cylinders and the edge.

22. 22. The memory cell of claim 21, wherein the at least one channel portion has a thickness that gradually decreases from the edge to the channel body.

23. 10. The memory cell of claim 9, wherein the first cylinder comprises a horizontally oriented first recessed portion and the second cylinder comprises a horizontally oriented second recessed portion, the horizontally oriented first recessed portion and the horizontally oriented second recessed portion facing each other along the second direction.

24. 24. The memory cell of claim 23, wherein the first cylinder is located between the capacitor and a horizontally oriented first recess and comprises a first vertical sidewall connected to the capacitor.

25. 24. The memory cell of claim 23, wherein the second cylinder is located between the bit line and a horizontally oriented second recess and comprises a second vertical sidewall connected to the bit line.

26. a vertical source region between the capacitor and the first cylinder; a vertical drain region between the second cylinder and a bit line; The memory cell of claim 9 further comprising:

27. a memory cell array including a plurality of memory cells arranged vertically along a first direction; Each of the memory cells bit lines and plate lines spaced apart from each other and vertically oriented along the first direction; a transistor having an active region horizontally oriented in a second direction intersecting the bit line, the active region comprising a first cylinder, a second cylinder, and at least one channel portion horizontally oriented between the first cylinder and the second cylinder; a word line extending in a third direction while surrounding at least one channel portion of the active region; a capacitor oriented horizontally along the second direction between the active region and a plate line; A memory device comprising:

28. The word line is a surround gate electrode surrounding the at least one channel portion; a first buried gate electrode extending from one side of the surround gate electrode and buried within the first cylinder; a second buried gate electrode extending from the other side of the surround gate electrode and buried within the second cylinder; 28. The memory device of claim 27, comprising:

29. 28. The memory device of claim 27, further comprising a peripheral circuit portion located below the memory cell array and including at least one control circuit for controlling the memory cells.

30. 28. The memory device of claim 27, further comprising a peripheral circuit portion located above the memory cell array and including at least one control circuit for controlling the memory cells.

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