Electronic apparatus

Abstract

To provide an electronic apparatus that prevents a failure in a field effect transistor caused by instantaneous power failure.SOLUTION: In an image forming apparatus 1, a power cut-off circuit 31 is provided between a power supply device 11 and a load 10. A controller 32 detects the instantaneous power failure of power supply voltage. During a period of instantaneous power failure, the power cut-off circuit 31 reduces the on-resistance of a field effect transistor FET compared to the on-resistance of the field effect transistor FET while the load 10 is stopped.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to an electronic device. [Background technology]

[0002] A power supply control device controls a field effect transistor (FET) between a load and a power supply to suppress a temporary drop in load voltage caused by an inrush current immediately after the FET is turned on (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2016-218582 Summary of the Invention [Problem to be solved by the invention]

[0004] When a momentary power outage causes a temporary drop in power supply voltage, causing the FET described above to turn off and on in a short period of time, control is carried out to suppress inrush current by gradually lowering the on-resistance of the FET. However, if the load continues to operate beyond the momentary power outage, an inrush current will occur when the FET turns on, at the point where the on-resistance of the FET is high, which could cause the FET to fail.

[0005] The present invention has been made in consideration of the above-mentioned problems, and aims to provide an electronic device that suppresses FET failures caused by momentary power outages.An object of the present invention is to provide an electronic device that suppresses FET failures caused by momentary power outages. [Means for solving the problem]

[0006] The electronic device according to the present invention includes a power supply device that generates a power supply voltage, a power interruption circuit between the power supply device and a load, an interlock switch between the power supply device and the power interruption circuit, and a controller that detects a momentary power interruption of the power supply voltage. The power interruption circuit includes a field-effect transistor (FET) between the power supply device and the load, and during the momentary power interruption, the on-resistance of the field-effect transistor is set lower than the on-resistance of the field-effect transistor when the load is stopped. [Effects of the Invention]

[0007] According to the present invention, an electronic device that suppresses FET failures caused by momentary power outages can be obtained.

[0008] The above and other objects, features and advantages of the present invention will become more apparent from the following detailed description taken in conjunction with the accompanying drawings. [Brief explanation of the drawings]

[0009] [Figure 1] FIG. 1 is a block diagram showing the configuration of an electronic device according to an embodiment of the present invention. [Figure 2] FIG. 2 is a circuit diagram showing an example of power supply cutoff circuit 31 according to the first embodiment. [Figure 3] FIG. 3 is a diagram illustrating the gate potential of the FET when an instantaneous power outage occurs during load operation in the electronic device according to the first embodiment. [Figure 4] FIG. 4 is a diagram illustrating the gate potential of the FET when the cover is opened or closed while the load is stopped in the electronic device according to the first embodiment. [Figure 5] FIG. 5 is a diagram illustrating the gate potential of the FET when the cover is opened or closed during load operation in the electronic device according to the first embodiment. [Figure 6] FIG. 6 is a circuit diagram showing an example of power supply cutoff circuit 31 according to the second embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0010] Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

[0011] Embodiment 1

[0012] FIG. 1 is a block diagram showing the configuration of an electronic device according to an embodiment of the present invention. The image forming apparatus 1 shown in FIG. 1 is an example of an electronic device, such as a printer or multifunction peripheral, and includes a load 10, such as a motor or a fan. The image forming apparatus 1 also includes a power supply 11, an interlock switch 12, and a control device 13. The control device 13 controls the load 10, operating and stopping the load 10. The power supply 11 is connected to a commercial power source (AC power source), and converts the power of the commercial power source to DC power using an AC / DC conversion circuit 21, which outputs the DC power source voltage at a predetermined reference value (e.g., 24 V). Thus, the power supply 11 generates a DC power source voltage. The power supply 11 also includes a zero-cross detection circuit 22. The zero-cross detection circuit 22 detects zero-crossings in the AC voltage waveform of the commercial power source (AC power source) and generates a detection signal indicating the detected timing.

[0013] The control device 13 further includes a power supply interruption circuit 31. The power supply interruption circuit 31 is provided on the power supply line between the power supply device 11 and the load 10. The interlock switch 12 is also provided on the power supply line between the power supply device 11 and the power supply interruption circuit 31.

[0014] Interlock switch 12 is a switch that operates in response to the opening and closing of a cover (not shown) installed on the housing of image forming apparatus 1. If the switch does not operate when the cover is opened and closed within a predetermined time, but the cover remains open for more than the predetermined time, it will operate and cut off the power supply. After cutting off the power supply, if it detects that the cover is closed, it will cancel the power cut-off and resume the power supply. This prevents the overlap of inrush currents caused by a momentary power outage and the short-term opening and closing of the cover by interlock switch 12.

[0015] FIG. 2 is a circuit diagram showing an example of the power supply interruption circuit 31 according to the first embodiment. For example, as shown in FIG. 2, the power supply interruption circuit 31 includes a field effect transistor (FET). The field effect transistor (FET) is an N-type field effect transistor, and when a positive gate-source voltage VGS is applied between the gate and source, the FET is turned on, and the source and drain are brought into a conductive state. Furthermore, the higher the gate-source voltage VGS, the smaller the on-resistance (i.e., the resistance between the source and drain).

[0016] The field effect transistor FET is provided between the power supply device 11 and the load 10, and particularly, here, between the interlock switch 12 and the load 10. Specifically, the drain of the field effect transistor FET is connected to the load 10, and the source of the field effect transistor FET is connected to the interlock switch 12.

[0017] The power supply cutoff circuit 31 makes the on-resistance of the field effect transistor FET lower during the period of the momentary power outage than the on-resistance of the field effect transistor FET when the load 10 is stopped.

[0018] In the first embodiment, the power supply cutoff circuit 31 sets the on-resistance of the field-effect transistor FET when the load 10 is operating lower than the on-resistance of the field-effect transistor when the load 10 is stopped. As a result, even if an instantaneous power outage occurs while the load 10 is operating, the on-resistance of the field-effect transistor FET remains low.

[0019] When the load 10 is stopped and the interlock switch 12 cancels the power cutoff, the power cutoff circuit 31 temporarily increases the on-resistance of the field effect transistor FET to suppress the inrush current.

[0020] For example, in the power supply interruption circuit 31 shown in FIG. 2, the source of the field-effect transistor FET (i.e., the output terminal of the interlock switch 12) is electrically connected to a series circuit of resistors R1 and R2 and a transistor TR serving as a switching element. The gate of the field-effect transistor FET is also connected to a series circuit of resistors R3 and R4 and a Zener diode ZD. The junction between resistors R1 and R2 is electrically connected to the junction between resistors R3 and R4. A capacitor C is connected between the gate and source of the field-effect transistor FET. Capacitor C is provided to temporarily maintain the gate-source voltage VGS. Diode D is provided to accelerate the discharge of capacitor C when the gate-source voltage VGS is switched down.

[0021] Furthermore, transistor TR is used as a switching element that is turned on / off by a VGS switching signal. When transistor TR is on, gate potential VG is a voltage (e.g., 8 V) divided by resistors R3 and R4, and when transistor TR is off, gate potential VG is the Zener voltage (e.g., 16 V) of Zener diode ZD, which is a higher potential than when transistor TR is on. In this case, gate-source voltage VGS is lower than when transistor TR is on, and the on-resistance of field-effect transistor FET is higher than when transistor TR is on.

[0022] That is, the gate-source voltage VGS of the field effect transistor FET is set to a predetermined first value (e.g., 16 V) when the load 10 is off, and is set to a predetermined second value (e.g., 8 V) that is smaller than the first value when the load 10 is operating. Therefore, when the load 10 is operating, the gate-source voltage VGS increases, and the on-resistance of the field effect transistor FET decreases.

[0023] In the first embodiment, the controller 32 generates a VGS switching signal so that the on-resistance of the field-effect transistor FET is smaller when the load 10 is operating than when the load 10 is stopped, and supplies the VGS switching signal to the transistor TR of the power supply interruption circuit 31. The controller 32 also detects an instantaneous power outage based on the detection signal from the zero-crossing detection circuit 22, and generates a VGS switching signal so that the on-resistance of the field-effect transistor FET continues to be smaller when the load 10 is stopped, even during the detected instantaneous power outage, and supplies the VGS switching signal to the transistor TR of the power supply interruption circuit 31. Here, the VGS switching signal is a binary signal with a value when the load 10 is operating and a value when the load 10 is stopped.

[0024] Next, the operation of the electronic device according to the first embodiment will be described.

[0025] Fig. 3 is a diagram illustrating the gate potential of the FET when an instantaneous power outage occurs during load operation in the electronic device according to embodiment 1. Fig. 4 is a diagram illustrating the gate potential of the FET when a cover is opened or closed during load stop in the electronic device according to embodiment 1. Fig. 5 is a diagram illustrating the gate potential of the FET when a cover is opened or closed during load operation in the electronic device according to embodiment 1.

[0026] 3, when the controller 32 starts operation of the load 10, it uses a VGS switching signal to lower the gate potential VG of the field effect transistor FET of the power supply cutoff circuit 31 from VG1 (for example, 16 V) to VG2 (for example, 8 V). As a result, the gate-source voltage VGS of the field effect transistor FET rises (to Vcc-VG2), and the on-resistance decreases.

[0027] If a momentary power outage occurs while the load 10 is operating, the power supply voltage Vcc, the output voltage V0 of the interlock switch 12, and the output voltage V1 of the power interruption circuit 31 will drop. At this time, the gate potential VG of the field-effect transistor FET will drop slightly as the output voltage V0 of the interlock switch 12 drops, but the on-resistance of the field-effect transistor FET will remain low. Also, at this time, even if the cover is opened and closed for a short period of time, the interlock switch 12 will not operate, as shown in Figure 3.

[0028] Then, when the momentary power outage ends, the power supply voltage Vcc, the output voltage V0 of the interlock switch 12, and the output voltage V1 of the power supply interruption circuit 31 rise to their reference values ​​(for example, 24 V). At this time, the controller 32 does not change the VGS switching signal, and keeps the on-resistance of the field-effect transistor FET low. As a result, when the momentary power outage ends, the output voltage V1 of the power supply interruption circuit 31 gradually recovers in the same way as the power supply voltage Vcc recovers, so the inrush current when the momentary power outage ends is reduced, and the loss in the field-effect transistor FET is also reduced.

[0029] On the other hand, if continuous cover opening is detected while the load 10 is stopped, and no momentary power outage occurs, as shown in Figure 4, the gate potential VG of the field-effect transistor FET of the power supply interruption circuit 31 is set to VG1, but the output power V0 of the interlock switch 12 becomes zero, so the field-effect transistor FET is in the OFF state. Then, when the cover is subsequently closed, the gate potential VG rises at a value roughly equal to the output power V0 of the interlock switch 12, and when the output power V0 of the interlock switch 12 recovers, the gate potential VG gradually decreases to VG1, at which point the field-effect transistor FET is in the ON state but with high ON resistance. Therefore, if no momentary power outage occurs, the inrush current when the cover is closed is suppressed.

[0030] Furthermore, if a continuous cover open state is detected while the load 10 is operating, and no momentary power outage occurs, the gate potential VG of the field-effect transistor FET of the power supply interruption circuit 31 is set to VG2 while the load 10 is operating, as shown in Figure 5. With the cover open, the output power V0 of the interlock switch 12 becomes zero, so the field-effect transistor FET is in the off state. The controller 32 shuts down the load 10 due to the continuous cover open state. Then, when the cover is closed after the load 10 is shut down, the gate potential VG rises at a value roughly equal to the output power V0 of the interlock switch 12. When the output power V0 of the interlock switch 12 recovers, the gate potential VG gradually decreases to VG1. At this time, the field-effect transistor FET is in the on state, but its on-resistance is high. Therefore, unless a momentary power outage occurs, the inrush current generated when the cover is closed is suppressed.

[0031] As described above, in the first embodiment, the power supply cutoff circuit 31 is provided between the power supply device 11 and the load 10. The controller 32 detects a momentary power outage of the power supply voltage. During the momentary power outage, the power supply cutoff circuit 31 sets the on-resistance of the field-effect transistor FET to be lower than the on-resistance of the field-effect transistor FET when the load 10 is stopped.

[0032] As a result, the field-effect transistor FET does not turn off and on in a short time due to a momentary power outage, but continues to be on with low on-resistance, thereby suppressing failure of the field-effect transistor FET due to a momentary power outage.

[0033] Embodiment 2

[0034] Fig. 6 is a circuit diagram showing an example of a power supply cutoff circuit 31 according to embodiment 2. For example, as shown in Fig. 6, in embodiment 2, power supply cutoff circuit 31 includes a detection circuit 51 that detects power supply voltage Vcc at a stage preceding interlock switch 12, and a discharge circuit 52 that discharges capacitor C.

[0035] In Embodiment 2, when the detected power supply voltage Vcc is less than a predetermined threshold value (for example, 16V) that is lower than a predetermined reference value (for example, 24V), the power-off circuit 31 makes the on-resistance of the field-effect transistor FET lower than when the detected power supply voltage Vcc is equal to or higher than the predetermined threshold value.

[0036] Specifically, the detection circuit 51 is a voltage-dividing circuit of resistors R11 and R12, and applies the divided voltage to the transistor TR and the discharge circuit 52.

[0037] The transistor TR is in an off state when the power supply voltage Vcc is equal to or higher than the predetermined threshold value, and the gate potential VG becomes the voltage VG3 divided by the voltage-dividing circuit of the resistor R1 and the resistor R4.

[0038] On the other hand, the transistor TR is in an on state when the power supply voltage Vcc is less than the predetermined threshold value, and the gate potential VG becomes the voltage VG4 divided by the voltage-dividing circuit of the parallel circuit of the resistor R1, the resistor R2, and the resistor R4 (VG4 < VG3), the gate-source voltage VGS increases, and the on-resistance of the field-effect transistor FET decreases.

[0039] Therefore, even when the power supply voltage Vcc temporarily decreases due to a momentary power failure, the field-effect transistor FET continues to be in an on state with a low on-resistance, so the loss in the field-effect transistor FET due to the inrush current at the end of the momentary power failure is reduced.

[0040] Also, the discharge circuit 52 is connected to both ends of the capacitor C. When the power supply voltage Vcc is less than the predetermined threshold value, the discharge circuit 52 does not discharge the capacitor C when the gate-source voltage VGS decreases, and continues the state where the on-resistance of the field-effect transistor FET is low. When the power supply voltage Vcc is equal to or higher than the predetermined threshold value, the discharge circuit 52 discharges the capacitor C when the gate-source voltage VGS decreases. In addition, when the cover is opened and closed within a predetermined time as described above, the discharge circuit 52 does not discharge the capacitor C and continues the state where the on-resistance of the field-effect transistor FET is low.

[0041] The other configurations and operations of the image forming apparatus 1 according to the second embodiment are the same as those of the first embodiment, and therefore the description thereof will be omitted.

[0042] It should be noted that various changes and modifications to the above-described embodiments will be apparent to those skilled in the art. Such changes and modifications may be made without departing from the spirit and scope of the subject matter and without diminishing its intended advantages. In other words, it is intended that such changes and modifications be included within the scope of the claims. [Industrial Applicability]

[0043] The present invention is applicable to, for example, electronic devices. [Explanation of symbols]

[0044] 1. Image forming device (an example of an electronic device) 10 Load 11 Power supply 12 Interlock Switch 31 Power cutoff circuit 32 Controller 51 Detection circuit

Claims

1. a power supply device that generates a power supply voltage; a power interruption circuit between the power supply device and a load; a controller for detecting an instantaneous power outage of the power supply voltage; the power supply cutoff circuit includes a field effect transistor (FET) between the power supply device and the load, and during the momentary power outage, an on-resistance of the field effect transistor is set lower than an on-resistance of the field effect transistor when the load is stopped; An electronic device characterized by:

2. an interlock switch between the power supply device and the power cutoff circuit; The interlock switch does not operate when the cover is opened or closed within a predetermined time, but operates when the cover remains open beyond the predetermined time.

2. The electronic device according to claim 1,

3. the power supply cutoff circuit sets the on-resistance of the field-effect transistor when the load is operating lower than the on-resistance of the field-effect transistor when the load is stopped; 2. The electronic device according to claim 1,

4. a detection circuit for detecting the power supply voltage at a stage upstream of the interlock switch; the power supply cutoff circuit, when the detected power supply voltage is less than a predetermined threshold value that is lower than the predetermined reference value, reduces the on-resistance of the field-effect transistor compared to when the detected power supply voltage is equal to or higher than the predetermined threshold value; 2. The electronic device according to claim 1,

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