Semiconductor storage device

Abstract

To provide a semiconductor storage device which enables high-speed operation.SOLUTION: A semiconductor storage device includes a substrate, a plurality of memory blocks, and a control circuit. The control circuit is configured to be able to consecutively execute a second program operation, after subsequently executing a first precharge operation and a first program operation in a first-mode write operation. In the first precharge operation, a predetermined voltage is supplied to a first word line. In the first program operation, a first voltage is supplied to a first selection gate line, a first program voltage is supplied to the first word line, and a write path voltage smaller than the first program voltage is supplied to a second word line. In the second program operation, the first voltage is supplied to a second selection gate line, a second program voltage larger than the write path voltage is supplied to the first word line, and the write path voltage is supplied to the second word line.SELECTED DRAWING: Figure 12

Description

[Technical Field]

[0001] The present embodiment relates to a semiconductor memory device. [Background technology]

[0002] 2. Description of the Related Art A semiconductor memory device is known that includes a substrate, a plurality of memory blocks arranged on the substrate, and a control circuit electrically connected to the plurality of memory blocks. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent Publication No. 2020-9511 Summary of the Invention [Problem to be solved by the invention]

[0004] A semiconductor memory device capable of high-speed operation is provided. [Means for solving the problem]

[0005] A semiconductor memory device according to one embodiment includes a substrate, a plurality of memory blocks aligned with the substrate in a first direction intersecting the surface of the substrate and aligned in a second direction intersecting the first direction, and a control circuit connected to the plurality of memory blocks and configured to perform a write operation. Each of the memory blocks includes a first drain side select transistor and a second drain side select transistor, a first source side select transistor and a second source side select transistor, a first memory cell transistor and a second memory cell transistor electrically connected in series between the first drain side select transistor and the first source side select transistor, a third memory cell transistor and a fourth memory cell transistor electrically connected in series between the second drain side select transistor and the second source side select transistor, a first bit line and a second bit line electrically connected to the first drain side select transistor and the second drain side select transistor, respectively, a first select gate line electrically connected to the gate electrode of the first drain side select transistor, a second select gate line electrically connected to the gate electrode of the second drain side select transistor, a third select gate line electrically connected to the gate electrodes of the first source side select transistor and the second source side select transistor, a source line electrically connected to the first source side select transistor and the second source side select transistor, a first word line electrically connected to the gate electrodes of the first memory cell transistor and the third memory cell transistor, and a second word line electrically connected to the gate electrodes of the second memory cell transistor and the fourth memory cell transistor.

[0006] The control circuit is configured to be able to execute a first-mode write operation in which a first precharge operation and a first program operation are executed in sequence, and then a second program operation is executed continuously.

[0007] The control circuit supplies a predetermined voltage to the first word line in a first precharge operation, and supplies a first voltage to the first select gate line, a second voltage lower than the first voltage to the second select gate line, a first program voltage to the first word line, and a write pass voltage lower than the first program voltage to the second word line in a first program operation. The control circuit supplies the second voltage to the first select gate line, a first voltage to the second select gate line, a second program voltage higher than the write pass voltage to the first word line, and a write pass voltage to the second word line in a second program operation. After supplying the first program voltage and before supplying the second program voltage, the control circuit switches the voltage of the first select gate line from the first voltage to the second voltage and switches the voltage of the second select gate line from the second voltage to the first voltage. [Brief explanation of the drawings]

[0008] [Figure 1] 1 is a schematic block diagram showing the configuration of a memory system 10. FIG. [Figure 2] FIG. 2 is a schematic block diagram showing the configuration of a memory die MD. [Figure 3] FIG. 2 is a schematic circuit diagram showing the configuration of a portion of a memory die MD. [Figure 4] FIG. 2 is a schematic circuit diagram showing the configuration of a portion of a memory die MD. [Figure 5] 1 is a schematic perspective view showing the configuration of a portion of a memory die MD. [Figure 6] FIG. 6 is a schematic enlarged view showing a part of the configuration of FIG. 5. [Figure 7] 10 is a schematic histogram for explaining the threshold voltage of a memory cell MC in which 1-bit data is stored. [Figure 8] 10 is a timing chart for explaining a write operation. [Figure 9] FIG. 10 is a schematic cross-sectional view for explaining a program operation. [Figure 10] 10A and 10B are schematic cross-sectional views for explaining the execution order of write operations. [Figure 11] 10 is a timing chart for explaining a write operation in a first mode. [Figure 12] 10 is a timing chart for explaining a write operation in a second mode. [Figure 13] 10 is a timing chart for explaining a write operation in a first mode according to the first modification. [Figure 14] 10 is a timing chart for explaining a write operation in a second mode according to the first modification. [Figure 15] 10 is a timing chart for explaining a write operation in a first mode according to Modification 2. [Figure 16] 10 is a timing chart for explaining a write operation in a second mode according to Modification 2. [Figure 17] 13 is a timing chart for explaining a write operation in a first mode according to Modification 3. [Figure 18] 13 is a timing chart for explaining a write operation in a second mode according to Modification 3. [Figure 19] 10 is a timing chart for explaining a write operation in a first mode according to the second embodiment. [Figure 20] 11 is a timing chart for explaining a write operation in a first mode according to the third embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0009] Next, a semiconductor memory device according to an embodiment will be described in detail with reference to the drawings. Note that the following embodiment is merely an example and is not intended to limit the present invention.

[0010] In addition, in this specification, the term "semiconductor memory device" may refer to a memory die (memory chip), or may refer to a memory system including a controller die, such as a memory card or SSD. Furthermore, it may refer to a configuration including a host computer, such as a smartphone, tablet terminal, or personal computer.

[0011] Furthermore, in this specification, the term "control circuit" may refer to a peripheral circuit such as a sequencer provided on a memory die, or may refer to a controller die or controller chip connected to a memory die, or may refer to a configuration that includes both of these.

[0012] Furthermore, in this specification, when a first component is said to be "electrically connected" to a second component, the first component may be directly connected to the second component, or the first component may be connected to the second component via wiring, a semiconductor member, a transistor, etc. For example, when three transistors are connected in series, the first transistor is "electrically connected" to the third transistor even if the second transistor is in the OFF state.

[0013] Furthermore, in this specification, when it is said that a first configuration is "connected between" a second configuration and a third configuration, it may mean that the first configuration, the second configuration, and the third configuration are connected in series, and that the second configuration is connected to the third configuration via the first configuration.

[0014] Furthermore, in this specification, when it is said that a circuit or the like "conducts" two wirings or the like, it may mean, for example, that the circuit or the like includes a transistor or the like, that the transistor or the like is provided in the current path between the two wirings, and that the transistor or the like is in the ON state.

[0015] In this specification, a predetermined direction parallel to the upper surface of the substrate is called the X direction, a direction parallel to the upper surface of the substrate and perpendicular to the X direction is called the Y direction, and a direction perpendicular to the upper surface of the substrate is called the Z direction.

[0016] [First embodiment] [Memory System 10] FIG. 1 is a schematic block diagram showing the configuration of a memory system 10. As shown in FIG.

[0017] The memory system 10 reads, writes, erases, etc. user data in response to signals transmitted from a host computer 20. The memory system 10 is, for example, a memory chip, a memory card, an SSD, or other system capable of storing user data. The memory system 10 includes a plurality of memory dies MD that store user data, and a controller CD connected to the plurality of memory dies MD and the host computer 20. The controller CD includes, for example, a processor, RAM, ROM, an ECC circuit, etc., and performs processes such as conversion between logical addresses and physical addresses, bit error detection / correction, and wear leveling. The controller CD also includes a storage area MEM10, which will be described later.

[0018] [Memory die MD configuration] Fig. 2 is a schematic block diagram showing the configuration of the memory die MD, and Fig. 3 and Fig. 4 are schematic circuit diagrams showing the configuration of a part of the memory die MD.

[0019] 2 illustrates a plurality of control terminals, etc. These control terminals may be represented as control terminals corresponding to high active signals (positive logic signals), control terminals corresponding to low active signals (negative logic signals), or control terminals corresponding to both high active signals and low active signals. In FIG. 2, the symbols of control terminals corresponding to low active signals include an overline. In this specification, the symbols of control terminals corresponding to low active signals include a slash (" / ").

[0020] 2 is an example, and the specific embodiment can be adjusted as appropriate. For example, it is possible to make some or all of the high-active signals low-active signals, or some or all of the low-active signals high-active signals. Furthermore, a terminal RY / ( / BY), which will be described later, is a terminal that outputs a ready signal as a high-active signal and a busy signal as a low-active signal. The slash (" / ") between RY and ( / BY) indicates the separation between the ready signal and the busy signal.

[0021] As shown in FIG. 2, the memory die MD includes a memory cell array MCA for storing data, and a peripheral circuit PC connected to the memory cell array MCA.

[0022] [Circuit configuration of memory cell array MCA] As shown in FIG. 3, the memory cell array MCA includes a plurality of memory blocks BLK. Each of the memory blocks BLK includes a plurality of string units SU. Each of the string units SU includes a plurality of memory strings MS. One end of each of the memory strings MS is connected to a peripheral circuit PC via a bit line BL. The other end of each of the memory strings MS is connected to the peripheral circuit PC via a common source line SL.

[0023] The memory string MS includes a drain-side select transistor STD, a plurality of memory cells MC (memory cell transistors), and a source-side select transistor STS, all connected in series between a bit line BL and a source line SL. Hereinafter, the drain-side select transistor STD and the source-side select transistor STS may be simply referred to as select transistors (STD, STS).

[0024] A memory cell MC is a field-effect transistor (memory transistor) that includes a semiconductor layer, a gate insulating film, and a gate electrode. The semiconductor layer functions as a channel region. The gate insulating film includes a charge storage film. The threshold voltage of the memory cell MC changes depending on the amount of charge in the charge storage film. The memory cell MC stores one or more bits of data. The memory cell MC stores data as the magnitude of the threshold voltage. A word line WL is connected to each of the gate electrodes of the memory cells MC corresponding to one memory string MS. Each of these word lines WL is commonly connected to all the memory strings MS in one memory block BLK.

[0025] The select transistors (STD, STS) are field-effect transistors comprising a semiconductor layer, a gate insulating film, and a gate electrode. The semiconductor layer functions as a channel region. A drain-side select gate line SGD is connected to the gate electrode of the drain-side select transistor STD. A source-side select gate line SGS is connected to the gate electrode of the source-side select transistor STS. The drain-side select gate line SGD is provided corresponding to a string unit SU and is commonly connected to all memory strings MS in one string unit SU. The source-side select gate line SGS is commonly connected to all memory strings MS in a memory block BLK. Hereinafter, the drain-side select gate line SGD and the source-side select gate line SGS may be simply referred to as select gate lines (SGD, SGS).

[0026] [Circuit configuration of peripheral circuit PC] 2, the peripheral circuit PC includes a row decoder RD, a sense amplifier module SAM, a cache memory CM, a counter CNT, a voltage generation circuit VG, and a sequencer SQC. The peripheral circuit PC also includes an address register ADR, a command register CMR, and a status register STR. The peripheral circuit PC also includes an input / output control circuit I / O and a logic circuit CTR.

[0027] [Configuration of row decoder RD] The row decoder RD (Fig. 2) receives address data D ADD The row decoder RD (FIG. 2) includes an address decoder for decoding a row address RA in the memory cell array MCA. The row decoder RD (FIG. 2) also includes a block selection circuit and a voltage selection circuit for transferring an operating voltage to the memory cell array MCA in response to an output signal of the address decoder.

[0028] [Configuration of the sense amplifier module SAM] The sense amplifier module SAM includes, for example, a plurality of sense amplifier units SAU (FIG. 4) provided corresponding to a plurality of bit lines BL. As shown in FIG. 4, the sense amplifier unit SAU includes a sense amplifier SA, a line LBUS, and latch circuits SDL, DL0 to DLn (n is a natural number). A charging transistor 55 (FIG. 4) for precharging is connected to the line LBUS. The line LBUS is connected to a line DBUS via a switch transistor DSW.

[0029] The sense amplifier SA includes a sense transistor 41. The sense transistor 41 discharges the charge on the line LBUS in response to the current flowing through the bit line BL. The source electrode of the sense transistor 41 is connected to a voltage V SS The sense node SEN is connected to a voltage supply line to which a ground voltage is supplied. The drain electrode is connected to a wiring LBUS via a switch transistor 42. The gate electrode is electrically connected to the bit line BL via a sense node SEN, a discharge transistor 43, a node COM, a clamp transistor 44, and a voltage-resistant transistor 45. The sense node SEN is connected to an internal control signal line CLKSA via a capacitor 48.

[0030] The sense amplifier SA also includes a voltage transfer circuit that transfers the node COM and the sense node SEN to a voltage V DD The voltage supply line or voltage V SSThe voltage transfer circuit includes a node N1, a charge transistor 46, a charge transistor 49, a charge transistor 47, and a discharge transistor 50. The charge transistor 46 is connected between the node N1 and a sense node SEN. The charge transistor 49 is connected between the node N1 and a node COM. The charge transistor 47 is connected between the node N1 and a voltage V DD The discharge transistor 50 is connected between the node N1 and the voltage supply line to which the voltage V SS The gate electrodes of the charge transistor 47 and the discharge transistor 50 are commonly connected to a node INV_S of the latch circuit SDL.

[0031] The sense transistor 41, switch transistor 42, discharge transistor 43, clamp transistor 44, charge transistor 46, charge transistor 49, and discharge transistor 50 are, for example, enhancement-type NMOS transistors. The voltage-resistant transistor 45 is, for example, a depletion-type NMOS transistor. The charge transistor 47 is, for example, a PMOS transistor.

[0032] Also, the gate electrode of the switch transistor 42 is connected to a signal line STB. The gate electrode of the discharge transistor 43 is connected to a signal line XXL. The gate electrode of the clamp transistor 44 is connected to a signal line BLC. The gate electrode of the voltage-resistant transistor 45 is connected to a signal line BLS. The gate electrode of the charge transistor 46 is connected to a signal line HLL. The gate electrode of the charge transistor 49 is connected to a signal line BLX. These signal lines STB, XXL, BLC, BLS, HLL, and BLX are connected to the sequencer SQC (Figure 2).

[0033] The latch circuit SDL includes nodes LAT_S and INV_S, an inverter 51, an inverter 52, a switch transistor 53, and a switch transistor 54. The inverter 51 has an output terminal connected to the node LAT_S and an input terminal connected to the node INV_S. The inverter 52 has an input terminal connected to the node LAT_S and an output terminal connected to the node INV_S. The switch transistor 53 is provided in a current path between the node LAT_S and a wiring LBUS. The switch transistor 54 is provided in a current path between the node INV_S and a wiring LBUS. The switch transistors 53 and 54 are, for example, NMOS transistors. The gate electrode of the switch transistor 53 is connected to the sequencer SQC via a signal line STL. The gate electrode of the switch transistor 54 is connected to the sequencer SQC via a signal line STI.

[0034] Each of the plurality of latch circuits SDL corresponding to the plurality of bit lines BL holds one bit of data written by a write operation.

[0035] The latch circuits DL0 to DLn are configured in almost the same manner as the latch circuit SDL. However, as described above, the node INV_S of the latch circuit SDL is electrically connected to the gate electrodes of the charge transistor 47 and the discharge transistor 50 in the sense amplifier SA. In this respect, the latch circuits DL0 to DLn differ from the latch circuit SDL.

[0036] Each of the plurality of latch circuits DL0 to DLn corresponding to the plurality of bit lines BL holds one bit of data written by a write operation.

[0037] The switch transistor DSW is, for example, an NMOS transistor. The switch transistor DSW is connected between the wiring LBUS and the wiring DBUS. The gate electrode of the switch transistor DSW is connected to the sequencer SQC via a signal line DBS.

[0038] The above-mentioned signal lines STB, HLL, XXL, BLX, BLC, and BLS are each commonly connected to all the sense amplifier units SAU included in the sense amplifier module SAM. DD The voltage supply line and voltage V SS The voltage supply lines to which the latch circuits SDL are supplied are commonly connected to all the sense amplifier units SAU included in the sense amplifier module SAM. The signal lines STI and STL of the latch circuits SDL are commonly connected to all the sense amplifier units SAU included in the sense amplifier module SAM.

[0039] [Cache memory CM configuration] The cache memory CM (Figure 2) includes multiple latch circuits. The multiple latch circuits in the cache memory CM are connected to the latch circuits in the sense amplifier module SAM via wiring DBUS. Data DAT contained in the multiple latch circuits in the cache memory CM is sequentially transferred to the sense amplifier module SAM or the input / output control circuit I / O.

[0040] In addition, a decode circuit and a switch circuit (not shown) are connected to the cache memory CM. The decode circuit decodes the column address CA held in the address register ADR (Fig. 2). The switch circuit connects the latch circuit corresponding to the column address CA to the bus DB (Fig. 2) in response to the output signal of the decode circuit.

[0041] [Counter CNT configuration] The counter CNT (Fig. 2) receives data transferred sequentially from the latch circuit of the cache memory CM and counts the number of bits in the received data that indicate "0" or "1".

[0042] [Circuit configuration of voltage generation circuit VG] The voltage generating circuit VG (FIG. 2) includes, for example, a step-down circuit and a step-up circuit. The step-down circuit is, for example, a regulator. The step-up circuit is, for example, a charge pump circuit. The step-down circuit and the step-up circuit are each connected to a power supply voltage supply line. The voltage generating circuit VG receives a power supply voltage V CC and voltage V SS are supplied. The voltage generation circuit VG generates a plurality of operating voltages and outputs them simultaneously to a plurality of voltage supply lines. These operating voltages are supplied to the bit lines BL, source lines SL, word lines WL, and select gate lines (SGD, SGS) during, for example, read operations, write operations, and erase operations on the memory cell array MCA. The operating voltages are adjusted appropriately in accordance with control signals from the sequencer SQC.

[0043] [Configuration of the SQC sequencer] The sequencer SQC (Fig. 2) reads the command data D stored in the command register CMR. CMD In accordance with the above, the sequencer SQC outputs an internal control signal to the row decoder RD, the sense amplifier module SAM, and the voltage generation circuit VG. In addition, the sequencer SQC outputs status data D indicating the state of the memory die MD. ST is output to the status register STR as appropriate.

[0044] The sequencer SQC also generates a ready / busy signal and outputs it to the terminal RY / ( / BY). While the terminal RY / ( / BY) is in the "L" state (busy period), access to the memory die MD is basically prohibited. Meanwhile, while the terminal RY / ( / BY) is in the "H" state (ready period), access to the memory die MD is permitted.

[0045] [Address register ADR configuration] As shown in FIG. 2, the address register ADR is connected to the input / output control circuit I / O and receives address data D ADDThe address register ADR includes, for example, a plurality of 8-bit register strings. When an internal operation such as a read operation, a write operation, or an erase operation is executed, the register string stores address data D corresponding to the internal operation being executed. ADD Hold.

[0046] Furthermore, address data D ADD For example, the address CA includes a column address CA (FIG. 2) and a row address RA (FIG. 2). The row address RA includes, for example, a block address that identifies a memory block BLK (FIG. 3), a page address that identifies a string unit SU and a word line WL, a plane address that identifies a memory cell array MCA (plane), and a chip address that identifies a memory die MD.

[0047] [Configuration of command register CMR] The command register CMR is connected to the input / output control circuit I / O and receives command data D CMD The command register CMR has at least one set of, for example, an 8-bit register array. CMD When this is stored, a control signal is sent to the sequencer SQC.

[0048] [Status register STR configuration] The status register STR is connected to the input / output control circuit I / O and outputs the status data D ST The status register STR includes, for example, a plurality of 8-bit register strings. When an internal operation such as a read operation, a write operation, or an erase operation is executed, the register string stores status data D relating to the internal operation being executed. ST The register string also holds, for example, ready / busy information of the memory cell array MCA.

[0049] [Configuration of input / output control circuit I / O] The input / output control circuit I / O (FIG. 2) includes data signal input / output terminals DQ0 to DQ7, data strobe signal input / output terminals DQS and / DQS, a shift register, and a buffer circuit. CCQ is supplied.

[0050] Data input via the data signal input / output terminals DQ0 to DQ7 is input from the buffer circuit to the cache memory CM, the address register ADR, or the command register CMR in response to an internal control signal from the logic circuit CTR. Data output via the data signal input / output terminals DQ0 to DQ7 is input from the cache memory CM or the status register STR to the buffer circuit in response to an internal control signal from the logic circuit CTR.

[0051] The signals input via the data strobe signal input / output terminals DQS, / DQS (for example, a data strobe signal and its complementary signal) are used when inputting data via the data signal input / output terminals DQ0 to DQ7. The data input via the data signal input / output terminals DQ0 to DQ7 is taken into a shift register in the input / output control circuit I / O at the timing of the rising edge of the voltage at the data strobe signal input / output terminal DQS (switching of the input signal) and the falling edge of the voltage at the data strobe signal input / output terminal / DQS (switching of the input signal), and at the timing of the falling edge of the voltage at the data strobe signal input / output terminal DQS (switching of the input signal) and the rising edge of the voltage at the data strobe signal input / output terminal / DQS (switching of the input signal).

[0052] [Configuration of logic circuit CTR] The logic circuit CTR (Fig. 2) comprises a plurality of external control terminals / CE, CLE, ALE, / WE, / RE, RE, and logic circuits connected to these plurality of external control terminals / CE, CLE, ALE, / WE, / RE, RE. The logic circuit CTR receives external control signals from the controller CD via the external control terminals / CE, CLE, ALE, / WE, / RE, RE, and outputs internal control signals to the input / output control circuit I / O in response to the external control terminals.

[0053] [Configuration of part of memory die MD] Fig. 5 is a schematic perspective view showing a partial configuration of the memory die MD. Fig. 6 is a schematic enlarged view showing a partial configuration of Fig. 5. Note that Figs. 5 and 6 show schematic configurations, and the specific configurations can be changed as appropriate. Also, some configurations are omitted in Figs. 5 and 6.

[0054] The memory cell array MCA includes a plurality of finger structures FS (memory blocks BLK) arranged in the Y direction. Each finger structure FS includes five string units SU arranged in the Y direction, as shown in FIG. 5, for example. An inter-finger structure ST is provided between two adjacent finger structures FS in the Y direction. Furthermore, an inter-string unit insulating member SHE made of silicon oxide (SiO2) or the like is provided between two adjacent string units SU in the Y direction.

[0055] In this embodiment, one finger structure FS functions as one memory block BLK. However, multiple finger structures FS may function as one memory block BLK. Furthermore, the finger structure FS may include one to four string units SU, or six or more string units SU.

[0056] The finger structure FS includes a plurality of conductive layers 110 arranged in the Z direction, a wiring layer 112 provided below the plurality of conductive layers 110, and a plurality of semiconductor pillars 120 extending in the Z direction. Furthermore, as shown in Fig. 6, a gate insulating film 130 is provided between each of the plurality of conductive layers 110 and the plurality of semiconductor pillars 120.

[0057] The conductive layer 110 has a generally plate-like shape extending in the X direction. The conductive layer 110 may include a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W). The conductive layer 110 may also include polycrystalline silicon containing impurities such as phosphorus (P) or boron (B). An insulating layer 101 (FIG. 6) such as silicon oxide (SiO2) is provided between the multiple conductive layers 110 arranged in the Z direction.

[0058] The plurality of conductive layers 110 function as word lines WL (FIG. 3) and gate electrodes of the plurality of memory cells MC connected thereto. In the following description, such conductive layers 110 may be referred to as conductive layers 110(WL). These conductive layers 110(WL) are electrically independent for each finger structure FS. When focusing on two finger structures FS adjacent in the Y direction, the plurality of conductive layers 110(WL) aligned in the Z direction in these two finger structures FS and the plurality of insulating layers 101 provided on the upper and lower surfaces thereof are separated in the Y direction by inter-finger structures ST.

[0059] One or more conductive layers 110 (FIG. 5) located below the plurality of conductive layers 110(WL) function as source-side select gate lines SGS (FIG. 3) and gate electrodes of the plurality of source-side select transistors STS connected thereto. In the following description, such a conductive layer 110 may be referred to as a conductive layer 110(SGS). When focusing on two finger structures FS adjacent in the Y direction, one or more conductive layers 110(SGS) in these two finger structures FS and the plurality of insulating layers 101 provided on the upper and lower surfaces thereof are separated in the Y direction by an inter-finger structure ST.

[0060] One or more conductive layers 110 located above the plurality of conductive layers 110(WL) function as the drain-side select gate lines SGD (FIG. 3) and the gate electrodes of the plurality of drain-side select transistors STD connected thereto. In the following description, such a conductive layer 110 may be referred to as the conductive layer 110(SGD).

[0061] The multiple conductive layers 110 (SGD) are electrically independent for each string unit SU. In each finger structure FS, when focusing on two string units SU adjacent to each other in the Y direction, one or more conductive layers 110 (SGD) in these two string units SU are separated in the Y direction by an inter-string unit insulating member SHE. When focusing on the string unit SU closest to the other string unit among the multiple string units SU included in one of two finger structures FS adjacent to each other in the Y direction, and the string unit SU closest to the one string unit among the multiple string units SU included in the other finger structure FS, the one or more conductive layers 110 (SGD) in these two string units SU are separated in the Y direction by an inter-finger structure ST.

[0062] The wiring layer 112 (FIG. 5) may include, for example, polycrystalline silicon containing N-type impurities such as phosphorus (P). A metal such as tungsten (W), a conductive material such as tungsten silicide, or other conductive materials may be provided on the lower surface of the wiring layer 112. The wiring layer 112 functions as a part of the source line SL (FIG. 3).

[0063] As shown in FIG. 5, a plurality of semiconductor pillars 120 are arranged in the X and Y directions. The semiconductor pillars 120 are, for example, semiconductor films made of undoped polycrystalline silicon (Si). The semiconductor pillars 120 have a substantially cylindrical shape, and an insulating film 125 (FIG. 6) made of silicon oxide or the like is provided in the center. The outer periphery of each semiconductor pillar 120 is surrounded by a conductive layer 110. The lower ends of the semiconductor pillars 120 are connected to the semiconductor layer in the wiring layer 112. The upper ends of the semiconductor pillars 120 are electrically connected to the bit line BL via contacts (not shown). Each semiconductor pillar 120 functions as a channel region for a plurality of memory cells MC and select transistors STD and STS included in one memory string MS (FIG. 3).

[0064] The gate insulating film 130 has a substantially cylindrical shape that covers the outer circumferential surface of the semiconductor pillar 120. The gate insulating film 130 includes a tunnel insulating film 131, a charge storage film 132, and a block insulating film 133 that are stacked between the semiconductor pillar 120 and the conductive layer 110, as shown in FIG. 6, for example. The tunnel insulating film 131 and the block insulating film 133 include, for example, silicon oxide (SiO2) or the like. The charge storage film 132 includes, for example, a film capable of storing charge, such as silicon nitride (SiN). The tunnel insulating film 131, the charge storage film 132, and the block insulating film 133 have a substantially cylindrical shape and extend in the Z direction along the outer circumferential surface of the semiconductor pillar 120 except for the contact portion between the semiconductor pillar 120 and the wiring layer 112 (FIG. 5).

[0065] 6 shows an example in which the gate insulating film 130 includes a charge storage film 132 made of silicon nitride or the like. However, the charge storage film included in the gate insulating film 130 may be, for example, a floating gate made of polycrystalline silicon or the like containing N-type or P-type impurities.

[0066] The inter-string unit insulating member SHE extends in the X and Z directions and divides the multiple conductive layers 110 (SGD) in the Y direction, as shown in FIG. 5, for example. The inter-string unit insulating member SHE includes, for example, silicon oxide (SiO2). As shown in FIG. 5, the lower end of the inter-string unit insulating member SHE is located above the lower surface of the conductive layer 110 (WL) located in the uppermost layer. In addition, the lower end of the inter-string unit insulating member SHE is located below the lower surface of the conductive layer 110 (SGD) located in the lowermost layer.

[0067] As shown in FIG. 5, the inter-finger structure ST includes an inter-finger electrode 141 extending in the X and Z directions and an inter-finger insulating member 142 made of silicon dioxide (SiO2) or the like provided on both Y-direction side surfaces of the inter-finger electrode 141. As shown in FIG. 5, the lower ends of the inter-finger electrode 141 and the inter-finger insulating member 142 are connected to the wiring layer 112. The inter-finger electrode 141 may be a conductive member including, for example, a stacked film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W). The inter-finger electrode 141 may also be a semiconductor member such as polycrystalline silicon containing impurities such as phosphorus (P) or boron (B). The inter-finger electrode 141 may include both a conductive member and a semiconductor member. The inter-finger electrode 141 functions as a part of the source line SL (FIG. 3).

[0068] The bit lines BL extend in the Y direction and are aligned in the X direction. The bit lines BL may include, for example, a stacked film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as copper (Cu).

[0069] [Threshold voltage of memory cell MC] As explained with reference to Fig. 3, the memory cell MC stores data as the magnitude of the threshold voltage. This point will be explained below.

[0070] 7 is a schematic histogram for explaining the threshold voltage of a memory cell MC in which 1-bit data is stored, where the horizontal axis represents the voltage of the word line WL and the vertical axis represents the number of memory cells MC.

[0071] 7, the threshold voltage of the memory cell MC is controlled to two states. For example, the threshold voltage of the memory cell MC controlled to the lower state is equal to the erase verify voltage V VFYEr The threshold voltage of the memory cell MC controlled to the upper state is smaller than the voltage V VFYS Larger than the read pass voltage V READ Smaller than.

[0072] In the example of FIG. 7, a read voltage V CGR is set.

[0073] For example, a lower state corresponds to a low threshold voltage. A memory cell MC in a lower state is, for example, a memory cell MC in an erased state. For example, data "1" is assigned to a memory cell MC in a lower state.

[0074] The higher state corresponds to a high threshold voltage. A memory cell MC in the higher state is, for example, a memory cell MC in a written state. For example, data "0" is assigned to the memory cell MC in the higher state.

[0075] [Write operation] Next, the write operation will be described.

[0076] FIG. 8 is a timing chart for explaining the write operation.

[0077] As described with reference to FIG. 2, the memory die MD has eight data signal input / output terminals DQ0 to DQ7. In the following description, 8-bit data input to these eight data signal input / output terminals DQ0 to DQ7 may be expressed using two-digit hexadecimal numbers. For example, when "0,0,0,0,0,0,0,0,0" is input to the eight data signal input / output terminals DQ0 to DQ7, this data may be expressed as data 00h, etc. Furthermore, when "1,1,1,1,1,1,1,1" is input, this data may be expressed as data FFh, etc.

[0078] FIG. 8 shows a command set CS input to the memory die MD during a write operation. W This command set CS W includes data 80h, A201, A202, A203, A204, A205, D201, D202 to D2XX and data 10h.

[0079] At timing t201, the controller CD sends command data D to the memory die MD. CMD Data 80h is input as the command. That is, the voltage of the data signal input / output terminals DQ0 to DQ7 is set to "H" or "L" according to each bit of data 80h, "H" is input to the external control terminal CLE, and "L" is input to the external control terminal ALE, and then the external control terminal / WE is raised from "L" to "H". Data 80h is the command input at the start of the write operation.

[0080] At timing t202, the controller CD sends address data D to the memory die MD. ADD Data A201 is input as "H" or "L" as shown in FIG. 2. That is, the voltages of the data signal input / output terminals DQ0 to DQ7 are set to "H" or "L" according to each bit of data A201, "L" is input to the external control terminal CLE, and with "H" input to the external control terminal ALE, the external control terminal / WE is raised from "L" to "H." Data A201 is 8-bit data that constitutes part of the column address CA (FIG. 2).

[0081] At timing t203, the controller CD sends address data D to the memory die MD. ADD The data A202 is input as the data A202. The data A202 is 8-bit data that constitutes part of the column address CA (FIG. 2).

[0082] At timing t204, the controller CD sends address data D to the memory die MD. ADD The data A203 is input as follows. The data A203 is 8-bit data that constitutes part of the row address RA (FIG. 2).

[0083] At timing t205, the controller CD sends address data D to the memory die MD. ADD The data A204 is input as the row address RA (FIG. 2).

[0084] At timing t206, the controller CD sends address data D to the memory die MD. ADD The data A205 is input as the data A204. The data A204 is 8-bit data that constitutes part of the row address RA (FIG. 2).

[0085] At timing t207, the controller CD inputs data D201 to the memory die MD as data DAT. That is, it sets the voltages of the data signal input / output terminals DQ0 to DQ7 to "H" or "L" according to each bit of data D201, inputs "L" to the external control terminal CLE, and switches (toggles) the input signals of the data strobe signal input / output terminals DQS, / DQS while inputting "L" to the external control terminal ALE. The data D201 is 8 bits of data out of the data DAT written to the memory cells MC by the write operation.

[0086] At timing t208, the controller CD inputs data D202 to the memory die MD as data DAT. The data D202 is 8 bits of data out of the data DAT written to the memory cell MC by the write operation. Similarly, the controller CD inputs data in 8-bit increments as data DAT to the memory die MD.

[0087] At timing t209, the controller CD inputs data D2XX to the memory die MD as data DAT. The data D2XX is 8 bits of data out of the data DAT to be written to the memory cells MC by the write operation.

[0088] At timing t210, the controller CD sends command data D to the memory die MD. CMD The data 10h is a command indicating that input of the command set for the write operation has ended.

[0089] At timing t211, the terminal RY / / BY changes from the “H” state to the “L” state, prohibiting access to the memory die MD. Also, a write operation is executed in the memory die MD.

[0090] At timing t212, the write operation on the memory die MD ends. Also, the terminal RY / / BY changes from the "L" state to the "H" state, and access to the memory die MD is permitted.

[0091] At timing t213, the controller CD sends, for example, command data D CMD The data 70h is input as the status data D held in the status register STR (Figure 2). ST This is a command that requests the output of

[0092] At timing t214, the controller CD outputs, for example, data D211 from the memory die MD. The data D211 is the status data D ST (Figure 2).

[0093] [Program operation] The write operation includes a number of operations. In the following, one of these operations, the program operation, will be explained. The program operation is performed by writing data to the selected word line WL S This is an operation of supplying a program voltage to the memory cell MC to increase the threshold voltage of the memory cell MC.

[0094] In the following description, the word line WL that is the target of an operation such as a write operation is referred to as the selected word line WL S and the other word lines WL are called unselected word lines WL U In the following description, the selected word line WL among the memory cells MC included in the string unit SU that is the target of an operation such as a write operation is referred to as a S connected to the selected page PG may be referred to as a “selected memory cell MC.” In the following description, a configuration including such a plurality of selected memory cells MC may be referred to as a selected page PG.

[0095] FIG. 9 is a schematic cross-sectional view for explaining the program operation.

[0096] In the program operation, for example, the bit line BL connected to the memory cell MC for which the threshold voltage is to be adjusted is W to voltage V SS Also, the bit line BL connected to the selected memory cells MC whose threshold voltages are not adjusted is supplied. P to voltage V DD Supply voltage V DD is the voltage V SS For example, the data to be written by the write operation is held in each of the latch circuits DL0 to DLn in the sense amplifier module SAM. In this state, if the states of the signal lines STB, XXL, BLC, BLS, HLL, and BLX described with reference to FIG. 4 are "L, L, H, H, L, H," the bit line BL W to voltage V SS is supplied to the bit line BL P to voltage V DD is supplied.

[0097] In addition, in the program operation, the drain side select gate line SGD is supplied with a voltage V SGD is supplied.

[0098] Voltage V SGD is the voltage V SS Also, the voltage V SGD and voltage V SS The voltage difference between the drain side select transistor STD and the bit line BL W An electron channel is formed in the channel region of the drain side select transistor STD connected to SS will be transferred.

[0099] On the other hand, the voltage V SGD and voltage V DDThe voltage difference between the drain side select transistor STD and the bit line BL P The drain side select transistor STD connected to is in the OFF state.

[0100] In the program operation, the source line SL is supplied with a voltage V SRC is supplied to the source side select gate line SGS, and the voltage V SS is supplied. SRC is the voltage V SS This causes the source side select transistor STS to be in the OFF state.

[0101] In addition, in the program operation, the unselected word lines WL U Write pass voltage V PASS Write pass voltage V PASS is the read pass voltage V READ Also, the write pass voltage V PASS and voltage V SS The voltage difference between the voltage V and the voltage V is greater than the threshold voltage when the memory cell MC functions as an NMOS transistor, regardless of the data stored in the memory cell MC. Therefore, an electron channel is formed in the channel region of the unselected memory cell MC, and a voltage V SS will be transferred.

[0102] In the program operation, the selected word line WL S Program voltage V PGM Supply the program voltage V PGM is the write pass voltage V PASS is greater than.

[0103] Here, the bit line BL W The channel of the semiconductor pillar 120 connected to SS The semiconductor pillar 120 and the selected word line WL SA relatively large electric field is generated between the semiconductor pillar 120 and the charge storage film 132. As a result, electrons in the channel of the semiconductor pillar 120 tunnel into the charge storage film 132 (FIG. 6) through the tunnel insulating film 131 (FIG. 6). This increases the threshold voltage of the write memory cell MC.

[0104] On the other hand, the bit line BL P The channel of the semiconductor pillar 120 connected to the selected word line WL is in an electrically floating state, and the potential of this channel is U The write path voltage V PASS The semiconductor pillar 120 and the selected word line WL S Therefore, electrons in the channel of the semiconductor pillar 120 do not tunnel into the charge storage film 132 (FIG. 6). Therefore, the threshold voltage of the inhibit memory cell MC does not increase.

[0105] In the program operation, for example, the bit lines BL connected to some of the selected memory cells MC for which the threshold voltage is to be adjusted are W , voltage V SS greater than the voltage V DD A smaller voltage may be supplied.

[0106] [Write operation execution order] Next, the execution order of the write operation will be described with reference to Fig. 10, which is a schematic cross-sectional view for explaining the execution order of the write operation.

[0107] Figure 10 illustrates two memory blocks BLK. In the example of Figure 10, the memory block BLK includes five word lines WL and five string units SUa to SUe. Therefore, in the example of Figure 10, the memory block BLK includes 25 pages PG. For example, when a memory cell MC stores 1-bit data, data corresponding to 25 pages PG is stored in the memory block BLK.

[0108] 10 also illustrates an example of the execution order of the write operation. In the example of FIG. 10, first, the write operation is executed in order on five pages PG corresponding to the first word line WL counting from the bottom. In each write operation, data corresponding to one page PG is stored in an erased page PG. That is, the memory cells MC corresponding to the lower state are controlled to two states by one write operation. Next, the write operation is executed in order on five pages PG corresponding to the second word line WL counting from the bottom. Similarly, the write operation is executed in order on 15 pages PG corresponding to the third to fifth word lines WL counting from the bottom.

[0109] [Write operation in the first mode] As described above, the write operation includes multiple operations including the program operation. For example, before the program operation, a precharge operation may be performed to charge the bit lines BL, etc. After the program operation, an equalization operation may be performed to discharge the word lines WL, etc.

[0110] Here, for example, when performing program operations consecutively on multiple pages PG, it is also possible to perform a precharge operation, a program operation, and an equalization operation corresponding to the first page PG, and then perform a precharge operation, a program operation, and an equalization operation corresponding to the second page PG.

[0111] On the other hand, it is also possible to execute the precharge operation and the program operation for the first page PG, and then execute the program operation and the equalization operation, omitting one discharge operation and one precharge operation. By using this method, it is possible to provide a semiconductor memory device that can operate at high speed by shortening the time required for the write operation.

[0112] This method will be described below as a first-mode write operation. In the first-mode write operation, a first precharge operation and a first program operation are executed in sequence, followed by a second program operation. In the first-mode write operation, two values ​​(1 bit) are held in multiple memory cells MC.

[0113] 11 is a timing chart for explaining the write operation in the first mode. In FIG. 11, the drain-side select gate lines SGD of two different string units SU in one memory block BLK are called select gate lines SGDstr0 and SGDstr1. The select gate line SGDstr0 is the drain-side select gate line SGD corresponding to the page PG that is the target of writing in the first program operation. The select gate line SGDstr1 is the drain-side select gate line SGD corresponding to the page PG that is the target of writing in the second program operation. In addition, a plurality of unselected word lines WL U Among them, the selected word line WL S The unselected word line WL located closer to the drain side select gate line SGD than the U The drain side unselected word line WL U_D and the selected word line WL S The unselected word line WL located closer to the source side select gate line SGS than the U the source side unselected word line WL U_S It is sometimes called.

[0114] From timing t221 to timing t231, a first precharge operation is executed in which a predetermined voltage is supplied to the target wiring to precharge it.

[0115] At timing t221 of the first precharge operation, for example, in the first program operation, the bit line BL W The bit line BL n to voltage V SS (second voltage) is supplied to the bit line BL P The bit line BL n+1 to voltage V DD (fourth voltage) is supplied to the source line SL, and the voltage VSL At timing t221 of the first precharge operation, the select gate lines SGDstr0 and SGDstr1 and the selected word line WL S , drain side unselected word line WL U_D , source side unselected word line WL U_S , the source side select gate line SGS is supplied with voltage V PRE (third voltage) and supplies voltage V SS voltage V PRE Voltage V DD , voltage V SL and voltage V PRE is the voltage V SS The voltage V PRE is the voltage V DD and voltage V SL The voltage V DD and voltage V SL are voltages of different magnitudes, but may be voltages of the same magnitude.

[0116] At timing t222 of the first precharge operation, the select gate lines SGDstr0 and SGDstr1 and the selected word line WL S , drain side unselected word line WL U_D , source side unselected word line WL U_S , the source side select gate line SGS is supplied with voltage V SS and supplies voltage V PRE voltage V SS Lower it.

[0117] At timing t223 of the first precharge operation, a voltage V SS and supplies voltage V SL voltage V SS Also, the source side select gate line SGS is set to voltage V SGS and supplies voltage V SS voltage V SGS Voltage V SGS has a magnitude such that the source side select transistor STS is not turned on. At timing t223 of the first precharge operation, the source side select gate line SGS is applied with a voltage V SSmay be left supplied.

[0118] At timing t224 of the first precharge operation, the source line SL is supplied with a voltage V SRC and supplies voltage V SS voltage V SRC At timing t224 of the first precharge operation, the source line SL is set to a voltage V SS may be left supplied.

[0119] At timing t225 of the first precharge operation, a voltage V SGD supply.

[0120] From timing t231 to timing t236, the first program operation is executed.

[0121] At timing t231 of the first program operation, for example, the bit line BL P The bit line BL n+1 to voltage V DD (first voltage) is supplied to the bit line BL W The bit line BL n to voltage V SS and supplies voltage V to the select gate line SGDstr0. SGD and supplies voltage V to the select gate line SGDstr1. SS At timing t231 of the first program operation, the selected word line WL S , drain side unselected word line WL U_D , source side unselected word line WL U_S to voltage V DD -V th and supplies voltage V SS voltage V DD -V th The voltage V DD is, for example, a voltage on the high voltage side of the power supply voltage. this, for example, a voltage approximately equal to the threshold voltage of the transistor having the largest threshold voltage among a plurality of transistors electrically connected between a pad electrode to which a voltage on the high voltage side of the power supply voltage is supplied and a word line WL.

[0122] At timing t232 of the first program operation, the selected word line WL S , drain side unselected word line WL U_D , source side unselected word line WL U_S Write pass voltage V PASS is supplied.

[0123] At timing t233 of the first program operation, the selected word line WL S to the first program voltage V PGM supply.

[0124] At timing t234 of the first program operation, the selected word line WL S Write pass voltage V PASS to generate the first program voltage V PGM Write pass voltage V PASS and the drain side unselected word line WL U_D , source side unselected word line WL U_S to voltage V DD -V th and write pass voltage V PASS voltage V DD -V th Lower it.

[0125] At timing t235 of the first program operation, the bit line BL n+1 , select gate line SGDstr0, select word line WL S , drain side unselected word line WL U_D , source side unselected word line WL U_S to voltage V SS and supplies the bit line BL n+1 Voltage V DD , the voltage V of the select gate line SGDstr0 SGD , selected word line WL S Write pass voltage VPASS , drain side unselected word line WL U_D , source side unselected word line WL U_S Voltage V DD -V th voltage V SS Lower it.

[0126] From timing t251 to timing t271, a recovery operation is executed.

[0127] At timing t251 of the recovery operation, for example, the bit line BL P The bit line BL n to voltage V DD , and in the first program operation, the bit line BL W The bit line BL n+1 to voltage V SS supply.

[0128] From timing t271 to timing t276, the second program operation is executed.

[0129] At timing t271 of the second program operation, for example, the bit line BL P The bit line BL n to voltage V DD , and in the first program operation, the bit line BL W The bit line BL n+1 to voltage V SS and supplies voltage V to the select gate line SGDstr1. SGD and supplies voltage V to the select gate line SGDstr0. SS At timing t271 of the second program operation, the selected word line WL S , drain side unselected word line WL U_D , source side unselected word line WL U_S to voltage V DD -V th and supplies voltage V SS voltage V DD -V th Launch.

[0130] During the period from timing t272 to t276 of the second program operation, the same operations as those during the period from timing t231 to t236 of the first program operation are executed.

[0131] After the second program operation, from timing t276 to timing t283, an equalizing operation (discharging) is performed.

[0132] At timing t281 of the equalization operation, the bit line BL n , bit line BL n+1 , select gate line SGDstr0, select gate line SGDstr1, select word line WL S , drain side unselected word line WL U_D , source side unselected word line WL U_S An open circuit voltage is supplied to the SU, and the select transistors (STD, STS) in the string unit SU and the multiple memory cells MC are turned on.

[0133] At timing t282 of the equalization operation, the bit line BL n , bit line BL n+1 , select gate line SGDstr0, select gate line SGDstr1, select word line WL S , drain side unselected word line WL U_D , source side unselected word line WL U_S , the source side select gate line SGS, the source line SL are supplied with a voltage V SS is supplied, turning off the select transistors (STD, STS) of the string units SU0, SU1 and the plurality of memory cells MC.

[0134] [Write operation in second mode] Next, a second-mode write operation in which a first precharge operation and a first program operation are sequentially performed, followed by a second precharge operation and a second program operation will be described with reference to Fig. 12. In the second-mode write operation, two values ​​(1 bit) are also held in the memory cells MC.

[0135] 12 is a timing chart for explaining the write operation in the second mode. In FIG. 12, the select gate lines SGDstr0 and SGDstr1, the select gate line SGDstr0, the select gate line SGDstr1, the drain-side unselected word line WL U_D , source side unselected word line WL U_S This is as explained in FIG.

[0136] From timing t221 to timing t231, a first precharge operation is executed to precharge the target wiring by supplying a predetermined voltage to the target wiring. The specific operation is the same as the first precharge operation described in the write operation of the first mode with reference to FIG. 11.

[0137] The first program operation is executed from timing t231 to timing t236. The specific operation is the same as the first program operation described in the write operation of the first mode with reference to FIG.

[0138] After the first program operation, from timing t236 to timing t243, an equalizing operation (discharging) is performed.

[0139] At timing t241 of the equalization operation, the bit line BL n , bit line BL n+1 , select gate line SGDstr0, select gate line SGDstr1, select word line WL S , drain side unselected word line WL U_D , source side unselected word line WL U_S An open circuit voltage is supplied to the string units SU0 and SU1, and the select transistors (STD, STS) of the string units SU0 and SU1 and the plurality of memory cells MC are turned on.

[0140] At timing t242 of the equalization operation, the bit line BL n , bit line BL n+1 , select gate line SGDstr0, select gate line SGDstr1, select word line WL S , drain side unselected word line WL U_D, source side unselected word line WL U_S , the source side select gate line SGS, the source line SL are supplied with a voltage V SS is supplied, turning off the select transistors (STD, STS) of the string units SU0, SU1 and the plurality of memory cells MC.

[0141] From timing t261 to timing t271, a second precharge operation is executed to supply a predetermined voltage to the target wiring to precharge it.

[0142] At timing t261 of the second precharge operation, for example, the bit line BL W The bit line BL n+1 to voltage V SS and in the second program operation, the bit line BL P The bit line BL n to voltage V DD and supplies a voltage V to the source line SL. SL Also, the select gate lines SGDstr0 and SGDstr1 and the select word line WL S , drain side unselected word line WL U_D , source side unselected word line WL U_S , the source side select gate line SGS is supplied with voltage V PRE and supplies voltage V SS voltage V PRE Launch.

[0143] At timing t262 of the second precharge operation, the select gate lines SGDstr0 and SGDstr1 and the selected word line WL S , drain side unselected word line WL U_D , source side unselected word line WL U_S , the source side select gate line SGS is supplied with voltage V SS and supplies voltage V PRE voltage V SS Lower it.

[0144] At timing t263 of the second precharge operation, the source line SL is supplied with a voltage V SS and supplies voltage V SLvoltage V SS Also, the source side select gate line SGS is set to voltage V SGS and supplies voltage V SS voltage V SGS At timing t263 of the precharge operation, the source side select gate line SGS is set to voltage V SS may be left supplied.

[0145] At timing t264 of the second precharge operation, the source line SL is supplied with a voltage V SRC and supplies voltage V SS voltage V SRC At timing t264 of the precharge operation, the source line SL is set to a voltage V SS may be left supplied.

[0146] At timing t265 of the second precharge operation, a voltage V SGD supply.

[0147] The second program operation is executed from timing t271 to timing t276. The specific operation is the same as the second program operation described in the write operation of the first mode with reference to FIG.

[0148] After the second program operation, from timing t276 to timing t283, an equalizing operation (discharging) is executed. The specific operation is the same as the equalizing operation (discharging) described in the write operation of the first mode with reference to FIG.

[0149] [effect] In a two-level operation (SLC) in which two values ​​(one bit) are held in multiple memory cells MC, although data integration is low, high-speed write and read operations are possible and the reliability is high. A write operation in the second mode is a write operation in which a first precharge operation and a first program operation are sequentially performed, followed by a second precharge operation and a second program operation, thereby writing data for each page PG. In contrast, a write operation in the first mode is a write operation in which a first precharge operation and a first program operation are sequentially performed, followed by a second program operation, thereby writing data to two pages PG consecutively. In this way, in the write operation in the first mode, the time for the equalization operation and the second precharge operation performed between the first and second program operations in the write operation in the second mode is integrated into the time for the first precharge operation before the first program operation and the time for the recovery operation after the first program operation, thereby shortening the time for the write operation and providing a semiconductor memory device capable of high-speed operation.

[0150] [Modification 1 of the First Embodiment] In the first embodiment described above, in the first precharge operation performed in the first mode write operation and the second mode write operation, the bit line BL P The bit line BL n In the conventional memory cell array, a precharge operation (bit line precharge operation) is performed on the drain side select gate line SGD and a precharge operation (channel precharge operation) is performed on the channels of the memory cells MC. The channel precharge operation is performed from both the drain side select gate line SGD side and the source side select gate line SGS side. In contrast, in this modified example, in the first precharge operation, the channel precharge operation is performed from the drain side select gate line SGD side.

[0151] [Write operation in the first mode] Next, a write operation in the first mode according to this modification will be described with reference to Fig. 13. In the write operation in the first mode according to this modification, two values ​​(one bit) are also held in a plurality of memory cells MC.

[0152] FIG. 13 is a timing chart for explaining the write operation in the first mode according to the first modification.

[0153] From timing t221 to timing t231, a first precharge operation is executed in which a predetermined voltage is supplied to the target wiring to precharge it.

[0154] At timing t221 of the first precharge operation, for example, in the first program operation, the bit line BL W The bit line BL n to voltage V SS , and in the first program operation, the bit line BL P The bit line BL n+1 to voltage V DD and supplies a voltage V to the source line SL. SL Also, the select gate lines SGDstr0 and SGDstr1 and the select word line WL S , drain side unselected word line WL U_D to voltage V PRE and supplies voltage V SS voltage V PRE The source side unselected word line WL U_S , the source side select gate line SGS is supplied with voltage V SS In this way, the channel precharge operation is performed from the drain side select gate line SGD side.

[0155] At timing t222 of the first precharge operation, the select gate lines SGDstr0 and SGDstr1 and the selected word line WL S , drain side unselected word line WL U_D to voltage V SS and supplies voltage V PRE voltage V SS Lower it.

[0156] The first precharge operation from timing t223 to timing t225 is the same as the first precharge operation described in the first mode write operation with reference to FIG.

[0157] The first program operation is executed from timing t231 to timing t236. The specific operation is the same as the first program operation described in the write operation of the first mode with reference to FIG.

[0158] After the first program operation and before the second program operation, a recovery operation is executed from timing t236 to timing t271. The specific operation is the same as the recovery operation described in the first mode write operation with reference to FIG. 11.

[0159] The second program operation is executed from timing t271 to timing t276. The specific operation is the same as the second program operation described in the write operation of the first mode with reference to FIG.

[0160] After the second program operation, from timing t276 to timing t283, an equalizing operation (discharging) is executed. The specific operation is the same as the equalizing operation (discharging) described in the write operation of the first mode with reference to FIG.

[0161] [Write operation in second mode] Next, the write operation in the second mode according to this modification will be described with reference to Fig. 14. In the write operation in the second mode according to this modification, two values ​​(one bit) are also held in a plurality of memory cells MC.

[0162] FIG. 14 is a timing chart for explaining the write operation in the second mode according to the first modification.

[0163] From timing t221 to timing t231, a first precharge operation is executed to precharge the target wiring by supplying a predetermined voltage to the target wiring. The specific operation is the same as the first precharge operation described in the write operation of the first mode according to this modification with reference to FIG. 13.

[0164] The first program operation is executed from timing t231 to timing t236. The specific operation is the same as the first program operation described in the write operation of the first mode with reference to FIG.

[0165] After the first program operation, from timing t236 to timing t243, an equalizing operation (discharging) is executed. The specific operation is the same as the equalizing operation (discharging) described in the second mode write operation with reference to FIG.

[0166] From timing t261 to timing t271, a second precharge operation is executed to precharge the target wiring by supplying a predetermined voltage to the target wiring. The specific operation is the same as the second precharge operation described in the second mode write operation with reference to FIG. 12.

[0167] The second program operation is executed from timing t271 to timing t276. The specific operation is the same as the second program operation described in the write operation of the first mode with reference to FIG.

[0168] After the second program operation, from timing t276 to timing t283, an equalizing operation (discharging) is executed. The specific operation is the same as the equalizing operation (discharging) described in the write operation of the first mode with reference to FIG.

[0169] [Modification 2 of the First Embodiment] In the first embodiment described above, in the first precharge operation executed in the first mode write operation and the second mode write operation, the channel precharge operation is performed from both the drain side select gate line SGD side and the source side select gate line SGS side. In contrast, in this modification, in the first precharge operation, the channel precharge operation is performed from the source side select gate line SGS side.

[0170] [Write operation in the first mode] Next, a write operation in the first mode according to this modification will be described with reference to Fig. 15. In the write operation in the first mode according to this modification, two values ​​(one bit) are also held in a plurality of memory cells MC.

[0171] FIG. 15 is a timing chart for explaining the write operation in the first mode according to the second modification.

[0172] From timing t221 to timing t231, a first precharge operation is executed in which a predetermined voltage is supplied to the target wiring to precharge it.

[0173] At timing t221 of the first precharge operation, for example, in the first program operation, the bit line BL W The bit line BL n to voltage V SS , and in the first program operation, the bit line BL P The bit line BL n+1 to voltage V DD and supplies a voltage V to the source line SL. SL Also, the selected word line WL S , source side unselected word line WL U_S , the source side select gate line SGS is supplied with voltage V PRE and supplies voltage V SS voltage V PRE The select gate lines SGDstr0 and SGDstr1 and the drain side unselected word lines WL U_D to voltage V SS In this way, the channel precharge operation is performed from the source side select gate line SGS side.

[0174] At timing t222 of the first precharge operation, the selected word line WL S , source side unselected word line WL U_S , the source side select gate line SGS is supplied with voltage V SS and supplies voltage V PRE voltage V SS Lower it.

[0175] The first precharge operation from timing t223 to timing t225 is the same as the first precharge operation described in the first mode write operation with reference to FIG.

[0176] The first program operation is executed from timing t231 to timing t236. The specific operation is the same as the first program operation described in the write operation of the first mode with reference to FIG.

[0177] After the first program operation and before the second program operation, a recovery operation is executed from timing t236 to timing t271. The specific operation is the same as the recovery operation described in the first mode write operation with reference to FIG. 11.

[0178] The second program operation is executed from timing t271 to timing t276. The specific operation is the same as the second program operation described in the write operation of the first mode with reference to FIG.

[0179] After the second program operation, from timing t276 to timing t283, an equalizing operation (discharging) is executed. The specific operation is the same as the equalizing operation (discharging) described in the write operation of the first mode with reference to FIG.

[0180] [Write operation in second mode] Next, the write operation in the second mode according to this modification will be described with reference to Fig. 16. In the write operation in the second mode according to this modification, two values ​​(one bit) are also held in a plurality of memory cells MC.

[0181] FIG. 16 is a timing chart for explaining the write operation in the second mode according to the second modification.

[0182] From timing t221 to timing t231, a first precharge operation is executed to precharge the target wiring by supplying a predetermined voltage to the target wiring. The specific operation is the same as the first precharge operation described in the write operation of the first mode according to this modification with reference to FIG. 15 .

[0183] The first program operation is executed from timing t231 to timing t236. The specific operation is the same as the first program operation described in the write operation of the first mode with reference to FIG.

[0184] After the first program operation, from timing t236 to timing t243, an equalizing operation (discharging) is executed. The specific operation is the same as the equalizing operation (discharging) described in the second mode write operation with reference to FIG.

[0185] From timing t261 to timing t271, a second precharge operation is executed to precharge the target wiring by supplying a predetermined voltage to the target wiring. The specific operation is the same as the second precharge operation described in the second mode write operation with reference to FIG. 12.

[0186] The second program operation is executed from timing t271 to timing t276. The specific operation is the same as the second program operation described in the write operation of the first mode with reference to FIG.

[0187] After the second program operation, from timing t276 to timing t283, an equalizing operation (discharging) is executed. The specific operation is the same as the equalizing operation (discharging) described in the write operation of the first mode with reference to FIG.

[0188] [Modification 3 of the First Embodiment] The write operation according to the first embodiment may include a verify operation in addition to the precharge operation, program operation, and equalize operation. The verify operation is performed after the program operation and is an operation for checking whether data has been properly written to each memory cell MC in the page PG. In this modification, the case where the verify operation is performed in the first-mode write operation and the second-mode write operation will be described using an example in which the channel precharge operation is performed from the source-side select gate line SGS side in the first precharge operation.

[0189] [Write operation in the first mode] Next, a write operation in the first mode according to this modification will be described with reference to Fig. 17. In the write operation in the first mode according to this modification, two values ​​(one bit) are also held in a plurality of memory cells MC.

[0190] FIG. 17 is a timing chart for explaining the write operation in the first mode according to the third modification.

[0191] From timing t221 to timing t231, a first precharge operation is executed to precharge the target wiring by supplying a predetermined voltage to the target wiring. The specific operation is the same as the first precharge operation described in the write operation of the first mode with reference to FIG. 15.

[0192] The first program operation is executed from timing t231 to timing t236. The specific operation is the same as the first program operation described in the write operation of the first mode with reference to FIG.

[0193] After the first program operation and before the second program operation, a recovery operation is executed from timing t236 to timing t271. The specific operation is the same as the recovery operation described in the first mode write operation with reference to FIG. 11.

[0194] The second program operation is executed from timing t271 to timing t276. The specific operation is the same as the second program operation described in the write operation of the first mode with reference to FIG.

[0195] After the second program operation, from timing t276 to timing t283, an equalizing operation (discharging) is executed. The specific operation is the same as the equalizing operation (discharging) described in the write operation of the first mode with reference to FIG.

[0196] From timing t283 to timing t2910, the first verify operation is executed.

[0197] At timing t291 of the first verify operation, a voltage V SG Supply voltage V SG The drain side unselected word line WL U_D , source side unselected word line WL U_S with respect to the read pass voltage V READ (FIG. 7) is supplied. Also, the selected word line WL S With respect to voltage V VFYS (FIG. 7) (fourth voltage) is supplied. n , bit line BL n+1 With respect to voltage V DD The voltage V SRC supply.

[0198] At timing t292 of the first verify operation, the select gate line SGDstr1 is applied with a voltage V SS and supplies the voltage V of the select gate line SGDstr1. VFYS voltage V SS Lower it.

[0199] Between timings t292 and t293 of the first verify operation, a sense operation is performed. During the sense operation, the sense node SEN described with reference to FIG. 4 is electrically connected to the bit line BL. The charge at the sense node SEN connected to the memory cell MC in the ON state is discharged, and the sense transistor 41 connected thereto is turned OFF. On the other hand, the charge at the sense node SEN connected to the memory cell MC in the OFF state is maintained, and the sense transistor 41 connected thereto is turned ON. When the signal line STB is turned ON in this state, data indicating whether the memory cell MC is in the ON state or the OFF state is transferred to the line LBUS. This data can be latched by any of the latch circuits SDL, DL0 to DLn.

[0200] At timing t293 of the first verify operation, the bit line BL n , bit line BL n+1 , select gate line SGDstr0, select gate line SGDstr1, drain side unselected word line WL U_D , selected word line WL S , source side unselected word line WL U_S , the source side select gate line SGS is supplied with voltage V SS and supplies the bit line BL n , bit line BL n+1 , select gate line SGDstr0, select gate line SGDstr1, drain side unselected word line WL U_D , selected word line WL S , source side unselected word line WL U_S , the voltage of the source side select gate line SGS is set to voltage V SS Lower it.

[0201] At timing t294 of the first verify operation, the source line SL is supplied with a voltage V SS and the voltage V of the source line SL SL voltage V SS Lower it.

[0202] From timing t2910 to timing t2915, the second verify operation is executed.

[0203] At timing t2911 of the second verify operation, a voltage V SG Also, the drain side unselected word line WL U_D , source side unselected word line WL U_S with respect to the read pass voltage V READ (FIG. 7) is supplied. Also, the selected word line WL S With respect to voltage V VFYS (fourth voltage) is supplied to the bit line BL n , bit line BL n+1 With respect to voltage V DD The voltage V SRC supply.

[0204] At timing t2912 of the second verify operation, the select gate line SGDstr0 is applied with a voltage V SS and supplies the voltage V of the select gate line SGDstr0. VFY voltage V SS Lower it.

[0205] During the first verify operation from timing t292 to t293, a sense operation is performed.

[0206] At timing t2913 of the second verify operation, the bit line BL n , bit line BL n+1 , select gate line SGDstr0, select gate line SGDstr1, drain side unselected word line WL U_D , selected word line WL S , source side unselected word line WL U_S , the source side select gate line SGS is supplied with voltage V SS and supplies the bit line BL n , bit line BL n+1 , select gate line SGDstr0, select gate line SGDstr1, drain side unselected word line WL U_D , selected word line WL S , source side unselected word line WL U_S, the voltage of the source side select gate line SGS is set to voltage V SS Lower it.

[0207] At timing t2914 of the second verify operation, the source line SL is supplied with a voltage V SS and the voltage V of the source line SL SL voltage V SS Lower it.

[0208] [Write operation in second mode] Next, the write operation in the second mode according to this modification will be described with reference to Fig. 18. In the write operation in the second mode according to this modification, two values ​​(one bit) are also held in a plurality of memory cells MC.

[0209] FIG. 18 is a timing chart for explaining the write operation in the second mode according to the third modification.

[0210] From timing t221 to timing t231, a first precharge operation is executed to precharge the target wiring by supplying a predetermined voltage to the target wiring. The specific operation is the same as the first precharge operation described in the write operation of the first mode according to this modification with reference to FIG. 15 .

[0211] The first program operation is executed from timing t231 to timing t236. The specific operation is the same as the first program operation described in the write operation of the first mode with reference to FIG.

[0212] After the first program operation, from timing t236 to timing t243, an equalizing operation (discharging) is executed. The specific operation is the same as the equalizing operation (discharging) described in the second mode write operation with reference to FIG.

[0213] The first verify operation is executed from timing t243 to timing t261. The specific operation is as described in the first verify operation with reference to FIG.

[0214] From timing t261 to timing t271, a second precharge operation is executed to precharge the target wiring by supplying a predetermined voltage to the target wiring. The specific operation is the same as the second precharge operation described in the second mode write operation with reference to FIG. 12.

[0215] The second program operation is executed from timing t271 to timing t276. The specific operation is the same as the second program operation described in the write operation of the first mode with reference to FIG.

[0216] After the second program operation, from timing t276 to timing t283, an equalizing operation (discharging) is executed. The specific operation is the same as the equalizing operation (discharging) described in the write operation of the first mode with reference to FIG.

[0217] The second verify operation is executed from timing t283 to timing t2915. The specific operation is as described in the second verify operation with reference to FIG.

[0218] [Second embodiment] In the first embodiment described above, a case where two pages PG are written consecutively in the write operation in the first mode has been described, but three or more pages PG can also be written consecutively. In this embodiment, a case where four pages PG are written consecutively in the write operation in the first mode will be described.

[0219] When a write operation is performed, data corresponding to three or more pages PG may be stored in three or more latch circuits D0 to DLn (FIG. 4) in advance. Furthermore, during the write operation, the data in the latch circuits D0 to DLn may be updated, and the updated data may be used to perform a program operation.

[0220] [Write operation in the first mode] Next, the write operation in the first mode according to this embodiment will be described with reference to Fig. 19. In the write operation in the first mode according to this embodiment as well, two values ​​(one bit) are held in a plurality of memory cells MC.

[0221] 19 is a timing chart for explaining the write operation in the first mode according to the second embodiment. In FIG. 19, the drain-side select gate lines SGD of four different string units SU in one memory block BLK are called select gate lines SGD STRn, SGD STRn+1, SGD STRn+2, and SGD STRn+3. The select gate line SGD STRn is the select gate line SGD that is the target of writing in the str0 program operation. The select gate line SGD STRn+1 is the select gate line SGD that is the target of writing in the str1 program operation. The select gate line SGD STRn+2 is the select gate line SGD that is the target of writing in the str2 program operation. The select gate line SGD STRn+3 is the select gate line SGD that is the target of writing in the str3 program operation.

[0222] From timing t321 to timing t331, a first precharge operation is executed in which a predetermined voltage is supplied to the target wiring to precharge it.

[0223] At timing t321 of the first precharge operation, for example, the bit line BL W The bit line BL n , bit line BL n+2 , bit line BL n+3 to voltage V SS (second voltage) is supplied, and the str0 program operation is P The bit line BL n+1 to voltage V DD (fourth voltage) is supplied to the source line SL, and the voltage V SL In addition, the select gate lines SGD STRn, SGD STRn+1, SGD STRn+2, and SGD STRn+3, and the drain-side unselected word lines WL U_D , selected word line WL S, source side unselected word line WL U_S , the source side select gate line SGS is supplied with voltage V PRE and supplies voltage V SS voltage V PRE In this way, the channel precharge operation is performed from both the drain side select gate line SGD side and the source side select gate line SGS side.

[0224] At timing t322 of the first precharge operation, the select gate lines SGD STRn, SGD STRn+1, SGD STRn+2, and SGD STRn+3, the drain-side unselected word lines WL U_D , selected word line WL S , source side unselected word line WL U_S , the source side select gate line SGS is supplied with voltage V SS and supplies voltage V PRE voltage V SS Lower it.

[0225] At timing t323 of the first precharge operation, the source line SL is supplied with a voltage V SS and supplies voltage V SL voltage V SS Also, the source side select gate line SGS is set to voltage V SGS and supplies voltage V SS voltage V SGS At timing t323 of the first precharge operation, the source side select gate line SGS is set to a voltage V SS may be left supplied.

[0226] At timing t324 of the first precharge operation, the source line SL is supplied with a voltage V SGS and supplies voltage V SS voltage V SGS At timing t324 of the first precharge operation, the source line SL is set to a voltage V SS may be left supplied.

[0227] At timing t325 of the first precharge operation, a voltage V SGD supply.

[0228] From timing t331 to timing t337, the str0 program operation is executed.

[0229] At timing t331 of the str0 program operation, for example, the bit line BL P The bit line BL n+1 to voltage V DD and the str0 program operation supplies the bit line BL W The bit line BL n , bit line BL n+2 , bit line BL n+3 to voltage V SS and supply voltage V to the select gate line SGD STRn. SGD and supplies voltage V to the select gate lines SGD STRn+1, SGD STRn+2, and SGD STRn+3. SS At timing t331 of the str0 program operation, the selected word line WL S , drain side unselected word line WL U_D , source side unselected word line WL U_S to voltage V DD -V th and supplies voltage V SS voltage V DD -V th Launch.

[0230] At timing t332 of the str0 program operation, the selected word line WL S , drain side unselected word line WL U_D , source side unselected word line WL U_S Write pass voltage V PASS is supplied.

[0231] At timing t333 of the str0 program operation, the selected word line WL S Str0 program voltage VPGM supply.

[0232] At timing t334 of the str0 program operation, the selected word line WL S Write pass voltage V PASS to supply the str0 program voltage V PGM Write pass voltage V PASS and the drain side unselected word line WL U_D , source side unselected word line WL U_S to voltage V DD -V th and write pass voltage V PASS voltage V DD -V th Lower it.

[0233] At timing t335 of the str0 program operation, the select gate line SGD STRn, the selected word line WL S , drain side unselected word line WL U_D , source side unselected word line WL U_S to voltage V SS and supplies the voltage V of the select gate line SGD STRn. SGD , selected word line WL S Write pass voltage V PASS , drain side unselected word line WL U_D , source side unselected word line WL U_S Voltage V DD -V th voltage V SS Lower it.

[0234] At timing t336 of the str0 program operation, the bit line BL n+1 to voltage V SS and supplies the bit line BL n+1 Voltage V DD voltage V SS Lower it.

[0235] After the str0 program operation and before the str1 program operation, from timing t337 to timing t351, a recovery operation is executed.

[0236] At timing t341 of the recovery operation, the bit line BL P The bit line BL n , bit line BL n+2 The recovery voltage is V DD supply.

[0237] At timing t342 of the recovery operation, the select gate line SGD STR that is the target of writing in the str1 program operation n+1 to voltage V SGD supply.

[0238] From timing t351 to timing t361, the str1 program operation is executed.

[0239] At timing t351 of the str1 program operation, for example, the bit line BL P The bit line BL n , bit line BL n+2 to voltage V DD and the str1 program operation supplies the bit line BL W The bit line BL n+1 , bit line BL n+3 to voltage V SS and supplies voltage V to the select gate line SGD STRn+1. SGD and supplies voltage V to the select gate lines SGD STRn+0, SGD STRn+2, and SGD STRn+3. SS At timing t351 of the str1 program operation, the selected word line WL S , drain side unselected word line WL U_D , source side unselected word line WL U_S to voltage V DD -V th and supplies voltage V SS voltage V DD -V th Launch.

[0240] At timing t352 of the str1 program operation, the selected word line WL S, drain side unselected word line WL U_D , source side unselected word line WL U_S Write pass voltage V PASS is supplied.

[0241] At timing t353 of the str1 program operation, the selected word line WL S Str1 program voltage V PGM The str0 program voltage V PGM and str1 program voltage V PGM The voltages are different from those described above, but may be the same.

[0242] At timing t354 of the str1 program operation, the selected word line WL S Write pass voltage V PASS to supply the str1 program voltage V PGM Write pass voltage V PASS and the drain side unselected word line WL U_D , source side unselected word line WL U_S to voltage V DD -V th and write pass voltage V PASS voltage V DD -V th Lower it.

[0243] At timing t355 of the str1 program operation, the select gate line SGD STRn+1, the selected word line WL S , drain side unselected word line WL U_D , source side unselected word line WL U_S to voltage V SS and supplies the voltage V of the select gate line SGD STRn+1. SGD , selected word line WL S Write pass voltage V PASS , drain side unselected word line WL U_D , source side unselected word line WL U_S Voltage V DD -V th voltage V SS Lower it.

[0244] At timing t356 of the str1 program operation, the bit line BL n , bit line BL n+2 to voltage V SS and supplies the bit line BL n , bit line BL n+2 Voltage V DD voltage V SS Lower it.

[0245] After the str1 program operation and before the str2 program operation, from timing t361 to timing t371, a recovery operation is executed.

[0246] At timing t361 of the recovery operation, the bit line BL P The bit line BL n+2 The recovery voltage is V DD supply.

[0247] At timing t362 of the recovery operation, the voltage V SGD supply.

[0248] From timing t371 to timing t381, the str2 program operation is executed.

[0249] At timing t371 of the str2 program operation, for example, the bit line BL P The bit line BL n+2 to voltage V DD (first voltage) is supplied, and the str2 program operation supplies the bit line BL W The bit line BL n , bit line BL n+1 , bit line BL n+3 to voltage V SS and supplies voltage V to the select gate line SGD STRn+2. SGD and supplies voltage V to the select gate lines SGD STRn+0, SGD STRn+1, and SGD STRn+3. SSAt timing t371 of the str2 program operation, the selected word line WL S , drain side unselected word line WL U_D , source side unselected word line WL U_S to voltage V DD -V th and supplies voltage V SS voltage V DD -V th Launch.

[0250] At timing t372 of the str2 program operation, the selected word line WL S , drain side unselected word line WL U_D , source side unselected word line WL U_S Write pass voltage V PASS is supplied.

[0251] At timing t373 of the str2 program operation, the selected word line WL S Str2 program voltage V PGM The str1 program voltage V PGM and str2 program voltage V PGM The voltages are different from those described above, but may be the same.

[0252] At timing t374 of the str2 program operation, the selected word line WL S Write pass voltage V PASS to supply the str2 program voltage V PGM Write pass voltage V PASS and the drain side unselected word line WL U_D , source side unselected word line WL U_S to voltage V DD -V th and write pass voltage V PASS voltage V DD -V th Lower it.

[0253] At timing t375 of the str2 program operation, the select gate line SGD STRn+2, the selected word line WL S, drain side unselected word line WL U_D , source side unselected word line WL U_S to voltage V SS and the voltage V of the select gate line SGD STRn+2 SGD , selected word line WL S Write pass voltage V PASS , drain side unselected word line WL U_D , source side unselected word line WL U_S Voltage V DD -V th voltage V SS Lower it.

[0254] At timing t376 of the str2 program operation, the bit line BL n+2 to voltage V SS and supplies the bit line BL n+2 Voltage V DD voltage V SS Lower it.

[0255] After the str2 program operation and before the str3 program operation, from timing t381 to timing t391, a recovery operation is executed.

[0256] At timing t381 of the recovery operation, the bit line BL P The bit line BL n+3 The recovery voltage is V DD supply.

[0257] At timing t382 of the recovery operation, the select gate line SGD STR that is the target of writing in the str3 program operation n+3 to voltage V SGD supply.

[0258] From timing t391 to timing t401, the str3 program operation is executed.

[0259] At timing t391 of the str3 program operation, for example, the bit line BL PThe bit line BL n+3 to voltage V DD (first voltage) is supplied, and the str3 program operation is W The bit line BL n , bit line BL n+1 , bit line BL n+2 to voltage V SS and supplies voltage V to the select gate line SGD STRn+3. SGD and supplies voltage V to the select gate lines SGD STRn+0, SGD STRn+1, and SGD STRn+2. SS At timing t391 of the str3 program operation, the selected word line WL S , drain side unselected word line WL U_D , source side unselected word line WL U_S to voltage V DD -V th and supplies voltage V SS voltage V DD -V th Launch.

[0260] At timing t392 of the str3 program operation, the selected word line WL S , drain side unselected word line WL U_D , source side unselected word line WL U_S Write pass voltage V PASS is supplied.

[0261] At timing t393 of the str3 program operation, the selected word line WL S Str3 program voltage V PGM The str2 program voltage V PGM and str3 program voltage V PGM The voltages are different from those described above, but may be the same.

[0262] At timing t394 of the str3 program operation, the selected word line WL S Write pass voltage V PASS to supply the str3 program voltage V PGM Write pass voltage V PASSand the drain side unselected word line WL U_D , source side unselected word line WL U_S to voltage V DD -V th and write pass voltage V PASS voltage V DD -V th Lower it.

[0263] At timing t395 of the str3 program operation, the select gate line SGD STRn+3 and the selected word line WL S , drain side unselected word line WL U_D , source side unselected word line WL U_S to voltage V SS and supplies the voltage V of the select gate line SGD STRn+3. SGD , selected word line WL S Write pass voltage V PASS , drain side unselected word line WL U_D , source side unselected word line WL U_S Voltage V DD -V th voltage V SS Lower it.

[0264] At timing t396 of the str3 program operation, the bit line BL n+3 to voltage V SS and supplies the bit line BL n+3 Voltage V DD voltage V SS Lower it.

[0265] After the str3 program operation, an equalizing operation (discharging) is performed from timing t401 to timing t403.

[0266] At timing t401 of the equalization operation, the bit line BL n ~Bit line BL n+3 , select gate line SGD STRn to select gate line SGD STRn+3, select word line WL S , drain side unselected word line WL U_D , source side unselected word line WL U_Sto supply the open circuit voltage.

[0267] At timing t402 of the equalization operation, the bit line BL n ~Bit line BL n+3 , select gate line SGD STRn to select gate line SGD STRn+3, select word line WL S , drain side unselected word line WL U_D , source side unselected word line WL U_S , the source side select gate line SGS, the source line SL are supplied with a voltage V SS supply.

[0268] [Third embodiment] The write operation in the first mode can also be applied to write across word lines WL, which will be described below as this embodiment.

[0269] [Write operation in the first mode] Next, the write operation in the first mode according to this embodiment will be described with reference to Fig. 20. In the write operation in the first mode according to this embodiment as well, two values ​​(one bit) are held in a plurality of memory cells MC.

[0270] 20 is a timing chart for explaining the write operation in the first mode according to the third embodiment. The select gate lines SGD STRn, SGD STRn+1, SGD STRn+2, and SGD STRn+3 in FIG. 20 are as described with reference to FIG. 19. The word line WL n and word line WL n+1 is the word line WL that is straddled, and when it is the write target, the selected word line WL S 20 shows a case where the channel precharge operation is performed from the source side select gate line SGS side in the first precharge operation.

[0271] From timing t521 to timing t531, a first precharge operation is executed in which a predetermined voltage is supplied to the target wiring to precharge it.

[0272] At timing t521 of the first precharge operation, for example, the bit line BL W The bit line BL n , bit line BL n+2 , bit line BL n+3 to voltage V SS and the str0 program operation supplies the bit line BL P The bit line BL n+1 to voltage V DD and supplies a voltage V to the source line SL. SL Also, the word line WL n , word line WL n+1 , source side unselected word line WL U_S , the source side select gate line SGS is supplied with voltage V PRE and supplies voltage V SS voltage V PRE The select gate lines SGD STRn, SGD STRn+1, SGD STRn+2, and SGD STRn+3, and the drain side unselected word lines WL U_D to voltage V SS In this way, the channel precharge operation is performed from the source side select gate line SGS side.

[0273] At timing t522 of the first precharge operation, the word line WL n , word line WL n+1 , source side unselected word line WL U_S , the source side select gate line SGS is supplied with voltage V SS and supplies voltage V PRE voltage V SS Lower it.

[0274] At timing t523 of the first precharge operation, the source line SL is supplied with a voltage V SS and supplies voltage V SL voltage V SS Also, the source side select gate line SGS is set to voltage V SGS and supplies voltage V SS voltage V SGS At timing t523 of the first precharge operation, the source side select gate line SGS is set to a voltage VSS may be left supplied.

[0275] At timing t524 of the first precharge operation, the source line SL is supplied with a voltage V SGS and supplies voltage V SS voltage V SGS At timing t524 of the first precharge operation, the source line SL is set to a voltage V SS may be left supplied.

[0276] At timing t525 of the first precharge operation, a voltage V SGD supply.

[0277] From timing t531 to timing t537, the str0 program operation is executed.

[0278] At timing t531 of the str0 program operation, for example, the bit line BL P The bit line BL n+1 to voltage V DD (first voltage) is supplied to the bit line BL W The bit line BL n , bit line BL n+2 , bit line BL n+3 to voltage V SS and supplies voltage V to the select gate line SGDstr0. SGD At timing t531 of the str0 program operation, the drain side unselected word line WL U_D , word line WL n , word line WL n+1 , source side unselected word line WL U_S to voltage V DD -V th and supplies voltage V SS voltage V DD -V th Launch.

[0279] At timing t532 of the str0 program operation, the drain side unselected word line WL U_D , word line WL n , word line WL n+1 , source side unselected word line WL U_S Write pass voltage V PASS is supplied.

[0280] At timing t533 of the str0 program operation, the word line WL n Str0 program voltage V PGM supply.

[0281] At timing t534 of the str0 program operation, the word line WL n Write pass voltage V PASS to supply the str0 program voltage V PGM Write pass voltage V PASS and the drain side unselected word line WL U_D , word line WL n+1 , source side unselected word line WL U_S to voltage V DD -V th and write pass voltage V PASS voltage V DD -V th Lower it.

[0282] At timing t535 of the str0 program operation, the select gate line SGD STRn+1, the drain side unselected word line WL U_D , word line WL n , word line WL n+1 , source side unselected word line WL U_S to voltage V SS and supplies the voltage V of the select gate line SGD STRn+1. SGD , word line WL n Write pass voltage V PASS , word line WL n+1 , drain side unselected word line WL U_D , source side unselected word line WL U_S Voltage V DD -V th voltage V SSLower it.

[0283] At timing t536 of the str0 program operation, the bit line BL n+1 to voltage V SS and supplies the bit line BL n+1 Voltage V DD voltage V SS Lower it.

[0284] After the str0 program operation and before the str1 program operation, from timing t537 to timing t551, a recovery operation is executed.

[0285] At timing t541 of the recovery operation, the bit line BL P The bit line BL n , bit line BL n+2 The recovery voltage is V DD supply.

[0286] At timing t542 of the recovery operation, the voltage V SGD supply.

[0287] From timing t551 to timing t561, the str1 program operation is executed.

[0288] At timing t551 of the str1 program operation, for example, the bit line BL P The bit line BL n , bit line BL n+2 to voltage V DD (first voltage) is supplied to the bit line BL W The bit line BL n+1 , bit line BL n+3 to voltage V SS and supplies voltage V to the select gate line SGD STRn+1. SGD At timing t551 of the str1 program operation, the drain side unselected word line WLU_D , word line WL n , word line WL n+1 , source side unselected word line WL U_S to voltage V DD -V th and supplies voltage V SS voltage V DD -V th Launch.

[0289] At timing t552 of the str1 program operation, the drain side unselected word line WL U_D , word line WL n , word line WL n+1 , source side unselected word line WL U_S Write pass voltage V PASS is supplied.

[0290] At timing t553 of the str1 program operation, the word line WL n Str1 program voltage V PGM supply.

[0291] At timing t554 of the str1 program operation, the word line WL n Write pass voltage V PASS to supply the str1 program voltage V PGM Write pass voltage V PASS and the drain side unselected word line WL U_D , word line WL n+1 , source side unselected word line WL U_S to voltage V DD -V th and write pass voltage V PASS voltage V DD -V th Lower it.

[0292] At timing t555 of the str1 program operation, the select gate line SGD STRn+2, the drain side unselected word line WL U_D , word line WL n , word line WL n+1 , source side unselected word line WL U_S to voltage V SSand the voltage V of the select gate line SGD STRn+2 SGD , word line WL n Write pass voltage V PASS , word line WL n+1 , drain side unselected word line WL U_D , source side unselected word line WL U_S Voltage V DD -V th voltage V SS Lower it.

[0293] At timing t556 of the str1 program operation, the bit line BL n , bit line BL n+2 to voltage V SS and supplies the bit line BL n , bit line BL n+2 Voltage V DD voltage V SS Lower it.

[0294] After the str1 program operation and before the str2 program operation, from timing t561 to timing t571, a recovery operation is executed.

[0295] At timing t561 of the recovery operation, the bit line BL P The bit line BL n+2 The recovery voltage is V DD supply.

[0296] At timing t562 of the recovery operation, the voltage V SGD supply.

[0297] From timing t571 to timing t581, the str2 program operation is executed.

[0298] At timing t571 of the str2 program operation, for example, the bit line BL P The bit line BL n+2 to voltage VDD (first voltage) is supplied, and the str2 program operation supplies the bit line BL W The bit line BL n , bit line BL n+1 , bit line BL n+3 to voltage V SS and supplies voltage V to the select gate line SGD STRn+3. SGD At timing t571 of the str2 program operation, the drain side unselected word line WL U_D , word line WL n , word line WL n+1 , source side unselected word line WL U_S to voltage V DD -V th and supplies voltage V SS voltage V DD -V th Launch.

[0299] At timing t572 of the str2 program operation, the drain side unselected word line WL U_D , word line WL n , word line WL n+1 , source side unselected word line WL U_S Write pass voltage V PASS is supplied.

[0300] At timing t573 of the str2 program operation, the word line WL n Str2 program voltage V PGM supply.

[0301] At timing t574 of the str2 program operation, the word line WL n Write pass voltage V PASS to supply the str2 program voltage V PGM Write pass voltage V PASS and the drain side unselected word line WL U_D , word line WL n+1 , source side unselected word line WL U_S to voltage V DD -V th and write pass voltage V PASS voltage VDD -V th Lower it.

[0302] At timing t575 of the str2 program operation, the select gate line SGD STRn+3, the drain side unselected word line WL U_D , word line WL n , word line WL n+1 , source side unselected word line WL U_S to voltage V SS and supplies the voltage V of the select gate line SGD STRn+3. SGD , word line WL n Write pass voltage V PASS , drain side unselected word line WL U_D , word line WL n+1 , source side unselected word line WL U_S Voltage V DD -V th voltage V SS Lower it.

[0303] At timing t576 of the str2 program operation, the bit line BL n+2 to voltage V SS and supplies the bit line BL n+2 Voltage V DD voltage V SS Lower it.

[0304] After the str2 program operation and before the str3 program operation, from timing t581 to timing t591, a recovery operation is executed.

[0305] At timing t581 of the recovery operation, the bit line BL P The bit line BL n+3 The recovery voltage is V DD supply.

[0306] At timing t582 of the recovery operation, the voltage V SGD supply.

[0307] From timing t591 to timing t601, the str3 program operation is executed.

[0308] At timing t591 of the str3 program operation, for example, the bit line BL P The bit line BL n+3 to voltage V DD (first voltage) is supplied, and the str3 program operation is W The bit line BL n , bit line BL n+1 , bit line BL n+2 to voltage V SS The select gate line SGD STRn+1 is supplied with a voltage V SGD At timing t591 of the str3 program operation, the drain side unselected word line WL U_D , word line WL n , word line WL n+1 , source side unselected word line WL U_S to voltage V DD -V th and supplies voltage V SS voltage V DD -V th Launch.

[0309] At timing t592 of the str3 program operation, the drain side unselected word line WL U_D , word line WL n , word line WL n+1 , source side unselected word line WL U_S Write pass voltage V PASS is supplied.

[0310] At timing t593 of the str3 program operation, the word line WL n+1 Str3 program voltage V PGM supply.

[0311] At timing t594 of the str3 program operation, the word line WL n+1 Write pass voltage V PASSto supply the str3 program voltage V PGM Write pass voltage V PASS and the drain side unselected word line WL U_D , word line WL n , source side unselected word line WL U_S to voltage V DD -V th and write pass voltage V PASS voltage V DD -V th Lower it.

[0312] At timing t595 of the str3 program operation, the select gate line SGD STRn+1, the drain side unselected word line WL U_D , word line WL n , word line WL n+1 , source side unselected word line WL U_S to voltage V SS and supplies the voltage V of the select gate line SGD STRn+1. SGD , word line WL n+1 Write pass voltage V PASS , drain side unselected word line WL U_D , word line WL n , source side unselected word line WL U_S Voltage V DD -V th voltage V SS Lower it.

[0313] At timing t596 of the str3 program operation, the bit line BL n+3 to voltage V SS and supplies the bit line BL n+3 Voltage V DD voltage V SS Lower it.

[0314] After the str3 program operation, an equalizing operation (discharging) is performed from timing t601 to timing t603.

[0315] At timing t601 of the equalization operation, the bit line BL n ~Bit line BL n+3, select gate lines SGD STRn to SGD STRn+3, drain-side unselected word lines WL U_D , word line WL n , word line WL n+1 , source side unselected word line WL U_S to supply the open circuit voltage.

[0316] At timing t502 of the equalization operation, the bit line BL n ~Bit line BL n+3 , select gate lines SGD STRn to SGD STRn+3, drain-side unselected word lines WL U_D , word line WL n , word line WL n+1 , source side unselected word line WL U_S , the source side select gate line SGS, the source line SL are supplied with a voltage V SS supply.

[0317] [others] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as defined in the claims. [Explanation of symbols]

[0318] BLK...memory block, MC...memory cell, MCA...memory cell array, PC...peripheral circuit, WL...word line, BL...bit line, SL...source line, SGD...drain side select gate line, SGS...source side select gate line, STD...drain side select transistor STD, STS...source side select transistor, 120...semiconductor pillar, 130...gate insulating film.

Claims

1. A substrate; a plurality of memory blocks aligned with the substrate in a first direction intersecting the surface of the substrate and aligned in a second direction intersecting the first direction; a control circuit connected to the plurality of memory blocks and configured to perform a write operation; Equipped with Each of the plurality of memory blocks includes: a first drain side select transistor and a second drain side select transistor; a first source side select transistor and a second source side select transistor; a first memory cell transistor and a second memory cell transistor electrically connected in series between the first drain side select transistor and the first source side select transistor; a third memory cell transistor and a fourth memory cell transistor electrically connected in series between the second drain side select transistor and the second source side select transistor; a first bit line and a second bit line electrically connected to the first drain side select transistor and the second drain side select transistor, respectively; a first select gate line electrically connected to the gate electrode of the first drain side select transistor; a second select gate line electrically connected to the gate electrode of the second drain side select transistor; a third select gate line electrically connected to the gate electrodes of the first source side select transistor and the second source side select transistor; a source line electrically connected to the first source side select transistor and the second source side select transistor; a first word line electrically connected to the gate electrodes of the first memory cell transistor and the third memory cell transistor; a second word line electrically connected to the gate electrodes of the second memory cell transistor and the fourth memory cell transistor; the control circuit is configured to be able to execute a first-mode write operation in which a first precharge operation and a first program operation are executed in sequence, and then a second program operation is executed continuously; The control circuit In the first precharge operation, a predetermined voltage is supplied to the first word line; In the first program operation, a first voltage is supplied to the first select gate line, a second voltage lower than the first voltage is supplied to the second select gate line, a first program voltage is supplied to the first word line, and a write pass voltage lower than the first program voltage is supplied to the second word line; In the second program operation, the second voltage is supplied to the first select gate line, the first voltage is supplied to the second select gate line, a second program voltage higher than the write pass voltage is supplied to the first word line, and the write pass voltage is supplied to the second word line; After the first program voltage is supplied and before the second program voltage is supplied, the voltage of the first select gate line is switched from the first voltage to the second voltage, and the voltage of the second select gate line is switched from the second voltage to the first voltage. Semiconductor memory device.

2. The control circuit causes the first memory cell transistor and the third memory cell transistor to hold binary data in the first program operation and the second program operation.

2. The semiconductor memory device according to claim 1.

3. The control circuit In the first program operation, a first bit line voltage is supplied to the first bit line, and a second bit line voltage is supplied to the second bit line; In the second program operation, a third bit line voltage is supplied to the first bit line and a fourth bit line voltage is supplied to the second bit line; After the first program voltage is supplied and before the second program voltage is supplied, the voltage of the first bit line is switched from the first bit line voltage to the third bit line voltage, and the voltage of the second bit line is switched from the second bit line voltage to the fourth bit line voltage.

2. The semiconductor memory device according to claim 1.

4. the first mode write operation further includes an equalization operation performed after the second program operation; In the equalizing operation, the control circuit switches the voltages of the first select gate line, the second select gate line, the first word line, and the second word line from the second voltage to a first open voltage that is higher than the second voltage.

4. The semiconductor memory device according to claim 3.

5. In the first precharge operation, the control circuit A third voltage higher than the second voltage is supplied to the first select gate line, the second select gate line, the first word line, the second word line, and the third select gate line.

2. The semiconductor memory device according to claim 1.

6. a fifth memory cell transistor provided between the first drain side select transistor and the first memory cell transistor; a sixth memory cell transistor provided between the second drain side select transistor and the third memory cell transistor; a third word line electrically connected to the gate electrodes of the fifth memory cell transistor and the sixth memory cell transistor; the second memory cell transistor is located between the first memory cell transistor and the first source side select transistor; the fourth memory cell transistor is located between the third memory cell transistor and the second source side select transistor; In the first precharge operation, the control circuit A third voltage greater than the second voltage is supplied to the first select gate line, the second select gate line, the first word line, and the third word line.

2. The semiconductor memory device according to claim 1.

7. a fifth memory cell transistor provided between the first drain side select transistor and the first memory cell transistor; a sixth memory cell transistor provided between the second drain side select transistor and the third memory cell transistor; a third word line electrically connected to the gate electrodes of the fifth memory cell transistor and the sixth memory cell transistor; the second memory cell transistor is located between the first memory cell transistor and the first source side select transistor; the fourth memory cell transistor is located between the third memory cell transistor and the second source side select transistor; In the first precharge operation, the control circuit a third voltage greater than the second voltage is supplied to the first word line, the second word line, and the third select gate line; 2. The semiconductor memory device according to claim 1.

8. the control circuit is configured to be further capable of executing a second-mode write operation in which, after sequentially executing the first precharge operation and the first program operation, a second precharge operation and the second program operation are sequentially executed; The control circuit In the second precharge operation, a predetermined voltage is supplied to the first word line.

2. The semiconductor memory device according to claim 1.

9. the first mode write operation further includes a first verify operation and a second verify operation performed after the second program operation; The control circuit In the first verify operation, supplying a fourth voltage greater than the first voltage to the first select gate line and the third select gate line; supplying the second voltage to the second select gate line; supplying a first verify voltage to the first word line, the first verify voltage being lower than the fourth voltage; In the second verify operation, supplying the fourth voltage to the second select gate line and the third select gate line; supplying the second voltage to the first select gate line; The first verify voltage is supplied to the first word line.

2. The semiconductor memory device according to claim 1.

10. The memory block comprises: a plurality of conductive layers aligned in the first direction; a semiconductor pillar extending in the first direction and facing the plurality of conductive layers; a charge storage film provided between the plurality of conductive layers and the semiconductor pillars; Equipped with one of the plurality of conductive layers functions as the first word line; Another one of the plurality of conductive layers functions as the second word line.

2. The semiconductor memory device according to claim 1.

11. A method for controlling a semiconductor memory device, comprising: The semiconductor memory device comprises: A substrate; a plurality of memory blocks aligned with the substrate in a first direction intersecting the surface of the substrate and aligned in a second direction intersecting the first direction; a control circuit connected to the plurality of memory blocks and configured to perform a write operation; Equipped with Each of the plurality of memory blocks includes: a first drain side select transistor and a second drain side select transistor; a first source side select transistor and a second source side select transistor; a first memory cell transistor and a second memory cell transistor electrically connected in series between the first drain side select transistor and the first source side select transistor; a third memory cell transistor and a fourth memory cell transistor electrically connected in series between the second drain side select transistor and the second source side select transistor; a first bit line and a second bit line electrically connected to the first drain side select transistor and the second drain side select transistor, respectively; a first select gate line electrically connected to the gate electrode of the first drain side select transistor; a second select gate line electrically connected to the gate electrode of the second drain side select transistor; a third select gate line electrically connected to the gate electrodes of the first source side select transistor and the second source side select transistor; a source line electrically connected to the first source side select transistor and the second source side select transistor; a first word line electrically connected to the gate electrodes of the first memory cell transistor and the third memory cell transistor; a second word line electrically connected to the gate electrodes of the second memory cell transistor and the fourth memory cell transistor; the control circuit sequentially performs a first precharge operation and a first program operation, and then performs a first-mode write operation in which a second program operation is performed; In the first precharge operation, a predetermined voltage is supplied to the first word line; In the first program operation, a first voltage is supplied to the first select gate line, a second voltage lower than the first voltage is supplied to the second select gate line, a first program voltage is supplied to the first word line, and a write pass voltage lower than the first program voltage is supplied to the second word line; In the second program operation, the second voltage is supplied to the first select gate line, the first voltage is supplied to the second select gate line, a second program voltage higher than the write pass voltage is supplied to the first word line, and a write pass voltage is supplied to the second word line; After the first program voltage is supplied and before the second program voltage is supplied, the voltage of the first select gate line is switched from the first voltage to the second voltage, and the voltage of the second select gate line is switched from the second voltage to the first voltage. A method for controlling a semiconductor memory device.

12. In the first program operation and the second program operation, the first memory cell transistor and the third memory cell transistor are caused to hold binary data.

12. The method for controlling a semiconductor memory device according to claim 11.

13. In the first program operation, a first bit line voltage is supplied to the first bit line, and a second bit line voltage is supplied to the second bit line; In the second program operation, a third bit line voltage is supplied to the first bit line and a fourth bit line voltage is supplied to the second bit line; After the first program voltage is supplied and before the second program voltage is supplied, the voltage of the first bit line is switched from the first bit line voltage to the third bit line voltage, and the voltage of the second bit line is switched from the second bit line voltage to the fourth bit line voltage.

12. The method for controlling a semiconductor memory device according to claim 11.

14. The first mode write operation further includes an equalization operation performed after the second program operation. In the equalizing operation, the voltages of the first select gate line, the second select gate line, the first word line, and the second word line are switched from the second voltage to a first open voltage that is higher than the second voltage.

14. The method for controlling a semiconductor memory device according to claim 13.

15. In the first precharge operation, A third voltage higher than the second voltage is supplied to the first select gate line, the second select gate line, the first word line, the second word line, and the third select gate line.

12. The method for controlling a semiconductor memory device according to claim 11.

16. The semiconductor memory device comprises: a fifth memory cell transistor provided between the first drain side select transistor and the first memory cell transistor; a sixth memory cell transistor provided between the second drain side select transistor and the third memory cell transistor; a third word line electrically connected to the gate electrodes of the fifth memory cell transistor and the sixth memory cell transistor; the second memory cell transistor is located between the first memory cell transistor and the first source side select transistor; the fourth memory cell transistor is located between the third memory cell transistor and the second source side select transistor; In the first precharge operation, A third voltage greater than the second voltage is supplied to the first select gate line, the second select gate line, the first word line, and the third word line.

12. The method for controlling a semiconductor memory device according to claim 11.

17. The semiconductor memory device comprises: a fifth memory cell transistor provided between the first drain side select transistor and the first memory cell transistor; a sixth memory cell transistor provided between the second drain side select transistor and the third memory cell transistor; a third word line electrically connected to the gate electrodes of the fifth memory cell transistor and the sixth memory cell transistor; the second memory cell transistor is located between the first memory cell transistor and the first source side select transistor; the fourth memory cell transistor is located between the third memory cell transistor and the second source side select transistor; In the first precharge operation, a third voltage greater than the second voltage is supplied to the first word line, the second word line, and the third select gate line; 12. The method for controlling a semiconductor memory device according to claim 11.

18. the control circuit is configured to be further capable of executing a second-mode write operation in which, after sequentially executing the first precharge operation and the first program operation, a second precharge operation and the second program operation are sequentially executed; In the second precharge operation, a predetermined voltage is supplied to the first word line.

12. The method for controlling a semiconductor memory device according to claim 11.

19. the first mode write operation further includes a first verify operation and a second verify operation performed after the second program operation; In the first verify operation, supplying a fourth voltage greater than the first voltage to the first select gate line and the third select gate line; supplying the second voltage to the second select gate line; supplying a first verify voltage to the first word line, the first verify voltage being lower than the fourth voltage; In the second verify operation, supplying the fourth voltage to the second select gate line and the third select gate line; The first verify voltage is supplied to the first word line.

12. The method for controlling a semiconductor memory device according to claim 11.

20. The memory block comprises: a plurality of conductive layers aligned in the first direction; a semiconductor pillar extending in the first direction and facing the plurality of conductive layers; a charge storage film provided between the plurality of conductive layers and the semiconductor pillars; Equipped with one of the plurality of conductive layers functions as the first word line; Another one of the plurality of conductive layers functions as the second word line.

12. The method for controlling a semiconductor memory device according to claim 11.

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